1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * Thanks to the following companies for their support: 7 * 8 * - JMicron (hardware and technical support) 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/string.h> 13 #include <linux/delay.h> 14 #include <linux/highmem.h> 15 #include <linux/module.h> 16 #include <linux/pci.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/slab.h> 19 #include <linux/device.h> 20 #include <linux/scatterlist.h> 21 #include <linux/io.h> 22 #include <linux/iopoll.h> 23 #include <linux/gpio.h> 24 #include <linux/gpio/machine.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/pm_qos.h> 27 #include <linux/debugfs.h> 28 #include <linux/acpi.h> 29 #include <linux/dmi.h> 30 31 #include <linux/mmc/host.h> 32 #include <linux/mmc/mmc.h> 33 #include <linux/mmc/slot-gpio.h> 34 35 #ifdef CONFIG_X86 36 #include <asm/iosf_mbi.h> 37 #endif 38 39 #include "cqhci.h" 40 41 #include "sdhci.h" 42 #include "sdhci-cqhci.h" 43 #include "sdhci-pci.h" 44 #include "sdhci-uhs2.h" 45 46 static void sdhci_pci_hw_reset(struct sdhci_host *host); 47 48 #ifdef CONFIG_PM_SLEEP 49 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 50 { 51 mmc_pm_flag_t pm_flags = 0; 52 bool cap_cd_wake = false; 53 int i; 54 55 for (i = 0; i < chip->num_slots; i++) { 56 struct sdhci_pci_slot *slot = chip->slots[i]; 57 58 if (slot) { 59 pm_flags |= slot->host->mmc->pm_flags; 60 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE) 61 cap_cd_wake = true; 62 } 63 } 64 65 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 66 return device_wakeup_enable(&chip->pdev->dev); 67 else if (!cap_cd_wake) 68 device_wakeup_disable(&chip->pdev->dev); 69 70 return 0; 71 } 72 73 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 74 { 75 int i, ret; 76 77 sdhci_pci_init_wakeup(chip); 78 79 for (i = 0; i < chip->num_slots; i++) { 80 struct sdhci_pci_slot *slot = chip->slots[i]; 81 struct sdhci_host *host; 82 83 if (!slot) 84 continue; 85 86 host = slot->host; 87 88 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 89 mmc_retune_needed(host->mmc); 90 91 ret = sdhci_suspend_host(host); 92 if (ret) 93 goto err_pci_suspend; 94 95 if (device_may_wakeup(&chip->pdev->dev)) 96 mmc_gpio_set_cd_wake(host->mmc, true); 97 } 98 99 return 0; 100 101 err_pci_suspend: 102 while (--i >= 0) 103 sdhci_resume_host(chip->slots[i]->host); 104 return ret; 105 } 106 107 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 108 { 109 struct sdhci_pci_slot *slot; 110 int i, ret; 111 112 for (i = 0; i < chip->num_slots; i++) { 113 slot = chip->slots[i]; 114 if (!slot) 115 continue; 116 117 ret = sdhci_resume_host(slot->host); 118 if (ret) 119 return ret; 120 121 mmc_gpio_set_cd_wake(slot->host->mmc, false); 122 } 123 124 return 0; 125 } 126 127 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip) 128 { 129 int ret; 130 131 ret = cqhci_suspend(chip->slots[0]->host->mmc); 132 if (ret) 133 return ret; 134 135 return sdhci_pci_suspend_host(chip); 136 } 137 138 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip) 139 { 140 int ret; 141 142 ret = sdhci_pci_resume_host(chip); 143 if (ret) 144 return ret; 145 146 return cqhci_resume(chip->slots[0]->host->mmc); 147 } 148 #endif 149 150 #ifdef CONFIG_PM 151 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 152 { 153 struct sdhci_pci_slot *slot; 154 struct sdhci_host *host; 155 int i, ret; 156 157 for (i = 0; i < chip->num_slots; i++) { 158 slot = chip->slots[i]; 159 if (!slot) 160 continue; 161 162 host = slot->host; 163 164 ret = sdhci_runtime_suspend_host(host); 165 if (ret) 166 goto err_pci_runtime_suspend; 167 168 if (chip->rpm_retune && 169 host->tuning_mode != SDHCI_TUNING_MODE_3) 170 mmc_retune_needed(host->mmc); 171 } 172 173 return 0; 174 175 err_pci_runtime_suspend: 176 while (--i >= 0) 177 sdhci_runtime_resume_host(chip->slots[i]->host, 0); 178 return ret; 179 } 180 181 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 182 { 183 struct sdhci_pci_slot *slot; 184 int i, ret; 185 186 for (i = 0; i < chip->num_slots; i++) { 187 slot = chip->slots[i]; 188 if (!slot) 189 continue; 190 191 ret = sdhci_runtime_resume_host(slot->host, 0); 192 if (ret) 193 return ret; 194 } 195 196 return 0; 197 } 198 199 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip) 200 { 201 int ret; 202 203 ret = cqhci_suspend(chip->slots[0]->host->mmc); 204 if (ret) 205 return ret; 206 207 return sdhci_pci_runtime_suspend_host(chip); 208 } 209 210 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip) 211 { 212 int ret; 213 214 ret = sdhci_pci_runtime_resume_host(chip); 215 if (ret) 216 return ret; 217 218 return cqhci_resume(chip->slots[0]->host->mmc); 219 } 220 #endif 221 222 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask) 223 { 224 int cmd_error = 0; 225 int data_error = 0; 226 227 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 228 return intmask; 229 230 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 231 232 return 0; 233 } 234 235 static void sdhci_pci_dumpregs(struct mmc_host *mmc) 236 { 237 sdhci_dumpregs(mmc_priv(mmc)); 238 } 239 240 /*****************************************************************************\ 241 * * 242 * Hardware specific quirk handling * 243 * * 244 \*****************************************************************************/ 245 246 static int ricoh_probe(struct sdhci_pci_chip *chip) 247 { 248 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 249 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 250 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 251 return 0; 252 } 253 254 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 255 { 256 u32 caps = 257 FIELD_PREP(SDHCI_TIMEOUT_CLK_MASK, 0x21) | 258 FIELD_PREP(SDHCI_CLOCK_BASE_MASK, 0x21) | 259 SDHCI_TIMEOUT_CLK_UNIT | 260 SDHCI_CAN_VDD_330 | 261 SDHCI_CAN_DO_HISPD | 262 SDHCI_CAN_DO_SDMA; 263 u32 caps1 = 0; 264 265 __sdhci_read_caps(slot->host, NULL, &caps, &caps1); 266 return 0; 267 } 268 269 #ifdef CONFIG_PM_SLEEP 270 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 271 { 272 /* Apply a delay to allow controller to settle */ 273 /* Otherwise it becomes confused if card state changed 274 during suspend */ 275 msleep(500); 276 return sdhci_pci_resume_host(chip); 277 } 278 #endif 279 280 static const struct sdhci_pci_fixes sdhci_ricoh = { 281 .probe = ricoh_probe, 282 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 283 SDHCI_QUIRK_FORCE_DMA | 284 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 285 }; 286 287 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 288 .probe_slot = ricoh_mmc_probe_slot, 289 #ifdef CONFIG_PM_SLEEP 290 .resume = ricoh_mmc_resume, 291 #endif 292 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 293 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 294 SDHCI_QUIRK_NO_CARD_NO_RESET, 295 }; 296 297 static void ene_714_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 298 { 299 struct sdhci_host *host = mmc_priv(mmc); 300 301 sdhci_set_ios(mmc, ios); 302 303 /* 304 * Some (ENE) controllers misbehave on some ios operations, 305 * signalling timeout and CRC errors even on CMD0. Resetting 306 * it on each ios seems to solve the problem. 307 */ 308 if (!(host->flags & SDHCI_DEVICE_DEAD)) 309 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 310 } 311 312 static int ene_714_probe_slot(struct sdhci_pci_slot *slot) 313 { 314 slot->host->mmc_host_ops.set_ios = ene_714_set_ios; 315 return 0; 316 } 317 318 static const struct sdhci_pci_fixes sdhci_ene_712 = { 319 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 320 SDHCI_QUIRK_BROKEN_DMA, 321 }; 322 323 static const struct sdhci_pci_fixes sdhci_ene_714 = { 324 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 325 SDHCI_QUIRK_BROKEN_DMA, 326 .probe_slot = ene_714_probe_slot, 327 }; 328 329 static const struct sdhci_pci_fixes sdhci_cafe = { 330 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 331 SDHCI_QUIRK_NO_BUSY_IRQ | 332 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 333 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 334 }; 335 336 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 337 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 338 }; 339 340 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 341 { 342 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 343 return 0; 344 } 345 346 /* 347 * ADMA operation is disabled for Moorestown platform due to 348 * hardware bugs. 349 */ 350 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 351 { 352 /* 353 * slots number is fixed here for MRST as SDIO3/5 are never used and 354 * have hardware bugs. 355 */ 356 chip->num_slots = 1; 357 return 0; 358 } 359 360 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 361 { 362 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 363 return 0; 364 } 365 366 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 367 { 368 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 369 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; 370 return 0; 371 } 372 373 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 374 { 375 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 376 return 0; 377 } 378 379 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 380 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 381 .probe_slot = mrst_hc_probe_slot, 382 }; 383 384 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 385 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 386 .probe = mrst_hc_probe, 387 }; 388 389 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 390 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 391 .allow_runtime_pm = true, 392 .own_cd_for_runtime_pm = true, 393 }; 394 395 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 396 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 397 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 398 .allow_runtime_pm = true, 399 .probe_slot = mfd_sdio_probe_slot, 400 }; 401 402 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 403 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 404 .allow_runtime_pm = true, 405 .probe_slot = mfd_emmc_probe_slot, 406 }; 407 408 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 409 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 410 .probe_slot = pch_hc_probe_slot, 411 }; 412 413 #ifdef CONFIG_X86 414 415 #define BYT_IOSF_SCCEP 0x63 416 #define BYT_IOSF_OCP_NETCTRL0 0x1078 417 #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8) 418 419 static void byt_ocp_setting(struct pci_dev *pdev) 420 { 421 u32 val = 0; 422 423 if (pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC && 424 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SDIO && 425 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SD && 426 pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC2) 427 return; 428 429 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0, 430 &val)) { 431 dev_err(&pdev->dev, "%s read error\n", __func__); 432 return; 433 } 434 435 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE)) 436 return; 437 438 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE; 439 440 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0, 441 val)) { 442 dev_err(&pdev->dev, "%s write error\n", __func__); 443 return; 444 } 445 446 dev_dbg(&pdev->dev, "%s completed\n", __func__); 447 } 448 449 #else 450 451 static inline void byt_ocp_setting(struct pci_dev *pdev) 452 { 453 } 454 455 #endif 456 457 enum { 458 INTEL_DSM_FNS = 0, 459 INTEL_DSM_V18_SWITCH = 3, 460 INTEL_DSM_V33_SWITCH = 4, 461 INTEL_DSM_DRV_STRENGTH = 9, 462 INTEL_DSM_D3_RETUNE = 10, 463 }; 464 465 struct intel_host { 466 u32 dsm_fns; 467 int drv_strength; 468 bool d3_retune; 469 bool rpm_retune_ok; 470 bool needs_pwr_off; 471 u32 glk_rx_ctrl1; 472 u32 glk_tun_val; 473 u32 active_ltr; 474 u32 idle_ltr; 475 }; 476 477 static const guid_t intel_dsm_guid = 478 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 479 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 480 481 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 482 unsigned int fn, u32 *result) 483 { 484 union acpi_object *obj; 485 int err = 0; 486 size_t len; 487 488 obj = acpi_evaluate_dsm_typed(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL, 489 ACPI_TYPE_BUFFER); 490 if (!obj) 491 return -EOPNOTSUPP; 492 493 if (obj->buffer.length < 1) { 494 err = -EINVAL; 495 goto out; 496 } 497 498 len = min_t(size_t, obj->buffer.length, 4); 499 500 *result = 0; 501 memcpy(result, obj->buffer.pointer, len); 502 out: 503 ACPI_FREE(obj); 504 505 return err; 506 } 507 508 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 509 unsigned int fn, u32 *result) 510 { 511 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 512 return -EOPNOTSUPP; 513 514 return __intel_dsm(intel_host, dev, fn, result); 515 } 516 517 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 518 struct mmc_host *mmc) 519 { 520 int err; 521 u32 val; 522 523 intel_host->d3_retune = true; 524 525 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 526 if (err) { 527 pr_debug("%s: DSM not supported, error %d\n", 528 mmc_hostname(mmc), err); 529 return; 530 } 531 532 pr_debug("%s: DSM function mask %#x\n", 533 mmc_hostname(mmc), intel_host->dsm_fns); 534 535 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 536 intel_host->drv_strength = err ? 0 : val; 537 538 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 539 intel_host->d3_retune = err ? true : !!val; 540 } 541 542 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 543 { 544 u8 reg; 545 546 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 547 reg |= 0x10; 548 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 549 /* For eMMC, minimum is 1us but give it 9us for good measure */ 550 udelay(9); 551 reg &= ~0x10; 552 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 553 /* For eMMC, minimum is 200us but give it 300us for good measure */ 554 usleep_range(300, 1000); 555 } 556 557 static int intel_select_drive_strength(struct mmc_card *card, 558 unsigned int max_dtr, int host_drv, 559 int card_drv, int *drv_type) 560 { 561 struct sdhci_host *host = mmc_priv(card->host); 562 struct sdhci_pci_slot *slot = sdhci_priv(host); 563 struct intel_host *intel_host = sdhci_pci_priv(slot); 564 565 if (!(mmc_driver_type_mask(intel_host->drv_strength) & card_drv)) 566 return 0; 567 568 return intel_host->drv_strength; 569 } 570 571 static int bxt_get_cd(struct mmc_host *mmc) 572 { 573 int gpio_cd = mmc_gpio_get_cd(mmc); 574 575 if (!gpio_cd) 576 return 0; 577 578 return sdhci_get_cd_nogpio(mmc); 579 } 580 581 static int mrfld_get_cd(struct mmc_host *mmc) 582 { 583 return sdhci_get_cd_nogpio(mmc); 584 } 585 586 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 587 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 588 589 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 590 unsigned short vdd) 591 { 592 struct sdhci_pci_slot *slot = sdhci_priv(host); 593 struct intel_host *intel_host = sdhci_pci_priv(slot); 594 int cntr; 595 u8 reg; 596 597 /* 598 * Bus power may control card power, but a full reset still may not 599 * reset the power, whereas a direct write to SDHCI_POWER_CONTROL can. 600 * That might be needed to initialize correctly, if the card was left 601 * powered on previously. 602 */ 603 if (intel_host->needs_pwr_off) { 604 intel_host->needs_pwr_off = false; 605 if (mode != MMC_POWER_OFF) { 606 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 607 usleep_range(10000, 12500); 608 } 609 } 610 611 sdhci_set_power(host, mode, vdd); 612 613 if (mode == MMC_POWER_OFF) { 614 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 615 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BYT_SD) 616 usleep_range(15000, 17500); 617 return; 618 } 619 620 /* 621 * Bus power might not enable after D3 -> D0 transition due to the 622 * present state not yet having propagated. Retry for up to 2ms. 623 */ 624 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 625 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 626 if (reg & SDHCI_POWER_ON) 627 break; 628 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 629 reg |= SDHCI_POWER_ON; 630 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 631 } 632 } 633 634 static void sdhci_intel_set_uhs_signaling(struct sdhci_host *host, 635 unsigned int timing) 636 { 637 /* Set UHS timing to SDR25 for High Speed mode */ 638 if (timing == MMC_TIMING_MMC_HS || timing == MMC_TIMING_SD_HS) 639 timing = MMC_TIMING_UHS_SDR25; 640 sdhci_set_uhs_signaling(host, timing); 641 } 642 643 #define INTEL_HS400_ES_REG 0x78 644 #define INTEL_HS400_ES_BIT BIT(0) 645 646 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, 647 struct mmc_ios *ios) 648 { 649 struct sdhci_host *host = mmc_priv(mmc); 650 u32 val; 651 652 val = sdhci_readl(host, INTEL_HS400_ES_REG); 653 if (ios->enhanced_strobe) 654 val |= INTEL_HS400_ES_BIT; 655 else 656 val &= ~INTEL_HS400_ES_BIT; 657 sdhci_writel(host, val, INTEL_HS400_ES_REG); 658 } 659 660 static int intel_start_signal_voltage_switch(struct mmc_host *mmc, 661 struct mmc_ios *ios) 662 { 663 struct device *dev = mmc_dev(mmc); 664 struct sdhci_host *host = mmc_priv(mmc); 665 struct sdhci_pci_slot *slot = sdhci_priv(host); 666 struct intel_host *intel_host = sdhci_pci_priv(slot); 667 unsigned int fn; 668 u32 result = 0; 669 int err; 670 671 err = sdhci_start_signal_voltage_switch(mmc, ios); 672 if (err) 673 return err; 674 675 switch (ios->signal_voltage) { 676 case MMC_SIGNAL_VOLTAGE_330: 677 fn = INTEL_DSM_V33_SWITCH; 678 break; 679 case MMC_SIGNAL_VOLTAGE_180: 680 fn = INTEL_DSM_V18_SWITCH; 681 break; 682 default: 683 return 0; 684 } 685 686 err = intel_dsm(intel_host, dev, fn, &result); 687 pr_debug("%s: %s DSM fn %u error %d result %u\n", 688 mmc_hostname(mmc), __func__, fn, err, result); 689 690 return 0; 691 } 692 693 static const struct sdhci_ops sdhci_intel_byt_ops = { 694 .set_clock = sdhci_set_clock, 695 .set_power = sdhci_intel_set_power, 696 .enable_dma = sdhci_pci_enable_dma, 697 .set_bus_width = sdhci_set_bus_width, 698 .reset = sdhci_reset, 699 .set_uhs_signaling = sdhci_intel_set_uhs_signaling, 700 .hw_reset = sdhci_pci_hw_reset, 701 }; 702 703 static const struct sdhci_ops sdhci_intel_glk_ops = { 704 .set_clock = sdhci_set_clock, 705 .set_power = sdhci_intel_set_power, 706 .enable_dma = sdhci_pci_enable_dma, 707 .set_bus_width = sdhci_set_bus_width, 708 .reset = sdhci_and_cqhci_reset, 709 .set_uhs_signaling = sdhci_intel_set_uhs_signaling, 710 .hw_reset = sdhci_pci_hw_reset, 711 .irq = sdhci_cqhci_irq, 712 }; 713 714 static void byt_read_dsm(struct sdhci_pci_slot *slot) 715 { 716 struct intel_host *intel_host = sdhci_pci_priv(slot); 717 struct device *dev = &slot->chip->pdev->dev; 718 struct mmc_host *mmc = slot->host->mmc; 719 720 intel_dsm_init(intel_host, dev, mmc); 721 slot->chip->rpm_retune = intel_host->d3_retune; 722 } 723 724 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode) 725 { 726 int err = sdhci_execute_tuning(mmc, opcode); 727 struct sdhci_host *host = mmc_priv(mmc); 728 729 if (err) 730 return err; 731 732 /* 733 * Tuning can leave the IP in an active state (Buffer Read Enable bit 734 * set) which prevents the entry to low power states (i.e. S0i3). Data 735 * reset will clear it. 736 */ 737 sdhci_reset(host, SDHCI_RESET_DATA); 738 739 return 0; 740 } 741 742 #define INTEL_ACTIVELTR 0x804 743 #define INTEL_IDLELTR 0x808 744 745 #define INTEL_LTR_REQ BIT(15) 746 #define INTEL_LTR_SCALE_MASK GENMASK(11, 10) 747 #define INTEL_LTR_SCALE_1US (2 << 10) 748 #define INTEL_LTR_SCALE_32US (3 << 10) 749 #define INTEL_LTR_VALUE_MASK GENMASK(9, 0) 750 751 static void intel_cache_ltr(struct sdhci_pci_slot *slot) 752 { 753 struct intel_host *intel_host = sdhci_pci_priv(slot); 754 struct sdhci_host *host = slot->host; 755 756 intel_host->active_ltr = readl(host->ioaddr + INTEL_ACTIVELTR); 757 intel_host->idle_ltr = readl(host->ioaddr + INTEL_IDLELTR); 758 } 759 760 static void intel_ltr_set(struct device *dev, s32 val) 761 { 762 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 763 struct sdhci_pci_slot *slot = chip->slots[0]; 764 struct intel_host *intel_host = sdhci_pci_priv(slot); 765 struct sdhci_host *host = slot->host; 766 u32 ltr; 767 768 pm_runtime_get_sync(dev); 769 770 /* 771 * Program latency tolerance (LTR) accordingly what has been asked 772 * by the PM QoS layer or disable it in case we were passed 773 * negative value or PM_QOS_LATENCY_ANY. 774 */ 775 ltr = readl(host->ioaddr + INTEL_ACTIVELTR); 776 777 if (val == PM_QOS_LATENCY_ANY || val < 0) { 778 ltr &= ~INTEL_LTR_REQ; 779 } else { 780 ltr |= INTEL_LTR_REQ; 781 ltr &= ~INTEL_LTR_SCALE_MASK; 782 ltr &= ~INTEL_LTR_VALUE_MASK; 783 784 if (val > INTEL_LTR_VALUE_MASK) { 785 val >>= 5; 786 if (val > INTEL_LTR_VALUE_MASK) 787 val = INTEL_LTR_VALUE_MASK; 788 ltr |= INTEL_LTR_SCALE_32US | val; 789 } else { 790 ltr |= INTEL_LTR_SCALE_1US | val; 791 } 792 } 793 794 if (ltr == intel_host->active_ltr) 795 goto out; 796 797 writel(ltr, host->ioaddr + INTEL_ACTIVELTR); 798 writel(ltr, host->ioaddr + INTEL_IDLELTR); 799 800 /* Cache the values into lpss structure */ 801 intel_cache_ltr(slot); 802 out: 803 pm_runtime_put_autosuspend(dev); 804 } 805 806 static bool intel_use_ltr(struct sdhci_pci_chip *chip) 807 { 808 switch (chip->pdev->device) { 809 case PCI_DEVICE_ID_INTEL_BYT_EMMC: 810 case PCI_DEVICE_ID_INTEL_BYT_EMMC2: 811 case PCI_DEVICE_ID_INTEL_BYT_SDIO: 812 case PCI_DEVICE_ID_INTEL_BYT_SD: 813 case PCI_DEVICE_ID_INTEL_BSW_EMMC: 814 case PCI_DEVICE_ID_INTEL_BSW_SDIO: 815 case PCI_DEVICE_ID_INTEL_BSW_SD: 816 return false; 817 default: 818 return true; 819 } 820 } 821 822 static void intel_ltr_expose(struct sdhci_pci_chip *chip) 823 { 824 struct device *dev = &chip->pdev->dev; 825 826 if (!intel_use_ltr(chip)) 827 return; 828 829 dev->power.set_latency_tolerance = intel_ltr_set; 830 dev_pm_qos_expose_latency_tolerance(dev); 831 } 832 833 static void intel_ltr_hide(struct sdhci_pci_chip *chip) 834 { 835 struct device *dev = &chip->pdev->dev; 836 837 if (!intel_use_ltr(chip)) 838 return; 839 840 dev_pm_qos_hide_latency_tolerance(dev); 841 dev->power.set_latency_tolerance = NULL; 842 } 843 844 static void byt_probe_slot(struct sdhci_pci_slot *slot) 845 { 846 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 847 struct device *dev = &slot->chip->pdev->dev; 848 struct mmc_host *mmc = slot->host->mmc; 849 850 byt_read_dsm(slot); 851 852 byt_ocp_setting(slot->chip->pdev); 853 854 ops->execute_tuning = intel_execute_tuning; 855 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch; 856 857 device_property_read_u32(dev, "max-frequency", &mmc->f_max); 858 859 if (!mmc->slotno) { 860 slot->chip->slots[mmc->slotno] = slot; 861 intel_ltr_expose(slot->chip); 862 } 863 } 864 865 static void byt_add_debugfs(struct sdhci_pci_slot *slot) 866 { 867 struct intel_host *intel_host = sdhci_pci_priv(slot); 868 struct mmc_host *mmc = slot->host->mmc; 869 struct dentry *dir = mmc->debugfs_root; 870 871 if (!intel_use_ltr(slot->chip)) 872 return; 873 874 debugfs_create_x32("active_ltr", 0444, dir, &intel_host->active_ltr); 875 debugfs_create_x32("idle_ltr", 0444, dir, &intel_host->idle_ltr); 876 877 intel_cache_ltr(slot); 878 } 879 880 static int byt_add_host(struct sdhci_pci_slot *slot) 881 { 882 int ret = sdhci_add_host(slot->host); 883 884 if (!ret) 885 byt_add_debugfs(slot); 886 return ret; 887 } 888 889 static void byt_remove_slot(struct sdhci_pci_slot *slot, int dead) 890 { 891 struct mmc_host *mmc = slot->host->mmc; 892 893 if (!mmc->slotno) 894 intel_ltr_hide(slot->chip); 895 } 896 897 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 898 { 899 byt_probe_slot(slot); 900 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 901 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 902 MMC_CAP_CMD_DURING_TFR | 903 MMC_CAP_WAIT_WHILE_BUSY; 904 slot->hw_reset = sdhci_pci_int_hw_reset; 905 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 906 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 907 slot->host->mmc_host_ops.select_drive_strength = 908 intel_select_drive_strength; 909 return 0; 910 } 911 912 static bool glk_broken_cqhci(struct sdhci_pci_slot *slot) 913 { 914 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 915 (dmi_match(DMI_BIOS_VENDOR, "LENOVO") || 916 dmi_match(DMI_SYS_VENDOR, "IRBIS")); 917 } 918 919 static bool jsl_broken_hs400es(struct sdhci_pci_slot *slot) 920 { 921 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_JSL_EMMC && 922 dmi_match(DMI_BIOS_VENDOR, "ASUSTeK COMPUTER INC."); 923 } 924 925 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) 926 { 927 int ret = byt_emmc_probe_slot(slot); 928 929 if (!glk_broken_cqhci(slot)) 930 slot->host->mmc->caps2 |= MMC_CAP2_CQE; 931 932 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { 933 if (!jsl_broken_hs400es(slot)) { 934 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES; 935 slot->host->mmc_host_ops.hs400_enhanced_strobe = 936 intel_hs400_enhanced_strobe; 937 } 938 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; 939 } 940 941 return ret; 942 } 943 944 static const struct cqhci_host_ops glk_cqhci_ops = { 945 .enable = sdhci_cqe_enable, 946 .disable = sdhci_cqe_disable, 947 .dumpregs = sdhci_pci_dumpregs, 948 }; 949 950 static int glk_emmc_add_host(struct sdhci_pci_slot *slot) 951 { 952 struct device *dev = &slot->chip->pdev->dev; 953 struct sdhci_host *host = slot->host; 954 struct cqhci_host *cq_host; 955 bool dma64; 956 int ret; 957 958 ret = sdhci_setup_host(host); 959 if (ret) 960 return ret; 961 962 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 963 if (!cq_host) { 964 ret = -ENOMEM; 965 goto cleanup; 966 } 967 968 cq_host->mmio = host->ioaddr + 0x200; 969 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 970 cq_host->ops = &glk_cqhci_ops; 971 972 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 973 if (dma64) 974 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 975 976 ret = cqhci_init(cq_host, host->mmc, dma64); 977 if (ret) 978 goto cleanup; 979 980 ret = __sdhci_add_host(host); 981 if (ret) 982 goto cleanup; 983 984 byt_add_debugfs(slot); 985 986 return 0; 987 988 cleanup: 989 sdhci_cleanup_host(host); 990 return ret; 991 } 992 993 #ifdef CONFIG_PM 994 #define GLK_RX_CTRL1 0x834 995 #define GLK_TUN_VAL 0x840 996 #define GLK_PATH_PLL GENMASK(13, 8) 997 #define GLK_DLY GENMASK(6, 0) 998 /* Workaround firmware failing to restore the tuning value */ 999 static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp) 1000 { 1001 struct sdhci_pci_slot *slot = chip->slots[0]; 1002 struct intel_host *intel_host = sdhci_pci_priv(slot); 1003 struct sdhci_host *host = slot->host; 1004 u32 glk_rx_ctrl1; 1005 u32 glk_tun_val; 1006 u32 dly; 1007 1008 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc)) 1009 return; 1010 1011 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1); 1012 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL); 1013 1014 if (susp) { 1015 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1; 1016 intel_host->glk_tun_val = glk_tun_val; 1017 return; 1018 } 1019 1020 if (!intel_host->glk_tun_val) 1021 return; 1022 1023 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) { 1024 intel_host->rpm_retune_ok = true; 1025 return; 1026 } 1027 1028 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) + 1029 (intel_host->glk_tun_val << 1)); 1030 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1)) 1031 return; 1032 1033 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly; 1034 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1); 1035 1036 intel_host->rpm_retune_ok = true; 1037 chip->rpm_retune = true; 1038 mmc_retune_needed(host->mmc); 1039 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc)); 1040 } 1041 1042 static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp) 1043 { 1044 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 1045 !chip->rpm_retune) 1046 glk_rpm_retune_wa(chip, susp); 1047 } 1048 1049 static int glk_runtime_suspend(struct sdhci_pci_chip *chip) 1050 { 1051 glk_rpm_retune_chk(chip, true); 1052 1053 return sdhci_cqhci_runtime_suspend(chip); 1054 } 1055 1056 static int glk_runtime_resume(struct sdhci_pci_chip *chip) 1057 { 1058 glk_rpm_retune_chk(chip, false); 1059 1060 return sdhci_cqhci_runtime_resume(chip); 1061 } 1062 #endif 1063 1064 #ifdef CONFIG_ACPI 1065 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 1066 { 1067 acpi_status status; 1068 unsigned long long max_freq; 1069 1070 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 1071 "MXFQ", NULL, &max_freq); 1072 if (ACPI_FAILURE(status)) { 1073 dev_err(&slot->chip->pdev->dev, 1074 "MXFQ not found in acpi table\n"); 1075 return -EINVAL; 1076 } 1077 1078 slot->host->mmc->f_max = max_freq * 1000000; 1079 1080 return 0; 1081 } 1082 #else 1083 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 1084 { 1085 return 0; 1086 } 1087 #endif 1088 1089 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 1090 { 1091 int err; 1092 1093 byt_probe_slot(slot); 1094 1095 err = ni_set_max_freq(slot); 1096 if (err) 1097 return err; 1098 1099 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 1100 MMC_CAP_WAIT_WHILE_BUSY; 1101 return 0; 1102 } 1103 1104 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 1105 { 1106 byt_probe_slot(slot); 1107 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 1108 MMC_CAP_WAIT_WHILE_BUSY; 1109 return 0; 1110 } 1111 1112 static void byt_needs_pwr_off(struct sdhci_pci_slot *slot) 1113 { 1114 struct intel_host *intel_host = sdhci_pci_priv(slot); 1115 u8 reg = sdhci_readb(slot->host, SDHCI_POWER_CONTROL); 1116 1117 intel_host->needs_pwr_off = reg & SDHCI_POWER_ON; 1118 } 1119 1120 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 1121 { 1122 byt_probe_slot(slot); 1123 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | 1124 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE; 1125 slot->cd_idx = 0; 1126 slot->cd_override_level = true; 1127 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 1128 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 1129 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 1130 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) 1131 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 1132 1133 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI && 1134 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3) 1135 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V; 1136 1137 byt_needs_pwr_off(slot); 1138 1139 return 0; 1140 } 1141 1142 #ifdef CONFIG_PM_SLEEP 1143 1144 static int byt_resume(struct sdhci_pci_chip *chip) 1145 { 1146 byt_ocp_setting(chip->pdev); 1147 1148 return sdhci_pci_resume_host(chip); 1149 } 1150 1151 #endif 1152 1153 #ifdef CONFIG_PM 1154 1155 static int byt_runtime_resume(struct sdhci_pci_chip *chip) 1156 { 1157 byt_ocp_setting(chip->pdev); 1158 1159 return sdhci_pci_runtime_resume_host(chip); 1160 } 1161 1162 #endif 1163 1164 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 1165 #ifdef CONFIG_PM_SLEEP 1166 .resume = byt_resume, 1167 #endif 1168 #ifdef CONFIG_PM 1169 .runtime_resume = byt_runtime_resume, 1170 #endif 1171 .allow_runtime_pm = true, 1172 .probe_slot = byt_emmc_probe_slot, 1173 .add_host = byt_add_host, 1174 .remove_slot = byt_remove_slot, 1175 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1176 SDHCI_QUIRK_NO_LED, 1177 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1178 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1179 SDHCI_QUIRK2_STOP_WITH_TC, 1180 .ops = &sdhci_intel_byt_ops, 1181 .priv_size = sizeof(struct intel_host), 1182 }; 1183 1184 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { 1185 .allow_runtime_pm = true, 1186 .probe_slot = glk_emmc_probe_slot, 1187 .add_host = glk_emmc_add_host, 1188 .remove_slot = byt_remove_slot, 1189 #ifdef CONFIG_PM_SLEEP 1190 .suspend = sdhci_cqhci_suspend, 1191 .resume = sdhci_cqhci_resume, 1192 #endif 1193 #ifdef CONFIG_PM 1194 .runtime_suspend = glk_runtime_suspend, 1195 .runtime_resume = glk_runtime_resume, 1196 #endif 1197 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1198 SDHCI_QUIRK_NO_LED, 1199 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1200 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1201 SDHCI_QUIRK2_STOP_WITH_TC, 1202 .ops = &sdhci_intel_glk_ops, 1203 .priv_size = sizeof(struct intel_host), 1204 }; 1205 1206 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 1207 #ifdef CONFIG_PM_SLEEP 1208 .resume = byt_resume, 1209 #endif 1210 #ifdef CONFIG_PM 1211 .runtime_resume = byt_runtime_resume, 1212 #endif 1213 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1214 SDHCI_QUIRK_NO_LED, 1215 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1216 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1217 .allow_runtime_pm = true, 1218 .probe_slot = ni_byt_sdio_probe_slot, 1219 .add_host = byt_add_host, 1220 .remove_slot = byt_remove_slot, 1221 .ops = &sdhci_intel_byt_ops, 1222 .priv_size = sizeof(struct intel_host), 1223 }; 1224 1225 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 1226 #ifdef CONFIG_PM_SLEEP 1227 .resume = byt_resume, 1228 #endif 1229 #ifdef CONFIG_PM 1230 .runtime_resume = byt_runtime_resume, 1231 #endif 1232 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1233 SDHCI_QUIRK_NO_LED, 1234 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1235 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1236 .allow_runtime_pm = true, 1237 .probe_slot = byt_sdio_probe_slot, 1238 .add_host = byt_add_host, 1239 .remove_slot = byt_remove_slot, 1240 .ops = &sdhci_intel_byt_ops, 1241 .priv_size = sizeof(struct intel_host), 1242 }; 1243 1244 /* DMI quirks for devices with missing or broken CD GPIO info */ 1245 static const struct gpiod_lookup_table vexia_edu_atla10_cd_gpios = { 1246 .dev_id = "0000:00:12.0", 1247 .table = { 1248 GPIO_LOOKUP("INT33FC:00", 38, "cd", GPIO_ACTIVE_HIGH), 1249 { } 1250 }, 1251 }; 1252 1253 static const struct dmi_system_id sdhci_intel_byt_cd_gpio_override[] = { 1254 { 1255 /* Vexia Edu Atla 10 tablet 9V version */ 1256 .matches = { 1257 DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"), 1258 DMI_MATCH(DMI_BOARD_NAME, "Aptio CRB"), 1259 /* Above strings are too generic, also match on BIOS date */ 1260 DMI_MATCH(DMI_BIOS_DATE, "08/25/2014"), 1261 }, 1262 .driver_data = (void *)&vexia_edu_atla10_cd_gpios, 1263 }, 1264 { } 1265 }; 1266 1267 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 1268 #ifdef CONFIG_PM_SLEEP 1269 .resume = byt_resume, 1270 #endif 1271 #ifdef CONFIG_PM 1272 .runtime_resume = byt_runtime_resume, 1273 #endif 1274 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1275 SDHCI_QUIRK_NO_LED, 1276 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 1277 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1278 SDHCI_QUIRK2_STOP_WITH_TC, 1279 .allow_runtime_pm = true, 1280 .own_cd_for_runtime_pm = true, 1281 .probe_slot = byt_sd_probe_slot, 1282 .add_host = byt_add_host, 1283 .remove_slot = byt_remove_slot, 1284 .ops = &sdhci_intel_byt_ops, 1285 .cd_gpio_override = sdhci_intel_byt_cd_gpio_override, 1286 .priv_size = sizeof(struct intel_host), 1287 }; 1288 1289 /* Define Host controllers for Intel Merrifield platform */ 1290 #define INTEL_MRFLD_EMMC_0 0 1291 #define INTEL_MRFLD_EMMC_1 1 1292 #define INTEL_MRFLD_SD 2 1293 #define INTEL_MRFLD_SDIO 3 1294 1295 #ifdef CONFIG_ACPI 1296 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) 1297 { 1298 struct acpi_device *device; 1299 1300 device = ACPI_COMPANION(&slot->chip->pdev->dev); 1301 if (device) 1302 acpi_device_fix_up_power_extended(device); 1303 } 1304 #else 1305 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {} 1306 #endif 1307 1308 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 1309 { 1310 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 1311 1312 switch (func) { 1313 case INTEL_MRFLD_EMMC_0: 1314 case INTEL_MRFLD_EMMC_1: 1315 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1316 MMC_CAP_8_BIT_DATA | 1317 MMC_CAP_1_8V_DDR; 1318 break; 1319 case INTEL_MRFLD_SD: 1320 slot->cd_idx = 0; 1321 slot->cd_override_level = true; 1322 /* 1323 * There are two PCB designs of SD card slot with the opposite 1324 * card detection sense. Quirk this out by ignoring GPIO state 1325 * completely in the custom ->get_cd() callback. 1326 */ 1327 slot->host->mmc_host_ops.get_cd = mrfld_get_cd; 1328 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1329 break; 1330 case INTEL_MRFLD_SDIO: 1331 /* Advertise 2.0v for compatibility with the SDIO card's OCR */ 1332 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195; 1333 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1334 MMC_CAP_POWER_OFF_CARD; 1335 break; 1336 default: 1337 return -ENODEV; 1338 } 1339 1340 intel_mrfld_mmc_fix_up_power_slot(slot); 1341 return 0; 1342 } 1343 1344 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 1345 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1346 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 1347 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1348 .allow_runtime_pm = true, 1349 .probe_slot = intel_mrfld_mmc_probe_slot, 1350 }; 1351 1352 #define JMB388_SAMPLE_COUNT 5 1353 1354 static int jmicron_jmb388_get_ro(struct mmc_host *mmc) 1355 { 1356 int i, ro_count; 1357 1358 ro_count = 0; 1359 for (i = 0; i < JMB388_SAMPLE_COUNT; i++) { 1360 if (sdhci_get_ro(mmc) > 0) { 1361 if (++ro_count > JMB388_SAMPLE_COUNT / 2) 1362 return 1; 1363 } 1364 msleep(30); 1365 } 1366 return 0; 1367 } 1368 1369 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 1370 { 1371 u8 scratch; 1372 int ret; 1373 1374 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 1375 if (ret) 1376 goto fail; 1377 1378 /* 1379 * Turn PMOS on [bit 0], set over current detection to 2.4 V 1380 * [bit 1:2] and enable over current debouncing [bit 6]. 1381 */ 1382 if (on) 1383 scratch |= 0x47; 1384 else 1385 scratch &= ~0x47; 1386 1387 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch); 1388 1389 fail: 1390 return pcibios_err_to_errno(ret); 1391 } 1392 1393 static int jmicron_probe(struct sdhci_pci_chip *chip) 1394 { 1395 int ret; 1396 u16 mmcdev = 0; 1397 1398 if (chip->pdev->revision == 0) { 1399 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 1400 SDHCI_QUIRK_32BIT_DMA_SIZE | 1401 SDHCI_QUIRK_32BIT_ADMA_SIZE | 1402 SDHCI_QUIRK_RESET_AFTER_REQUEST | 1403 SDHCI_QUIRK_BROKEN_SMALL_PIO; 1404 } 1405 1406 /* 1407 * JMicron chips can have two interfaces to the same hardware 1408 * in order to work around limitations in Microsoft's driver. 1409 * We need to make sure we only bind to one of them. 1410 * 1411 * This code assumes two things: 1412 * 1413 * 1. The PCI code adds subfunctions in order. 1414 * 1415 * 2. The MMC interface has a lower subfunction number 1416 * than the SD interface. 1417 */ 1418 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 1419 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 1420 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 1421 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 1422 1423 if (mmcdev) { 1424 struct pci_dev *sd_dev; 1425 1426 sd_dev = NULL; 1427 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 1428 mmcdev, sd_dev)) != NULL) { 1429 if ((PCI_SLOT(chip->pdev->devfn) == 1430 PCI_SLOT(sd_dev->devfn)) && 1431 (chip->pdev->bus == sd_dev->bus)) 1432 break; 1433 } 1434 1435 if (sd_dev) { 1436 pci_dev_put(sd_dev); 1437 dev_info(&chip->pdev->dev, "Refusing to bind to " 1438 "secondary interface.\n"); 1439 return -ENODEV; 1440 } 1441 } 1442 1443 /* 1444 * JMicron chips need a bit of a nudge to enable the power 1445 * output pins. 1446 */ 1447 ret = jmicron_pmos(chip, 1); 1448 if (ret) { 1449 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1450 return ret; 1451 } 1452 1453 return 0; 1454 } 1455 1456 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 1457 { 1458 u8 scratch; 1459 1460 scratch = readb(host->ioaddr + 0xC0); 1461 1462 if (on) 1463 scratch |= 0x01; 1464 else 1465 scratch &= ~0x01; 1466 1467 writeb(scratch, host->ioaddr + 0xC0); 1468 } 1469 1470 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 1471 { 1472 if (slot->chip->pdev->revision == 0) { 1473 u16 version; 1474 1475 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 1476 version = (version & SDHCI_VENDOR_VER_MASK) >> 1477 SDHCI_VENDOR_VER_SHIFT; 1478 1479 /* 1480 * Older versions of the chip have lots of nasty glitches 1481 * in the ADMA engine. It's best just to avoid it 1482 * completely. 1483 */ 1484 if (version < 0xAC) 1485 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1486 } 1487 1488 /* JM388 MMC doesn't support 1.8V while SD supports it */ 1489 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1490 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 1491 MMC_VDD_29_30 | MMC_VDD_30_31 | 1492 MMC_VDD_165_195; /* allow 1.8V */ 1493 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 1494 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 1495 } 1496 1497 /* 1498 * The secondary interface requires a bit set to get the 1499 * interrupts. 1500 */ 1501 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1502 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1503 jmicron_enable_mmc(slot->host, 1); 1504 1505 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 1506 1507 /* Handle unstable RO-detection on JM388 chips */ 1508 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 1509 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1510 slot->host->mmc_host_ops.get_ro = jmicron_jmb388_get_ro; 1511 1512 return 0; 1513 } 1514 1515 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 1516 { 1517 if (dead) 1518 return; 1519 1520 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1521 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1522 jmicron_enable_mmc(slot->host, 0); 1523 } 1524 1525 #ifdef CONFIG_PM_SLEEP 1526 static int jmicron_suspend(struct sdhci_pci_chip *chip) 1527 { 1528 int i, ret; 1529 1530 ret = sdhci_pci_suspend_host(chip); 1531 if (ret) 1532 return ret; 1533 1534 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1535 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1536 for (i = 0; i < chip->num_slots; i++) 1537 jmicron_enable_mmc(chip->slots[i]->host, 0); 1538 } 1539 1540 return 0; 1541 } 1542 1543 static int jmicron_resume(struct sdhci_pci_chip *chip) 1544 { 1545 int ret, i; 1546 1547 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1548 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1549 for (i = 0; i < chip->num_slots; i++) 1550 jmicron_enable_mmc(chip->slots[i]->host, 1); 1551 } 1552 1553 ret = jmicron_pmos(chip, 1); 1554 if (ret) { 1555 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1556 return ret; 1557 } 1558 1559 return sdhci_pci_resume_host(chip); 1560 } 1561 #endif 1562 1563 static const struct sdhci_pci_fixes sdhci_jmicron = { 1564 .probe = jmicron_probe, 1565 1566 .probe_slot = jmicron_probe_slot, 1567 .remove_slot = jmicron_remove_slot, 1568 1569 #ifdef CONFIG_PM_SLEEP 1570 .suspend = jmicron_suspend, 1571 .resume = jmicron_resume, 1572 #endif 1573 }; 1574 1575 /* SysKonnect CardBus2SDIO extra registers */ 1576 #define SYSKT_CTRL 0x200 1577 #define SYSKT_RDFIFO_STAT 0x204 1578 #define SYSKT_WRFIFO_STAT 0x208 1579 #define SYSKT_POWER_DATA 0x20c 1580 #define SYSKT_POWER_330 0xef 1581 #define SYSKT_POWER_300 0xf8 1582 #define SYSKT_POWER_184 0xcc 1583 #define SYSKT_POWER_CMD 0x20d 1584 #define SYSKT_POWER_START (1 << 7) 1585 #define SYSKT_POWER_STATUS 0x20e 1586 #define SYSKT_POWER_STATUS_OK (1 << 0) 1587 #define SYSKT_BOARD_REV 0x210 1588 #define SYSKT_CHIP_REV 0x211 1589 #define SYSKT_CONF_DATA 0x212 1590 #define SYSKT_CONF_DATA_1V8 (1 << 2) 1591 #define SYSKT_CONF_DATA_2V5 (1 << 1) 1592 #define SYSKT_CONF_DATA_3V3 (1 << 0) 1593 1594 static int syskt_probe(struct sdhci_pci_chip *chip) 1595 { 1596 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1597 chip->pdev->class &= ~0x0000FF; 1598 chip->pdev->class |= PCI_SDHCI_IFDMA; 1599 } 1600 return 0; 1601 } 1602 1603 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 1604 { 1605 int tm, ps; 1606 1607 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 1608 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 1609 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 1610 "board rev %d.%d, chip rev %d.%d\n", 1611 board_rev >> 4, board_rev & 0xf, 1612 chip_rev >> 4, chip_rev & 0xf); 1613 if (chip_rev >= 0x20) 1614 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 1615 1616 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 1617 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 1618 udelay(50); 1619 tm = 10; /* Wait max 1 ms */ 1620 do { 1621 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 1622 if (ps & SYSKT_POWER_STATUS_OK) 1623 break; 1624 udelay(100); 1625 } while (--tm); 1626 if (!tm) { 1627 dev_err(&slot->chip->pdev->dev, 1628 "power regulator never stabilized"); 1629 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1630 return -ENODEV; 1631 } 1632 1633 return 0; 1634 } 1635 1636 static const struct sdhci_pci_fixes sdhci_syskt = { 1637 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1638 .probe = syskt_probe, 1639 .probe_slot = syskt_probe_slot, 1640 }; 1641 1642 static int via_probe(struct sdhci_pci_chip *chip) 1643 { 1644 if (chip->pdev->revision == 0x10) 1645 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1646 1647 return 0; 1648 } 1649 1650 static const struct sdhci_pci_fixes sdhci_via = { 1651 .probe = via_probe, 1652 }; 1653 1654 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1655 { 1656 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1657 return 0; 1658 } 1659 1660 static const struct sdhci_pci_fixes sdhci_rtsx = { 1661 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1662 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1663 SDHCI_QUIRK2_BROKEN_DDR50, 1664 .probe_slot = rtsx_probe_slot, 1665 }; 1666 1667 /*AMD chipset generation*/ 1668 enum amd_chipset_gen { 1669 AMD_CHIPSET_BEFORE_ML, 1670 AMD_CHIPSET_CZ, 1671 AMD_CHIPSET_NL, 1672 AMD_CHIPSET_UNKNOWN, 1673 }; 1674 1675 /* AMD registers */ 1676 #define AMD_SD_AUTO_PATTERN 0xB8 1677 #define AMD_MSLEEP_DURATION 4 1678 #define AMD_SD_MISC_CONTROL 0xD0 1679 #define AMD_MAX_TUNE_VALUE 0x0B 1680 #define AMD_AUTO_TUNE_SEL 0x10800 1681 #define AMD_FIFO_PTR 0x30 1682 #define AMD_BIT_MASK 0x1F 1683 1684 static void amd_tuning_reset(struct sdhci_host *host) 1685 { 1686 unsigned int val; 1687 1688 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1689 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1690 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1691 1692 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1693 val &= ~SDHCI_CTRL_EXEC_TUNING; 1694 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1695 } 1696 1697 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1698 { 1699 unsigned int val; 1700 1701 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1702 val &= ~AMD_BIT_MASK; 1703 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1704 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1705 } 1706 1707 static void amd_enable_manual_tuning(struct pci_dev *pdev) 1708 { 1709 unsigned int val; 1710 1711 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1712 val |= AMD_FIFO_PTR; 1713 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1714 } 1715 1716 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode) 1717 { 1718 struct sdhci_pci_slot *slot = sdhci_priv(host); 1719 struct pci_dev *pdev = slot->chip->pdev; 1720 u8 valid_win = 0; 1721 u8 valid_win_max = 0; 1722 u8 valid_win_end = 0; 1723 u8 ctrl, tune_around; 1724 1725 amd_tuning_reset(host); 1726 1727 for (tune_around = 0; tune_around < 12; tune_around++) { 1728 amd_config_tuning_phase(pdev, tune_around); 1729 1730 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1731 valid_win = 0; 1732 msleep(AMD_MSLEEP_DURATION); 1733 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1734 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1735 } else if (++valid_win > valid_win_max) { 1736 valid_win_max = valid_win; 1737 valid_win_end = tune_around; 1738 } 1739 } 1740 1741 if (!valid_win_max) { 1742 dev_err(&pdev->dev, "no tuning point found\n"); 1743 return -EIO; 1744 } 1745 1746 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1747 1748 amd_enable_manual_tuning(pdev); 1749 1750 host->mmc->retune_period = 0; 1751 1752 return 0; 1753 } 1754 1755 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode) 1756 { 1757 struct sdhci_host *host = mmc_priv(mmc); 1758 1759 /* AMD requires custom HS200 tuning */ 1760 if (host->timing == MMC_TIMING_MMC_HS200) 1761 return amd_execute_tuning_hs200(host, opcode); 1762 1763 /* Otherwise perform standard SDHCI tuning */ 1764 return sdhci_execute_tuning(mmc, opcode); 1765 } 1766 1767 static int amd_probe_slot(struct sdhci_pci_slot *slot) 1768 { 1769 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 1770 1771 ops->execute_tuning = amd_execute_tuning; 1772 1773 return 0; 1774 } 1775 1776 static int amd_probe(struct sdhci_pci_chip *chip) 1777 { 1778 struct pci_dev *smbus_dev; 1779 enum amd_chipset_gen gen; 1780 1781 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1782 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1783 if (smbus_dev) { 1784 gen = AMD_CHIPSET_BEFORE_ML; 1785 } else { 1786 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1787 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1788 if (smbus_dev) { 1789 if (smbus_dev->revision < 0x51) 1790 gen = AMD_CHIPSET_CZ; 1791 else 1792 gen = AMD_CHIPSET_NL; 1793 } else { 1794 gen = AMD_CHIPSET_UNKNOWN; 1795 } 1796 } 1797 1798 pci_dev_put(smbus_dev); 1799 1800 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1801 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1802 1803 return 0; 1804 } 1805 1806 static u32 sdhci_read_present_state(struct sdhci_host *host) 1807 { 1808 return sdhci_readl(host, SDHCI_PRESENT_STATE); 1809 } 1810 1811 static void amd_sdhci_reset(struct sdhci_host *host, u8 mask) 1812 { 1813 struct sdhci_pci_slot *slot = sdhci_priv(host); 1814 struct pci_dev *pdev = slot->chip->pdev; 1815 u32 present_state; 1816 1817 /* 1818 * SDHC 0x7906 requires a hard reset to clear all internal state. 1819 * Otherwise it can get into a bad state where the DATA lines are always 1820 * read as zeros. 1821 */ 1822 if (pdev->device == 0x7906 && (mask & SDHCI_RESET_ALL)) { 1823 pci_clear_master(pdev); 1824 1825 pci_save_state(pdev); 1826 1827 pci_set_power_state(pdev, PCI_D3cold); 1828 pr_debug("%s: power_state=%u\n", mmc_hostname(host->mmc), 1829 pdev->current_state); 1830 pci_set_power_state(pdev, PCI_D0); 1831 1832 pci_restore_state(pdev); 1833 1834 /* 1835 * SDHCI_RESET_ALL says the card detect logic should not be 1836 * reset, but since we need to reset the entire controller 1837 * we should wait until the card detect logic has stabilized. 1838 * 1839 * This normally takes about 40ms. 1840 */ 1841 readx_poll_timeout( 1842 sdhci_read_present_state, 1843 host, 1844 present_state, 1845 present_state & SDHCI_CD_STABLE, 1846 10000, 1847 100000 1848 ); 1849 } 1850 1851 return sdhci_reset(host, mask); 1852 } 1853 1854 static const struct sdhci_ops amd_sdhci_pci_ops = { 1855 .set_clock = sdhci_set_clock, 1856 .enable_dma = sdhci_pci_enable_dma, 1857 .set_bus_width = sdhci_set_bus_width, 1858 .reset = amd_sdhci_reset, 1859 .set_uhs_signaling = sdhci_set_uhs_signaling, 1860 }; 1861 1862 static const struct sdhci_pci_fixes sdhci_amd = { 1863 .probe = amd_probe, 1864 .ops = &amd_sdhci_pci_ops, 1865 .probe_slot = amd_probe_slot, 1866 }; 1867 1868 static const struct pci_device_id pci_ids[] = { 1869 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), 1870 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), 1871 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), 1872 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), 1873 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), 1874 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), 1875 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), 1876 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), 1877 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), 1878 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), 1879 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), 1880 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), 1881 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), 1882 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), 1883 SDHCI_PCI_DEVICE(VIA, 95D0, via), 1884 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), 1885 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), 1886 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), 1887 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), 1888 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), 1889 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), 1890 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), 1891 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), 1892 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), 1893 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), 1894 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), 1895 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), 1896 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), 1897 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), 1898 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), 1899 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), 1900 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), 1901 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), 1902 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), 1903 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), 1904 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), 1905 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), 1906 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), 1907 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), 1908 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), 1909 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), 1910 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), 1911 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), 1912 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), 1913 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), 1914 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc), 1915 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), 1916 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), 1917 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), 1918 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), 1919 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), 1920 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), 1921 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), 1922 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), 1923 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), 1924 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), 1925 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), 1926 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), 1927 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), 1928 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), 1929 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), 1930 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc), 1931 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd), 1932 SDHCI_PCI_DEVICE(INTEL, EHL_EMMC, intel_glk_emmc), 1933 SDHCI_PCI_DEVICE(INTEL, EHL_SD, intel_byt_sd), 1934 SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc), 1935 SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd), 1936 SDHCI_PCI_DEVICE(INTEL, CMLH_SD, intel_byt_sd), 1937 SDHCI_PCI_DEVICE(INTEL, JSL_EMMC, intel_glk_emmc), 1938 SDHCI_PCI_DEVICE(INTEL, JSL_SD, intel_byt_sd), 1939 SDHCI_PCI_DEVICE(INTEL, LKF_EMMC, intel_glk_emmc), 1940 SDHCI_PCI_DEVICE(INTEL, LKF_SD, intel_byt_sd), 1941 SDHCI_PCI_DEVICE(INTEL, ADL_EMMC, intel_glk_emmc), 1942 SDHCI_PCI_DEVICE(O2, 8120, o2), 1943 SDHCI_PCI_DEVICE(O2, 8220, o2), 1944 SDHCI_PCI_DEVICE(O2, 8221, o2), 1945 SDHCI_PCI_DEVICE(O2, 8320, o2), 1946 SDHCI_PCI_DEVICE(O2, 8321, o2), 1947 SDHCI_PCI_DEVICE(O2, FUJIN2, o2), 1948 SDHCI_PCI_DEVICE(O2, SDS0, o2), 1949 SDHCI_PCI_DEVICE(O2, SDS1, o2), 1950 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), 1951 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), 1952 SDHCI_PCI_DEVICE(O2, GG8_9860, o2), 1953 SDHCI_PCI_DEVICE(O2, GG8_9861, o2), 1954 SDHCI_PCI_DEVICE(O2, GG8_9862, o2), 1955 SDHCI_PCI_DEVICE(O2, GG8_9863, o2), 1956 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan), 1957 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps), 1958 SDHCI_PCI_DEVICE(GLI, 9750, gl9750), 1959 SDHCI_PCI_DEVICE(GLI, 9755, gl9755), 1960 SDHCI_PCI_DEVICE(GLI, 9763E, gl9763e), 1961 SDHCI_PCI_DEVICE(GLI, 9767, gl9767), 1962 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), 1963 /* Generic SD host controller */ 1964 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, 1965 { /* end: all zeroes */ }, 1966 }; 1967 1968 MODULE_DEVICE_TABLE(pci, pci_ids); 1969 1970 /*****************************************************************************\ 1971 * * 1972 * SDHCI core callbacks * 1973 * * 1974 \*****************************************************************************/ 1975 1976 int sdhci_pci_enable_dma(struct sdhci_host *host) 1977 { 1978 struct sdhci_pci_slot *slot; 1979 struct pci_dev *pdev; 1980 1981 slot = sdhci_priv(host); 1982 pdev = slot->chip->pdev; 1983 1984 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1985 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1986 (host->flags & SDHCI_USE_SDMA)) { 1987 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1988 "doesn't fully claim to support it.\n"); 1989 } 1990 1991 pci_set_master(pdev); 1992 1993 return 0; 1994 } 1995 1996 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1997 { 1998 struct sdhci_pci_slot *slot = sdhci_priv(host); 1999 2000 if (slot->hw_reset) 2001 slot->hw_reset(host); 2002 } 2003 2004 static const struct sdhci_ops sdhci_pci_ops = { 2005 .set_clock = sdhci_set_clock, 2006 .enable_dma = sdhci_pci_enable_dma, 2007 .set_bus_width = sdhci_set_bus_width, 2008 .reset = sdhci_reset, 2009 .set_uhs_signaling = sdhci_set_uhs_signaling, 2010 .hw_reset = sdhci_pci_hw_reset, 2011 }; 2012 2013 /*****************************************************************************\ 2014 * * 2015 * Suspend/resume * 2016 * * 2017 \*****************************************************************************/ 2018 2019 #ifdef CONFIG_PM_SLEEP 2020 static int sdhci_pci_suspend(struct device *dev) 2021 { 2022 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2023 2024 if (!chip) 2025 return 0; 2026 2027 if (chip->fixes && chip->fixes->suspend) 2028 return chip->fixes->suspend(chip); 2029 2030 return sdhci_pci_suspend_host(chip); 2031 } 2032 2033 static int sdhci_pci_resume(struct device *dev) 2034 { 2035 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2036 2037 if (!chip) 2038 return 0; 2039 2040 if (chip->fixes && chip->fixes->resume) 2041 return chip->fixes->resume(chip); 2042 2043 return sdhci_pci_resume_host(chip); 2044 } 2045 #endif 2046 2047 #ifdef CONFIG_PM 2048 static int sdhci_pci_runtime_suspend(struct device *dev) 2049 { 2050 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2051 2052 if (!chip) 2053 return 0; 2054 2055 if (chip->fixes && chip->fixes->runtime_suspend) 2056 return chip->fixes->runtime_suspend(chip); 2057 2058 return sdhci_pci_runtime_suspend_host(chip); 2059 } 2060 2061 static int sdhci_pci_runtime_resume(struct device *dev) 2062 { 2063 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2064 2065 if (!chip) 2066 return 0; 2067 2068 if (chip->fixes && chip->fixes->runtime_resume) 2069 return chip->fixes->runtime_resume(chip); 2070 2071 return sdhci_pci_runtime_resume_host(chip); 2072 } 2073 #endif 2074 2075 static const struct dev_pm_ops sdhci_pci_pm_ops = { 2076 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 2077 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 2078 sdhci_pci_runtime_resume, NULL) 2079 }; 2080 2081 /*****************************************************************************\ 2082 * * 2083 * Device probing/removal * 2084 * * 2085 \*****************************************************************************/ 2086 2087 static struct gpiod_lookup_table *sdhci_pci_add_gpio_lookup_table( 2088 struct sdhci_pci_chip *chip) 2089 { 2090 struct gpiod_lookup_table *cd_gpio_lookup_table; 2091 const struct dmi_system_id *dmi_id = NULL; 2092 size_t count; 2093 2094 if (chip->fixes && chip->fixes->cd_gpio_override) 2095 dmi_id = dmi_first_match(chip->fixes->cd_gpio_override); 2096 2097 if (!dmi_id) 2098 return NULL; 2099 2100 cd_gpio_lookup_table = dmi_id->driver_data; 2101 for (count = 0; cd_gpio_lookup_table->table[count].key; count++) 2102 ; 2103 2104 cd_gpio_lookup_table = kmemdup(dmi_id->driver_data, 2105 /* count + 1 terminating entry */ 2106 struct_size(cd_gpio_lookup_table, table, count + 1), 2107 GFP_KERNEL); 2108 if (!cd_gpio_lookup_table) 2109 return ERR_PTR(-ENOMEM); 2110 2111 gpiod_add_lookup_table(cd_gpio_lookup_table); 2112 return cd_gpio_lookup_table; 2113 } 2114 2115 static void sdhci_pci_remove_gpio_lookup_table(struct gpiod_lookup_table *lookup_table) 2116 { 2117 if (lookup_table) { 2118 gpiod_remove_lookup_table(lookup_table); 2119 kfree(lookup_table); 2120 } 2121 } 2122 2123 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 2124 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 2125 int slotno) 2126 { 2127 struct sdhci_pci_slot *slot; 2128 struct sdhci_host *host; 2129 int ret, bar = first_bar + slotno; 2130 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 2131 2132 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 2133 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 2134 return ERR_PTR(-ENODEV); 2135 } 2136 2137 if (pci_resource_len(pdev, bar) < 0x100) { 2138 dev_err(&pdev->dev, "Invalid iomem size. You may " 2139 "experience problems.\n"); 2140 } 2141 2142 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 2143 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 2144 return ERR_PTR(-ENODEV); 2145 } 2146 2147 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 2148 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 2149 return ERR_PTR(-ENODEV); 2150 } 2151 2152 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 2153 if (IS_ERR(host)) { 2154 dev_err(&pdev->dev, "cannot allocate host\n"); 2155 return ERR_CAST(host); 2156 } 2157 2158 slot = sdhci_priv(host); 2159 2160 slot->chip = chip; 2161 slot->host = host; 2162 slot->cd_idx = -1; 2163 2164 host->hw_name = "PCI"; 2165 host->ops = chip->fixes && chip->fixes->ops ? 2166 chip->fixes->ops : 2167 &sdhci_pci_ops; 2168 host->quirks = chip->quirks; 2169 host->quirks2 = chip->quirks2; 2170 2171 host->irq = pdev->irq; 2172 2173 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 2174 if (ret) { 2175 dev_err(&pdev->dev, "cannot request region\n"); 2176 goto cleanup; 2177 } 2178 2179 host->ioaddr = pcim_iomap_table(pdev)[bar]; 2180 2181 if (chip->fixes && chip->fixes->probe_slot) { 2182 ret = chip->fixes->probe_slot(slot); 2183 if (ret) 2184 goto cleanup; 2185 } 2186 2187 host->mmc->pm_caps = MMC_PM_KEEP_POWER; 2188 host->mmc->slotno = slotno; 2189 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 2190 2191 if (device_can_wakeup(&pdev->dev)) 2192 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 2193 2194 if (host->mmc->caps & MMC_CAP_CD_WAKE) 2195 device_init_wakeup(&pdev->dev, true); 2196 2197 if (slot->cd_idx >= 0) { 2198 struct gpiod_lookup_table *cd_gpio_lookup_table; 2199 2200 cd_gpio_lookup_table = sdhci_pci_add_gpio_lookup_table(chip); 2201 if (IS_ERR(cd_gpio_lookup_table)) { 2202 ret = PTR_ERR(cd_gpio_lookup_table); 2203 goto remove; 2204 } 2205 2206 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx, 2207 slot->cd_override_level, 0); 2208 2209 sdhci_pci_remove_gpio_lookup_table(cd_gpio_lookup_table); 2210 2211 if (ret && ret != -EPROBE_DEFER) 2212 ret = mmc_gpiod_request_cd(host->mmc, NULL, 2213 slot->cd_idx, 2214 slot->cd_override_level, 2215 0); 2216 if (ret == -EPROBE_DEFER) 2217 goto remove; 2218 2219 if (ret) { 2220 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 2221 slot->cd_idx = -1; 2222 } 2223 } 2224 2225 if (chip->fixes && chip->fixes->add_host) 2226 ret = chip->fixes->add_host(slot); 2227 else 2228 ret = sdhci_add_host(host); 2229 if (ret) 2230 goto remove; 2231 2232 /* 2233 * Check if the chip needs a separate GPIO for card detect to wake up 2234 * from runtime suspend. If it is not there, don't allow runtime PM. 2235 */ 2236 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && slot->cd_idx < 0) 2237 chip->allow_runtime_pm = false; 2238 2239 return slot; 2240 2241 remove: 2242 if (chip->fixes && chip->fixes->remove_slot) 2243 chip->fixes->remove_slot(slot, 0); 2244 2245 cleanup: 2246 sdhci_free_host(host); 2247 2248 return ERR_PTR(ret); 2249 } 2250 2251 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 2252 { 2253 int dead; 2254 u32 scratch; 2255 2256 dead = 0; 2257 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 2258 if (scratch == (u32)-1) 2259 dead = 1; 2260 2261 if (slot->chip->fixes && slot->chip->fixes->remove_host) 2262 slot->chip->fixes->remove_host(slot, dead); 2263 else 2264 sdhci_remove_host(slot->host, dead); 2265 2266 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 2267 slot->chip->fixes->remove_slot(slot, dead); 2268 2269 sdhci_free_host(slot->host); 2270 } 2271 2272 int sdhci_pci_uhs2_add_host(struct sdhci_pci_slot *slot) 2273 { 2274 return sdhci_uhs2_add_host(slot->host); 2275 } 2276 2277 void sdhci_pci_uhs2_remove_host(struct sdhci_pci_slot *slot, int dead) 2278 { 2279 sdhci_uhs2_remove_host(slot->host, dead); 2280 } 2281 2282 static void sdhci_pci_runtime_pm_allow(struct device *dev) 2283 { 2284 pm_suspend_ignore_children(dev, 1); 2285 pm_runtime_set_autosuspend_delay(dev, 50); 2286 pm_runtime_use_autosuspend(dev); 2287 pm_runtime_allow(dev); 2288 /* Stay active until mmc core scans for a card */ 2289 pm_runtime_put_noidle(dev); 2290 } 2291 2292 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 2293 { 2294 pm_runtime_forbid(dev); 2295 pm_runtime_get_noresume(dev); 2296 } 2297 2298 static int sdhci_pci_probe(struct pci_dev *pdev, 2299 const struct pci_device_id *ent) 2300 { 2301 struct sdhci_pci_chip *chip; 2302 struct sdhci_pci_slot *slot; 2303 2304 u8 slots, first_bar; 2305 int ret, i; 2306 2307 BUG_ON(pdev == NULL); 2308 BUG_ON(ent == NULL); 2309 2310 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 2311 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 2312 2313 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 2314 if (ret) 2315 return pcibios_err_to_errno(ret); 2316 2317 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 2318 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 2319 2320 BUG_ON(slots > MAX_SLOTS); 2321 2322 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 2323 if (ret) 2324 return pcibios_err_to_errno(ret); 2325 2326 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 2327 2328 if (first_bar > 5) { 2329 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 2330 return -ENODEV; 2331 } 2332 2333 ret = pcim_enable_device(pdev); 2334 if (ret) 2335 return ret; 2336 2337 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 2338 if (!chip) 2339 return -ENOMEM; 2340 2341 chip->pdev = pdev; 2342 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 2343 if (chip->fixes) { 2344 chip->quirks = chip->fixes->quirks; 2345 chip->quirks2 = chip->fixes->quirks2; 2346 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 2347 } 2348 chip->num_slots = slots; 2349 chip->pm_retune = true; 2350 chip->rpm_retune = true; 2351 2352 pci_set_drvdata(pdev, chip); 2353 2354 if (chip->fixes && chip->fixes->probe) { 2355 ret = chip->fixes->probe(chip); 2356 if (ret) 2357 return ret; 2358 } 2359 2360 slots = chip->num_slots; /* Quirk may have changed this */ 2361 2362 for (i = 0; i < slots; i++) { 2363 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 2364 if (IS_ERR(slot)) { 2365 for (i--; i >= 0; i--) 2366 sdhci_pci_remove_slot(chip->slots[i]); 2367 return PTR_ERR(slot); 2368 } 2369 2370 chip->slots[i] = slot; 2371 } 2372 2373 if (chip->allow_runtime_pm) 2374 sdhci_pci_runtime_pm_allow(&pdev->dev); 2375 2376 return 0; 2377 } 2378 2379 static void sdhci_pci_remove(struct pci_dev *pdev) 2380 { 2381 int i; 2382 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 2383 2384 if (chip->allow_runtime_pm) 2385 sdhci_pci_runtime_pm_forbid(&pdev->dev); 2386 2387 for (i = 0; i < chip->num_slots; i++) 2388 sdhci_pci_remove_slot(chip->slots[i]); 2389 } 2390 2391 static struct pci_driver sdhci_driver = { 2392 .name = "sdhci-pci", 2393 .id_table = pci_ids, 2394 .probe = sdhci_pci_probe, 2395 .remove = sdhci_pci_remove, 2396 .driver = { 2397 .pm = &sdhci_pci_pm_ops, 2398 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2399 }, 2400 }; 2401 2402 module_pci_driver(sdhci_driver); 2403 2404 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2405 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2406 MODULE_LICENSE("GPL"); 2407