1# SPDX-License-Identifier: GPL-2.0-only 2menuconfig MAILBOX 3 bool "Mailbox Hardware Support" 4 help 5 Mailbox is a framework to control hardware communication between 6 on-chip processors through queued messages and interrupt driven 7 signals. Say Y if your platform supports hardware mailboxes. 8 9if MAILBOX 10 11config ARM_MHU 12 tristate "ARM MHU Mailbox" 13 depends on ARM_AMBA 14 help 15 Say Y here if you want to build the ARM MHU controller driver. 16 The controller has 3 mailbox channels, the last of which can be 17 used in Secure mode only. 18 19config ARM_MHU_V2 20 tristate "ARM MHUv2 Mailbox" 21 depends on ARM_AMBA 22 help 23 Say Y here if you want to build the ARM MHUv2 controller driver, 24 which provides unidirectional mailboxes between processing elements. 25 26config ARM_MHU_V3 27 tristate "ARM MHUv3 Mailbox" 28 depends on ARM64 || COMPILE_TEST 29 depends on HAS_IOMEM || COMPILE_TEST 30 depends on OF 31 help 32 Say Y here if you want to build the ARM MHUv3 controller driver, 33 which provides unidirectional mailboxes between processing elements. 34 35 ARM MHUv3 controllers can implement a varying number of extensions 36 that provides different means of transports: supported extensions 37 will be discovered and possibly managed at probe-time. 38 39config AST2700_MBOX 40 tristate "ASPEED AST2700 IPC driver" 41 depends on ARCH_ASPEED || COMPILE_TEST 42 help 43 Mailbox driver implementation for ASPEED AST27XX SoCs. This driver 44 can be used to send message between different processors in SoC. 45 The driver provides mailbox support for sending interrupts to the 46 clients. Say Y here if you want to build this driver. 47 48config CV1800_MBOX 49 tristate "cv1800 mailbox" 50 depends on ARCH_SOPHGO || COMPILE_TEST 51 help 52 Mailbox driver implementation for Sophgo CV18XX SoCs. This driver 53 can be used to send message between different processors in SoC. Any 54 processer can write data in a channel, and set co-responding register 55 to raise interrupt to notice another processor, and it is allowed to 56 send data to itself. 57 58config EXYNOS_MBOX 59 tristate "Exynos Mailbox" 60 depends on ARCH_EXYNOS || COMPILE_TEST 61 help 62 Say Y here if you want to build the Samsung Exynos Mailbox controller 63 driver. The controller has 16 flag bits for hardware interrupt 64 generation and a shared register for passing mailbox messages. 65 When the controller is used by the ACPM interface the shared register 66 is ignored and the mailbox controller acts as a doorbell that raises 67 the interrupt to the ACPM firmware. 68 69config IMX_MBOX 70 tristate "i.MX Mailbox" 71 depends on ARCH_MXC || COMPILE_TEST 72 help 73 Mailbox implementation for i.MX Messaging Unit (MU). 74 75config PLATFORM_MHU 76 tristate "Platform MHU Mailbox" 77 depends on OF 78 depends on HAS_IOMEM 79 help 80 Say Y here if you want to build a platform specific variant MHU 81 controller driver. 82 The controller has a maximum of 3 mailbox channels, the last of 83 which can be used in Secure mode only. 84 85config PL320_MBOX 86 bool "ARM PL320 Mailbox" 87 depends on ARM_AMBA 88 help 89 An implementation of the ARM PL320 Interprocessor Communication 90 Mailbox (IPCM), tailored for the Calxeda Highbank. It is used to 91 send short messages between Highbank's A9 cores and the EnergyCore 92 Management Engine, primarily for cpufreq. Say Y here if you want 93 to use the PL320 IPCM support. 94 95config ARMADA_37XX_RWTM_MBOX 96 tristate "Armada 37xx rWTM BIU Mailbox" 97 depends on ARCH_MVEBU || COMPILE_TEST 98 depends on OF 99 help 100 Mailbox implementation for communication with the the firmware 101 running on the Cortex-M3 rWTM secure processor of the Armada 37xx 102 SOC. Say Y here if you are building for such a device (for example 103 the Turris Mox router). 104 105config OMAP2PLUS_MBOX 106 tristate "OMAP2+ Mailbox framework support" 107 depends on ARCH_OMAP2PLUS || ARCH_K3 || COMPILE_TEST 108 help 109 Mailbox implementation for OMAP family chips with hardware for 110 interprocessor communication involving DSP, IVA1.0 and IVA2 in 111 OMAP2/3; or IPU, IVA HD and DSP in OMAP4/5. Say Y here if you 112 want to use OMAP2+ Mailbox framework support. 113 114config ROCKCHIP_MBOX 115 bool "Rockchip Soc Integrated Mailbox Support" 116 depends on ARCH_ROCKCHIP || COMPILE_TEST 117 help 118 This driver provides support for inter-processor communication 119 between CPU cores and MCU processor on Some Rockchip SOCs. 120 Please check it that the Soc you use have Mailbox hardware. 121 Say Y here if you want to use the Rockchip Mailbox support. 122 123config PCC 124 bool "Platform Communication Channel Driver" 125 depends on ACPI 126 default n 127 help 128 ACPI 5.0+ spec defines a generic mode of communication 129 between the OS and a platform such as the BMC. This medium 130 (PCC) is typically used by CPPC (ACPI CPU Performance management), 131 RAS (ACPI reliability protocol) and MPST (ACPI Memory power 132 states). Select this driver if your platform implements the 133 PCC clients mentioned above. 134 135config ALTERA_MBOX 136 tristate "Altera Mailbox" 137 depends on HAS_IOMEM 138 help 139 An implementation of the Altera Mailbox soft core. It is used 140 to send message between processors. Say Y here if you want to use the 141 Altera mailbox support. 142 143config BCM2835_MBOX 144 tristate "BCM2835 Mailbox" 145 depends on ARCH_BCM2835 146 help 147 An implementation of the BCM2385 Mailbox. It is used to invoke 148 the services of the Videocore. Say Y here if you want to use the 149 BCM2835 Mailbox. 150 151config STI_MBOX 152 tristate "STI Mailbox framework support" 153 depends on ARCH_STI && OF 154 help 155 Mailbox implementation for STMicroelectonics family chips with 156 hardware for interprocessor communication. 157 158config TI_MESSAGE_MANAGER 159 tristate "Texas Instruments Message Manager Driver" 160 depends on ARCH_KEYSTONE || ARCH_K3 || COMPILE_TEST 161 default ARCH_K3 162 help 163 An implementation of Message Manager slave driver for Keystone 164 and K3 architecture SoCs from Texas Instruments. Message Manager 165 is a communication entity found on few of Texas Instrument's keystone 166 and K3 architecture SoCs. These may be used for communication between 167 multiple processors within the SoC. Select this driver if your 168 platform has support for the hardware block. 169 170config HI3660_MBOX 171 tristate "Hi3660 Mailbox" if EXPERT 172 depends on (ARCH_HISI || COMPILE_TEST) 173 depends on OF 174 default ARCH_HISI 175 help 176 An implementation of the hi3660 mailbox. It is used to send message 177 between application processors and other processors/MCU/DSP. Select 178 Y here if you want to use Hi3660 mailbox controller. 179 180config HI6220_MBOX 181 tristate "Hi6220 Mailbox" if EXPERT 182 depends on (ARCH_HISI || COMPILE_TEST) 183 depends on OF 184 default ARCH_HISI 185 help 186 An implementation of the hi6220 mailbox. It is used to send message 187 between application processors and MCU. Say Y here if you want to 188 build Hi6220 mailbox controller driver. 189 190config MAILBOX_TEST 191 tristate "Mailbox Test Client" 192 depends on OF 193 depends on HAS_IOMEM 194 help 195 Test client to help with testing new Controller driver 196 implementations. 197 198config POLARFIRE_SOC_MAILBOX 199 tristate "PolarFire SoC (MPFS) Mailbox" 200 depends on HAS_IOMEM 201 depends on MFD_SYSCON 202 depends on ARCH_MICROCHIP_POLARFIRE || COMPILE_TEST 203 help 204 This driver adds support for the PolarFire SoC (MPFS) mailbox controller. 205 206 To compile this driver as a module, choose M here. the 207 module will be called mailbox-mpfs. 208 209 If unsure, say N. 210 211config MCHP_SBI_IPC_MBOX 212 tristate "Microchip Inter-processor Communication (IPC) SBI driver" 213 depends on RISCV_SBI 214 depends on ARCH_MICROCHIP || COMPILE_TEST 215 help 216 Mailbox implementation for Microchip devices with an 217 Inter-process communication (IPC) controller. 218 219 To compile this driver as a module, choose M here. the 220 module will be called mailbox-mchp-ipc-sbi. 221 222 If unsure, say N. 223 224config QCOM_APCS_IPC 225 tristate "Qualcomm APCS IPC driver" 226 depends on ARCH_QCOM || COMPILE_TEST 227 help 228 Say y here to enable support for the APCS IPC mailbox driver, 229 providing an interface for invoking the inter-process communication 230 signals from the application processor to other masters. 231 232config TEGRA_HSP_MBOX 233 bool "Tegra HSP (Hardware Synchronization Primitives) Driver" 234 depends on ARCH_TEGRA 235 help 236 The Tegra HSP driver is used for the interprocessor communication 237 between different remote processors and host processors on Tegra186 238 and later SoCs. Say Y here if you want to have this support. 239 If unsure say N. 240 241config XGENE_SLIMPRO_MBOX 242 tristate "APM SoC X-Gene SLIMpro Mailbox Controller" 243 depends on ARCH_XGENE 244 help 245 An implementation of the APM X-Gene Interprocessor Communication 246 Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller. 247 It is used to send short messages between ARM64-bit cores and 248 the SLIMpro Management Engine, primarily for PM. Say Y here if you 249 want to use the APM X-Gene SLIMpro IPCM support. 250 251config BCM_PDC_MBOX 252 tristate "Broadcom FlexSparx DMA Mailbox" 253 depends on ARCH_BCM_IPROC || COMPILE_TEST 254 help 255 Mailbox implementation for the Broadcom FlexSparx DMA ring manager, 256 which provides access to various offload engines on Broadcom 257 SoCs, including FA2/FA+ on Northstar Plus and PDC on Northstar 2. 258 259config BCM_FLEXRM_MBOX 260 tristate "Broadcom FlexRM Mailbox" 261 depends on ARM64 262 depends on ARCH_BCM_IPROC || COMPILE_TEST 263 select GENERIC_MSI_IRQ 264 default m if ARCH_BCM_IPROC 265 help 266 Mailbox implementation of the Broadcom FlexRM ring manager, 267 which provides access to various offload engines on Broadcom 268 SoCs. Say Y here if you want to use the Broadcom FlexRM. 269 270config STM32_IPCC 271 tristate "STM32 IPCC Mailbox" 272 depends on MACH_STM32MP157 || COMPILE_TEST 273 help 274 Mailbox implementation for STMicroelectonics STM32 family chips 275 with hardware for Inter-Processor Communication Controller (IPCC) 276 between processors. Say Y here if you want to have this support. 277 278config MTK_ADSP_MBOX 279 tristate "MediaTek ADSP Mailbox Controller" 280 depends on ARCH_MEDIATEK || COMPILE_TEST 281 help 282 Say yes here to add support for "MediaTek ADSP Mailbox Controller. 283 This mailbox driver is used to send notification or short message 284 between processors with ADSP. It will place the message to share 285 buffer and will access the ipc control. 286 287config MTK_CMDQ_MBOX 288 tristate "MediaTek CMDQ Mailbox Support" 289 depends on ARCH_MEDIATEK || COMPILE_TEST 290 select MTK_INFRACFG 291 help 292 Say yes here to add support for the MediaTek Command Queue (CMDQ) 293 mailbox driver. The CMDQ is used to help read/write registers with 294 critical time limitation, such as updating display configuration 295 during the vblank. 296 297config ZYNQMP_IPI_MBOX 298 tristate "Xilinx ZynqMP IPI Mailbox" 299 depends on ARCH_ZYNQMP && OF 300 help 301 Say yes here to add support for Xilinx IPI mailbox driver. 302 This mailbox driver is used to send notification or short message 303 between processors with Xilinx ZynqMP IPI. It will place the 304 message to the IPI buffer and will access the IPI control 305 registers to kick the other processor or enquire status. 306 307config SUN6I_MSGBOX 308 tristate "Allwinner sun6i/sun8i/sun9i/sun50i Message Box" 309 depends on ARCH_SUNXI || COMPILE_TEST 310 default ARCH_SUNXI 311 help 312 Mailbox implementation for the hardware message box present in 313 various Allwinner SoCs. This mailbox is used for communication 314 between the application CPUs and the power management coprocessor. 315 316config SPRD_MBOX 317 tristate "Spreadtrum Mailbox" 318 depends on ARCH_SPRD || COMPILE_TEST 319 help 320 Mailbox driver implementation for the Spreadtrum platform. It is used 321 to send message between application processors and MCU. Say Y here if 322 you want to build the Spreatrum mailbox controller driver. 323 324config QCOM_CPUCP_MBOX 325 tristate "Qualcomm Technologies, Inc. CPUCP mailbox driver" 326 depends on (ARCH_QCOM || COMPILE_TEST) && 64BIT 327 help 328 Qualcomm Technologies, Inc. CPUSS Control Processor (CPUCP) mailbox 329 controller driver enables communication between AP and CPUCP. Say 330 Y here if you want to build this driver. 331 332config QCOM_IPCC 333 tristate "Qualcomm Technologies, Inc. IPCC driver" 334 depends on ARCH_QCOM || COMPILE_TEST 335 help 336 Qualcomm Technologies, Inc. Inter-Processor Communication Controller 337 (IPCC) driver for MSM devices. The driver provides mailbox support for 338 sending interrupts to the clients. On the other hand, the driver also 339 acts as an interrupt controller for receiving interrupts from clients. 340 Say Y here if you want to build this driver. 341 342config THEAD_TH1520_MBOX 343 tristate "T-head TH1520 Mailbox" 344 depends on ARCH_THEAD || COMPILE_TEST 345 help 346 Mailbox driver implementation for the Thead TH-1520 platform. Enables 347 two cores within the SoC to communicate and coordinate by passing 348 messages. Could be used to communicate between E910 core, on which the 349 kernel is running, and E902 core used for power management among other 350 things. 351 352config CIX_MBOX 353 tristate "CIX Mailbox" 354 depends on ARCH_CIX || COMPILE_TEST 355 depends on OF 356 help 357 Mailbox implementation for CIX IPC system. The controller supports 358 11 mailbox channels with different operating mode and every channel 359 is unidirectional. Say Y here if you want to use the CIX Mailbox 360 support. 361 362config BCM74110_MAILBOX 363 tristate "Brcmstb BCM74110 Mailbox" 364 depends on ARCH_BRCMSTB || COMPILE_TEST 365 default ARCH_BRCMSTB 366 help 367 Broadcom STB mailbox driver present starting with brcmstb bcm74110 368 SoCs. The mailbox is a communication channel between the host 369 processor and coprocessor that handles various power management task 370 and more. 371 372endif 373