1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * JZ47xx SoCs TCU IRQ driver 4 * Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/interrupt.h> 9 #include <linux/irqchip.h> 10 #include <linux/irqchip/chained_irq.h> 11 #include <linux/mfd/ingenic-tcu.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/of_irq.h> 14 #include <linux/regmap.h> 15 16 struct ingenic_tcu { 17 struct regmap *map; 18 struct clk *clk; 19 struct irq_domain *domain; 20 unsigned int nb_parent_irqs; 21 u32 parent_irqs[3]; 22 }; 23 24 static void ingenic_tcu_intc_cascade(struct irq_desc *desc) 25 { 26 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data); 27 struct irq_domain *domain = irq_desc_get_handler_data(desc); 28 struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0); 29 struct regmap *map = gc->private; 30 uint32_t irq_reg, irq_mask; 31 unsigned long bits; 32 unsigned int i; 33 34 regmap_read(map, TCU_REG_TFR, &irq_reg); 35 regmap_read(map, TCU_REG_TMR, &irq_mask); 36 37 chained_irq_enter(irq_chip, desc); 38 39 irq_reg &= ~irq_mask; 40 bits = irq_reg; 41 42 for_each_set_bit(i, &bits, 32) 43 generic_handle_domain_irq(domain, i); 44 45 chained_irq_exit(irq_chip, desc); 46 } 47 48 static void ingenic_tcu_gc_unmask_enable_reg(struct irq_data *d) 49 { 50 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 51 struct irq_chip_type *ct = irq_data_get_chip_type(d); 52 struct regmap *map = gc->private; 53 u32 mask = d->mask; 54 55 guard(raw_spinlock)(&gc->lock); 56 regmap_write(map, ct->regs.ack, mask); 57 regmap_write(map, ct->regs.enable, mask); 58 *ct->mask_cache |= mask; 59 } 60 61 static void ingenic_tcu_gc_mask_disable_reg(struct irq_data *d) 62 { 63 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 64 struct irq_chip_type *ct = irq_data_get_chip_type(d); 65 struct regmap *map = gc->private; 66 u32 mask = d->mask; 67 68 guard(raw_spinlock)(&gc->lock); 69 regmap_write(map, ct->regs.disable, mask); 70 *ct->mask_cache &= ~mask; 71 } 72 73 static void ingenic_tcu_gc_mask_disable_reg_and_ack(struct irq_data *d) 74 { 75 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 76 struct irq_chip_type *ct = irq_data_get_chip_type(d); 77 struct regmap *map = gc->private; 78 u32 mask = d->mask; 79 80 guard(raw_spinlock)(&gc->lock); 81 regmap_write(map, ct->regs.ack, mask); 82 regmap_write(map, ct->regs.disable, mask); 83 } 84 85 static int __init ingenic_tcu_irq_init(struct device_node *np, 86 struct device_node *parent) 87 { 88 struct irq_chip_generic *gc; 89 struct irq_chip_type *ct; 90 struct ingenic_tcu *tcu; 91 struct regmap *map; 92 unsigned int i; 93 int ret, irqs; 94 95 map = device_node_to_regmap(np); 96 if (IS_ERR(map)) 97 return PTR_ERR(map); 98 99 tcu = kzalloc(sizeof(*tcu), GFP_KERNEL); 100 if (!tcu) 101 return -ENOMEM; 102 103 tcu->map = map; 104 105 irqs = of_property_count_elems_of_size(np, "interrupts", sizeof(u32)); 106 if (irqs < 0 || irqs > ARRAY_SIZE(tcu->parent_irqs)) { 107 pr_crit("%s: Invalid 'interrupts' property\n", __func__); 108 ret = -EINVAL; 109 goto err_free_tcu; 110 } 111 112 tcu->nb_parent_irqs = irqs; 113 114 tcu->domain = irq_domain_create_linear(of_fwnode_handle(np), 32, &irq_generic_chip_ops, 115 NULL); 116 if (!tcu->domain) { 117 ret = -ENOMEM; 118 goto err_free_tcu; 119 } 120 121 ret = irq_alloc_domain_generic_chips(tcu->domain, 32, 1, "TCU", 122 handle_level_irq, 0, 123 IRQ_NOPROBE | IRQ_LEVEL, 0); 124 if (ret) { 125 pr_crit("%s: Invalid 'interrupts' property\n", __func__); 126 goto out_domain_remove; 127 } 128 129 gc = irq_get_domain_generic_chip(tcu->domain, 0); 130 ct = gc->chip_types; 131 132 gc->wake_enabled = IRQ_MSK(32); 133 gc->private = tcu->map; 134 135 ct->regs.disable = TCU_REG_TMSR; 136 ct->regs.enable = TCU_REG_TMCR; 137 ct->regs.ack = TCU_REG_TFCR; 138 ct->chip.irq_unmask = ingenic_tcu_gc_unmask_enable_reg; 139 ct->chip.irq_mask = ingenic_tcu_gc_mask_disable_reg; 140 ct->chip.irq_mask_ack = ingenic_tcu_gc_mask_disable_reg_and_ack; 141 ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE; 142 143 /* Mask all IRQs by default */ 144 regmap_write(tcu->map, TCU_REG_TMSR, IRQ_MSK(32)); 145 146 /* 147 * On JZ4740, timer 0 and timer 1 have their own interrupt line; 148 * timers 2-7 share one interrupt. 149 * On SoCs >= JZ4770, timer 5 has its own interrupt line; 150 * timers 0-4 and 6-7 share one single interrupt. 151 * 152 * To keep things simple, we just register the same handler to 153 * all parent interrupts. The handler will properly detect which 154 * channel fired the interrupt. 155 */ 156 for (i = 0; i < irqs; i++) { 157 tcu->parent_irqs[i] = irq_of_parse_and_map(np, i); 158 if (!tcu->parent_irqs[i]) { 159 ret = -EINVAL; 160 goto out_unmap_irqs; 161 } 162 163 irq_set_chained_handler_and_data(tcu->parent_irqs[i], 164 ingenic_tcu_intc_cascade, 165 tcu->domain); 166 } 167 168 return 0; 169 170 out_unmap_irqs: 171 for (; i > 0; i--) 172 irq_dispose_mapping(tcu->parent_irqs[i - 1]); 173 out_domain_remove: 174 irq_domain_remove(tcu->domain); 175 err_free_tcu: 176 kfree(tcu); 177 return ret; 178 } 179 IRQCHIP_DECLARE(jz4740_tcu_irq, "ingenic,jz4740-tcu", ingenic_tcu_irq_init); 180 IRQCHIP_DECLARE(jz4725b_tcu_irq, "ingenic,jz4725b-tcu", ingenic_tcu_irq_init); 181 IRQCHIP_DECLARE(jz4760_tcu_irq, "ingenic,jz4760-tcu", ingenic_tcu_irq_init); 182 IRQCHIP_DECLARE(jz4770_tcu_irq, "ingenic,jz4770-tcu", ingenic_tcu_irq_init); 183 IRQCHIP_DECLARE(x1000_tcu_irq, "ingenic,x1000-tcu", ingenic_tcu_irq_init); 184