1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Broadcom BCM7120 style Level 2 interrupt controller driver
4  *
5  * Copyright (C) 2014 Broadcom Corporation
6  */
7 
8 #define pr_fmt(fmt)	KBUILD_MODNAME	": " fmt
9 
10 #include <linux/init.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/platform_device.h>
15 #include <linux/of.h>
16 #include <linux/of_irq.h>
17 #include <linux/of_address.h>
18 #include <linux/of_platform.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/io.h>
22 #include <linux/irqdomain.h>
23 #include <linux/reboot.h>
24 #include <linux/bitops.h>
25 #include <linux/irqchip.h>
26 #include <linux/irqchip/chained_irq.h>
27 
28 /* Register offset in the L2 interrupt controller */
29 #define IRQEN		0x00
30 #define IRQSTAT		0x04
31 
32 #define MAX_WORDS	4
33 #define MAX_MAPPINGS	(MAX_WORDS * 2)
34 #define IRQS_PER_WORD	32
35 
36 struct bcm7120_l1_intc_data {
37 	struct bcm7120_l2_intc_data *b;
38 	u32 irq_map_mask[MAX_WORDS];
39 };
40 
41 struct bcm7120_l2_intc_data {
42 	unsigned int n_words;
43 	void __iomem *map_base[MAX_MAPPINGS];
44 	void __iomem *pair_base[MAX_WORDS];
45 	int en_offset[MAX_WORDS];
46 	int stat_offset[MAX_WORDS];
47 	struct irq_domain *domain;
48 	bool can_wake;
49 	u32 irq_fwd_mask[MAX_WORDS];
50 	struct bcm7120_l1_intc_data *l1_data;
51 	int num_parent_irqs;
52 	const __be32 *map_mask_prop;
53 };
54 
55 static void bcm7120_l2_intc_irq_handle(struct irq_desc *desc)
56 {
57 	struct bcm7120_l1_intc_data *data = irq_desc_get_handler_data(desc);
58 	struct bcm7120_l2_intc_data *b = data->b;
59 	struct irq_chip *chip = irq_desc_get_chip(desc);
60 	unsigned int idx;
61 
62 	chained_irq_enter(chip, desc);
63 
64 	for (idx = 0; idx < b->n_words; idx++) {
65 		int base = idx * IRQS_PER_WORD;
66 		struct irq_chip_generic *gc;
67 		unsigned long pending;
68 		int hwirq;
69 
70 		gc = irq_get_domain_generic_chip(b->domain, base);
71 		scoped_guard (raw_spinlock, &gc->lock) {
72 			pending = irq_reg_readl(gc, b->stat_offset[idx]) & gc->mask_cache &
73 				data->irq_map_mask[idx];
74 		}
75 
76 		for_each_set_bit(hwirq, &pending, IRQS_PER_WORD)
77 			generic_handle_domain_irq(b->domain, base + hwirq);
78 	}
79 
80 	chained_irq_exit(chip, desc);
81 }
82 
83 static void bcm7120_l2_intc_suspend(struct irq_chip_generic *gc)
84 {
85 	struct bcm7120_l2_intc_data *b = gc->private;
86 	struct irq_chip_type *ct = gc->chip_types;
87 
88 	guard(raw_spinlock)(&gc->lock);
89 	if (b->can_wake)
90 		irq_reg_writel(gc, gc->mask_cache | gc->wake_active, ct->regs.mask);
91 }
92 
93 static void bcm7120_l2_intc_resume(struct irq_chip_generic *gc)
94 {
95 	struct irq_chip_type *ct = gc->chip_types;
96 
97 	/* Restore the saved mask */
98 	guard(raw_spinlock)(&gc->lock);
99 	irq_reg_writel(gc, gc->mask_cache, ct->regs.mask);
100 }
101 
102 static int bcm7120_l2_intc_init_one(struct device_node *dn,
103 					struct bcm7120_l2_intc_data *data,
104 					int irq, u32 *valid_mask)
105 {
106 	struct bcm7120_l1_intc_data *l1_data = &data->l1_data[irq];
107 	int parent_irq;
108 	unsigned int idx;
109 
110 	parent_irq = irq_of_parse_and_map(dn, irq);
111 	if (!parent_irq) {
112 		pr_err("failed to map interrupt %d\n", irq);
113 		return -EINVAL;
114 	}
115 
116 	/* For multiple parent IRQs with multiple words, this looks like:
117 	 * <irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...>
118 	 *
119 	 * We need to associate a given parent interrupt with its corresponding
120 	 * map_mask in order to mask the status register with it because we
121 	 * have the same handler being called for multiple parent interrupts.
122 	 *
123 	 * This is typically something needed on BCM7xxx (STB chips).
124 	 */
125 	for (idx = 0; idx < data->n_words; idx++) {
126 		if (data->map_mask_prop) {
127 			l1_data->irq_map_mask[idx] |=
128 				be32_to_cpup(data->map_mask_prop +
129 					     irq * data->n_words + idx);
130 		} else {
131 			l1_data->irq_map_mask[idx] = 0xffffffff;
132 		}
133 		valid_mask[idx] |= l1_data->irq_map_mask[idx];
134 	}
135 
136 	l1_data->b = data;
137 
138 	irq_set_chained_handler_and_data(parent_irq,
139 					 bcm7120_l2_intc_irq_handle, l1_data);
140 	if (data->can_wake)
141 		enable_irq_wake(parent_irq);
142 
143 	return 0;
144 }
145 
146 static int __init bcm7120_l2_intc_iomap_7120(struct device_node *dn,
147 					     struct bcm7120_l2_intc_data *data)
148 {
149 	int ret;
150 
151 	data->map_base[0] = of_iomap(dn, 0);
152 	if (!data->map_base[0]) {
153 		pr_err("unable to map registers\n");
154 		return -ENOMEM;
155 	}
156 
157 	data->pair_base[0] = data->map_base[0];
158 	data->en_offset[0] = IRQEN;
159 	data->stat_offset[0] = IRQSTAT;
160 	data->n_words = 1;
161 
162 	ret = of_property_read_u32_array(dn, "brcm,int-fwd-mask",
163 					 data->irq_fwd_mask, data->n_words);
164 	if (ret != 0 && ret != -EINVAL) {
165 		/* property exists but has the wrong number of words */
166 		pr_err("invalid brcm,int-fwd-mask property\n");
167 		return -EINVAL;
168 	}
169 
170 	data->map_mask_prop = of_get_property(dn, "brcm,int-map-mask", &ret);
171 	if (!data->map_mask_prop ||
172 	    (ret != (sizeof(__be32) * data->num_parent_irqs * data->n_words))) {
173 		pr_err("invalid brcm,int-map-mask property\n");
174 		return -EINVAL;
175 	}
176 
177 	return 0;
178 }
179 
180 static int __init bcm7120_l2_intc_iomap_3380(struct device_node *dn,
181 					     struct bcm7120_l2_intc_data *data)
182 {
183 	unsigned int gc_idx;
184 
185 	for (gc_idx = 0; gc_idx < MAX_WORDS; gc_idx++) {
186 		unsigned int map_idx = gc_idx * 2;
187 		void __iomem *en = of_iomap(dn, map_idx + 0);
188 		void __iomem *stat = of_iomap(dn, map_idx + 1);
189 		void __iomem *base = min(en, stat);
190 
191 		data->map_base[map_idx + 0] = en;
192 		data->map_base[map_idx + 1] = stat;
193 
194 		if (!base)
195 			break;
196 
197 		data->pair_base[gc_idx] = base;
198 		data->en_offset[gc_idx] = en - base;
199 		data->stat_offset[gc_idx] = stat - base;
200 	}
201 
202 	if (!gc_idx) {
203 		pr_err("unable to map registers\n");
204 		return -EINVAL;
205 	}
206 
207 	data->n_words = gc_idx;
208 	return 0;
209 }
210 
211 static int __init bcm7120_l2_intc_probe(struct device_node *dn,
212 				 struct device_node *parent,
213 				 int (*iomap_regs_fn)(struct device_node *,
214 					struct bcm7120_l2_intc_data *),
215 				 const char *intc_name)
216 {
217 	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
218 	struct bcm7120_l2_intc_data *data;
219 	struct platform_device *pdev;
220 	struct irq_chip_generic *gc;
221 	struct irq_chip_type *ct;
222 	int ret = 0;
223 	unsigned int idx, irq, flags;
224 	u32 valid_mask[MAX_WORDS] = { };
225 
226 	data = kzalloc(sizeof(*data), GFP_KERNEL);
227 	if (!data)
228 		return -ENOMEM;
229 
230 	pdev = of_find_device_by_node(dn);
231 	if (!pdev) {
232 		ret = -ENODEV;
233 		goto out_free_data;
234 	}
235 
236 	data->num_parent_irqs = platform_irq_count(pdev);
237 	put_device(&pdev->dev);
238 	if (data->num_parent_irqs <= 0) {
239 		pr_err("invalid number of parent interrupts\n");
240 		ret = -ENOMEM;
241 		goto out_unmap;
242 	}
243 
244 	data->l1_data = kcalloc(data->num_parent_irqs, sizeof(*data->l1_data),
245 				GFP_KERNEL);
246 	if (!data->l1_data) {
247 		ret = -ENOMEM;
248 		goto out_free_l1_data;
249 	}
250 
251 	ret = iomap_regs_fn(dn, data);
252 	if (ret < 0)
253 		goto out_free_l1_data;
254 
255 	data->can_wake = of_property_read_bool(dn, "brcm,irq-can-wake");
256 
257 	for (irq = 0; irq < data->num_parent_irqs; irq++) {
258 		ret = bcm7120_l2_intc_init_one(dn, data, irq, valid_mask);
259 		if (ret)
260 			goto out_free_l1_data;
261 	}
262 
263 	data->domain = irq_domain_create_linear(of_fwnode_handle(dn), IRQS_PER_WORD * data->n_words,
264 					     &irq_generic_chip_ops, NULL);
265 	if (!data->domain) {
266 		ret = -ENOMEM;
267 		goto out_free_l1_data;
268 	}
269 
270 	/* MIPS chips strapped for BE will automagically configure the
271 	 * peripheral registers for CPU-native byte order.
272 	 */
273 	flags = IRQ_GC_INIT_MASK_CACHE;
274 	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
275 		flags |= IRQ_GC_BE_IO;
276 
277 	ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1,
278 				dn->full_name, handle_level_irq, clr,
279 				IRQ_LEVEL, flags);
280 	if (ret) {
281 		pr_err("failed to allocate generic irq chip\n");
282 		goto out_free_domain;
283 	}
284 
285 	for (idx = 0; idx < data->n_words; idx++) {
286 		irq = idx * IRQS_PER_WORD;
287 		gc = irq_get_domain_generic_chip(data->domain, irq);
288 
289 		gc->unused = 0xffffffff & ~valid_mask[idx];
290 		gc->private = data;
291 		ct = gc->chip_types;
292 
293 		gc->reg_base = data->pair_base[idx];
294 		ct->regs.mask = data->en_offset[idx];
295 
296 		/* gc->reg_base is defined and so is gc->writel */
297 		irq_reg_writel(gc, data->irq_fwd_mask[idx],
298 			       data->en_offset[idx]);
299 
300 		ct->chip.irq_mask = irq_gc_mask_clr_bit;
301 		ct->chip.irq_unmask = irq_gc_mask_set_bit;
302 		ct->chip.irq_ack = irq_gc_noop;
303 		gc->suspend = bcm7120_l2_intc_suspend;
304 		gc->resume = bcm7120_l2_intc_resume;
305 
306 		/*
307 		 * Initialize mask-cache, in case we need it for
308 		 * saving/restoring fwd mask even w/o any child interrupts
309 		 * installed
310 		 */
311 		gc->mask_cache = irq_reg_readl(gc, ct->regs.mask);
312 
313 		if (data->can_wake) {
314 			/* This IRQ chip can wake the system, set all
315 			 * relevant child interrupts in wake_enabled mask
316 			 */
317 			gc->wake_enabled = 0xffffffff;
318 			gc->wake_enabled &= ~gc->unused;
319 			ct->chip.irq_set_wake = irq_gc_set_wake;
320 		}
321 	}
322 
323 	pr_info("registered %s intc (%pOF, parent IRQ(s): %d)\n",
324 		intc_name, dn, data->num_parent_irqs);
325 
326 	return 0;
327 
328 out_free_domain:
329 	irq_domain_remove(data->domain);
330 out_free_l1_data:
331 	kfree(data->l1_data);
332 out_unmap:
333 	for (idx = 0; idx < MAX_MAPPINGS; idx++) {
334 		if (data->map_base[idx])
335 			iounmap(data->map_base[idx]);
336 	}
337 out_free_data:
338 	kfree(data);
339 	return ret;
340 }
341 
342 static int __init bcm7120_l2_intc_probe_7120(struct device_node *dn,
343 					     struct device_node *parent)
344 {
345 	return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_7120,
346 				     "BCM7120 L2");
347 }
348 
349 static int __init bcm7120_l2_intc_probe_3380(struct device_node *dn,
350 					     struct device_node *parent)
351 {
352 	return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_3380,
353 				     "BCM3380 L2");
354 }
355 
356 IRQCHIP_PLATFORM_DRIVER_BEGIN(bcm7120_l2)
357 IRQCHIP_MATCH("brcm,bcm7120-l2-intc", bcm7120_l2_intc_probe_7120)
358 IRQCHIP_MATCH("brcm,bcm3380-l2-intc", bcm7120_l2_intc_probe_3380)
359 IRQCHIP_PLATFORM_DRIVER_END(bcm7120_l2)
360 MODULE_DESCRIPTION("Broadcom STB 7120-style L2 interrupt controller driver");
361 MODULE_LICENSE("GPL v2");
362