1f6e916b8SThomas Petazzoniconfig IRQCHIP 2f6e916b8SThomas Petazzoni def_bool y 3f6e916b8SThomas Petazzoni depends on OF_IRQ 4f6e916b8SThomas Petazzoni 581243e44SRob Herringconfig ARM_GIC 681243e44SRob Herring bool 781243e44SRob Herring select IRQ_DOMAIN 881243e44SRob Herring select MULTI_IRQ_HANDLER 981243e44SRob Herring 1081243e44SRob Herringconfig GIC_NON_BANKED 1181243e44SRob Herring bool 1281243e44SRob Herring 13*44430ec0SRob Herringconfig ARM_VIC 14*44430ec0SRob Herring bool 15*44430ec0SRob Herring select IRQ_DOMAIN 16*44430ec0SRob Herring select MULTI_IRQ_HANDLER 17*44430ec0SRob Herring 18*44430ec0SRob Herringconfig ARM_VIC_NR 19*44430ec0SRob Herring int 20*44430ec0SRob Herring default 4 if ARCH_S5PV210 21*44430ec0SRob Herring default 3 if ARCH_S5PC100 22*44430ec0SRob Herring default 2 23*44430ec0SRob Herring depends on ARM_VIC 24*44430ec0SRob Herring help 25*44430ec0SRob Herring The maximum number of VICs available in the system, for 26*44430ec0SRob Herring power management. 27*44430ec0SRob Herring 282389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ 292389d501SLinus Walleij bool 302389d501SLinus Walleij select IRQ_DOMAIN 312389d501SLinus Walleij 322389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ_NR 332389d501SLinus Walleij int 342389d501SLinus Walleij default 4 352389d501SLinus Walleij depends on VERSATILE_FPGA_IRQ 36