1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on (OF_IRQ || ACPI_GENERIC_GSI) 7 8config ARM_GIC 9 bool 10 depends on OF 11 select IRQ_DOMAIN_HIERARCHY 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 19config ARM_GIC_MAX_NR 20 int 21 depends on ARM_GIC 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select IRQ_MSI_LIB 30 select PCI_MSI 31 select IRQ_MSI_IOMMU 32 33config GIC_NON_BANKED 34 bool 35 36config ARM_GIC_V3 37 bool 38 select IRQ_DOMAIN_HIERARCHY 39 select PARTITION_PERCPU 40 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 41 select HAVE_ARM_SMCCC_DISCOVERY 42 select IRQ_MSI_IOMMU 43 44config ARM_GIC_V3_ITS 45 bool 46 select GENERIC_MSI_IRQ 47 select IRQ_MSI_LIB 48 default ARM_GIC_V3 49 select IRQ_MSI_IOMMU 50 51config ARM_GIC_V3_ITS_FSL_MC 52 bool 53 depends on ARM_GIC_V3_ITS 54 depends on FSL_MC_BUS 55 default ARM_GIC_V3_ITS 56 57config ARM_NVIC 58 bool 59 select IRQ_DOMAIN_HIERARCHY 60 select GENERIC_IRQ_CHIP 61 62config ARM_VIC 63 bool 64 select IRQ_DOMAIN 65 66config ARM_VIC_NR 67 int 68 default 4 if ARCH_S5PV210 69 default 2 70 depends on ARM_VIC 71 help 72 The maximum number of VICs available in the system, for 73 power management. 74 75config IRQ_MSI_LIB 76 bool 77 78config ARMADA_370_XP_IRQ 79 bool 80 select GENERIC_IRQ_CHIP 81 select PCI_MSI if PCI 82 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 83 84config ALPINE_MSI 85 bool 86 depends on PCI 87 select PCI_MSI 88 select GENERIC_IRQ_CHIP 89 90config AL_FIC 91 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 92 depends on OF 93 depends on HAS_IOMEM 94 select GENERIC_IRQ_CHIP 95 select IRQ_DOMAIN 96 help 97 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 98 99config ATMEL_AIC_IRQ 100 bool 101 select GENERIC_IRQ_CHIP 102 select IRQ_DOMAIN 103 select SPARSE_IRQ 104 105config ATMEL_AIC5_IRQ 106 bool 107 select GENERIC_IRQ_CHIP 108 select IRQ_DOMAIN 109 select SPARSE_IRQ 110 111config I8259 112 bool 113 select IRQ_DOMAIN 114 115config BCM2712_MIP 116 tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support" 117 depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 118 default m if ARCH_BRCMSTB || ARCH_BCM2835 119 depends on ARM_GIC 120 select GENERIC_IRQ_CHIP 121 select IRQ_DOMAIN_HIERARCHY 122 select GENERIC_MSI_IRQ 123 select IRQ_MSI_LIB 124 help 125 Enable support for the Broadcom BCM2712 MSI-X target peripheral 126 (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on 127 Raspberry Pi 5. 128 129 If unsure say n. 130 131config BCM6345_L1_IRQ 132 bool 133 select GENERIC_IRQ_CHIP 134 select IRQ_DOMAIN 135 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 136 137config BCM7038_L1_IRQ 138 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 139 depends on ARCH_BRCMSTB || BMIPS_GENERIC 140 default ARCH_BRCMSTB || BMIPS_GENERIC 141 select GENERIC_IRQ_CHIP 142 select IRQ_DOMAIN 143 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 144 145config BCM7120_L2_IRQ 146 tristate "Broadcom STB 7120-style L2 interrupt controller driver" 147 depends on ARCH_BRCMSTB || BMIPS_GENERIC 148 default ARCH_BRCMSTB || BMIPS_GENERIC 149 select GENERIC_IRQ_CHIP 150 select IRQ_DOMAIN 151 152config BRCMSTB_L2_IRQ 153 tristate "Broadcom STB generic L2 interrupt controller driver" 154 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 155 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 156 select GENERIC_IRQ_CHIP 157 select IRQ_DOMAIN 158 159config DAVINCI_CP_INTC 160 bool 161 select GENERIC_IRQ_CHIP 162 select IRQ_DOMAIN 163 164config DW_APB_ICTL 165 bool 166 select GENERIC_IRQ_CHIP 167 select IRQ_DOMAIN_HIERARCHY 168 169config ECONET_EN751221_INTC 170 bool 171 select GENERIC_IRQ_CHIP 172 select IRQ_DOMAIN 173 174config FARADAY_FTINTC010 175 bool 176 select IRQ_DOMAIN 177 select SPARSE_IRQ 178 179config HISILICON_IRQ_MBIGEN 180 bool 181 select ARM_GIC_V3 182 select ARM_GIC_V3_ITS 183 184config IMGPDC_IRQ 185 bool 186 select GENERIC_IRQ_CHIP 187 select IRQ_DOMAIN 188 189config IXP4XX_IRQ 190 bool 191 select IRQ_DOMAIN 192 select SPARSE_IRQ 193 194config LAN966X_OIC 195 tristate "Microchip LAN966x OIC Support" 196 depends on MCHP_LAN966X_PCI || COMPILE_TEST 197 select GENERIC_IRQ_CHIP 198 select IRQ_DOMAIN 199 help 200 Enable support for the LAN966x Outbound Interrupt Controller. 201 This controller is present on the Microchip LAN966x PCI device and 202 maps the internal interrupts sources to PCIe interrupt. 203 204 To compile this driver as a module, choose M here: the module 205 will be called irq-lan966x-oic. 206 207config MADERA_IRQ 208 tristate 209 210config IRQ_MIPS_CPU 211 bool 212 select GENERIC_IRQ_CHIP 213 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 214 select IRQ_DOMAIN 215 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 216 217config CLPS711X_IRQCHIP 218 bool 219 depends on ARCH_CLPS711X 220 select IRQ_DOMAIN 221 select SPARSE_IRQ 222 default y 223 224config OMPIC 225 bool 226 227config OR1K_PIC 228 bool 229 select IRQ_DOMAIN 230 231config OMAP_IRQCHIP 232 bool 233 select GENERIC_IRQ_CHIP 234 select IRQ_DOMAIN 235 236config ORION_IRQCHIP 237 bool 238 select IRQ_DOMAIN 239 240config PIC32_EVIC 241 bool 242 select GENERIC_IRQ_CHIP 243 select IRQ_DOMAIN 244 245config JCORE_AIC 246 bool "J-Core integrated AIC" if COMPILE_TEST 247 depends on OF 248 select IRQ_DOMAIN 249 help 250 Support for the J-Core integrated AIC. 251 252config RDA_INTC 253 bool 254 select IRQ_DOMAIN 255 256config RENESAS_INTC_IRQPIN 257 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 258 select IRQ_DOMAIN 259 help 260 Enable support for the Renesas Interrupt Controller for external 261 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 262 263config RENESAS_IRQC 264 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 265 select GENERIC_IRQ_CHIP 266 select IRQ_DOMAIN 267 help 268 Enable support for the Renesas Interrupt Controller for external 269 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 270 271config RENESAS_RZA1_IRQC 272 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 273 select IRQ_DOMAIN_HIERARCHY 274 help 275 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 276 to 8 external interrupts with configurable sense select. 277 278config RENESAS_RZG2L_IRQC 279 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 280 select GENERIC_IRQ_CHIP 281 select IRQ_DOMAIN_HIERARCHY 282 help 283 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 284 for external devices. 285 286config RENESAS_RZV2H_ICU 287 bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST 288 select GENERIC_IRQ_CHIP 289 select IRQ_DOMAIN_HIERARCHY 290 help 291 Enable support for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU) 292 293config SL28CPLD_INTC 294 bool "Kontron sl28cpld IRQ controller" 295 depends on MFD_SL28CPLD=y || COMPILE_TEST 296 select REGMAP_IRQ 297 help 298 Interrupt controller driver for the board management controller 299 found on the Kontron sl28 CPLD. 300 301config ST_IRQCHIP 302 bool 303 select REGMAP 304 select MFD_SYSCON 305 help 306 Enables SysCfg Controlled IRQs on STi based platforms. 307 308config SUN4I_INTC 309 bool 310 311config SUN6I_R_INTC 312 bool 313 select IRQ_DOMAIN_HIERARCHY 314 select IRQ_FASTEOI_HIERARCHY_HANDLERS 315 316config SUNXI_NMI_INTC 317 bool 318 select GENERIC_IRQ_CHIP 319 320config TB10X_IRQC 321 bool 322 select IRQ_DOMAIN 323 select GENERIC_IRQ_CHIP 324 325config TS4800_IRQ 326 tristate "TS-4800 IRQ controller" 327 select IRQ_DOMAIN 328 depends on HAS_IOMEM 329 depends on SOC_IMX51 || COMPILE_TEST 330 help 331 Support for the TS-4800 FPGA IRQ controller 332 333config VERSATILE_FPGA_IRQ 334 bool 335 select IRQ_DOMAIN 336 337config VERSATILE_FPGA_IRQ_NR 338 int 339 default 4 340 depends on VERSATILE_FPGA_IRQ 341 342config XTENSA_MX 343 bool 344 select IRQ_DOMAIN 345 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 346 347config XILINX_INTC 348 bool "Xilinx Interrupt Controller IP" 349 depends on OF_ADDRESS 350 select IRQ_DOMAIN 351 help 352 Support for the Xilinx Interrupt Controller IP core. 353 This is used as a primary controller with MicroBlaze and can also 354 be used as a secondary chained controller on other platforms. 355 356config IRQ_CROSSBAR 357 bool 358 help 359 Support for a CROSSBAR ip that precedes the main interrupt controller. 360 The primary irqchip invokes the crossbar's callback which inturn allocates 361 a free irq and configures the IP. Thus the peripheral interrupts are 362 routed to one of the free irqchip interrupt lines. 363 364config KEYSTONE_IRQ 365 tristate "Keystone 2 IRQ controller IP" 366 depends on ARCH_KEYSTONE 367 help 368 Support for Texas Instruments Keystone 2 IRQ controller IP which 369 is part of the Keystone 2 IPC mechanism 370 371config MIPS_GIC 372 bool 373 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 374 select GENERIC_IRQ_IPI if SMP 375 select IRQ_DOMAIN_HIERARCHY 376 select MIPS_CM 377 378config INGENIC_IRQ 379 bool 380 depends on MACH_INGENIC 381 default y 382 383config INGENIC_TCU_IRQ 384 bool "Ingenic JZ47xx TCU interrupt controller" 385 default MACH_INGENIC 386 depends on MIPS || COMPILE_TEST 387 select MFD_SYSCON 388 select GENERIC_IRQ_CHIP 389 help 390 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 391 JZ47xx SoCs. 392 393 If unsure, say N. 394 395config IMX_GPCV2 396 bool 397 select IRQ_DOMAIN 398 help 399 Enables the wakeup IRQs for IMX platforms with GPCv2 block 400 401config IRQ_MXS 402 def_bool y if MACH_ASM9260 || ARCH_MXS 403 select IRQ_DOMAIN 404 select STMP_DEVICE 405 406config MSCC_OCELOT_IRQ 407 bool 408 select IRQ_DOMAIN 409 select GENERIC_IRQ_CHIP 410 411config MVEBU_GICP 412 select IRQ_MSI_LIB 413 bool 414 415config MVEBU_ICU 416 bool 417 418config MVEBU_ODMI 419 bool 420 select IRQ_MSI_LIB 421 select GENERIC_MSI_IRQ 422 423config MVEBU_PIC 424 bool 425 426config MVEBU_SEI 427 bool 428 429config LS_EXTIRQ 430 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 431 select MFD_SYSCON 432 433config LS_SCFG_MSI 434 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 435 select IRQ_MSI_IOMMU 436 depends on PCI_MSI 437 438config PARTITION_PERCPU 439 bool 440 441config STM32MP_EXTI 442 tristate "STM32MP extended interrupts and event controller" 443 depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST 444 default ARCH_STM32 && !ARM_SINGLE_ARMV7M 445 select IRQ_DOMAIN_HIERARCHY 446 select GENERIC_IRQ_CHIP 447 help 448 Support STM32MP EXTI (extended interrupts and event) controller. 449 450config STM32_EXTI 451 bool 452 select IRQ_DOMAIN 453 select GENERIC_IRQ_CHIP 454 455config QCOM_IRQ_COMBINER 456 bool "QCOM IRQ combiner support" 457 depends on ARCH_QCOM && ACPI 458 select IRQ_DOMAIN_HIERARCHY 459 help 460 Say yes here to add support for the IRQ combiner devices embedded 461 in Qualcomm Technologies chips. 462 463config IRQ_UNIPHIER_AIDET 464 bool "UniPhier AIDET support" if COMPILE_TEST 465 depends on ARCH_UNIPHIER || COMPILE_TEST 466 default ARCH_UNIPHIER 467 select IRQ_DOMAIN_HIERARCHY 468 help 469 Support for the UniPhier AIDET (ARM Interrupt Detector). 470 471config MESON_IRQ_GPIO 472 tristate "Meson GPIO Interrupt Multiplexer" 473 depends on ARCH_MESON || COMPILE_TEST 474 default ARCH_MESON 475 select IRQ_DOMAIN_HIERARCHY 476 help 477 Support Meson SoC Family GPIO Interrupt Multiplexer 478 479config GOLDFISH_PIC 480 bool "Goldfish programmable interrupt controller" 481 depends on MIPS && (GOLDFISH || COMPILE_TEST) 482 select GENERIC_IRQ_CHIP 483 select IRQ_DOMAIN 484 help 485 Say yes here to enable Goldfish interrupt controller driver used 486 for Goldfish based virtual platforms. 487 488config QCOM_PDC 489 tristate "QCOM PDC" 490 depends on ARCH_QCOM 491 select IRQ_DOMAIN_HIERARCHY 492 help 493 Power Domain Controller driver to manage and configure wakeup 494 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 495 496config QCOM_MPM 497 tristate "QCOM MPM" 498 depends on ARCH_QCOM 499 depends on MAILBOX 500 select IRQ_DOMAIN_HIERARCHY 501 help 502 MSM Power Manager driver to manage and configure wakeup 503 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 504 505config CSKY_MPINTC 506 bool 507 depends on CSKY 508 help 509 Say yes here to enable C-SKY SMP interrupt controller driver used 510 for C-SKY SMP system. 511 In fact it's not mmio map in hardware and it uses ld/st to visit the 512 controller's register inside CPU. 513 514config CSKY_APB_INTC 515 bool "C-SKY APB Interrupt Controller" 516 depends on CSKY 517 help 518 Say yes here to enable C-SKY APB interrupt controller driver used 519 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 520 the controller's register. 521 522config IMX_IRQSTEER 523 bool "i.MX IRQSTEER support" 524 depends on ARCH_MXC || COMPILE_TEST 525 default ARCH_MXC 526 select IRQ_DOMAIN 527 help 528 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 529 530config IMX_INTMUX 531 bool "i.MX INTMUX support" if COMPILE_TEST 532 default y if ARCH_MXC 533 select IRQ_DOMAIN 534 help 535 Support for the i.MX INTMUX interrupt multiplexer. 536 537config IMX_MU_MSI 538 tristate "i.MX MU used as MSI controller" 539 depends on OF && HAS_IOMEM 540 depends on ARCH_MXC || COMPILE_TEST 541 default m if ARCH_MXC 542 select IRQ_DOMAIN 543 select IRQ_DOMAIN_HIERARCHY 544 select GENERIC_MSI_IRQ 545 select IRQ_MSI_LIB 546 help 547 Provide a driver for the i.MX Messaging Unit block used as a 548 CPU-to-CPU MSI controller. This requires a specially crafted DT 549 to make use of this driver. 550 551 If unsure, say N 552 553config LS1X_IRQ 554 bool "Loongson-1 Interrupt Controller" 555 depends on MACH_LOONGSON32 556 default y 557 select IRQ_DOMAIN 558 select GENERIC_IRQ_CHIP 559 help 560 Support for the Loongson-1 platform Interrupt Controller. 561 562config TI_SCI_INTR_IRQCHIP 563 tristate "TI SCI INTR Interrupt Controller" 564 depends on TI_SCI_PROTOCOL 565 depends on ARCH_K3 || COMPILE_TEST 566 select IRQ_DOMAIN_HIERARCHY 567 help 568 This enables the irqchip driver support for K3 Interrupt router 569 over TI System Control Interface available on some new TI's SoCs. 570 If you wish to use interrupt router irq resources managed by the 571 TI System Controller, say Y here. Otherwise, say N. 572 573config TI_SCI_INTA_IRQCHIP 574 tristate "TI SCI INTA Interrupt Controller" 575 depends on TI_SCI_PROTOCOL 576 depends on ARCH_K3 || (COMPILE_TEST && ARM64) 577 select IRQ_DOMAIN_HIERARCHY 578 select TI_SCI_INTA_MSI_DOMAIN 579 help 580 This enables the irqchip driver support for K3 Interrupt aggregator 581 over TI System Control Interface available on some new TI's SoCs. 582 If you wish to use interrupt aggregator irq resources managed by the 583 TI System Controller, say Y here. Otherwise, say N. 584 585config TI_PRUSS_INTC 586 tristate 587 depends on TI_PRUSS 588 default TI_PRUSS 589 select IRQ_DOMAIN 590 help 591 This enables support for the PRU-ICSS Local Interrupt Controller 592 present within a PRU-ICSS subsystem present on various TI SoCs. 593 The PRUSS INTC enables various interrupts to be routed to multiple 594 different processors within the SoC. 595 596config RISCV_INTC 597 bool 598 depends on RISCV 599 select IRQ_DOMAIN_HIERARCHY 600 601config RISCV_APLIC 602 bool 603 depends on RISCV 604 select IRQ_DOMAIN_HIERARCHY 605 606config RISCV_APLIC_MSI 607 bool 608 depends on RISCV_APLIC 609 select GENERIC_MSI_IRQ 610 default RISCV_APLIC 611 612config RISCV_IMSIC 613 bool 614 depends on RISCV 615 select IRQ_DOMAIN_HIERARCHY 616 select GENERIC_IRQ_MATRIX_ALLOCATOR 617 select GENERIC_MSI_IRQ 618 select IRQ_MSI_LIB 619 620config SIFIVE_PLIC 621 bool 622 depends on RISCV 623 select IRQ_DOMAIN_HIERARCHY 624 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 625 626config STARFIVE_JH8100_INTC 627 bool "StarFive JH8100 External Interrupt Controller" 628 depends on ARCH_STARFIVE || COMPILE_TEST 629 default ARCH_STARFIVE 630 select IRQ_DOMAIN_HIERARCHY 631 help 632 This enables support for the INTC chip found in StarFive JH8100 633 SoC. 634 635 If you don't know what to do here, say Y. 636 637config THEAD_C900_ACLINT_SSWI 638 bool "THEAD C9XX ACLINT S-mode IPI Interrupt Controller" 639 depends on RISCV 640 depends on SMP 641 select IRQ_DOMAIN_HIERARCHY 642 select GENERIC_IRQ_IPI_MUX 643 help 644 This enables support for T-HEAD specific ACLINT SSWI device 645 support. 646 647 If you don't know what to do here, say Y. 648 649config EXYNOS_IRQ_COMBINER 650 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 651 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 652 help 653 Say yes here to add support for the IRQ combiner devices embedded 654 in Samsung Exynos chips. 655 656config IRQ_LOONGARCH_CPU 657 bool 658 select GENERIC_IRQ_CHIP 659 select IRQ_DOMAIN 660 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 661 select LOONGSON_HTVEC 662 select LOONGSON_LIOINTC 663 select LOONGSON_EIOINTC 664 select LOONGSON_PCH_PIC 665 select LOONGSON_PCH_MSI 666 select LOONGSON_PCH_LPC 667 help 668 Support for the LoongArch CPU Interrupt Controller. For details of 669 irq chip hierarchy on LoongArch platforms please read the document 670 Documentation/arch/loongarch/irq-chip-model.rst. 671 672config LOONGSON_LIOINTC 673 bool "Loongson Local I/O Interrupt Controller" 674 depends on MACH_LOONGSON64 675 default y 676 select IRQ_DOMAIN 677 select GENERIC_IRQ_CHIP 678 help 679 Support for the Loongson Local I/O Interrupt Controller. 680 681config LOONGSON_EIOINTC 682 bool "Loongson Extend I/O Interrupt Controller" 683 depends on LOONGARCH 684 depends on MACH_LOONGSON64 685 default MACH_LOONGSON64 686 select IRQ_DOMAIN_HIERARCHY 687 select GENERIC_IRQ_CHIP 688 help 689 Support for the Loongson3 Extend I/O Interrupt Vector Controller. 690 691config LOONGSON_HTPIC 692 bool "Loongson3 HyperTransport PIC Controller" 693 depends on MACH_LOONGSON64 && MIPS 694 default y 695 select IRQ_DOMAIN 696 select GENERIC_IRQ_CHIP 697 help 698 Support for the Loongson-3 HyperTransport PIC Controller. 699 700config LOONGSON_HTVEC 701 bool "Loongson HyperTransport Interrupt Vector Controller" 702 depends on MACH_LOONGSON64 703 default MACH_LOONGSON64 704 select IRQ_DOMAIN_HIERARCHY 705 help 706 Support for the Loongson HyperTransport Interrupt Vector Controller. 707 708config LOONGSON_PCH_PIC 709 bool "Loongson PCH PIC Controller" 710 depends on MACH_LOONGSON64 711 default MACH_LOONGSON64 712 select IRQ_DOMAIN_HIERARCHY 713 select IRQ_FASTEOI_HIERARCHY_HANDLERS 714 help 715 Support for the Loongson PCH PIC Controller. 716 717config LOONGSON_PCH_MSI 718 bool "Loongson PCH MSI Controller" 719 depends on MACH_LOONGSON64 720 depends on PCI 721 default MACH_LOONGSON64 722 select IRQ_DOMAIN_HIERARCHY 723 select IRQ_MSI_LIB 724 select PCI_MSI 725 help 726 Support for the Loongson PCH MSI Controller. 727 728config LOONGSON_PCH_LPC 729 bool "Loongson PCH LPC Controller" 730 depends on LOONGARCH 731 depends on MACH_LOONGSON64 732 default MACH_LOONGSON64 733 select IRQ_DOMAIN_HIERARCHY 734 help 735 Support for the Loongson PCH LPC Controller. 736 737config MST_IRQ 738 bool "MStar Interrupt Controller" 739 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 740 default ARCH_MEDIATEK 741 select IRQ_DOMAIN 742 select IRQ_DOMAIN_HIERARCHY 743 help 744 Support MStar Interrupt Controller. 745 746config WPCM450_AIC 747 bool "Nuvoton WPCM450 Advanced Interrupt Controller" 748 depends on ARCH_WPCM450 749 help 750 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 751 752config IRQ_IDT3243X 753 bool 754 select GENERIC_IRQ_CHIP 755 select IRQ_DOMAIN 756 757config APPLE_AIC 758 bool "Apple Interrupt Controller (AIC)" 759 depends on ARM64 760 depends on ARCH_APPLE || COMPILE_TEST 761 select GENERIC_IRQ_IPI_MUX 762 help 763 Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 764 such as the M1. 765 766config MCHP_EIC 767 bool "Microchip External Interrupt Controller" 768 depends on ARCH_AT91 || COMPILE_TEST 769 select IRQ_DOMAIN 770 select IRQ_DOMAIN_HIERARCHY 771 help 772 Support for Microchip External Interrupt Controller. 773 774config SOPHGO_SG2042_MSI 775 bool "Sophgo SG2042 MSI Controller" 776 depends on ARCH_SOPHGO || COMPILE_TEST 777 depends on PCI 778 select IRQ_DOMAIN_HIERARCHY 779 select IRQ_MSI_LIB 780 select PCI_MSI 781 help 782 Support for the Sophgo SG2042 MSI Controller. 783 This on-chip interrupt controller enables MSI sources to be 784 routed to the primary PLIC controller on SoC. 785 786config SUNPLUS_SP7021_INTC 787 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 788 default SOC_SP7021 789 help 790 Support for the Sunplus SP7021 Interrupt Controller IP core. 791 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 792 chained controller, routing all interrupt source in P-Chip to 793 the primary controller on C-Chip. 794 795endmenu 796