1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/acpi.h> 34 #include <linux/etherdevice.h> 35 #include <linux/interrupt.h> 36 #include <linux/iopoll.h> 37 #include <linux/kernel.h> 38 #include <linux/types.h> 39 #include <linux/workqueue.h> 40 #include <net/addrconf.h> 41 #include <rdma/ib_addr.h> 42 #include <rdma/ib_cache.h> 43 #include <rdma/ib_umem.h> 44 #include <rdma/uverbs_ioctl.h> 45 46 #include "hns_roce_common.h" 47 #include "hns_roce_device.h" 48 #include "hns_roce_cmd.h" 49 #include "hns_roce_hem.h" 50 #include "hns_roce_hw_v2.h" 51 52 #define CREATE_TRACE_POINTS 53 #include "hns_roce_trace.h" 54 55 enum { 56 CMD_RST_PRC_OTHERS, 57 CMD_RST_PRC_SUCCESS, 58 CMD_RST_PRC_EBUSY, 59 }; 60 61 enum ecc_resource_type { 62 ECC_RESOURCE_QPC, 63 ECC_RESOURCE_CQC, 64 ECC_RESOURCE_MPT, 65 ECC_RESOURCE_SRQC, 66 ECC_RESOURCE_GMV, 67 ECC_RESOURCE_QPC_TIMER, 68 ECC_RESOURCE_CQC_TIMER, 69 ECC_RESOURCE_SCCC, 70 ECC_RESOURCE_COUNT, 71 }; 72 73 static const struct { 74 const char *name; 75 u8 read_bt0_op; 76 u8 write_bt0_op; 77 } fmea_ram_res[] = { 78 { "ECC_RESOURCE_QPC", 79 HNS_ROCE_CMD_READ_QPC_BT0, HNS_ROCE_CMD_WRITE_QPC_BT0 }, 80 { "ECC_RESOURCE_CQC", 81 HNS_ROCE_CMD_READ_CQC_BT0, HNS_ROCE_CMD_WRITE_CQC_BT0 }, 82 { "ECC_RESOURCE_MPT", 83 HNS_ROCE_CMD_READ_MPT_BT0, HNS_ROCE_CMD_WRITE_MPT_BT0 }, 84 { "ECC_RESOURCE_SRQC", 85 HNS_ROCE_CMD_READ_SRQC_BT0, HNS_ROCE_CMD_WRITE_SRQC_BT0 }, 86 /* ECC_RESOURCE_GMV is handled by cmdq, not mailbox */ 87 { "ECC_RESOURCE_GMV", 88 0, 0 }, 89 { "ECC_RESOURCE_QPC_TIMER", 90 HNS_ROCE_CMD_READ_QPC_TIMER_BT0, HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0 }, 91 { "ECC_RESOURCE_CQC_TIMER", 92 HNS_ROCE_CMD_READ_CQC_TIMER_BT0, HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0 }, 93 { "ECC_RESOURCE_SCCC", 94 HNS_ROCE_CMD_READ_SCCC_BT0, HNS_ROCE_CMD_WRITE_SCCC_BT0 }, 95 }; 96 97 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, 98 struct ib_sge *sg) 99 { 100 dseg->lkey = cpu_to_le32(sg->lkey); 101 dseg->addr = cpu_to_le64(sg->addr); 102 dseg->len = cpu_to_le32(sg->length); 103 } 104 105 /* 106 * mapped-value = 1 + real-value 107 * The hns wr opcode real value is start from 0, In order to distinguish between 108 * initialized and uninitialized map values, we plus 1 to the actual value when 109 * defining the mapping, so that the validity can be identified by checking the 110 * mapped value is greater than 0. 111 */ 112 #define HR_OPC_MAP(ib_key, hr_key) \ 113 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key 114 115 static const u32 hns_roce_op_code[] = { 116 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE), 117 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM), 118 HR_OPC_MAP(SEND, SEND), 119 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM), 120 HR_OPC_MAP(RDMA_READ, RDMA_READ), 121 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP), 122 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD), 123 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV), 124 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP), 125 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD), 126 HR_OPC_MAP(REG_MR, FAST_REG_PMR), 127 }; 128 129 static u32 to_hr_opcode(u32 ib_opcode) 130 { 131 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code)) 132 return HNS_ROCE_V2_WQE_OP_MASK; 133 134 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 : 135 HNS_ROCE_V2_WQE_OP_MASK; 136 } 137 138 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 139 const struct ib_reg_wr *wr) 140 { 141 struct hns_roce_wqe_frmr_seg *fseg = 142 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 143 struct hns_roce_mr *mr = to_hr_mr(wr->mr); 144 u64 pbl_ba; 145 146 /* use ib_access_flags */ 147 hr_reg_write_bool(fseg, FRMR_BIND_EN, wr->access & IB_ACCESS_MW_BIND); 148 hr_reg_write_bool(fseg, FRMR_ATOMIC, 149 wr->access & IB_ACCESS_REMOTE_ATOMIC); 150 hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ); 151 hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE); 152 hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE); 153 154 /* Data structure reuse may lead to confusion */ 155 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba; 156 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba)); 157 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba)); 158 159 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff); 160 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32); 161 rc_sq_wqe->rkey = cpu_to_le32(wr->key); 162 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova); 163 164 hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages); 165 hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ, 166 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 167 hr_reg_clear(fseg, FRMR_BLK_MODE); 168 } 169 170 static void set_atomic_seg(const struct ib_send_wr *wr, 171 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 172 unsigned int valid_num_sge) 173 { 174 struct hns_roce_v2_wqe_data_seg *dseg = 175 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 176 struct hns_roce_wqe_atomic_seg *aseg = 177 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg); 178 179 set_data_seg_v2(dseg, wr->sg_list); 180 181 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 182 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap); 183 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add); 184 } else { 185 aseg->fetchadd_swap_data = 186 cpu_to_le64(atomic_wr(wr)->compare_add); 187 aseg->cmp_data = 0; 188 } 189 190 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 191 } 192 193 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp, 194 const struct ib_send_wr *wr, 195 unsigned int *sge_idx, u32 msg_len) 196 { 197 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev; 198 unsigned int left_len_in_pg; 199 unsigned int idx = *sge_idx; 200 unsigned int i = 0; 201 unsigned int len; 202 void *addr; 203 void *dseg; 204 205 if (msg_len > qp->sq.ext_sge_cnt * HNS_ROCE_SGE_SIZE) { 206 ibdev_err(ibdev, 207 "no enough extended sge space for inline data.\n"); 208 return -EINVAL; 209 } 210 211 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 212 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg; 213 len = wr->sg_list[0].length; 214 addr = (void *)(unsigned long)(wr->sg_list[0].addr); 215 216 /* When copying data to extended sge space, the left length in page may 217 * not long enough for current user's sge. So the data should be 218 * splited into several parts, one in the first page, and the others in 219 * the subsequent pages. 220 */ 221 while (1) { 222 if (len <= left_len_in_pg) { 223 memcpy(dseg, addr, len); 224 225 idx += len / HNS_ROCE_SGE_SIZE; 226 227 i++; 228 if (i >= wr->num_sge) 229 break; 230 231 left_len_in_pg -= len; 232 len = wr->sg_list[i].length; 233 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 234 dseg += len; 235 } else { 236 memcpy(dseg, addr, left_len_in_pg); 237 238 len -= left_len_in_pg; 239 addr += left_len_in_pg; 240 idx += left_len_in_pg / HNS_ROCE_SGE_SIZE; 241 dseg = hns_roce_get_extend_sge(qp, 242 idx & (qp->sge.sge_cnt - 1)); 243 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT; 244 } 245 } 246 247 *sge_idx = idx; 248 249 return 0; 250 } 251 252 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge, 253 unsigned int *sge_ind, unsigned int cnt) 254 { 255 struct hns_roce_v2_wqe_data_seg *dseg; 256 unsigned int idx = *sge_ind; 257 258 while (cnt > 0) { 259 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 260 if (likely(sge->length)) { 261 set_data_seg_v2(dseg, sge); 262 idx++; 263 cnt--; 264 } 265 sge++; 266 } 267 268 *sge_ind = idx; 269 } 270 271 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len) 272 { 273 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 274 int mtu = ib_mtu_enum_to_int(qp->path_mtu); 275 276 if (mtu < 0 || len > qp->max_inline_data || len > mtu) { 277 ibdev_err(&hr_dev->ib_dev, 278 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n", 279 len, qp->max_inline_data, mtu); 280 return false; 281 } 282 283 return true; 284 } 285 286 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr, 287 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 288 unsigned int *sge_idx) 289 { 290 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 291 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len); 292 struct ib_device *ibdev = &hr_dev->ib_dev; 293 unsigned int curr_idx = *sge_idx; 294 void *dseg = rc_sq_wqe; 295 unsigned int i; 296 int ret; 297 298 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) { 299 ibdev_err(ibdev, "invalid inline parameters!\n"); 300 return -EINVAL; 301 } 302 303 if (!check_inl_data_len(qp, msg_len)) 304 return -EINVAL; 305 306 dseg += sizeof(struct hns_roce_v2_rc_send_wqe); 307 308 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) { 309 hr_reg_clear(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 310 311 for (i = 0; i < wr->num_sge; i++) { 312 memcpy(dseg, ((void *)wr->sg_list[i].addr), 313 wr->sg_list[i].length); 314 dseg += wr->sg_list[i].length; 315 } 316 } else { 317 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 318 319 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len); 320 if (ret) 321 return ret; 322 323 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, curr_idx - *sge_idx); 324 } 325 326 *sge_idx = curr_idx; 327 328 return 0; 329 } 330 331 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr, 332 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 333 unsigned int *sge_ind, 334 unsigned int valid_num_sge) 335 { 336 struct hns_roce_v2_wqe_data_seg *dseg = 337 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 338 struct hns_roce_qp *qp = to_hr_qp(ibqp); 339 int j = 0; 340 int i; 341 342 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_MSG_START_SGE_IDX, 343 (*sge_ind) & (qp->sge.sge_cnt - 1)); 344 345 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_INLINE, 346 !!(wr->send_flags & IB_SEND_INLINE)); 347 if (wr->send_flags & IB_SEND_INLINE) 348 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind); 349 350 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) { 351 for (i = 0; i < wr->num_sge; i++) { 352 if (likely(wr->sg_list[i].length)) { 353 set_data_seg_v2(dseg, wr->sg_list + i); 354 dseg++; 355 } 356 } 357 } else { 358 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) { 359 if (likely(wr->sg_list[i].length)) { 360 set_data_seg_v2(dseg, wr->sg_list + i); 361 dseg++; 362 j++; 363 } 364 } 365 366 set_extend_sge(qp, wr->sg_list + i, sge_ind, 367 valid_num_sge - HNS_ROCE_SGE_IN_WQE); 368 } 369 370 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 371 372 return 0; 373 } 374 375 static int check_send_valid(struct hns_roce_dev *hr_dev, 376 struct hns_roce_qp *hr_qp) 377 { 378 if (unlikely(hr_qp->state == IB_QPS_RESET || 379 hr_qp->state == IB_QPS_INIT || 380 hr_qp->state == IB_QPS_RTR)) 381 return -EINVAL; 382 else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 383 return -EIO; 384 385 return 0; 386 } 387 388 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr, 389 unsigned int *sge_len) 390 { 391 unsigned int valid_num = 0; 392 unsigned int len = 0; 393 int i; 394 395 for (i = 0; i < wr->num_sge; i++) { 396 if (likely(wr->sg_list[i].length)) { 397 len += wr->sg_list[i].length; 398 valid_num++; 399 } 400 } 401 402 *sge_len = len; 403 return valid_num; 404 } 405 406 static __le32 get_immtdata(const struct ib_send_wr *wr) 407 { 408 switch (wr->opcode) { 409 case IB_WR_SEND_WITH_IMM: 410 case IB_WR_RDMA_WRITE_WITH_IMM: 411 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 412 default: 413 return 0; 414 } 415 } 416 417 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 418 const struct ib_send_wr *wr) 419 { 420 u32 ib_op = wr->opcode; 421 422 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM) 423 return -EINVAL; 424 425 ud_sq_wqe->immtdata = get_immtdata(wr); 426 427 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 428 429 return 0; 430 } 431 432 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 433 struct hns_roce_ah *ah) 434 { 435 struct ib_device *ib_dev = ah->ibah.device; 436 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 437 438 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_UDPSPN, ah->av.udp_sport); 439 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_HOPLIMIT, ah->av.hop_limit); 440 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_TCLASS, ah->av.tclass); 441 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_FLOW_LABEL, ah->av.flowlabel); 442 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SL, ah->av.sl); 443 444 ud_sq_wqe->sgid_index = ah->av.gid_index; 445 446 memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN); 447 memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2); 448 449 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 450 return 0; 451 452 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN_EN, ah->av.vlan_en); 453 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN, ah->av.vlan_id); 454 455 return 0; 456 } 457 458 static inline int set_ud_wqe(struct hns_roce_qp *qp, 459 const struct ib_send_wr *wr, 460 void *wqe, unsigned int *sge_idx, 461 unsigned int owner_bit) 462 { 463 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 464 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe; 465 unsigned int curr_idx = *sge_idx; 466 unsigned int valid_num_sge; 467 u32 msg_len = 0; 468 int ret; 469 470 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 471 472 ret = set_ud_opcode(ud_sq_wqe, wr); 473 if (WARN_ON_ONCE(ret)) 474 return ret; 475 476 ud_sq_wqe->msg_len = cpu_to_le32(msg_len); 477 478 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_CQE, 479 !!(wr->send_flags & IB_SEND_SIGNALED)); 480 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SE, 481 !!(wr->send_flags & IB_SEND_SOLICITED)); 482 483 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_PD, to_hr_pd(qp->ibqp.pd)->pdn); 484 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SGE_NUM, valid_num_sge); 485 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_MSG_START_SGE_IDX, 486 curr_idx & (qp->sge.sge_cnt - 1)); 487 488 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ? 489 qp->qkey : ud_wr(wr)->remote_qkey); 490 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_DQPN, ud_wr(wr)->remote_qpn); 491 492 ret = fill_ud_av(ud_sq_wqe, ah); 493 if (ret) 494 return ret; 495 496 qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl; 497 498 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge); 499 500 /* 501 * The pipeline can sequentially post all valid WQEs into WQ buffer, 502 * including new WQEs waiting for the doorbell to update the PI again. 503 * Therefore, the owner bit of WQE MUST be updated after all fields 504 * and extSGEs have been written into DDR instead of cache. 505 */ 506 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 507 dma_wmb(); 508 509 *sge_idx = curr_idx; 510 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OWNER, owner_bit); 511 512 return 0; 513 } 514 515 static int set_rc_opcode(struct hns_roce_dev *hr_dev, 516 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 517 const struct ib_send_wr *wr) 518 { 519 u32 ib_op = wr->opcode; 520 int ret = 0; 521 522 rc_sq_wqe->immtdata = get_immtdata(wr); 523 524 switch (ib_op) { 525 case IB_WR_RDMA_READ: 526 case IB_WR_RDMA_WRITE: 527 case IB_WR_RDMA_WRITE_WITH_IMM: 528 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey); 529 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr); 530 break; 531 case IB_WR_SEND: 532 case IB_WR_SEND_WITH_IMM: 533 break; 534 case IB_WR_ATOMIC_CMP_AND_SWP: 535 case IB_WR_ATOMIC_FETCH_AND_ADD: 536 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey); 537 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr); 538 break; 539 case IB_WR_REG_MR: 540 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 541 set_frmr_seg(rc_sq_wqe, reg_wr(wr)); 542 else 543 ret = -EOPNOTSUPP; 544 break; 545 case IB_WR_SEND_WITH_INV: 546 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); 547 break; 548 default: 549 ret = -EINVAL; 550 } 551 552 if (unlikely(ret)) 553 return ret; 554 555 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 556 557 return ret; 558 } 559 560 static inline int set_rc_wqe(struct hns_roce_qp *qp, 561 const struct ib_send_wr *wr, 562 void *wqe, unsigned int *sge_idx, 563 unsigned int owner_bit) 564 { 565 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 566 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 567 unsigned int curr_idx = *sge_idx; 568 unsigned int valid_num_sge; 569 u32 msg_len = 0; 570 int ret; 571 572 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 573 574 rc_sq_wqe->msg_len = cpu_to_le32(msg_len); 575 576 ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr); 577 if (WARN_ON_ONCE(ret)) 578 return ret; 579 580 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SO, 581 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); 582 583 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SE, 584 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 585 586 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_CQE, 587 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 588 589 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP || 590 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) { 591 if (msg_len != ATOMIC_WR_LEN) 592 return -EINVAL; 593 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge); 594 } else if (wr->opcode != IB_WR_REG_MR) { 595 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe, 596 &curr_idx, valid_num_sge); 597 if (ret) 598 return ret; 599 } 600 601 /* 602 * The pipeline can sequentially post all valid WQEs into WQ buffer, 603 * including new WQEs waiting for the doorbell to update the PI again. 604 * Therefore, the owner bit of WQE MUST be updated after all fields 605 * and extSGEs have been written into DDR instead of cache. 606 */ 607 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 608 dma_wmb(); 609 610 *sge_idx = curr_idx; 611 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OWNER, owner_bit); 612 613 return ret; 614 } 615 616 static inline void update_sq_db(struct hns_roce_dev *hr_dev, 617 struct hns_roce_qp *qp) 618 { 619 if (unlikely(qp->state == IB_QPS_ERR)) { 620 flush_cqe(hr_dev, qp); 621 } else { 622 struct hns_roce_v2_db sq_db = {}; 623 624 hr_reg_write(&sq_db, DB_TAG, qp->qpn); 625 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB); 626 hr_reg_write(&sq_db, DB_PI, qp->sq.head); 627 hr_reg_write(&sq_db, DB_SL, qp->sl); 628 629 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg); 630 } 631 } 632 633 static inline void update_rq_db(struct hns_roce_dev *hr_dev, 634 struct hns_roce_qp *qp) 635 { 636 if (unlikely(qp->state == IB_QPS_ERR)) { 637 flush_cqe(hr_dev, qp); 638 } else { 639 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) { 640 *qp->rdb.db_record = 641 qp->rq.head & V2_DB_PRODUCER_IDX_M; 642 } else { 643 struct hns_roce_v2_db rq_db = {}; 644 645 hr_reg_write(&rq_db, DB_TAG, qp->qpn); 646 hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB); 647 hr_reg_write(&rq_db, DB_PI, qp->rq.head); 648 649 hns_roce_write64(hr_dev, (__le32 *)&rq_db, 650 qp->rq.db_reg); 651 } 652 } 653 } 654 655 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val, 656 u64 __iomem *dest) 657 { 658 #define HNS_ROCE_WRITE_TIMES 8 659 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 660 struct hnae3_handle *handle = priv->handle; 661 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 662 int i; 663 664 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle)) 665 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++) 666 writeq_relaxed(*(val + i), dest + i); 667 } 668 669 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 670 void *wqe) 671 { 672 #define HNS_ROCE_SL_SHIFT 2 673 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 674 675 if (unlikely(qp->state == IB_QPS_ERR)) { 676 flush_cqe(hr_dev, qp); 677 return; 678 } 679 /* All kinds of DirectWQE have the same header field layout */ 680 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_FLAG); 681 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_L, qp->sl); 682 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_H, 683 qp->sl >> HNS_ROCE_SL_SHIFT); 684 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_WQE_INDEX, qp->sq.head); 685 686 hns_roce_write512(hr_dev, wqe, qp->sq.db_reg); 687 } 688 689 static int hns_roce_v2_post_send(struct ib_qp *ibqp, 690 const struct ib_send_wr *wr, 691 const struct ib_send_wr **bad_wr) 692 { 693 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 694 struct ib_device *ibdev = &hr_dev->ib_dev; 695 struct hns_roce_qp *qp = to_hr_qp(ibqp); 696 unsigned long flags = 0; 697 unsigned int owner_bit; 698 unsigned int sge_idx; 699 unsigned int wqe_idx; 700 void *wqe = NULL; 701 u32 nreq; 702 int ret; 703 704 spin_lock_irqsave(&qp->sq.lock, flags); 705 706 ret = check_send_valid(hr_dev, qp); 707 if (unlikely(ret)) { 708 *bad_wr = wr; 709 nreq = 0; 710 goto out; 711 } 712 713 sge_idx = qp->next_sge; 714 715 for (nreq = 0; wr; ++nreq, wr = wr->next) { 716 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 717 ret = -ENOMEM; 718 *bad_wr = wr; 719 goto out; 720 } 721 722 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1); 723 724 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 725 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n", 726 wr->num_sge, qp->sq.max_gs); 727 ret = -EINVAL; 728 *bad_wr = wr; 729 goto out; 730 } 731 732 wqe = hns_roce_get_send_wqe(qp, wqe_idx); 733 qp->sq.wrid[wqe_idx] = wr->wr_id; 734 owner_bit = 735 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1); 736 737 /* Corresponding to the QP type, wqe process separately */ 738 if (ibqp->qp_type == IB_QPT_RC) 739 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit); 740 else 741 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit); 742 743 trace_hns_sq_wqe(qp->qpn, wqe_idx, wqe, 1 << qp->sq.wqe_shift, 744 wr->wr_id, TRACE_SQ); 745 if (unlikely(ret)) { 746 *bad_wr = wr; 747 goto out; 748 } 749 } 750 751 out: 752 if (likely(nreq)) { 753 qp->sq.head += nreq; 754 qp->next_sge = sge_idx; 755 756 if (nreq == 1 && !ret && 757 (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE)) 758 write_dwqe(hr_dev, qp, wqe); 759 else 760 update_sq_db(hr_dev, qp); 761 } 762 763 spin_unlock_irqrestore(&qp->sq.lock, flags); 764 765 return ret; 766 } 767 768 static int check_recv_valid(struct hns_roce_dev *hr_dev, 769 struct hns_roce_qp *hr_qp) 770 { 771 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 772 return -EIO; 773 774 if (hr_qp->state == IB_QPS_RESET) 775 return -EINVAL; 776 777 return 0; 778 } 779 780 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe, 781 u32 max_sge, bool rsv) 782 { 783 struct hns_roce_v2_wqe_data_seg *dseg = wqe; 784 u32 i, cnt; 785 786 for (i = 0, cnt = 0; i < wr->num_sge; i++) { 787 /* Skip zero-length sge */ 788 if (!wr->sg_list[i].length) 789 continue; 790 set_data_seg_v2(dseg + cnt, wr->sg_list + i); 791 cnt++; 792 } 793 794 /* Fill a reserved sge to make hw stop reading remaining segments */ 795 if (rsv) { 796 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 797 dseg[cnt].addr = 0; 798 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH); 799 } else { 800 /* Clear remaining segments to make ROCEE ignore sges */ 801 if (cnt < max_sge) 802 memset(dseg + cnt, 0, 803 (max_sge - cnt) * HNS_ROCE_SGE_SIZE); 804 } 805 } 806 807 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr, 808 u32 wqe_idx, u32 max_sge) 809 { 810 void *wqe = NULL; 811 812 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx); 813 fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge); 814 815 trace_hns_rq_wqe(hr_qp->qpn, wqe_idx, wqe, 1 << hr_qp->rq.wqe_shift, 816 wr->wr_id, TRACE_RQ); 817 } 818 819 static int hns_roce_v2_post_recv(struct ib_qp *ibqp, 820 const struct ib_recv_wr *wr, 821 const struct ib_recv_wr **bad_wr) 822 { 823 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 824 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 825 struct ib_device *ibdev = &hr_dev->ib_dev; 826 u32 wqe_idx, nreq, max_sge; 827 unsigned long flags; 828 int ret; 829 830 spin_lock_irqsave(&hr_qp->rq.lock, flags); 831 832 ret = check_recv_valid(hr_dev, hr_qp); 833 if (unlikely(ret)) { 834 *bad_wr = wr; 835 nreq = 0; 836 goto out; 837 } 838 839 max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 840 for (nreq = 0; wr; ++nreq, wr = wr->next) { 841 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq, 842 hr_qp->ibqp.recv_cq))) { 843 ret = -ENOMEM; 844 *bad_wr = wr; 845 goto out; 846 } 847 848 if (unlikely(wr->num_sge > max_sge)) { 849 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n", 850 wr->num_sge, max_sge); 851 ret = -EINVAL; 852 *bad_wr = wr; 853 goto out; 854 } 855 856 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1); 857 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge); 858 hr_qp->rq.wrid[wqe_idx] = wr->wr_id; 859 } 860 861 out: 862 if (likely(nreq)) { 863 hr_qp->rq.head += nreq; 864 865 update_rq_db(hr_dev, hr_qp); 866 } 867 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 868 869 return ret; 870 } 871 872 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n) 873 { 874 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift); 875 } 876 877 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n) 878 { 879 return hns_roce_buf_offset(idx_que->mtr.kmem, 880 n << idx_que->entry_shift); 881 } 882 883 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index) 884 { 885 /* always called with interrupts disabled. */ 886 spin_lock(&srq->lock); 887 888 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1); 889 srq->idx_que.tail++; 890 891 spin_unlock(&srq->lock); 892 } 893 894 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq) 895 { 896 struct hns_roce_idx_que *idx_que = &srq->idx_que; 897 898 return idx_que->head - idx_que->tail >= srq->wqe_cnt; 899 } 900 901 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge, 902 const struct ib_recv_wr *wr) 903 { 904 struct ib_device *ib_dev = srq->ibsrq.device; 905 906 if (unlikely(wr->num_sge > max_sge)) { 907 ibdev_err(ib_dev, 908 "failed to check sge, wr->num_sge = %d, max_sge = %u.\n", 909 wr->num_sge, max_sge); 910 return -EINVAL; 911 } 912 913 if (unlikely(hns_roce_srqwq_overflow(srq))) { 914 ibdev_err(ib_dev, 915 "failed to check srqwq status, srqwq is full.\n"); 916 return -ENOMEM; 917 } 918 919 return 0; 920 } 921 922 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx) 923 { 924 struct hns_roce_idx_que *idx_que = &srq->idx_que; 925 u32 pos; 926 927 pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt); 928 if (unlikely(pos == srq->wqe_cnt)) 929 return -ENOSPC; 930 931 bitmap_set(idx_que->bitmap, pos, 1); 932 *wqe_idx = pos; 933 return 0; 934 } 935 936 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx) 937 { 938 struct hns_roce_idx_que *idx_que = &srq->idx_que; 939 unsigned int head; 940 __le32 *buf; 941 942 head = idx_que->head & (srq->wqe_cnt - 1); 943 944 buf = get_idx_buf(idx_que, head); 945 *buf = cpu_to_le32(wqe_idx); 946 947 idx_que->head++; 948 } 949 950 static void update_srq_db(struct hns_roce_srq *srq) 951 { 952 struct hns_roce_dev *hr_dev = to_hr_dev(srq->ibsrq.device); 953 struct hns_roce_v2_db db = {}; 954 955 hr_reg_write(&db, DB_TAG, srq->srqn); 956 hr_reg_write(&db, DB_CMD, HNS_ROCE_V2_SRQ_DB); 957 hr_reg_write(&db, DB_PI, srq->idx_que.head); 958 959 hns_roce_write64(hr_dev, (__le32 *)&db, srq->db_reg); 960 } 961 962 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq, 963 const struct ib_recv_wr *wr, 964 const struct ib_recv_wr **bad_wr) 965 { 966 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 967 unsigned long flags; 968 int ret = 0; 969 u32 max_sge; 970 u32 wqe_idx; 971 void *wqe; 972 u32 nreq; 973 974 spin_lock_irqsave(&srq->lock, flags); 975 976 max_sge = srq->max_gs - srq->rsv_sge; 977 for (nreq = 0; wr; ++nreq, wr = wr->next) { 978 ret = check_post_srq_valid(srq, max_sge, wr); 979 if (ret) { 980 *bad_wr = wr; 981 break; 982 } 983 984 ret = get_srq_wqe_idx(srq, &wqe_idx); 985 if (unlikely(ret)) { 986 *bad_wr = wr; 987 break; 988 } 989 990 wqe = get_srq_wqe_buf(srq, wqe_idx); 991 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge); 992 fill_wqe_idx(srq, wqe_idx); 993 srq->wrid[wqe_idx] = wr->wr_id; 994 995 trace_hns_srq_wqe(srq->srqn, wqe_idx, wqe, 1 << srq->wqe_shift, 996 wr->wr_id, TRACE_SRQ); 997 } 998 999 if (likely(nreq)) { 1000 if (srq->cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB) 1001 *srq->rdb.db_record = srq->idx_que.head & 1002 V2_DB_PRODUCER_IDX_M; 1003 else 1004 update_srq_db(srq); 1005 } 1006 1007 spin_unlock_irqrestore(&srq->lock, flags); 1008 1009 return ret; 1010 } 1011 1012 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev, 1013 unsigned long instance_stage, 1014 unsigned long reset_stage) 1015 { 1016 /* When hardware reset has been completed once or more, we should stop 1017 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance() 1018 * function, we should exit with error. If now at HNAE3_INIT_CLIENT 1019 * stage of soft reset process, we should exit with error, and then 1020 * HNAE3_INIT_CLIENT related process can rollback the operation like 1021 * notifing hardware to free resources, HNAE3_INIT_CLIENT related 1022 * process will exit with error to notify NIC driver to reschedule soft 1023 * reset process once again. 1024 */ 1025 hr_dev->is_reset = true; 1026 hr_dev->dis_db = true; 1027 1028 if (reset_stage == HNS_ROCE_STATE_RST_INIT || 1029 instance_stage == HNS_ROCE_STATE_INIT) 1030 return CMD_RST_PRC_EBUSY; 1031 1032 return CMD_RST_PRC_SUCCESS; 1033 } 1034 1035 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev, 1036 unsigned long instance_stage, 1037 unsigned long reset_stage) 1038 { 1039 #define HW_RESET_TIMEOUT_US 1000000 1040 #define HW_RESET_SLEEP_US 1000 1041 1042 struct hns_roce_v2_priv *priv = hr_dev->priv; 1043 struct hnae3_handle *handle = priv->handle; 1044 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1045 unsigned long val; 1046 int ret; 1047 1048 /* When hardware reset is detected, we should stop sending mailbox&cmq& 1049 * doorbell to hardware. If now in .init_instance() function, we should 1050 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset 1051 * process, we should exit with error, and then HNAE3_INIT_CLIENT 1052 * related process can rollback the operation like notifing hardware to 1053 * free resources, HNAE3_INIT_CLIENT related process will exit with 1054 * error to notify NIC driver to reschedule soft reset process once 1055 * again. 1056 */ 1057 hr_dev->dis_db = true; 1058 1059 ret = read_poll_timeout(ops->ae_dev_reset_cnt, val, 1060 val > hr_dev->reset_cnt, HW_RESET_SLEEP_US, 1061 HW_RESET_TIMEOUT_US, false, handle); 1062 if (!ret) 1063 hr_dev->is_reset = true; 1064 1065 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT || 1066 instance_stage == HNS_ROCE_STATE_INIT) 1067 return CMD_RST_PRC_EBUSY; 1068 1069 return CMD_RST_PRC_SUCCESS; 1070 } 1071 1072 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev) 1073 { 1074 struct hns_roce_v2_priv *priv = hr_dev->priv; 1075 struct hnae3_handle *handle = priv->handle; 1076 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1077 1078 /* When software reset is detected at .init_instance() function, we 1079 * should stop sending mailbox&cmq&doorbell to hardware, and exit 1080 * with error. 1081 */ 1082 hr_dev->dis_db = true; 1083 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) 1084 hr_dev->is_reset = true; 1085 1086 return CMD_RST_PRC_EBUSY; 1087 } 1088 1089 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev, 1090 struct hnae3_handle *handle) 1091 { 1092 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1093 unsigned long instance_stage; /* the current instance stage */ 1094 unsigned long reset_stage; /* the current reset stage */ 1095 unsigned long reset_cnt; 1096 bool sw_resetting; 1097 bool hw_resetting; 1098 1099 /* Get information about reset from NIC driver or RoCE driver itself, 1100 * the meaning of the following variables from NIC driver are described 1101 * as below: 1102 * reset_cnt -- The count value of completed hardware reset. 1103 * hw_resetting -- Whether hardware device is resetting now. 1104 * sw_resetting -- Whether NIC's software reset process is running now. 1105 */ 1106 instance_stage = handle->rinfo.instance_state; 1107 reset_stage = handle->rinfo.reset_state; 1108 reset_cnt = ops->ae_dev_reset_cnt(handle); 1109 if (reset_cnt != hr_dev->reset_cnt) 1110 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage, 1111 reset_stage); 1112 1113 hw_resetting = ops->get_cmdq_stat(handle); 1114 if (hw_resetting) 1115 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage, 1116 reset_stage); 1117 1118 sw_resetting = ops->ae_dev_resetting(handle); 1119 if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) 1120 return hns_roce_v2_cmd_sw_resetting(hr_dev); 1121 1122 return CMD_RST_PRC_OTHERS; 1123 } 1124 1125 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev) 1126 { 1127 struct hns_roce_v2_priv *priv = hr_dev->priv; 1128 struct hnae3_handle *handle = priv->handle; 1129 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1130 1131 if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle)) 1132 return true; 1133 1134 if (ops->get_hw_reset_stat(handle)) 1135 return true; 1136 1137 if (ops->ae_dev_resetting(handle)) 1138 return true; 1139 1140 return false; 1141 } 1142 1143 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy) 1144 { 1145 struct hns_roce_v2_priv *priv = hr_dev->priv; 1146 u32 status; 1147 1148 if (hr_dev->is_reset) 1149 status = CMD_RST_PRC_SUCCESS; 1150 else 1151 status = check_aedev_reset_status(hr_dev, priv->handle); 1152 1153 *busy = (status == CMD_RST_PRC_EBUSY); 1154 1155 return status == CMD_RST_PRC_OTHERS; 1156 } 1157 1158 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, 1159 struct hns_roce_v2_cmq_ring *ring) 1160 { 1161 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); 1162 1163 ring->desc = dma_alloc_coherent(hr_dev->dev, size, 1164 &ring->desc_dma_addr, GFP_KERNEL); 1165 if (!ring->desc) 1166 return -ENOMEM; 1167 1168 return 0; 1169 } 1170 1171 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, 1172 struct hns_roce_v2_cmq_ring *ring) 1173 { 1174 dma_free_coherent(hr_dev->dev, 1175 ring->desc_num * sizeof(struct hns_roce_cmq_desc), 1176 ring->desc, ring->desc_dma_addr); 1177 1178 ring->desc_dma_addr = 0; 1179 } 1180 1181 static int init_csq(struct hns_roce_dev *hr_dev, 1182 struct hns_roce_v2_cmq_ring *csq) 1183 { 1184 dma_addr_t dma; 1185 int ret; 1186 1187 csq->desc_num = CMD_CSQ_DESC_NUM; 1188 spin_lock_init(&csq->lock); 1189 csq->flag = TYPE_CSQ; 1190 csq->head = 0; 1191 1192 ret = hns_roce_alloc_cmq_desc(hr_dev, csq); 1193 if (ret) 1194 return ret; 1195 1196 dma = csq->desc_dma_addr; 1197 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma)); 1198 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma)); 1199 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, 1200 (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); 1201 1202 /* Make sure to write CI first and then PI */ 1203 roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0); 1204 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0); 1205 1206 return 0; 1207 } 1208 1209 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) 1210 { 1211 struct hns_roce_v2_priv *priv = hr_dev->priv; 1212 int ret; 1213 1214 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; 1215 1216 ret = init_csq(hr_dev, &priv->cmq.csq); 1217 if (ret) 1218 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret); 1219 1220 return ret; 1221 } 1222 1223 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) 1224 { 1225 struct hns_roce_v2_priv *priv = hr_dev->priv; 1226 1227 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 1228 } 1229 1230 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 1231 enum hns_roce_opcode_type opcode, 1232 bool is_read) 1233 { 1234 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); 1235 desc->opcode = cpu_to_le16(opcode); 1236 desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1237 if (is_read) 1238 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); 1239 else 1240 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1241 } 1242 1243 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) 1244 { 1245 u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1246 struct hns_roce_v2_priv *priv = hr_dev->priv; 1247 1248 return tail == priv->cmq.csq.head; 1249 } 1250 1251 static void update_cmdq_status(struct hns_roce_dev *hr_dev) 1252 { 1253 struct hns_roce_v2_priv *priv = hr_dev->priv; 1254 struct hnae3_handle *handle = priv->handle; 1255 1256 if (handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 1257 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) 1258 hr_dev->cmd.state = HNS_ROCE_CMDQ_STATE_FATAL_ERR; 1259 } 1260 1261 static int hns_roce_cmd_err_convert_errno(u16 desc_ret) 1262 { 1263 struct hns_roce_cmd_errcode errcode_table[] = { 1264 {CMD_EXEC_SUCCESS, 0}, 1265 {CMD_NO_AUTH, -EPERM}, 1266 {CMD_NOT_EXIST, -EOPNOTSUPP}, 1267 {CMD_CRQ_FULL, -EXFULL}, 1268 {CMD_NEXT_ERR, -ENOSR}, 1269 {CMD_NOT_EXEC, -ENOTBLK}, 1270 {CMD_PARA_ERR, -EINVAL}, 1271 {CMD_RESULT_ERR, -ERANGE}, 1272 {CMD_TIMEOUT, -ETIME}, 1273 {CMD_HILINK_ERR, -ENOLINK}, 1274 {CMD_INFO_ILLEGAL, -ENXIO}, 1275 {CMD_INVALID, -EBADR}, 1276 }; 1277 u16 i; 1278 1279 for (i = 0; i < ARRAY_SIZE(errcode_table); i++) 1280 if (desc_ret == errcode_table[i].return_status) 1281 return errcode_table[i].errno; 1282 return -EIO; 1283 } 1284 1285 static u32 hns_roce_cmdq_tx_timeout(u16 opcode, u32 tx_timeout) 1286 { 1287 static const struct hns_roce_cmdq_tx_timeout_map cmdq_tx_timeout[] = { 1288 {HNS_ROCE_OPC_POST_MB, HNS_ROCE_OPC_POST_MB_TIMEOUT}, 1289 }; 1290 int i; 1291 1292 for (i = 0; i < ARRAY_SIZE(cmdq_tx_timeout); i++) 1293 if (cmdq_tx_timeout[i].opcode == opcode) 1294 return cmdq_tx_timeout[i].tx_timeout; 1295 1296 return tx_timeout; 1297 } 1298 1299 static void hns_roce_wait_csq_done(struct hns_roce_dev *hr_dev, u32 tx_timeout) 1300 { 1301 u32 timeout = 0; 1302 1303 do { 1304 if (hns_roce_cmq_csq_done(hr_dev)) 1305 break; 1306 udelay(1); 1307 } while (++timeout < tx_timeout); 1308 } 1309 1310 static int __hns_roce_cmq_send_one(struct hns_roce_dev *hr_dev, 1311 struct hns_roce_cmq_desc *desc, 1312 int num, u32 tx_timeout) 1313 { 1314 struct hns_roce_v2_priv *priv = hr_dev->priv; 1315 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1316 u16 desc_ret; 1317 u32 tail; 1318 int ret; 1319 int i; 1320 1321 tail = csq->head; 1322 1323 for (i = 0; i < num; i++) { 1324 trace_hns_cmdq_req(hr_dev, &desc[i]); 1325 1326 csq->desc[csq->head++] = desc[i]; 1327 if (csq->head == csq->desc_num) 1328 csq->head = 0; 1329 } 1330 1331 /* Write to hardware */ 1332 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head); 1333 1334 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CMDS_CNT]); 1335 1336 hns_roce_wait_csq_done(hr_dev, tx_timeout); 1337 if (hns_roce_cmq_csq_done(hr_dev)) { 1338 ret = 0; 1339 for (i = 0; i < num; i++) { 1340 trace_hns_cmdq_resp(hr_dev, &csq->desc[tail]); 1341 1342 /* check the result of hardware write back */ 1343 desc_ret = le16_to_cpu(csq->desc[tail++].retval); 1344 if (tail == csq->desc_num) 1345 tail = 0; 1346 if (likely(desc_ret == CMD_EXEC_SUCCESS)) 1347 continue; 1348 1349 ret = hns_roce_cmd_err_convert_errno(desc_ret); 1350 } 1351 } else { 1352 /* FW/HW reset or incorrect number of desc */ 1353 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1354 dev_warn(hr_dev->dev, "CMDQ move tail from %u to %u.\n", 1355 csq->head, tail); 1356 csq->head = tail; 1357 1358 update_cmdq_status(hr_dev); 1359 1360 ret = -EAGAIN; 1361 } 1362 1363 if (ret) 1364 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CMDS_ERR_CNT]); 1365 1366 return ret; 1367 } 1368 1369 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1370 struct hns_roce_cmq_desc *desc, int num) 1371 { 1372 struct hns_roce_v2_priv *priv = hr_dev->priv; 1373 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1374 u16 opcode = le16_to_cpu(desc->opcode); 1375 u32 tx_timeout = hns_roce_cmdq_tx_timeout(opcode, priv->cmq.tx_timeout); 1376 u8 try_cnt = HNS_ROCE_OPC_POST_MB_TRY_CNT; 1377 u32 rsv_tail; 1378 int ret; 1379 int i; 1380 1381 while (try_cnt) { 1382 try_cnt--; 1383 1384 spin_lock_bh(&csq->lock); 1385 rsv_tail = csq->head; 1386 ret = __hns_roce_cmq_send_one(hr_dev, desc, num, tx_timeout); 1387 if (opcode == HNS_ROCE_OPC_POST_MB && ret == -ETIME && 1388 try_cnt) { 1389 spin_unlock_bh(&csq->lock); 1390 mdelay(HNS_ROCE_OPC_POST_MB_RETRY_GAP_MSEC); 1391 continue; 1392 } 1393 1394 for (i = 0; i < num; i++) { 1395 desc[i] = csq->desc[rsv_tail++]; 1396 if (rsv_tail == csq->desc_num) 1397 rsv_tail = 0; 1398 } 1399 spin_unlock_bh(&csq->lock); 1400 break; 1401 } 1402 1403 if (ret) 1404 dev_err_ratelimited(hr_dev->dev, 1405 "Cmdq IO error, opcode = 0x%x, return = %d.\n", 1406 opcode, ret); 1407 1408 return ret; 1409 } 1410 1411 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1412 struct hns_roce_cmq_desc *desc, int num) 1413 { 1414 bool busy; 1415 int ret; 1416 1417 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1418 return -EIO; 1419 1420 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1421 return busy ? -EBUSY : 0; 1422 1423 ret = __hns_roce_cmq_send(hr_dev, desc, num); 1424 if (ret) { 1425 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1426 return busy ? -EBUSY : 0; 1427 } 1428 1429 return ret; 1430 } 1431 1432 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev, 1433 dma_addr_t base_addr, u8 cmd, unsigned long tag) 1434 { 1435 struct hns_roce_cmd_mailbox *mbox; 1436 int ret; 1437 1438 mbox = hns_roce_alloc_cmd_mailbox(hr_dev); 1439 if (IS_ERR(mbox)) 1440 return PTR_ERR(mbox); 1441 1442 ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, cmd, tag); 1443 hns_roce_free_cmd_mailbox(hr_dev, mbox); 1444 return ret; 1445 } 1446 1447 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) 1448 { 1449 struct hns_roce_query_version *resp; 1450 struct hns_roce_cmq_desc desc; 1451 int ret; 1452 1453 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); 1454 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1455 if (ret) 1456 return ret; 1457 1458 resp = (struct hns_roce_query_version *)desc.data; 1459 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version); 1460 hr_dev->vendor_id = hr_dev->pci_dev->vendor; 1461 1462 return 0; 1463 } 1464 1465 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev, 1466 struct hnae3_handle *handle) 1467 { 1468 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1469 unsigned long end; 1470 1471 hr_dev->dis_db = true; 1472 1473 dev_warn(hr_dev->dev, 1474 "func clear is pending, device in resetting state.\n"); 1475 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1476 while (end) { 1477 if (!ops->get_hw_reset_stat(handle)) { 1478 hr_dev->is_reset = true; 1479 dev_info(hr_dev->dev, 1480 "func clear success after reset.\n"); 1481 return; 1482 } 1483 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1484 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1485 } 1486 1487 dev_warn(hr_dev->dev, "func clear failed.\n"); 1488 } 1489 1490 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev, 1491 struct hnae3_handle *handle) 1492 { 1493 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1494 unsigned long end; 1495 1496 hr_dev->dis_db = true; 1497 1498 dev_warn(hr_dev->dev, 1499 "func clear is pending, device in resetting state.\n"); 1500 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1501 while (end) { 1502 if (ops->ae_dev_reset_cnt(handle) != 1503 hr_dev->reset_cnt) { 1504 hr_dev->is_reset = true; 1505 dev_info(hr_dev->dev, 1506 "func clear success after sw reset\n"); 1507 return; 1508 } 1509 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1510 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1511 } 1512 1513 dev_warn(hr_dev->dev, "func clear failed because of unfinished sw reset\n"); 1514 } 1515 1516 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval, 1517 int flag) 1518 { 1519 struct hns_roce_v2_priv *priv = hr_dev->priv; 1520 struct hnae3_handle *handle = priv->handle; 1521 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1522 1523 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) { 1524 hr_dev->dis_db = true; 1525 hr_dev->is_reset = true; 1526 dev_info(hr_dev->dev, "func clear success after reset.\n"); 1527 return; 1528 } 1529 1530 if (ops->get_hw_reset_stat(handle)) { 1531 func_clr_hw_resetting_state(hr_dev, handle); 1532 return; 1533 } 1534 1535 if (ops->ae_dev_resetting(handle) && 1536 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) { 1537 func_clr_sw_resetting_state(hr_dev, handle); 1538 return; 1539 } 1540 1541 if (retval && !flag) 1542 dev_warn(hr_dev->dev, 1543 "func clear read failed, ret = %d.\n", retval); 1544 1545 dev_warn(hr_dev->dev, "func clear failed.\n"); 1546 } 1547 1548 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id) 1549 { 1550 bool fclr_write_fail_flag = false; 1551 struct hns_roce_func_clear *resp; 1552 struct hns_roce_cmq_desc desc; 1553 unsigned long end; 1554 int ret = 0; 1555 1556 if (check_device_is_in_reset(hr_dev)) 1557 goto out; 1558 1559 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false); 1560 resp = (struct hns_roce_func_clear *)desc.data; 1561 resp->rst_funcid_en = cpu_to_le32(vf_id); 1562 1563 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1564 if (ret) { 1565 fclr_write_fail_flag = true; 1566 dev_err(hr_dev->dev, "func clear write failed, ret = %d.\n", 1567 ret); 1568 goto out; 1569 } 1570 1571 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL); 1572 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS; 1573 while (end) { 1574 if (check_device_is_in_reset(hr_dev)) 1575 goto out; 1576 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT); 1577 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT; 1578 1579 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, 1580 true); 1581 1582 resp->rst_funcid_en = cpu_to_le32(vf_id); 1583 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1584 if (ret) 1585 continue; 1586 1587 if (hr_reg_read(resp, FUNC_CLEAR_RST_FUN_DONE)) { 1588 if (vf_id == 0) 1589 hr_dev->is_reset = true; 1590 return; 1591 } 1592 } 1593 1594 out: 1595 hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag); 1596 } 1597 1598 static int hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id) 1599 { 1600 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1601 struct hns_roce_cmq_desc desc[2]; 1602 struct hns_roce_cmq_req *req_a; 1603 1604 req_a = (struct hns_roce_cmq_req *)desc[0].data; 1605 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1606 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1607 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1608 hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id); 1609 1610 return hns_roce_cmq_send(hr_dev, desc, 2); 1611 } 1612 1613 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev) 1614 { 1615 int ret; 1616 int i; 1617 1618 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1619 return; 1620 1621 for (i = hr_dev->func_num - 1; i >= 0; i--) { 1622 __hns_roce_function_clear(hr_dev, i); 1623 1624 if (i == 0) 1625 continue; 1626 1627 ret = hns_roce_free_vf_resource(hr_dev, i); 1628 if (ret) 1629 ibdev_err(&hr_dev->ib_dev, 1630 "failed to free vf resource, vf_id = %d, ret = %d.\n", 1631 i, ret); 1632 } 1633 } 1634 1635 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev) 1636 { 1637 struct hns_roce_cmq_desc desc; 1638 int ret; 1639 1640 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO, 1641 false); 1642 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1643 if (ret) 1644 ibdev_err(&hr_dev->ib_dev, 1645 "failed to clear extended doorbell info, ret = %d.\n", 1646 ret); 1647 1648 return ret; 1649 } 1650 1651 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev) 1652 { 1653 struct hns_roce_query_fw_info *resp; 1654 struct hns_roce_cmq_desc desc; 1655 int ret; 1656 1657 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true); 1658 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1659 if (ret) 1660 return ret; 1661 1662 resp = (struct hns_roce_query_fw_info *)desc.data; 1663 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver)); 1664 1665 return 0; 1666 } 1667 1668 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev) 1669 { 1670 struct hns_roce_cmq_desc desc; 1671 int ret; 1672 1673 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 1674 hr_dev->func_num = 1; 1675 return 0; 1676 } 1677 1678 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO, 1679 true); 1680 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1681 if (ret) { 1682 hr_dev->func_num = 1; 1683 return ret; 1684 } 1685 1686 hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num); 1687 hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id); 1688 1689 return 0; 1690 } 1691 1692 static int hns_roce_hw_v2_query_counter(struct hns_roce_dev *hr_dev, 1693 u64 *stats, u32 port, int *num_counters) 1694 { 1695 #define CNT_PER_DESC 3 1696 struct hns_roce_cmq_desc *desc; 1697 int bd_idx, cnt_idx; 1698 __le64 *cnt_data; 1699 int desc_num; 1700 int ret; 1701 int i; 1702 1703 if (port > hr_dev->caps.num_ports) 1704 return -EINVAL; 1705 1706 desc_num = DIV_ROUND_UP(HNS_ROCE_HW_CNT_TOTAL, CNT_PER_DESC); 1707 desc = kcalloc(desc_num, sizeof(*desc), GFP_KERNEL); 1708 if (!desc) 1709 return -ENOMEM; 1710 1711 for (i = 0; i < desc_num; i++) { 1712 hns_roce_cmq_setup_basic_desc(&desc[i], 1713 HNS_ROCE_OPC_QUERY_COUNTER, true); 1714 if (i != desc_num - 1) 1715 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1716 } 1717 1718 ret = hns_roce_cmq_send(hr_dev, desc, desc_num); 1719 if (ret) { 1720 ibdev_err(&hr_dev->ib_dev, 1721 "failed to get counter, ret = %d.\n", ret); 1722 goto err_out; 1723 } 1724 1725 for (i = 0; i < HNS_ROCE_HW_CNT_TOTAL && i < *num_counters; i++) { 1726 bd_idx = i / CNT_PER_DESC; 1727 if (bd_idx != HNS_ROCE_HW_CNT_TOTAL / CNT_PER_DESC && 1728 !(desc[bd_idx].flag & cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT))) 1729 break; 1730 1731 cnt_data = (__le64 *)&desc[bd_idx].data[0]; 1732 cnt_idx = i % CNT_PER_DESC; 1733 stats[i] = le64_to_cpu(cnt_data[cnt_idx]); 1734 } 1735 *num_counters = i; 1736 1737 err_out: 1738 kfree(desc); 1739 return ret; 1740 } 1741 1742 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) 1743 { 1744 struct hns_roce_cmq_desc desc; 1745 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1746 u32 clock_cycles_of_1us; 1747 1748 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, 1749 false); 1750 1751 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 1752 clock_cycles_of_1us = HNS_ROCE_1NS_CFG; 1753 else 1754 clock_cycles_of_1us = HNS_ROCE_1US_CFG; 1755 1756 hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, clock_cycles_of_1us); 1757 hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT); 1758 1759 return hns_roce_cmq_send(hr_dev, &desc, 1); 1760 } 1761 1762 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1763 { 1764 struct hns_roce_cmq_desc desc[2]; 1765 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1766 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1767 struct hns_roce_caps *caps = &hr_dev->caps; 1768 enum hns_roce_opcode_type opcode; 1769 u32 func_num; 1770 int ret; 1771 1772 if (is_vf) { 1773 opcode = HNS_ROCE_OPC_QUERY_VF_RES; 1774 func_num = 1; 1775 } else { 1776 opcode = HNS_ROCE_OPC_QUERY_PF_RES; 1777 func_num = hr_dev->func_num; 1778 } 1779 1780 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true); 1781 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1782 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true); 1783 1784 ret = hns_roce_cmq_send(hr_dev, desc, 2); 1785 if (ret) 1786 return ret; 1787 1788 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num; 1789 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num; 1790 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num; 1791 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num; 1792 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num; 1793 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num; 1794 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num; 1795 caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num; 1796 1797 if (is_vf) { 1798 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num; 1799 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) / 1800 func_num; 1801 } else { 1802 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num; 1803 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) / 1804 func_num; 1805 } 1806 1807 return 0; 1808 } 1809 1810 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev) 1811 { 1812 struct hns_roce_cmq_desc desc; 1813 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1814 struct hns_roce_caps *caps = &hr_dev->caps; 1815 int ret; 1816 1817 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES, 1818 true); 1819 1820 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1821 if (ret) 1822 return ret; 1823 1824 caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM); 1825 caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM); 1826 1827 return 0; 1828 } 1829 1830 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 1831 { 1832 struct device *dev = hr_dev->dev; 1833 int ret; 1834 1835 ret = load_func_res_caps(hr_dev, false); 1836 if (ret) { 1837 dev_err(dev, "failed to load pf res caps, ret = %d.\n", ret); 1838 return ret; 1839 } 1840 1841 ret = load_pf_timer_res_caps(hr_dev); 1842 if (ret) 1843 dev_err(dev, "failed to load pf timer resource, ret = %d.\n", 1844 ret); 1845 1846 return ret; 1847 } 1848 1849 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev) 1850 { 1851 struct device *dev = hr_dev->dev; 1852 int ret; 1853 1854 ret = load_func_res_caps(hr_dev, true); 1855 if (ret) 1856 dev_err(dev, "failed to load vf res caps, ret = %d.\n", ret); 1857 1858 return ret; 1859 } 1860 1861 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, 1862 u32 vf_id) 1863 { 1864 struct hns_roce_vf_switch *swt; 1865 struct hns_roce_cmq_desc desc; 1866 int ret; 1867 1868 swt = (struct hns_roce_vf_switch *)desc.data; 1869 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true); 1870 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL); 1871 hr_reg_write(swt, VF_SWITCH_VF_ID, vf_id); 1872 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1873 if (ret) 1874 return ret; 1875 1876 desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1877 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1878 hr_reg_enable(swt, VF_SWITCH_ALW_LPBK); 1879 hr_reg_clear(swt, VF_SWITCH_ALW_LCL_LPBK); 1880 hr_reg_enable(swt, VF_SWITCH_ALW_DST_OVRD); 1881 1882 return hns_roce_cmq_send(hr_dev, &desc, 1); 1883 } 1884 1885 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev) 1886 { 1887 u32 vf_id; 1888 int ret; 1889 1890 for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) { 1891 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id); 1892 if (ret) 1893 return ret; 1894 } 1895 return 0; 1896 } 1897 1898 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id) 1899 { 1900 struct hns_roce_cmq_desc desc[2]; 1901 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1902 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1903 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1904 struct hns_roce_caps *caps = &hr_dev->caps; 1905 1906 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1907 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1908 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1909 1910 hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id); 1911 1912 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num); 1913 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num); 1914 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num); 1915 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num); 1916 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num); 1917 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num); 1918 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num); 1919 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num); 1920 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num); 1921 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num); 1922 hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num); 1923 hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num); 1924 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num); 1925 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num); 1926 1927 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1928 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num); 1929 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX, 1930 vf_id * caps->gmv_bt_num); 1931 } else { 1932 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num); 1933 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX, 1934 vf_id * caps->sgid_bt_num); 1935 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num); 1936 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX, 1937 vf_id * caps->smac_bt_num); 1938 } 1939 1940 return hns_roce_cmq_send(hr_dev, desc, 2); 1941 } 1942 1943 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 1944 { 1945 u32 func_num = max_t(u32, 1, hr_dev->func_num); 1946 u32 vf_id; 1947 int ret; 1948 1949 for (vf_id = 0; vf_id < func_num; vf_id++) { 1950 ret = config_vf_hem_resource(hr_dev, vf_id); 1951 if (ret) { 1952 dev_err(hr_dev->dev, 1953 "failed to config vf-%u hem res, ret = %d.\n", 1954 vf_id, ret); 1955 return ret; 1956 } 1957 } 1958 1959 return 0; 1960 } 1961 1962 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 1963 { 1964 struct hns_roce_cmq_desc desc; 1965 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1966 struct hns_roce_caps *caps = &hr_dev->caps; 1967 1968 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); 1969 1970 hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ, 1971 caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET); 1972 hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ, 1973 caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET); 1974 hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM, 1975 to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps)); 1976 1977 hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ, 1978 caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET); 1979 hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ, 1980 caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET); 1981 hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM, 1982 to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs)); 1983 1984 hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ, 1985 caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET); 1986 hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ, 1987 caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET); 1988 hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM, 1989 to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs)); 1990 1991 hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ, 1992 caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET); 1993 hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ, 1994 caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET); 1995 hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM, 1996 to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts)); 1997 1998 hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ, 1999 caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET); 2000 hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ, 2001 caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET); 2002 hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM, 2003 to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps)); 2004 2005 return hns_roce_cmq_send(hr_dev, &desc, 1); 2006 } 2007 2008 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num, 2009 u32 *buf_page_size, u32 *bt_page_size, u32 hem_type) 2010 { 2011 u64 obj_per_chunk; 2012 u64 bt_chunk_size = PAGE_SIZE; 2013 u64 buf_chunk_size = PAGE_SIZE; 2014 u64 obj_per_chunk_default = buf_chunk_size / obj_size; 2015 2016 *buf_page_size = 0; 2017 *bt_page_size = 0; 2018 2019 switch (hop_num) { 2020 case 3: 2021 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2022 (bt_chunk_size / BA_BYTE_LEN) * 2023 (bt_chunk_size / BA_BYTE_LEN) * 2024 obj_per_chunk_default; 2025 break; 2026 case 2: 2027 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2028 (bt_chunk_size / BA_BYTE_LEN) * 2029 obj_per_chunk_default; 2030 break; 2031 case 1: 2032 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2033 obj_per_chunk_default; 2034 break; 2035 case HNS_ROCE_HOP_NUM_0: 2036 obj_per_chunk = ctx_bt_num * obj_per_chunk_default; 2037 break; 2038 default: 2039 pr_err("table %u not support hop_num = %u!\n", hem_type, 2040 hop_num); 2041 return; 2042 } 2043 2044 if (hem_type >= HEM_TYPE_MTT) 2045 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 2046 else 2047 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 2048 } 2049 2050 static void set_hem_page_size(struct hns_roce_dev *hr_dev) 2051 { 2052 struct hns_roce_caps *caps = &hr_dev->caps; 2053 2054 /* EQ */ 2055 caps->eqe_ba_pg_sz = 0; 2056 caps->eqe_buf_pg_sz = 0; 2057 2058 /* Link Table */ 2059 caps->llm_buf_pg_sz = 0; 2060 2061 /* MR */ 2062 caps->mpt_ba_pg_sz = 0; 2063 caps->mpt_buf_pg_sz = 0; 2064 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K; 2065 caps->pbl_buf_pg_sz = 0; 2066 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num, 2067 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz, 2068 HEM_TYPE_MTPT); 2069 2070 /* QP */ 2071 caps->qpc_ba_pg_sz = 0; 2072 caps->qpc_buf_pg_sz = 0; 2073 caps->qpc_timer_ba_pg_sz = 0; 2074 caps->qpc_timer_buf_pg_sz = 0; 2075 caps->sccc_ba_pg_sz = 0; 2076 caps->sccc_buf_pg_sz = 0; 2077 caps->mtt_ba_pg_sz = 0; 2078 caps->mtt_buf_pg_sz = 0; 2079 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num, 2080 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz, 2081 HEM_TYPE_QPC); 2082 2083 if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) 2084 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num, 2085 caps->sccc_bt_num, &caps->sccc_buf_pg_sz, 2086 &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC); 2087 2088 /* CQ */ 2089 caps->cqc_ba_pg_sz = 0; 2090 caps->cqc_buf_pg_sz = 0; 2091 caps->cqc_timer_ba_pg_sz = 0; 2092 caps->cqc_timer_buf_pg_sz = 0; 2093 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K; 2094 caps->cqe_buf_pg_sz = 0; 2095 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num, 2096 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz, 2097 HEM_TYPE_CQC); 2098 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num, 2099 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE); 2100 2101 /* SRQ */ 2102 if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) { 2103 caps->srqc_ba_pg_sz = 0; 2104 caps->srqc_buf_pg_sz = 0; 2105 caps->srqwqe_ba_pg_sz = 0; 2106 caps->srqwqe_buf_pg_sz = 0; 2107 caps->idx_ba_pg_sz = 0; 2108 caps->idx_buf_pg_sz = 0; 2109 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, 2110 caps->srqc_hop_num, caps->srqc_bt_num, 2111 &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz, 2112 HEM_TYPE_SRQC); 2113 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz, 2114 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz, 2115 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE); 2116 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, 2117 caps->idx_hop_num, 1, &caps->idx_buf_pg_sz, 2118 &caps->idx_ba_pg_sz, HEM_TYPE_IDX); 2119 } 2120 2121 /* GMV */ 2122 caps->gmv_ba_pg_sz = 0; 2123 caps->gmv_buf_pg_sz = 0; 2124 } 2125 2126 /* Apply all loaded caps before setting to hardware */ 2127 static void apply_func_caps(struct hns_roce_dev *hr_dev) 2128 { 2129 #define MAX_GID_TBL_LEN 256 2130 struct hns_roce_caps *caps = &hr_dev->caps; 2131 struct hns_roce_v2_priv *priv = hr_dev->priv; 2132 2133 /* The following configurations don't need to be got from firmware. */ 2134 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; 2135 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; 2136 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 2137 2138 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; 2139 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2140 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2141 2142 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; 2143 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; 2144 2145 if (!caps->num_comp_vectors) 2146 caps->num_comp_vectors = 2147 min_t(u32, caps->eqc_bt_num - HNS_ROCE_V2_AEQE_VEC_NUM, 2148 (u32)priv->handle->rinfo.num_vectors - 2149 (HNS_ROCE_V2_AEQE_VEC_NUM + HNS_ROCE_V2_ABNORMAL_VEC_NUM)); 2150 2151 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 2152 caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM; 2153 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE; 2154 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE; 2155 2156 /* The following configurations will be overwritten */ 2157 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ; 2158 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE; 2159 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ; 2160 2161 /* The following configurations are not got from firmware */ 2162 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ; 2163 2164 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0; 2165 2166 /* It's meaningless to support excessively large gid_table_len, 2167 * as the type of sgid_index in kernel struct ib_global_route 2168 * and userspace struct ibv_global_route are u8/uint8_t (0-255). 2169 */ 2170 caps->gid_table_len[0] = min_t(u32, MAX_GID_TBL_LEN, 2171 caps->gmv_bt_num * 2172 (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz)); 2173 2174 caps->gmv_entry_num = caps->gmv_bt_num * (HNS_HW_PAGE_SIZE / 2175 caps->gmv_entry_sz); 2176 } else { 2177 u32 func_num = max_t(u32, 1, hr_dev->func_num); 2178 2179 caps->eqe_hop_num = HNS_ROCE_V2_EQE_HOP_NUM; 2180 caps->ceqe_size = HNS_ROCE_CEQE_SIZE; 2181 caps->aeqe_size = HNS_ROCE_AEQE_SIZE; 2182 caps->gid_table_len[0] /= func_num; 2183 } 2184 2185 if (hr_dev->is_vf) { 2186 caps->default_aeq_arm_st = 0x3; 2187 caps->default_ceq_arm_st = 0x3; 2188 caps->default_ceq_max_cnt = 0x1; 2189 caps->default_ceq_period = 0x10; 2190 caps->default_aeq_max_cnt = 0x1; 2191 caps->default_aeq_period = 0x10; 2192 } 2193 2194 set_hem_page_size(hr_dev); 2195 } 2196 2197 static int hns_roce_query_caps(struct hns_roce_dev *hr_dev) 2198 { 2199 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM]; 2200 struct hns_roce_caps *caps = &hr_dev->caps; 2201 struct hns_roce_query_pf_caps_a *resp_a; 2202 struct hns_roce_query_pf_caps_b *resp_b; 2203 struct hns_roce_query_pf_caps_c *resp_c; 2204 struct hns_roce_query_pf_caps_d *resp_d; 2205 struct hns_roce_query_pf_caps_e *resp_e; 2206 enum hns_roce_opcode_type cmd; 2207 int ctx_hop_num; 2208 int pbl_hop_num; 2209 int ret; 2210 int i; 2211 2212 cmd = hr_dev->is_vf ? HNS_ROCE_OPC_QUERY_VF_CAPS_NUM : 2213 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM; 2214 2215 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) { 2216 hns_roce_cmq_setup_basic_desc(&desc[i], cmd, true); 2217 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1)) 2218 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2219 else 2220 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2221 } 2222 2223 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM); 2224 if (ret) 2225 return ret; 2226 2227 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data; 2228 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data; 2229 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data; 2230 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data; 2231 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data; 2232 2233 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay; 2234 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg); 2235 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline); 2236 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg); 2237 caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg); 2238 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges); 2239 caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges); 2240 caps->num_aeq_vectors = resp_a->num_aeq_vectors; 2241 caps->num_other_vectors = resp_a->num_other_vectors; 2242 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz; 2243 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz; 2244 2245 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz; 2246 caps->irrl_entry_sz = resp_b->irrl_entry_sz; 2247 caps->trrl_entry_sz = resp_b->trrl_entry_sz; 2248 caps->cqc_entry_sz = resp_b->cqc_entry_sz; 2249 caps->srqc_entry_sz = resp_b->srqc_entry_sz; 2250 caps->idx_entry_sz = resp_b->idx_entry_sz; 2251 caps->sccc_sz = resp_b->sccc_sz; 2252 caps->max_mtu = resp_b->max_mtu; 2253 caps->min_cqes = resp_b->min_cqes; 2254 caps->min_wqes = resp_b->min_wqes; 2255 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap); 2256 caps->pkey_table_len[0] = resp_b->pkey_table_len; 2257 caps->phy_num_uars = resp_b->phy_num_uars; 2258 ctx_hop_num = resp_b->ctx_hop_num; 2259 pbl_hop_num = resp_b->pbl_hop_num; 2260 2261 caps->num_pds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_PDS); 2262 2263 caps->flags = hr_reg_read(resp_c, PF_CAPS_C_CAP_FLAGS); 2264 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) << 2265 HNS_ROCE_CAP_FLAGS_EX_SHIFT; 2266 2267 caps->num_cqs = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_CQS); 2268 caps->gid_table_len[0] = hr_reg_read(resp_c, PF_CAPS_C_MAX_GID); 2269 caps->max_cqes = 1 << hr_reg_read(resp_c, PF_CAPS_C_CQ_DEPTH); 2270 caps->num_xrcds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_XRCDS); 2271 caps->num_mtpts = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_MRWS); 2272 caps->num_qps = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_QPS); 2273 caps->max_qp_init_rdma = hr_reg_read(resp_c, PF_CAPS_C_MAX_ORD); 2274 caps->max_qp_dest_rdma = caps->max_qp_init_rdma; 2275 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth); 2276 2277 caps->num_srqs = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_SRQS); 2278 caps->cong_cap = hr_reg_read(resp_d, PF_CAPS_D_CONG_CAP); 2279 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth); 2280 caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH); 2281 caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS); 2282 caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH); 2283 caps->default_cong_type = hr_reg_read(resp_d, PF_CAPS_D_DEFAULT_ALG); 2284 caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS); 2285 caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS); 2286 caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS); 2287 caps->reserved_uars = hr_reg_read(resp_d, PF_CAPS_D_RSV_UARS); 2288 2289 caps->reserved_mrws = hr_reg_read(resp_e, PF_CAPS_E_RSV_MRWS); 2290 caps->chunk_sz = 1 << hr_reg_read(resp_e, PF_CAPS_E_CHUNK_SIZE_SHIFT); 2291 caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS); 2292 caps->reserved_xrcds = hr_reg_read(resp_e, PF_CAPS_E_RSV_XRCDS); 2293 caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS); 2294 caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS); 2295 2296 caps->qpc_hop_num = ctx_hop_num; 2297 caps->sccc_hop_num = ctx_hop_num; 2298 caps->srqc_hop_num = ctx_hop_num; 2299 caps->cqc_hop_num = ctx_hop_num; 2300 caps->mpt_hop_num = ctx_hop_num; 2301 caps->mtt_hop_num = pbl_hop_num; 2302 caps->cqe_hop_num = pbl_hop_num; 2303 caps->srqwqe_hop_num = pbl_hop_num; 2304 caps->idx_hop_num = pbl_hop_num; 2305 caps->wqe_sq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_SQWQE_HOP_NUM); 2306 caps->wqe_sge_hop_num = hr_reg_read(resp_d, PF_CAPS_D_EX_SGE_HOP_NUM); 2307 caps->wqe_rq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_RQWQE_HOP_NUM); 2308 2309 if (!(caps->page_size_cap & PAGE_SIZE)) 2310 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 2311 2312 if (!hr_dev->is_vf) { 2313 caps->cqe_sz = resp_a->cqe_sz; 2314 caps->qpc_sz = le16_to_cpu(resp_b->qpc_sz); 2315 caps->default_aeq_arm_st = 2316 hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST); 2317 caps->default_ceq_arm_st = 2318 hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST); 2319 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt); 2320 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period); 2321 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt); 2322 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period); 2323 } 2324 2325 return 0; 2326 } 2327 2328 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val) 2329 { 2330 struct hns_roce_cmq_desc desc; 2331 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 2332 2333 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE, 2334 false); 2335 2336 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type); 2337 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val); 2338 2339 return hns_roce_cmq_send(hr_dev, &desc, 1); 2340 } 2341 2342 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev) 2343 { 2344 struct hns_roce_caps *caps = &hr_dev->caps; 2345 int ret; 2346 2347 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 2348 return 0; 2349 2350 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE, 2351 caps->qpc_sz); 2352 if (ret) { 2353 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret); 2354 return ret; 2355 } 2356 2357 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE, 2358 caps->sccc_sz); 2359 if (ret) 2360 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret); 2361 2362 return ret; 2363 } 2364 2365 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev) 2366 { 2367 struct device *dev = hr_dev->dev; 2368 int ret; 2369 2370 hr_dev->func_num = 1; 2371 2372 ret = hns_roce_query_caps(hr_dev); 2373 if (ret) { 2374 dev_err(dev, "failed to query VF caps, ret = %d.\n", ret); 2375 return ret; 2376 } 2377 2378 ret = hns_roce_query_vf_resource(hr_dev); 2379 if (ret) { 2380 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret); 2381 return ret; 2382 } 2383 2384 apply_func_caps(hr_dev); 2385 2386 ret = hns_roce_v2_set_bt(hr_dev); 2387 if (ret) 2388 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret); 2389 2390 return ret; 2391 } 2392 2393 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev) 2394 { 2395 struct device *dev = hr_dev->dev; 2396 int ret; 2397 2398 ret = hns_roce_query_func_info(hr_dev); 2399 if (ret) { 2400 dev_err(dev, "failed to query func info, ret = %d.\n", ret); 2401 return ret; 2402 } 2403 2404 ret = hns_roce_config_global_param(hr_dev); 2405 if (ret) { 2406 dev_err(dev, "failed to config global param, ret = %d.\n", ret); 2407 return ret; 2408 } 2409 2410 ret = hns_roce_set_vf_switch_param(hr_dev); 2411 if (ret) { 2412 dev_err(dev, "failed to set switch param, ret = %d.\n", ret); 2413 return ret; 2414 } 2415 2416 ret = hns_roce_query_caps(hr_dev); 2417 if (ret) { 2418 dev_err(dev, "failed to query PF caps, ret = %d.\n", ret); 2419 return ret; 2420 } 2421 2422 ret = hns_roce_query_pf_resource(hr_dev); 2423 if (ret) { 2424 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret); 2425 return ret; 2426 } 2427 2428 apply_func_caps(hr_dev); 2429 2430 ret = hns_roce_alloc_vf_resource(hr_dev); 2431 if (ret) { 2432 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret); 2433 return ret; 2434 } 2435 2436 ret = hns_roce_v2_set_bt(hr_dev); 2437 if (ret) { 2438 dev_err(dev, "failed to config BA table, ret = %d.\n", ret); 2439 return ret; 2440 } 2441 2442 /* Configure the size of QPC, SCCC, etc. */ 2443 return hns_roce_config_entry_size(hr_dev); 2444 } 2445 2446 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 2447 { 2448 struct device *dev = hr_dev->dev; 2449 int ret; 2450 2451 ret = hns_roce_cmq_query_hw_info(hr_dev); 2452 if (ret) { 2453 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret); 2454 return ret; 2455 } 2456 2457 ret = hns_roce_query_fw_ver(hr_dev); 2458 if (ret) { 2459 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret); 2460 return ret; 2461 } 2462 2463 hr_dev->vendor_part_id = hr_dev->pci_dev->device; 2464 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid); 2465 2466 if (hr_dev->is_vf) 2467 return hns_roce_v2_vf_profile(hr_dev); 2468 else 2469 return hns_roce_v2_pf_profile(hr_dev); 2470 } 2471 2472 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf) 2473 { 2474 u32 i, next_ptr, page_num; 2475 __le64 *entry = cfg_buf; 2476 dma_addr_t addr; 2477 u64 val; 2478 2479 page_num = data_buf->npages; 2480 for (i = 0; i < page_num; i++) { 2481 addr = hns_roce_buf_page(data_buf, i); 2482 if (i == (page_num - 1)) 2483 next_ptr = 0; 2484 else 2485 next_ptr = i + 1; 2486 2487 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr); 2488 entry[i] = cpu_to_le64(val); 2489 } 2490 } 2491 2492 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev, 2493 struct hns_roce_link_table *table) 2494 { 2495 struct hns_roce_cmq_desc desc[2]; 2496 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 2497 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 2498 struct hns_roce_buf *buf = table->buf; 2499 enum hns_roce_opcode_type opcode; 2500 dma_addr_t addr; 2501 2502 opcode = HNS_ROCE_OPC_CFG_EXT_LLM; 2503 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 2504 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2505 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 2506 2507 hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map)); 2508 hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map)); 2509 hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages); 2510 hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift)); 2511 hr_reg_enable(r_a, CFG_LLM_A_INIT_EN); 2512 2513 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0)); 2514 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr)); 2515 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr)); 2516 hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1); 2517 hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0); 2518 2519 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1)); 2520 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr)); 2521 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr)); 2522 hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1); 2523 2524 return hns_roce_cmq_send(hr_dev, desc, 2); 2525 } 2526 2527 static struct hns_roce_link_table * 2528 alloc_link_table_buf(struct hns_roce_dev *hr_dev) 2529 { 2530 u16 total_sl = hr_dev->caps.sl_num * hr_dev->func_num; 2531 struct hns_roce_v2_priv *priv = hr_dev->priv; 2532 struct hns_roce_link_table *link_tbl; 2533 u32 pg_shift, size, min_size; 2534 2535 link_tbl = &priv->ext_llm; 2536 pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT; 2537 size = hr_dev->caps.num_qps * hr_dev->func_num * 2538 HNS_ROCE_V2_EXT_LLM_ENTRY_SZ; 2539 min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(total_sl) << pg_shift; 2540 2541 /* Alloc data table */ 2542 size = max(size, min_size); 2543 link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0); 2544 if (IS_ERR(link_tbl->buf)) 2545 return ERR_PTR(-ENOMEM); 2546 2547 /* Alloc config table */ 2548 size = link_tbl->buf->npages * sizeof(u64); 2549 link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size, 2550 &link_tbl->table.map, 2551 GFP_KERNEL); 2552 if (!link_tbl->table.buf) { 2553 hns_roce_buf_free(hr_dev, link_tbl->buf); 2554 return ERR_PTR(-ENOMEM); 2555 } 2556 2557 return link_tbl; 2558 } 2559 2560 static void free_link_table_buf(struct hns_roce_dev *hr_dev, 2561 struct hns_roce_link_table *tbl) 2562 { 2563 if (tbl->buf) { 2564 u32 size = tbl->buf->npages * sizeof(u64); 2565 2566 dma_free_coherent(hr_dev->dev, size, tbl->table.buf, 2567 tbl->table.map); 2568 } 2569 2570 hns_roce_buf_free(hr_dev, tbl->buf); 2571 } 2572 2573 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev) 2574 { 2575 struct hns_roce_link_table *link_tbl; 2576 int ret; 2577 2578 link_tbl = alloc_link_table_buf(hr_dev); 2579 if (IS_ERR(link_tbl)) 2580 return -ENOMEM; 2581 2582 if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) { 2583 ret = -EINVAL; 2584 goto err_alloc; 2585 } 2586 2587 config_llm_table(link_tbl->buf, link_tbl->table.buf); 2588 ret = set_llm_cfg_to_hw(hr_dev, link_tbl); 2589 if (ret) 2590 goto err_alloc; 2591 2592 return 0; 2593 2594 err_alloc: 2595 free_link_table_buf(hr_dev, link_tbl); 2596 return ret; 2597 } 2598 2599 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev) 2600 { 2601 struct hns_roce_v2_priv *priv = hr_dev->priv; 2602 2603 free_link_table_buf(hr_dev, &priv->ext_llm); 2604 } 2605 2606 static void free_dip_entry(struct hns_roce_dev *hr_dev) 2607 { 2608 struct hns_roce_dip *hr_dip; 2609 unsigned long idx; 2610 2611 xa_lock(&hr_dev->qp_table.dip_xa); 2612 2613 xa_for_each(&hr_dev->qp_table.dip_xa, idx, hr_dip) { 2614 __xa_erase(&hr_dev->qp_table.dip_xa, hr_dip->dip_idx); 2615 kfree(hr_dip); 2616 } 2617 2618 xa_unlock(&hr_dev->qp_table.dip_xa); 2619 } 2620 2621 static struct ib_pd *free_mr_init_pd(struct hns_roce_dev *hr_dev) 2622 { 2623 struct hns_roce_v2_priv *priv = hr_dev->priv; 2624 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2625 struct ib_device *ibdev = &hr_dev->ib_dev; 2626 struct hns_roce_pd *hr_pd; 2627 struct ib_pd *pd; 2628 2629 hr_pd = kzalloc(sizeof(*hr_pd), GFP_KERNEL); 2630 if (ZERO_OR_NULL_PTR(hr_pd)) 2631 return NULL; 2632 pd = &hr_pd->ibpd; 2633 pd->device = ibdev; 2634 2635 if (hns_roce_alloc_pd(pd, NULL)) { 2636 ibdev_err(ibdev, "failed to create pd for free mr.\n"); 2637 kfree(hr_pd); 2638 return NULL; 2639 } 2640 free_mr->rsv_pd = to_hr_pd(pd); 2641 free_mr->rsv_pd->ibpd.device = &hr_dev->ib_dev; 2642 free_mr->rsv_pd->ibpd.uobject = NULL; 2643 free_mr->rsv_pd->ibpd.__internal_mr = NULL; 2644 atomic_set(&free_mr->rsv_pd->ibpd.usecnt, 0); 2645 2646 return pd; 2647 } 2648 2649 static struct ib_cq *free_mr_init_cq(struct hns_roce_dev *hr_dev) 2650 { 2651 struct hns_roce_v2_priv *priv = hr_dev->priv; 2652 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2653 struct ib_device *ibdev = &hr_dev->ib_dev; 2654 struct ib_cq_init_attr cq_init_attr = {}; 2655 struct hns_roce_cq *hr_cq; 2656 struct ib_cq *cq; 2657 2658 cq_init_attr.cqe = HNS_ROCE_FREE_MR_USED_CQE_NUM; 2659 2660 hr_cq = kzalloc(sizeof(*hr_cq), GFP_KERNEL); 2661 if (ZERO_OR_NULL_PTR(hr_cq)) 2662 return NULL; 2663 2664 cq = &hr_cq->ib_cq; 2665 cq->device = ibdev; 2666 2667 if (hns_roce_create_cq(cq, &cq_init_attr, NULL)) { 2668 ibdev_err(ibdev, "failed to create cq for free mr.\n"); 2669 kfree(hr_cq); 2670 return NULL; 2671 } 2672 free_mr->rsv_cq = to_hr_cq(cq); 2673 free_mr->rsv_cq->ib_cq.device = &hr_dev->ib_dev; 2674 free_mr->rsv_cq->ib_cq.uobject = NULL; 2675 free_mr->rsv_cq->ib_cq.comp_handler = NULL; 2676 free_mr->rsv_cq->ib_cq.event_handler = NULL; 2677 free_mr->rsv_cq->ib_cq.cq_context = NULL; 2678 atomic_set(&free_mr->rsv_cq->ib_cq.usecnt, 0); 2679 2680 return cq; 2681 } 2682 2683 static int free_mr_init_qp(struct hns_roce_dev *hr_dev, struct ib_cq *cq, 2684 struct ib_qp_init_attr *init_attr, int i) 2685 { 2686 struct hns_roce_v2_priv *priv = hr_dev->priv; 2687 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2688 struct ib_device *ibdev = &hr_dev->ib_dev; 2689 struct hns_roce_qp *hr_qp; 2690 struct ib_qp *qp; 2691 int ret; 2692 2693 hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL); 2694 if (ZERO_OR_NULL_PTR(hr_qp)) 2695 return -ENOMEM; 2696 2697 qp = &hr_qp->ibqp; 2698 qp->device = ibdev; 2699 2700 ret = hns_roce_create_qp(qp, init_attr, NULL); 2701 if (ret) { 2702 ibdev_err(ibdev, "failed to create qp for free mr.\n"); 2703 kfree(hr_qp); 2704 return ret; 2705 } 2706 2707 free_mr->rsv_qp[i] = hr_qp; 2708 free_mr->rsv_qp[i]->ibqp.recv_cq = cq; 2709 free_mr->rsv_qp[i]->ibqp.send_cq = cq; 2710 2711 return 0; 2712 } 2713 2714 static void free_mr_exit(struct hns_roce_dev *hr_dev) 2715 { 2716 struct hns_roce_v2_priv *priv = hr_dev->priv; 2717 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2718 struct ib_qp *qp; 2719 int i; 2720 2721 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2722 if (free_mr->rsv_qp[i]) { 2723 qp = &free_mr->rsv_qp[i]->ibqp; 2724 hns_roce_v2_destroy_qp(qp, NULL); 2725 kfree(free_mr->rsv_qp[i]); 2726 free_mr->rsv_qp[i] = NULL; 2727 } 2728 } 2729 2730 if (free_mr->rsv_cq) { 2731 hns_roce_destroy_cq(&free_mr->rsv_cq->ib_cq, NULL); 2732 kfree(free_mr->rsv_cq); 2733 free_mr->rsv_cq = NULL; 2734 } 2735 2736 if (free_mr->rsv_pd) { 2737 hns_roce_dealloc_pd(&free_mr->rsv_pd->ibpd, NULL); 2738 kfree(free_mr->rsv_pd); 2739 free_mr->rsv_pd = NULL; 2740 } 2741 2742 mutex_destroy(&free_mr->mutex); 2743 } 2744 2745 static int free_mr_alloc_res(struct hns_roce_dev *hr_dev) 2746 { 2747 struct hns_roce_v2_priv *priv = hr_dev->priv; 2748 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2749 struct ib_qp_init_attr qp_init_attr = {}; 2750 struct ib_pd *pd; 2751 struct ib_cq *cq; 2752 int ret; 2753 int i; 2754 2755 pd = free_mr_init_pd(hr_dev); 2756 if (!pd) 2757 return -ENOMEM; 2758 2759 cq = free_mr_init_cq(hr_dev); 2760 if (!cq) { 2761 ret = -ENOMEM; 2762 goto create_failed_cq; 2763 } 2764 2765 qp_init_attr.qp_type = IB_QPT_RC; 2766 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR; 2767 qp_init_attr.send_cq = cq; 2768 qp_init_attr.recv_cq = cq; 2769 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2770 qp_init_attr.cap.max_send_wr = HNS_ROCE_FREE_MR_USED_SQWQE_NUM; 2771 qp_init_attr.cap.max_send_sge = HNS_ROCE_FREE_MR_USED_SQSGE_NUM; 2772 qp_init_attr.cap.max_recv_wr = HNS_ROCE_FREE_MR_USED_RQWQE_NUM; 2773 qp_init_attr.cap.max_recv_sge = HNS_ROCE_FREE_MR_USED_RQSGE_NUM; 2774 2775 ret = free_mr_init_qp(hr_dev, cq, &qp_init_attr, i); 2776 if (ret) 2777 goto create_failed_qp; 2778 } 2779 2780 return 0; 2781 2782 create_failed_qp: 2783 for (i--; i >= 0; i--) { 2784 hns_roce_v2_destroy_qp(&free_mr->rsv_qp[i]->ibqp, NULL); 2785 kfree(free_mr->rsv_qp[i]); 2786 } 2787 hns_roce_destroy_cq(cq, NULL); 2788 kfree(cq); 2789 2790 create_failed_cq: 2791 hns_roce_dealloc_pd(pd, NULL); 2792 kfree(pd); 2793 2794 return ret; 2795 } 2796 2797 static int free_mr_modify_rsv_qp(struct hns_roce_dev *hr_dev, 2798 struct ib_qp_attr *attr, int sl_num) 2799 { 2800 struct hns_roce_v2_priv *priv = hr_dev->priv; 2801 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2802 struct ib_device *ibdev = &hr_dev->ib_dev; 2803 struct hns_roce_qp *hr_qp; 2804 int loopback; 2805 int mask; 2806 int ret; 2807 2808 hr_qp = to_hr_qp(&free_mr->rsv_qp[sl_num]->ibqp); 2809 hr_qp->free_mr_en = 1; 2810 hr_qp->ibqp.device = ibdev; 2811 hr_qp->ibqp.qp_type = IB_QPT_RC; 2812 2813 mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS; 2814 attr->qp_state = IB_QPS_INIT; 2815 attr->port_num = 1; 2816 attr->qp_access_flags = IB_ACCESS_REMOTE_WRITE; 2817 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 2818 IB_QPS_INIT, NULL); 2819 if (ret) { 2820 ibdev_err_ratelimited(ibdev, "failed to modify qp to init, ret = %d.\n", 2821 ret); 2822 return ret; 2823 } 2824 2825 loopback = hr_dev->loop_idc; 2826 /* Set qpc lbi = 1 incidate loopback IO */ 2827 hr_dev->loop_idc = 1; 2828 2829 mask = IB_QP_STATE | IB_QP_AV | IB_QP_PATH_MTU | IB_QP_DEST_QPN | 2830 IB_QP_RQ_PSN | IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER; 2831 attr->qp_state = IB_QPS_RTR; 2832 attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 2833 attr->path_mtu = IB_MTU_256; 2834 attr->dest_qp_num = hr_qp->qpn; 2835 attr->rq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2836 2837 rdma_ah_set_sl(&attr->ah_attr, (u8)sl_num); 2838 2839 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 2840 IB_QPS_RTR, NULL); 2841 hr_dev->loop_idc = loopback; 2842 if (ret) { 2843 ibdev_err(ibdev, "failed to modify qp to rtr, ret = %d.\n", 2844 ret); 2845 return ret; 2846 } 2847 2848 mask = IB_QP_STATE | IB_QP_SQ_PSN | IB_QP_RETRY_CNT | IB_QP_TIMEOUT | 2849 IB_QP_RNR_RETRY | IB_QP_MAX_QP_RD_ATOMIC; 2850 attr->qp_state = IB_QPS_RTS; 2851 attr->sq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2852 attr->retry_cnt = HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT; 2853 attr->timeout = HNS_ROCE_FREE_MR_USED_QP_TIMEOUT; 2854 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_RTR, 2855 IB_QPS_RTS, NULL); 2856 if (ret) 2857 ibdev_err(ibdev, "failed to modify qp to rts, ret = %d.\n", 2858 ret); 2859 2860 return ret; 2861 } 2862 2863 static int free_mr_modify_qp(struct hns_roce_dev *hr_dev) 2864 { 2865 struct hns_roce_v2_priv *priv = hr_dev->priv; 2866 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2867 struct ib_qp_attr attr = {}; 2868 int ret; 2869 int i; 2870 2871 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0); 2872 rdma_ah_set_static_rate(&attr.ah_attr, 3); 2873 rdma_ah_set_port_num(&attr.ah_attr, 1); 2874 2875 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2876 ret = free_mr_modify_rsv_qp(hr_dev, &attr, i); 2877 if (ret) 2878 return ret; 2879 } 2880 2881 return 0; 2882 } 2883 2884 static int free_mr_init(struct hns_roce_dev *hr_dev) 2885 { 2886 struct hns_roce_v2_priv *priv = hr_dev->priv; 2887 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2888 int ret; 2889 2890 mutex_init(&free_mr->mutex); 2891 2892 ret = free_mr_alloc_res(hr_dev); 2893 if (ret) { 2894 mutex_destroy(&free_mr->mutex); 2895 return ret; 2896 } 2897 2898 ret = free_mr_modify_qp(hr_dev); 2899 if (ret) 2900 goto err_modify_qp; 2901 2902 return 0; 2903 2904 err_modify_qp: 2905 free_mr_exit(hr_dev); 2906 2907 return ret; 2908 } 2909 2910 static int get_hem_table(struct hns_roce_dev *hr_dev) 2911 { 2912 unsigned int qpc_count; 2913 unsigned int cqc_count; 2914 unsigned int gmv_count; 2915 int ret; 2916 int i; 2917 2918 /* Alloc memory for source address table buffer space chunk */ 2919 for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num; 2920 gmv_count++) { 2921 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count); 2922 if (ret) 2923 goto err_gmv_failed; 2924 } 2925 2926 if (hr_dev->is_vf) 2927 return 0; 2928 2929 /* Alloc memory for QPC Timer buffer space chunk */ 2930 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num; 2931 qpc_count++) { 2932 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table, 2933 qpc_count); 2934 if (ret) { 2935 dev_err(hr_dev->dev, "QPC Timer get failed\n"); 2936 goto err_qpc_timer_failed; 2937 } 2938 } 2939 2940 /* Alloc memory for CQC Timer buffer space chunk */ 2941 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num; 2942 cqc_count++) { 2943 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table, 2944 cqc_count); 2945 if (ret) { 2946 dev_err(hr_dev->dev, "CQC Timer get failed\n"); 2947 goto err_cqc_timer_failed; 2948 } 2949 } 2950 2951 return 0; 2952 2953 err_cqc_timer_failed: 2954 for (i = 0; i < cqc_count; i++) 2955 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2956 2957 err_qpc_timer_failed: 2958 for (i = 0; i < qpc_count; i++) 2959 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2960 2961 err_gmv_failed: 2962 for (i = 0; i < gmv_count; i++) 2963 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2964 2965 return ret; 2966 } 2967 2968 static void put_hem_table(struct hns_roce_dev *hr_dev) 2969 { 2970 int i; 2971 2972 for (i = 0; i < hr_dev->caps.gmv_entry_num; i++) 2973 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2974 2975 if (hr_dev->is_vf) 2976 return; 2977 2978 for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++) 2979 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2980 2981 for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++) 2982 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2983 } 2984 2985 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev) 2986 { 2987 int ret; 2988 2989 /* The hns ROCEE requires the extdb info to be cleared before using */ 2990 ret = hns_roce_clear_extdb_list_info(hr_dev); 2991 if (ret) 2992 return ret; 2993 2994 ret = get_hem_table(hr_dev); 2995 if (ret) 2996 return ret; 2997 2998 if (hr_dev->is_vf) 2999 return 0; 3000 3001 ret = hns_roce_init_link_table(hr_dev); 3002 if (ret) { 3003 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret); 3004 goto err_llm_init_failed; 3005 } 3006 3007 return 0; 3008 3009 err_llm_init_failed: 3010 put_hem_table(hr_dev); 3011 3012 return ret; 3013 } 3014 3015 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev) 3016 { 3017 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 3018 free_mr_exit(hr_dev); 3019 3020 hns_roce_function_clear(hr_dev); 3021 3022 if (!hr_dev->is_vf) 3023 hns_roce_free_link_table(hr_dev); 3024 3025 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP09) 3026 free_dip_entry(hr_dev); 3027 } 3028 3029 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, 3030 struct hns_roce_mbox_msg *mbox_msg) 3031 { 3032 struct hns_roce_cmq_desc desc; 3033 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data; 3034 3035 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false); 3036 3037 mb->in_param_l = cpu_to_le32(mbox_msg->in_param); 3038 mb->in_param_h = cpu_to_le32(mbox_msg->in_param >> 32); 3039 mb->out_param_l = cpu_to_le32(mbox_msg->out_param); 3040 mb->out_param_h = cpu_to_le32(mbox_msg->out_param >> 32); 3041 mb->cmd_tag = cpu_to_le32(mbox_msg->tag << 8 | mbox_msg->cmd); 3042 mb->token_event_en = cpu_to_le32(mbox_msg->event_en << 16 | 3043 mbox_msg->token); 3044 3045 return hns_roce_cmq_send(hr_dev, &desc, 1); 3046 } 3047 3048 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout, 3049 u8 *complete_status) 3050 { 3051 struct hns_roce_mbox_status *mb_st; 3052 struct hns_roce_cmq_desc desc; 3053 unsigned long end; 3054 int ret = -EBUSY; 3055 u32 status; 3056 bool busy; 3057 3058 mb_st = (struct hns_roce_mbox_status *)desc.data; 3059 end = msecs_to_jiffies(timeout) + jiffies; 3060 while (v2_chk_mbox_is_avail(hr_dev, &busy)) { 3061 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 3062 return -EIO; 3063 3064 status = 0; 3065 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, 3066 true); 3067 ret = __hns_roce_cmq_send(hr_dev, &desc, 1); 3068 if (!ret) { 3069 status = le32_to_cpu(mb_st->mb_status_hw_run); 3070 /* No pending message exists in ROCEE mbox. */ 3071 if (!(status & MB_ST_HW_RUN_M)) 3072 break; 3073 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 3074 break; 3075 } 3076 3077 if (time_after(jiffies, end)) { 3078 dev_err_ratelimited(hr_dev->dev, 3079 "failed to wait mbox status 0x%x\n", 3080 status); 3081 return -ETIMEDOUT; 3082 } 3083 3084 cond_resched(); 3085 ret = -EBUSY; 3086 } 3087 3088 if (!ret) { 3089 *complete_status = (u8)(status & MB_ST_COMPLETE_M); 3090 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 3091 /* Ignore all errors if the mbox is unavailable. */ 3092 ret = 0; 3093 *complete_status = MB_ST_COMPLETE_M; 3094 } 3095 3096 return ret; 3097 } 3098 3099 static int v2_post_mbox(struct hns_roce_dev *hr_dev, 3100 struct hns_roce_mbox_msg *mbox_msg) 3101 { 3102 u8 status = 0; 3103 int ret; 3104 3105 /* Waiting for the mbox to be idle */ 3106 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS, 3107 &status); 3108 if (unlikely(ret)) { 3109 dev_err_ratelimited(hr_dev->dev, 3110 "failed to check post mbox status = 0x%x, ret = %d.\n", 3111 status, ret); 3112 return ret; 3113 } 3114 3115 /* Post new message to mbox */ 3116 ret = hns_roce_mbox_post(hr_dev, mbox_msg); 3117 if (ret) 3118 dev_err_ratelimited(hr_dev->dev, 3119 "failed to post mailbox, ret = %d.\n", ret); 3120 3121 return ret; 3122 } 3123 3124 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev) 3125 { 3126 u8 status = 0; 3127 int ret; 3128 3129 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_CMD_TIMEOUT_MSECS, 3130 &status); 3131 if (!ret) { 3132 if (status != MB_ST_COMPLETE_SUCC) 3133 return -EBUSY; 3134 } else { 3135 dev_err_ratelimited(hr_dev->dev, 3136 "failed to check mbox status = 0x%x, ret = %d.\n", 3137 status, ret); 3138 } 3139 3140 return ret; 3141 } 3142 3143 static void copy_gid(void *dest, const union ib_gid *gid) 3144 { 3145 #define GID_SIZE 4 3146 const union ib_gid *src = gid; 3147 __le32 (*p)[GID_SIZE] = dest; 3148 int i; 3149 3150 if (!gid) 3151 src = &zgid; 3152 3153 for (i = 0; i < GID_SIZE; i++) 3154 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]); 3155 } 3156 3157 static int config_sgid_table(struct hns_roce_dev *hr_dev, 3158 int gid_index, const union ib_gid *gid, 3159 enum hns_roce_sgid_type sgid_type) 3160 { 3161 struct hns_roce_cmq_desc desc; 3162 struct hns_roce_cfg_sgid_tb *sgid_tb = 3163 (struct hns_roce_cfg_sgid_tb *)desc.data; 3164 3165 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false); 3166 3167 hr_reg_write(sgid_tb, CFG_SGID_TB_TABLE_IDX, gid_index); 3168 hr_reg_write(sgid_tb, CFG_SGID_TB_VF_SGID_TYPE, sgid_type); 3169 3170 copy_gid(&sgid_tb->vf_sgid_l, gid); 3171 3172 return hns_roce_cmq_send(hr_dev, &desc, 1); 3173 } 3174 3175 static int config_gmv_table(struct hns_roce_dev *hr_dev, 3176 int gid_index, const union ib_gid *gid, 3177 enum hns_roce_sgid_type sgid_type, 3178 const struct ib_gid_attr *attr) 3179 { 3180 struct hns_roce_cmq_desc desc[2]; 3181 struct hns_roce_cfg_gmv_tb_a *tb_a = 3182 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data; 3183 struct hns_roce_cfg_gmv_tb_b *tb_b = 3184 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data; 3185 3186 u16 vlan_id = VLAN_CFI_MASK; 3187 u8 mac[ETH_ALEN] = {}; 3188 int ret; 3189 3190 if (gid) { 3191 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac); 3192 if (ret) 3193 return ret; 3194 } 3195 3196 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3197 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 3198 3199 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3200 3201 copy_gid(&tb_a->vf_sgid_l, gid); 3202 3203 hr_reg_write(tb_a, GMV_TB_A_VF_SGID_TYPE, sgid_type); 3204 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_EN, vlan_id < VLAN_CFI_MASK); 3205 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_ID, vlan_id); 3206 3207 tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac); 3208 3209 hr_reg_write(tb_b, GMV_TB_B_SMAC_H, *(u16 *)&mac[4]); 3210 hr_reg_write(tb_b, GMV_TB_B_SGID_IDX, gid_index); 3211 3212 return hns_roce_cmq_send(hr_dev, desc, 2); 3213 } 3214 3215 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, int gid_index, 3216 const union ib_gid *gid, 3217 const struct ib_gid_attr *attr) 3218 { 3219 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; 3220 int ret; 3221 3222 if (gid) { 3223 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 3224 if (ipv6_addr_v4mapped((void *)gid)) 3225 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; 3226 else 3227 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; 3228 } else if (attr->gid_type == IB_GID_TYPE_ROCE) { 3229 sgid_type = GID_TYPE_FLAG_ROCE_V1; 3230 } 3231 } 3232 3233 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 3234 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr); 3235 else 3236 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type); 3237 3238 if (ret) 3239 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n", 3240 ret); 3241 3242 return ret; 3243 } 3244 3245 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, 3246 const u8 *addr) 3247 { 3248 struct hns_roce_cmq_desc desc; 3249 struct hns_roce_cfg_smac_tb *smac_tb = 3250 (struct hns_roce_cfg_smac_tb *)desc.data; 3251 u16 reg_smac_h; 3252 u32 reg_smac_l; 3253 3254 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false); 3255 3256 reg_smac_l = *(u32 *)(&addr[0]); 3257 reg_smac_h = *(u16 *)(&addr[4]); 3258 3259 hr_reg_write(smac_tb, CFG_SMAC_TB_IDX, phy_port); 3260 hr_reg_write(smac_tb, CFG_SMAC_TB_VF_SMAC_H, reg_smac_h); 3261 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l); 3262 3263 return hns_roce_cmq_send(hr_dev, &desc, 1); 3264 } 3265 3266 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev, 3267 struct hns_roce_v2_mpt_entry *mpt_entry, 3268 struct hns_roce_mr *mr) 3269 { 3270 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 }; 3271 struct ib_device *ibdev = &hr_dev->ib_dev; 3272 dma_addr_t pbl_ba; 3273 int ret; 3274 int i; 3275 3276 ret = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages, 3277 min_t(int, ARRAY_SIZE(pages), mr->npages)); 3278 if (ret) { 3279 ibdev_err(ibdev, "failed to find PBL mtr, ret = %d.\n", ret); 3280 return ret; 3281 } 3282 3283 /* Aligned to the hardware address access unit */ 3284 for (i = 0; i < ARRAY_SIZE(pages); i++) 3285 pages[i] >>= MPT_PBL_BUF_ADDR_S; 3286 3287 pbl_ba = hns_roce_get_mtr_ba(&mr->pbl_mtr); 3288 3289 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3290 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> MPT_PBL_BA_ADDR_S); 3291 hr_reg_write(mpt_entry, MPT_PBL_BA_H, 3292 upper_32_bits(pbl_ba >> MPT_PBL_BA_ADDR_S)); 3293 3294 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); 3295 hr_reg_write(mpt_entry, MPT_PA0_H, upper_32_bits(pages[0])); 3296 3297 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); 3298 hr_reg_write(mpt_entry, MPT_PA1_H, upper_32_bits(pages[1])); 3299 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3300 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3301 3302 return 0; 3303 } 3304 3305 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev, 3306 void *mb_buf, struct hns_roce_mr *mr) 3307 { 3308 struct hns_roce_v2_mpt_entry *mpt_entry; 3309 3310 mpt_entry = mb_buf; 3311 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3312 3313 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3314 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3315 3316 hr_reg_write_bool(mpt_entry, MPT_BIND_EN, 3317 mr->access & IB_ACCESS_MW_BIND); 3318 hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN, 3319 mr->access & IB_ACCESS_REMOTE_ATOMIC); 3320 hr_reg_write_bool(mpt_entry, MPT_RR_EN, 3321 mr->access & IB_ACCESS_REMOTE_READ); 3322 hr_reg_write_bool(mpt_entry, MPT_RW_EN, 3323 mr->access & IB_ACCESS_REMOTE_WRITE); 3324 hr_reg_write_bool(mpt_entry, MPT_LW_EN, 3325 mr->access & IB_ACCESS_LOCAL_WRITE); 3326 3327 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3328 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3329 mpt_entry->lkey = cpu_to_le32(mr->key); 3330 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3331 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3332 3333 if (mr->type != MR_TYPE_MR) 3334 hr_reg_enable(mpt_entry, MPT_PA); 3335 3336 if (mr->type == MR_TYPE_DMA) 3337 return 0; 3338 3339 if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0) 3340 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num); 3341 3342 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3343 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3344 hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD); 3345 3346 return set_mtpt_pbl(hr_dev, mpt_entry, mr); 3347 } 3348 3349 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, 3350 struct hns_roce_mr *mr, int flags, 3351 void *mb_buf) 3352 { 3353 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; 3354 u32 mr_access_flags = mr->access; 3355 int ret = 0; 3356 3357 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3358 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3359 3360 if (flags & IB_MR_REREG_ACCESS) { 3361 hr_reg_write(mpt_entry, MPT_BIND_EN, 3362 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0)); 3363 hr_reg_write(mpt_entry, MPT_ATOMIC_EN, 3364 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 3365 hr_reg_write(mpt_entry, MPT_RR_EN, 3366 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0); 3367 hr_reg_write(mpt_entry, MPT_RW_EN, 3368 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0); 3369 hr_reg_write(mpt_entry, MPT_LW_EN, 3370 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0); 3371 } 3372 3373 if (flags & IB_MR_REREG_TRANS) { 3374 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3375 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3376 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3377 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3378 3379 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 3380 } 3381 3382 return ret; 3383 } 3384 3385 static int hns_roce_v2_frmr_write_mtpt(void *mb_buf, struct hns_roce_mr *mr) 3386 { 3387 dma_addr_t pbl_ba = hns_roce_get_mtr_ba(&mr->pbl_mtr); 3388 struct hns_roce_v2_mpt_entry *mpt_entry; 3389 3390 mpt_entry = mb_buf; 3391 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3392 3393 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3394 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3395 3396 hr_reg_enable(mpt_entry, MPT_RA_EN); 3397 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3398 3399 hr_reg_enable(mpt_entry, MPT_FRE); 3400 hr_reg_clear(mpt_entry, MPT_MR_MW); 3401 hr_reg_enable(mpt_entry, MPT_BPD); 3402 hr_reg_clear(mpt_entry, MPT_PA); 3403 3404 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 1); 3405 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3406 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3407 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3408 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3409 3410 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3411 3412 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3413 MPT_PBL_BA_ADDR_S)); 3414 hr_reg_write(mpt_entry, MPT_PBL_BA_H, 3415 upper_32_bits(pbl_ba >> MPT_PBL_BA_ADDR_S)); 3416 3417 return 0; 3418 } 3419 3420 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw) 3421 { 3422 struct hns_roce_v2_mpt_entry *mpt_entry; 3423 3424 mpt_entry = mb_buf; 3425 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3426 3427 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3428 hr_reg_write(mpt_entry, MPT_PD, mw->pdn); 3429 3430 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3431 hr_reg_enable(mpt_entry, MPT_LW_EN); 3432 3433 hr_reg_enable(mpt_entry, MPT_MR_MW); 3434 hr_reg_enable(mpt_entry, MPT_BPD); 3435 hr_reg_clear(mpt_entry, MPT_PA); 3436 hr_reg_write(mpt_entry, MPT_BQP, 3437 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1); 3438 3439 mpt_entry->lkey = cpu_to_le32(mw->rkey); 3440 3441 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 3442 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : 3443 mw->pbl_hop_num); 3444 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3445 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET); 3446 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3447 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET); 3448 3449 return 0; 3450 } 3451 3452 static int free_mr_post_send_lp_wqe(struct hns_roce_qp *hr_qp) 3453 { 3454 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device); 3455 struct ib_device *ibdev = &hr_dev->ib_dev; 3456 const struct ib_send_wr *bad_wr; 3457 struct ib_rdma_wr rdma_wr = {}; 3458 struct ib_send_wr *send_wr; 3459 int ret; 3460 3461 send_wr = &rdma_wr.wr; 3462 send_wr->opcode = IB_WR_RDMA_WRITE; 3463 3464 ret = hns_roce_v2_post_send(&hr_qp->ibqp, send_wr, &bad_wr); 3465 if (ret) { 3466 ibdev_err_ratelimited(ibdev, "failed to post wqe for free mr, ret = %d.\n", 3467 ret); 3468 return ret; 3469 } 3470 3471 return 0; 3472 } 3473 3474 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3475 struct ib_wc *wc); 3476 3477 static void free_mr_send_cmd_to_hw(struct hns_roce_dev *hr_dev) 3478 { 3479 struct hns_roce_v2_priv *priv = hr_dev->priv; 3480 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 3481 struct ib_wc wc[ARRAY_SIZE(free_mr->rsv_qp)]; 3482 struct ib_device *ibdev = &hr_dev->ib_dev; 3483 struct hns_roce_qp *hr_qp; 3484 unsigned long end; 3485 int cqe_cnt = 0; 3486 int npolled; 3487 int ret; 3488 int i; 3489 3490 /* 3491 * If the device initialization is not complete or in the uninstall 3492 * process, then there is no need to execute free mr. 3493 */ 3494 if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 3495 priv->handle->rinfo.instance_state == HNS_ROCE_STATE_INIT || 3496 hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) 3497 return; 3498 3499 mutex_lock(&free_mr->mutex); 3500 3501 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 3502 hr_qp = free_mr->rsv_qp[i]; 3503 3504 ret = free_mr_post_send_lp_wqe(hr_qp); 3505 if (ret) { 3506 ibdev_err_ratelimited(ibdev, 3507 "failed to send wqe (qp:0x%lx) for free mr, ret = %d.\n", 3508 hr_qp->qpn, ret); 3509 break; 3510 } 3511 3512 cqe_cnt++; 3513 } 3514 3515 end = msecs_to_jiffies(HNS_ROCE_V2_FREE_MR_TIMEOUT) + jiffies; 3516 while (cqe_cnt) { 3517 npolled = hns_roce_v2_poll_cq(&free_mr->rsv_cq->ib_cq, cqe_cnt, wc); 3518 if (npolled < 0) { 3519 ibdev_err_ratelimited(ibdev, 3520 "failed to poll cqe for free mr, remain %d cqe.\n", 3521 cqe_cnt); 3522 goto out; 3523 } 3524 3525 if (time_after(jiffies, end)) { 3526 ibdev_err_ratelimited(ibdev, 3527 "failed to poll cqe for free mr and timeout, remain %d cqe.\n", 3528 cqe_cnt); 3529 goto out; 3530 } 3531 cqe_cnt -= npolled; 3532 } 3533 3534 out: 3535 mutex_unlock(&free_mr->mutex); 3536 } 3537 3538 static void hns_roce_v2_dereg_mr(struct hns_roce_dev *hr_dev) 3539 { 3540 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 3541 free_mr_send_cmd_to_hw(hr_dev); 3542 } 3543 3544 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) 3545 { 3546 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size); 3547 } 3548 3549 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n) 3550 { 3551 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); 3552 3553 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ 3554 return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe : 3555 NULL; 3556 } 3557 3558 static inline void update_cq_db(struct hns_roce_dev *hr_dev, 3559 struct hns_roce_cq *hr_cq) 3560 { 3561 if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) { 3562 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M; 3563 } else { 3564 struct hns_roce_v2_db cq_db = {}; 3565 3566 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3567 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB); 3568 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3569 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1); 3570 3571 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3572 } 3573 } 3574 3575 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3576 struct hns_roce_srq *srq) 3577 { 3578 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3579 struct hns_roce_v2_cqe *cqe, *dest; 3580 u32 prod_index; 3581 int nfreed = 0; 3582 int wqe_index; 3583 u8 owner_bit; 3584 3585 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); 3586 ++prod_index) { 3587 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe) 3588 break; 3589 } 3590 3591 /* 3592 * Now backwards through the CQ, removing CQ entries 3593 * that match our QP by overwriting them with next entries. 3594 */ 3595 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 3596 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); 3597 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) { 3598 if (srq && hr_reg_read(cqe, CQE_S_R)) { 3599 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX); 3600 hns_roce_free_srq_wqe(srq, wqe_index); 3601 } 3602 ++nfreed; 3603 } else if (nfreed) { 3604 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & 3605 hr_cq->ib_cq.cqe); 3606 owner_bit = hr_reg_read(dest, CQE_OWNER); 3607 memcpy(dest, cqe, hr_cq->cqe_size); 3608 hr_reg_write(dest, CQE_OWNER, owner_bit); 3609 } 3610 } 3611 3612 if (nfreed) { 3613 hr_cq->cons_index += nfreed; 3614 update_cq_db(hr_dev, hr_cq); 3615 } 3616 } 3617 3618 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3619 struct hns_roce_srq *srq) 3620 { 3621 spin_lock_irq(&hr_cq->lock); 3622 __hns_roce_v2_cq_clean(hr_cq, qpn, srq); 3623 spin_unlock_irq(&hr_cq->lock); 3624 } 3625 3626 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 3627 struct hns_roce_cq *hr_cq, void *mb_buf, 3628 u64 *mtts, dma_addr_t dma_handle) 3629 { 3630 struct hns_roce_v2_cq_context *cq_context; 3631 3632 cq_context = mb_buf; 3633 memset(cq_context, 0, sizeof(*cq_context)); 3634 3635 hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID); 3636 hr_reg_write(cq_context, CQC_ARM_ST, NO_ARMED); 3637 hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth)); 3638 hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector); 3639 hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn); 3640 3641 if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE) 3642 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B); 3643 3644 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 3645 hr_reg_enable(cq_context, CQC_STASH); 3646 3647 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L, 3648 to_hr_hw_page_addr(mtts[0])); 3649 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H, 3650 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 3651 hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num == 3652 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 3653 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L, 3654 to_hr_hw_page_addr(mtts[1])); 3655 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H, 3656 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 3657 hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ, 3658 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift)); 3659 hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ, 3660 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift)); 3661 hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> CQC_CQE_BA_L_S); 3662 hr_reg_write(cq_context, CQC_CQE_BA_H, dma_handle >> CQC_CQE_BA_H_S); 3663 hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN, 3664 hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB); 3665 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L, 3666 ((u32)hr_cq->db.dma) >> 1); 3667 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H, 3668 hr_cq->db.dma >> CQC_CQE_DB_RECORD_ADDR_H_S); 3669 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, 3670 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 3671 hr_reg_write(cq_context, CQC_CQ_PERIOD, 3672 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 3673 } 3674 3675 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, 3676 enum ib_cq_notify_flags flags) 3677 { 3678 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3679 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3680 struct hns_roce_v2_db cq_db = {}; 3681 u32 notify_flag; 3682 3683 /* 3684 * flags = 0, then notify_flag : next 3685 * flags = 1, then notify flag : solocited 3686 */ 3687 notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 3688 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; 3689 3690 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3691 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY); 3692 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3693 hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn); 3694 hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag); 3695 3696 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3697 3698 return 0; 3699 } 3700 3701 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq, 3702 int num_entries, struct ib_wc *wc) 3703 { 3704 unsigned int left; 3705 int npolled = 0; 3706 3707 left = wq->head - wq->tail; 3708 if (left == 0) 3709 return 0; 3710 3711 left = min_t(unsigned int, (unsigned int)num_entries, left); 3712 while (npolled < left) { 3713 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3714 wc->status = IB_WC_WR_FLUSH_ERR; 3715 wc->vendor_err = 0; 3716 wc->qp = &hr_qp->ibqp; 3717 3718 wq->tail++; 3719 wc++; 3720 npolled++; 3721 } 3722 3723 return npolled; 3724 } 3725 3726 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries, 3727 struct ib_wc *wc) 3728 { 3729 struct hns_roce_qp *hr_qp; 3730 int npolled = 0; 3731 3732 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) { 3733 npolled += sw_comp(hr_qp, &hr_qp->sq, 3734 num_entries - npolled, wc + npolled); 3735 if (npolled >= num_entries) 3736 goto out; 3737 } 3738 3739 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) { 3740 npolled += sw_comp(hr_qp, &hr_qp->rq, 3741 num_entries - npolled, wc + npolled); 3742 if (npolled >= num_entries) 3743 goto out; 3744 } 3745 3746 out: 3747 return npolled; 3748 } 3749 3750 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 3751 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe, 3752 struct ib_wc *wc) 3753 { 3754 static const struct { 3755 u32 cqe_status; 3756 enum ib_wc_status wc_status; 3757 } map[] = { 3758 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS }, 3759 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR }, 3760 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR }, 3761 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR }, 3762 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR }, 3763 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR }, 3764 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR }, 3765 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR }, 3766 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR }, 3767 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR }, 3768 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR }, 3769 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR, 3770 IB_WC_RETRY_EXC_ERR }, 3771 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR }, 3772 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR }, 3773 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR} 3774 }; 3775 3776 u32 cqe_status = hr_reg_read(cqe, CQE_STATUS); 3777 int i; 3778 3779 wc->status = IB_WC_GENERAL_ERR; 3780 for (i = 0; i < ARRAY_SIZE(map); i++) 3781 if (cqe_status == map[i].cqe_status) { 3782 wc->status = map[i].wc_status; 3783 break; 3784 } 3785 3786 if (likely(wc->status == IB_WC_SUCCESS || 3787 wc->status == IB_WC_WR_FLUSH_ERR)) 3788 return; 3789 3790 ibdev_err_ratelimited(&hr_dev->ib_dev, "error cqe status 0x%x:\n", 3791 cqe_status); 3792 print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_NONE, 16, 4, cqe, 3793 cq->cqe_size, false); 3794 wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS); 3795 3796 /* 3797 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in 3798 * the standard protocol, the driver must ignore it and needn't to set 3799 * the QP to an error state. 3800 */ 3801 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR) 3802 return; 3803 3804 flush_cqe(hr_dev, qp); 3805 } 3806 3807 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe, 3808 struct hns_roce_qp **cur_qp) 3809 { 3810 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3811 struct hns_roce_qp *hr_qp = *cur_qp; 3812 u32 qpn; 3813 3814 qpn = hr_reg_read(cqe, CQE_LCL_QPN); 3815 3816 if (!hr_qp || qpn != hr_qp->qpn) { 3817 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 3818 if (unlikely(!hr_qp)) { 3819 ibdev_err(&hr_dev->ib_dev, 3820 "CQ %06lx with entry for unknown QPN %06x\n", 3821 hr_cq->cqn, qpn); 3822 return -EINVAL; 3823 } 3824 *cur_qp = hr_qp; 3825 } 3826 3827 return 0; 3828 } 3829 3830 /* 3831 * mapped-value = 1 + real-value 3832 * The ib wc opcode's real value is start from 0, In order to distinguish 3833 * between initialized and uninitialized map values, we plus 1 to the actual 3834 * value when defining the mapping, so that the validity can be identified by 3835 * checking whether the mapped value is greater than 0. 3836 */ 3837 #define HR_WC_OP_MAP(hr_key, ib_key) \ 3838 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key 3839 3840 static const u32 wc_send_op_map[] = { 3841 HR_WC_OP_MAP(SEND, SEND), 3842 HR_WC_OP_MAP(SEND_WITH_INV, SEND), 3843 HR_WC_OP_MAP(SEND_WITH_IMM, SEND), 3844 HR_WC_OP_MAP(RDMA_READ, RDMA_READ), 3845 HR_WC_OP_MAP(RDMA_WRITE, RDMA_WRITE), 3846 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE), 3847 HR_WC_OP_MAP(ATOM_CMP_AND_SWAP, COMP_SWAP), 3848 HR_WC_OP_MAP(ATOM_FETCH_AND_ADD, FETCH_ADD), 3849 HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP, MASKED_COMP_SWAP), 3850 HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD, MASKED_FETCH_ADD), 3851 HR_WC_OP_MAP(FAST_REG_PMR, REG_MR), 3852 HR_WC_OP_MAP(BIND_MW, REG_MR), 3853 }; 3854 3855 static int to_ib_wc_send_op(u32 hr_opcode) 3856 { 3857 if (hr_opcode >= ARRAY_SIZE(wc_send_op_map)) 3858 return -EINVAL; 3859 3860 return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 : 3861 -EINVAL; 3862 } 3863 3864 static const u32 wc_recv_op_map[] = { 3865 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, WITH_IMM), 3866 HR_WC_OP_MAP(SEND, RECV), 3867 HR_WC_OP_MAP(SEND_WITH_IMM, WITH_IMM), 3868 HR_WC_OP_MAP(SEND_WITH_INV, RECV), 3869 }; 3870 3871 static int to_ib_wc_recv_op(u32 hr_opcode) 3872 { 3873 if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map)) 3874 return -EINVAL; 3875 3876 return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 : 3877 -EINVAL; 3878 } 3879 3880 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3881 { 3882 u32 hr_opcode; 3883 int ib_opcode; 3884 3885 wc->wc_flags = 0; 3886 3887 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3888 switch (hr_opcode) { 3889 case HNS_ROCE_V2_WQE_OP_RDMA_READ: 3890 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3891 break; 3892 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM: 3893 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM: 3894 wc->wc_flags |= IB_WC_WITH_IMM; 3895 break; 3896 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP: 3897 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD: 3898 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP: 3899 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD: 3900 wc->byte_len = 8; 3901 break; 3902 default: 3903 break; 3904 } 3905 3906 ib_opcode = to_ib_wc_send_op(hr_opcode); 3907 if (ib_opcode < 0) 3908 wc->status = IB_WC_GENERAL_ERR; 3909 else 3910 wc->opcode = ib_opcode; 3911 } 3912 3913 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3914 { 3915 u32 hr_opcode; 3916 int ib_opcode; 3917 3918 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3919 3920 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3921 switch (hr_opcode) { 3922 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: 3923 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: 3924 wc->wc_flags = IB_WC_WITH_IMM; 3925 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata)); 3926 break; 3927 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: 3928 wc->wc_flags = IB_WC_WITH_INVALIDATE; 3929 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); 3930 break; 3931 default: 3932 wc->wc_flags = 0; 3933 } 3934 3935 ib_opcode = to_ib_wc_recv_op(hr_opcode); 3936 if (ib_opcode < 0) 3937 wc->status = IB_WC_GENERAL_ERR; 3938 else 3939 wc->opcode = ib_opcode; 3940 3941 wc->sl = hr_reg_read(cqe, CQE_SL); 3942 wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN); 3943 wc->slid = 0; 3944 wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0; 3945 wc->port_num = hr_reg_read(cqe, CQE_PORTN); 3946 wc->pkey_index = 0; 3947 3948 if (hr_reg_read(cqe, CQE_VID_VLD)) { 3949 wc->vlan_id = hr_reg_read(cqe, CQE_VID); 3950 wc->wc_flags |= IB_WC_WITH_VLAN; 3951 } else { 3952 wc->vlan_id = 0xffff; 3953 } 3954 3955 wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE); 3956 3957 return 0; 3958 } 3959 3960 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, 3961 struct hns_roce_qp **cur_qp, struct ib_wc *wc) 3962 { 3963 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3964 struct hns_roce_qp *qp = *cur_qp; 3965 struct hns_roce_srq *srq = NULL; 3966 struct hns_roce_v2_cqe *cqe; 3967 struct hns_roce_wq *wq; 3968 int is_send; 3969 u16 wqe_idx; 3970 int ret; 3971 3972 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index); 3973 if (!cqe) 3974 return -EAGAIN; 3975 3976 ++hr_cq->cons_index; 3977 /* Memory barrier */ 3978 rmb(); 3979 3980 ret = get_cur_qp(hr_cq, cqe, &qp); 3981 if (ret) 3982 return ret; 3983 3984 wc->qp = &qp->ibqp; 3985 wc->vendor_err = 0; 3986 3987 wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX); 3988 3989 is_send = !hr_reg_read(cqe, CQE_S_R); 3990 if (is_send) { 3991 wq = &qp->sq; 3992 3993 /* If sg_signal_bit is set, tail pointer will be updated to 3994 * the WQE corresponding to the current CQE. 3995 */ 3996 if (qp->sq_signal_bits) 3997 wq->tail += (wqe_idx - (u16)wq->tail) & 3998 (wq->wqe_cnt - 1); 3999 4000 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 4001 ++wq->tail; 4002 4003 fill_send_wc(wc, cqe); 4004 } else { 4005 if (qp->ibqp.srq) { 4006 srq = to_hr_srq(qp->ibqp.srq); 4007 wc->wr_id = srq->wrid[wqe_idx]; 4008 hns_roce_free_srq_wqe(srq, wqe_idx); 4009 } else { 4010 wq = &qp->rq; 4011 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 4012 ++wq->tail; 4013 } 4014 4015 ret = fill_recv_wc(wc, cqe); 4016 } 4017 4018 get_cqe_status(hr_dev, qp, hr_cq, cqe, wc); 4019 if (unlikely(wc->status != IB_WC_SUCCESS)) 4020 return 0; 4021 4022 return ret; 4023 } 4024 4025 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 4026 struct ib_wc *wc) 4027 { 4028 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 4029 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 4030 struct hns_roce_qp *cur_qp = NULL; 4031 unsigned long flags; 4032 int npolled; 4033 4034 spin_lock_irqsave(&hr_cq->lock, flags); 4035 4036 /* 4037 * When the device starts to reset, the state is RST_DOWN. At this time, 4038 * there may still be some valid CQEs in the hardware that are not 4039 * polled. Therefore, it is not allowed to switch to the software mode 4040 * immediately. When the state changes to UNINIT, CQE no longer exists 4041 * in the hardware, and then switch to software mode. 4042 */ 4043 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) { 4044 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc); 4045 goto out; 4046 } 4047 4048 for (npolled = 0; npolled < num_entries; ++npolled) { 4049 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) 4050 break; 4051 } 4052 4053 if (npolled) 4054 update_cq_db(hr_dev, hr_cq); 4055 4056 out: 4057 spin_unlock_irqrestore(&hr_cq->lock, flags); 4058 4059 return npolled; 4060 } 4061 4062 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type, 4063 u32 step_idx, u8 *mbox_cmd) 4064 { 4065 u8 cmd; 4066 4067 switch (type) { 4068 case HEM_TYPE_QPC: 4069 cmd = HNS_ROCE_CMD_WRITE_QPC_BT0; 4070 break; 4071 case HEM_TYPE_MTPT: 4072 cmd = HNS_ROCE_CMD_WRITE_MPT_BT0; 4073 break; 4074 case HEM_TYPE_CQC: 4075 cmd = HNS_ROCE_CMD_WRITE_CQC_BT0; 4076 break; 4077 case HEM_TYPE_SRQC: 4078 cmd = HNS_ROCE_CMD_WRITE_SRQC_BT0; 4079 break; 4080 case HEM_TYPE_SCCC: 4081 cmd = HNS_ROCE_CMD_WRITE_SCCC_BT0; 4082 break; 4083 case HEM_TYPE_QPC_TIMER: 4084 cmd = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0; 4085 break; 4086 case HEM_TYPE_CQC_TIMER: 4087 cmd = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0; 4088 break; 4089 default: 4090 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type); 4091 return -EINVAL; 4092 } 4093 4094 *mbox_cmd = cmd + step_idx; 4095 4096 return 0; 4097 } 4098 4099 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj, 4100 dma_addr_t base_addr) 4101 { 4102 struct hns_roce_cmq_desc desc; 4103 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 4104 u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz); 4105 u64 addr = to_hr_hw_page_addr(base_addr); 4106 4107 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 4108 4109 hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr)); 4110 hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr)); 4111 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 4112 4113 return hns_roce_cmq_send(hr_dev, &desc, 1); 4114 } 4115 4116 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj, 4117 dma_addr_t base_addr, u32 hem_type, u32 step_idx) 4118 { 4119 int ret; 4120 u8 cmd; 4121 4122 if (unlikely(hem_type == HEM_TYPE_GMV)) 4123 return config_gmv_ba_to_hw(hr_dev, obj, base_addr); 4124 4125 if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx)) 4126 return 0; 4127 4128 ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &cmd); 4129 if (ret < 0) 4130 return ret; 4131 4132 return config_hem_ba_to_hw(hr_dev, base_addr, cmd, obj); 4133 } 4134 4135 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 4136 struct hns_roce_hem_table *table, int obj, 4137 u32 step_idx) 4138 { 4139 struct hns_roce_hem_mhop mhop; 4140 struct hns_roce_hem *hem; 4141 unsigned long mhop_obj = obj; 4142 int i, j, k; 4143 int ret = 0; 4144 u64 hem_idx = 0; 4145 u64 l1_idx = 0; 4146 u64 bt_ba = 0; 4147 u32 chunk_ba_num; 4148 u32 hop_num; 4149 4150 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4151 return 0; 4152 4153 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); 4154 i = mhop.l0_idx; 4155 j = mhop.l1_idx; 4156 k = mhop.l2_idx; 4157 hop_num = mhop.hop_num; 4158 chunk_ba_num = mhop.bt_chunk_size / 8; 4159 4160 if (hop_num == 2) { 4161 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + 4162 k; 4163 l1_idx = i * chunk_ba_num + j; 4164 } else if (hop_num == 1) { 4165 hem_idx = i * chunk_ba_num + j; 4166 } else if (hop_num == HNS_ROCE_HOP_NUM_0) { 4167 hem_idx = i; 4168 } 4169 4170 if (table->type == HEM_TYPE_SCCC) 4171 obj = mhop.l0_idx; 4172 4173 if (check_whether_last_step(hop_num, step_idx)) { 4174 hem = table->hem[hem_idx]; 4175 4176 ret = set_hem_to_hw(hr_dev, obj, hem->dma, table->type, step_idx); 4177 } else { 4178 if (step_idx == 0) 4179 bt_ba = table->bt_l0_dma_addr[i]; 4180 else if (step_idx == 1 && hop_num == 2) 4181 bt_ba = table->bt_l1_dma_addr[l1_idx]; 4182 4183 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx); 4184 } 4185 4186 return ret; 4187 } 4188 4189 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 4190 struct hns_roce_hem_table *table, 4191 int tag, u32 step_idx) 4192 { 4193 struct hns_roce_cmd_mailbox *mailbox; 4194 struct device *dev = hr_dev->dev; 4195 u8 cmd = 0xff; 4196 int ret; 4197 4198 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4199 return 0; 4200 4201 switch (table->type) { 4202 case HEM_TYPE_QPC: 4203 cmd = HNS_ROCE_CMD_DESTROY_QPC_BT0; 4204 break; 4205 case HEM_TYPE_MTPT: 4206 cmd = HNS_ROCE_CMD_DESTROY_MPT_BT0; 4207 break; 4208 case HEM_TYPE_CQC: 4209 cmd = HNS_ROCE_CMD_DESTROY_CQC_BT0; 4210 break; 4211 case HEM_TYPE_SRQC: 4212 cmd = HNS_ROCE_CMD_DESTROY_SRQC_BT0; 4213 break; 4214 case HEM_TYPE_SCCC: 4215 case HEM_TYPE_QPC_TIMER: 4216 case HEM_TYPE_CQC_TIMER: 4217 case HEM_TYPE_GMV: 4218 return 0; 4219 default: 4220 dev_warn(dev, "table %u not to be destroyed by mailbox!\n", 4221 table->type); 4222 return 0; 4223 } 4224 4225 cmd += step_idx; 4226 4227 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4228 if (IS_ERR(mailbox)) 4229 return PTR_ERR(mailbox); 4230 4231 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, cmd, tag); 4232 4233 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4234 return ret; 4235 } 4236 4237 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, 4238 struct hns_roce_v2_qp_context *context, 4239 struct hns_roce_v2_qp_context *qpc_mask, 4240 struct hns_roce_qp *hr_qp) 4241 { 4242 struct hns_roce_cmd_mailbox *mailbox; 4243 int qpc_size; 4244 int ret; 4245 4246 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4247 if (IS_ERR(mailbox)) 4248 return PTR_ERR(mailbox); 4249 4250 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */ 4251 qpc_size = hr_dev->caps.qpc_sz; 4252 memcpy(mailbox->buf, context, qpc_size); 4253 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size); 4254 4255 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 4256 HNS_ROCE_CMD_MODIFY_QPC, hr_qp->qpn); 4257 4258 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4259 4260 return ret; 4261 } 4262 4263 static void set_access_flags(struct hns_roce_qp *hr_qp, 4264 struct hns_roce_v2_qp_context *context, 4265 struct hns_roce_v2_qp_context *qpc_mask, 4266 const struct ib_qp_attr *attr, int attr_mask) 4267 { 4268 u8 dest_rd_atomic; 4269 u32 access_flags; 4270 4271 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? 4272 attr->max_dest_rd_atomic : hr_qp->resp_depth; 4273 4274 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ? 4275 attr->qp_access_flags : hr_qp->atomic_rd_en; 4276 4277 if (!dest_rd_atomic) 4278 access_flags &= IB_ACCESS_REMOTE_WRITE; 4279 4280 hr_reg_write_bool(context, QPC_RRE, 4281 access_flags & IB_ACCESS_REMOTE_READ); 4282 hr_reg_clear(qpc_mask, QPC_RRE); 4283 4284 hr_reg_write_bool(context, QPC_RWE, 4285 access_flags & IB_ACCESS_REMOTE_WRITE); 4286 hr_reg_clear(qpc_mask, QPC_RWE); 4287 4288 hr_reg_write_bool(context, QPC_ATE, 4289 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4290 hr_reg_clear(qpc_mask, QPC_ATE); 4291 hr_reg_write_bool(context, QPC_EXT_ATE, 4292 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4293 hr_reg_clear(qpc_mask, QPC_EXT_ATE); 4294 } 4295 4296 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp, 4297 struct hns_roce_v2_qp_context *context) 4298 { 4299 hr_reg_write(context, QPC_SGE_SHIFT, 4300 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt, 4301 hr_qp->sge.sge_shift)); 4302 4303 hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt)); 4304 4305 hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt)); 4306 } 4307 4308 static inline int get_cqn(struct ib_cq *ib_cq) 4309 { 4310 return ib_cq ? to_hr_cq(ib_cq)->cqn : 0; 4311 } 4312 4313 static inline int get_pdn(struct ib_pd *ib_pd) 4314 { 4315 return ib_pd ? to_hr_pd(ib_pd)->pdn : 0; 4316 } 4317 4318 static void modify_qp_reset_to_init(struct ib_qp *ibqp, 4319 struct hns_roce_v2_qp_context *context) 4320 { 4321 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4322 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4323 4324 /* 4325 * In v2 engine, software pass context and context mask to hardware 4326 * when modifying qp. If software need modify some fields in context, 4327 * we should set all bits of the relevant fields in context mask to 4328 * 0 at the same time, else set them to 0x1. 4329 */ 4330 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4331 4332 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4333 4334 hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs)); 4335 4336 set_qpc_wqe_cnt(hr_qp, context); 4337 4338 /* No VLAN need to set 0xFFF */ 4339 hr_reg_write(context, QPC_VLAN_ID, 0xfff); 4340 4341 if (ibqp->qp_type == IB_QPT_XRC_TGT) { 4342 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn); 4343 4344 hr_reg_enable(context, QPC_XRC_QP_TYPE); 4345 } 4346 4347 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 4348 hr_reg_enable(context, QPC_RQ_RECORD_EN); 4349 4350 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 4351 hr_reg_enable(context, QPC_OWNER_MODE); 4352 4353 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L, 4354 lower_32_bits(hr_qp->rdb.dma) >> 1); 4355 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H, 4356 upper_32_bits(hr_qp->rdb.dma)); 4357 4358 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4359 4360 if (ibqp->srq) { 4361 hr_reg_enable(context, QPC_SRQ_EN); 4362 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4363 } 4364 4365 hr_reg_enable(context, QPC_FRE); 4366 4367 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4368 4369 if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ) 4370 return; 4371 4372 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 4373 hr_reg_enable(&context->ext, QPCEX_STASH); 4374 } 4375 4376 static void modify_qp_init_to_init(struct ib_qp *ibqp, 4377 struct hns_roce_v2_qp_context *context, 4378 struct hns_roce_v2_qp_context *qpc_mask) 4379 { 4380 /* 4381 * In v2 engine, software pass context and context mask to hardware 4382 * when modifying qp. If software need modify some fields in context, 4383 * we should set all bits of the relevant fields in context mask to 4384 * 0 at the same time, else set them to 0x1. 4385 */ 4386 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4387 hr_reg_clear(qpc_mask, QPC_TST); 4388 4389 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4390 hr_reg_clear(qpc_mask, QPC_PD); 4391 4392 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4393 hr_reg_clear(qpc_mask, QPC_RX_CQN); 4394 4395 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4396 hr_reg_clear(qpc_mask, QPC_TX_CQN); 4397 4398 if (ibqp->srq) { 4399 hr_reg_enable(context, QPC_SRQ_EN); 4400 hr_reg_clear(qpc_mask, QPC_SRQ_EN); 4401 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4402 hr_reg_clear(qpc_mask, QPC_SRQN); 4403 } 4404 } 4405 4406 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev, 4407 struct hns_roce_qp *hr_qp, 4408 struct hns_roce_v2_qp_context *context, 4409 struct hns_roce_v2_qp_context *qpc_mask) 4410 { 4411 u64 mtts[MTT_MIN_COUNT] = { 0 }; 4412 u64 wqe_sge_ba; 4413 int ret; 4414 4415 /* Search qp buf's mtts */ 4416 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts, 4417 MTT_MIN_COUNT); 4418 if (hr_qp->rq.wqe_cnt && ret) { 4419 ibdev_err(&hr_dev->ib_dev, 4420 "failed to find QP(0x%lx) RQ WQE buf, ret = %d.\n", 4421 hr_qp->qpn, ret); 4422 return ret; 4423 } 4424 4425 wqe_sge_ba = hns_roce_get_mtr_ba(&hr_qp->mtr); 4426 4427 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3); 4428 qpc_mask->wqe_sge_ba = 0; 4429 4430 /* 4431 * In v2 engine, software pass context and context mask to hardware 4432 * when modifying qp. If software need modify some fields in context, 4433 * we should set all bits of the relevant fields in context mask to 4434 * 0 at the same time, else set them to 0x1. 4435 */ 4436 hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3)); 4437 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H); 4438 4439 hr_reg_write(context, QPC_SQ_HOP_NUM, 4440 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num, 4441 hr_qp->sq.wqe_cnt)); 4442 hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM); 4443 4444 hr_reg_write(context, QPC_SGE_HOP_NUM, 4445 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num, 4446 hr_qp->sge.sge_cnt)); 4447 hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM); 4448 4449 hr_reg_write(context, QPC_RQ_HOP_NUM, 4450 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num, 4451 hr_qp->rq.wqe_cnt)); 4452 4453 hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM); 4454 4455 hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ, 4456 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift)); 4457 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ); 4458 4459 hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ, 4460 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift)); 4461 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ); 4462 4463 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 4464 qpc_mask->rq_cur_blk_addr = 0; 4465 4466 hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H, 4467 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 4468 hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H); 4469 4470 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 4471 context->rq_nxt_blk_addr = 4472 cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 4473 qpc_mask->rq_nxt_blk_addr = 0; 4474 hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H, 4475 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 4476 hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H); 4477 } 4478 4479 return 0; 4480 } 4481 4482 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev, 4483 struct hns_roce_qp *hr_qp, 4484 struct hns_roce_v2_qp_context *context, 4485 struct hns_roce_v2_qp_context *qpc_mask) 4486 { 4487 struct ib_device *ibdev = &hr_dev->ib_dev; 4488 u64 sge_cur_blk = 0; 4489 u64 sq_cur_blk = 0; 4490 int ret; 4491 4492 /* search qp buf's mtts */ 4493 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->sq.offset, 4494 &sq_cur_blk, 1); 4495 if (ret) { 4496 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ WQE buf, ret = %d.\n", 4497 hr_qp->qpn, ret); 4498 return ret; 4499 } 4500 if (hr_qp->sge.sge_cnt > 0) { 4501 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 4502 hr_qp->sge.offset, &sge_cur_blk, 1); 4503 if (ret) { 4504 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf, ret = %d.\n", 4505 hr_qp->qpn, ret); 4506 return ret; 4507 } 4508 } 4509 4510 /* 4511 * In v2 engine, software pass context and context mask to hardware 4512 * when modifying qp. If software need modify some fields in context, 4513 * we should set all bits of the relevant fields in context mask to 4514 * 0 at the same time, else set them to 0x1. 4515 */ 4516 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L, 4517 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4518 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H, 4519 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4520 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L); 4521 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H); 4522 4523 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L, 4524 lower_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4525 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H, 4526 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4527 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L); 4528 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H); 4529 4530 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L, 4531 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4532 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H, 4533 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4534 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L); 4535 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H); 4536 4537 return 0; 4538 } 4539 4540 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp, 4541 const struct ib_qp_attr *attr) 4542 { 4543 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 4544 return IB_MTU_4096; 4545 4546 return attr->path_mtu; 4547 } 4548 4549 static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 4550 const struct ib_qp_attr *attr, int attr_mask, 4551 struct hns_roce_v2_qp_context *context, 4552 struct hns_roce_v2_qp_context *qpc_mask, 4553 struct ib_udata *udata) 4554 { 4555 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(udata, 4556 struct hns_roce_ucontext, ibucontext); 4557 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4558 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4559 struct ib_device *ibdev = &hr_dev->ib_dev; 4560 dma_addr_t trrl_ba; 4561 dma_addr_t irrl_ba; 4562 enum ib_mtu ib_mtu; 4563 const u8 *smac; 4564 u8 lp_pktn_ini; 4565 u64 *mtts; 4566 u8 *dmac; 4567 u32 port; 4568 int mtu; 4569 int ret; 4570 4571 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask); 4572 if (ret) { 4573 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret); 4574 return ret; 4575 } 4576 4577 /* Search IRRL's mtts */ 4578 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, 4579 hr_qp->qpn, &irrl_ba); 4580 if (!mtts) { 4581 ibdev_err(ibdev, "failed to find qp irrl_table.\n"); 4582 return -EINVAL; 4583 } 4584 4585 /* Search TRRL's mtts */ 4586 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, 4587 hr_qp->qpn, &trrl_ba); 4588 if (!mtts) { 4589 ibdev_err(ibdev, "failed to find qp trrl_table.\n"); 4590 return -EINVAL; 4591 } 4592 4593 if (attr_mask & IB_QP_ALT_PATH) { 4594 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n", 4595 attr_mask); 4596 return -EINVAL; 4597 } 4598 4599 hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> QPC_TRRL_BA_L_S); 4600 hr_reg_clear(qpc_mask, QPC_TRRL_BA_L); 4601 context->trrl_ba = cpu_to_le32(trrl_ba >> QPC_TRRL_BA_M_S); 4602 qpc_mask->trrl_ba = 0; 4603 hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> QPC_TRRL_BA_H_S); 4604 hr_reg_clear(qpc_mask, QPC_TRRL_BA_H); 4605 4606 context->irrl_ba = cpu_to_le32(irrl_ba >> QPC_IRRL_BA_L_S); 4607 qpc_mask->irrl_ba = 0; 4608 hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> QPC_IRRL_BA_H_S); 4609 hr_reg_clear(qpc_mask, QPC_IRRL_BA_H); 4610 4611 hr_reg_enable(context, QPC_RMT_E2E); 4612 hr_reg_clear(qpc_mask, QPC_RMT_E2E); 4613 4614 hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits); 4615 hr_reg_clear(qpc_mask, QPC_SIG_TYPE); 4616 4617 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; 4618 4619 smac = (const u8 *)hr_dev->dev_addr[port]; 4620 dmac = (u8 *)attr->ah_attr.roce.dmac; 4621 /* when dmac equals smac or loop_idc is 1, it should loopback */ 4622 if (ether_addr_equal_unaligned(dmac, smac) || 4623 hr_dev->loop_idc == 0x1) { 4624 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc); 4625 hr_reg_clear(qpc_mask, QPC_LBI); 4626 } 4627 4628 if (attr_mask & IB_QP_DEST_QPN) { 4629 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num); 4630 hr_reg_clear(qpc_mask, QPC_DQPN); 4631 } 4632 4633 memcpy(&context->dmac, dmac, sizeof(u32)); 4634 hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4]))); 4635 qpc_mask->dmac = 0; 4636 hr_reg_clear(qpc_mask, QPC_DMAC_H); 4637 4638 ib_mtu = get_mtu(ibqp, attr); 4639 hr_qp->path_mtu = ib_mtu; 4640 4641 mtu = ib_mtu_enum_to_int(ib_mtu); 4642 if (WARN_ON(mtu <= 0)) 4643 return -EINVAL; 4644 #define MIN_LP_MSG_LEN 1024 4645 /* mtu * (2 ^ lp_pktn_ini) should be in the range of 1024 to mtu */ 4646 lp_pktn_ini = ilog2(max(mtu, MIN_LP_MSG_LEN) / mtu); 4647 4648 if (attr_mask & IB_QP_PATH_MTU) { 4649 hr_reg_write(context, QPC_MTU, ib_mtu); 4650 hr_reg_clear(qpc_mask, QPC_MTU); 4651 } 4652 4653 hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini); 4654 hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI); 4655 4656 /* ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI */ 4657 hr_reg_write(context, QPC_ACK_REQ_FREQ, lp_pktn_ini); 4658 hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ); 4659 4660 hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR); 4661 hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN); 4662 hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE); 4663 4664 context->rq_rnr_timer = 0; 4665 qpc_mask->rq_rnr_timer = 0; 4666 4667 hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX); 4668 hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX); 4669 4670 #define MAX_LP_SGEN 3 4671 /* rocee send 2^lp_sgen_ini segs every time */ 4672 hr_reg_write(context, QPC_LP_SGEN_INI, MAX_LP_SGEN); 4673 hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI); 4674 4675 if (udata && ibqp->qp_type == IB_QPT_RC && 4676 (uctx->config & HNS_ROCE_RQ_INLINE_FLAGS)) { 4677 hr_reg_write_bool(context, QPC_RQIE, 4678 hr_dev->caps.flags & 4679 HNS_ROCE_CAP_FLAG_RQ_INLINE); 4680 hr_reg_clear(qpc_mask, QPC_RQIE); 4681 } 4682 4683 if (udata && 4684 (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_XRC_TGT) && 4685 (uctx->config & HNS_ROCE_CQE_INLINE_FLAGS)) { 4686 hr_reg_write_bool(context, QPC_CQEIE, 4687 hr_dev->caps.flags & 4688 HNS_ROCE_CAP_FLAG_CQE_INLINE); 4689 hr_reg_clear(qpc_mask, QPC_CQEIE); 4690 4691 hr_reg_write(context, QPC_CQEIS, 0); 4692 hr_reg_clear(qpc_mask, QPC_CQEIS); 4693 } 4694 4695 return 0; 4696 } 4697 4698 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, int attr_mask, 4699 struct hns_roce_v2_qp_context *context, 4700 struct hns_roce_v2_qp_context *qpc_mask) 4701 { 4702 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4703 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4704 struct ib_device *ibdev = &hr_dev->ib_dev; 4705 int ret; 4706 4707 /* Not support alternate path and path migration */ 4708 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) { 4709 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); 4710 return -EINVAL; 4711 } 4712 4713 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask); 4714 if (ret) { 4715 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret); 4716 return ret; 4717 } 4718 4719 /* 4720 * Set some fields in context to zero, Because the default values 4721 * of all fields in context are zero, we need not set them to 0 again. 4722 * but we should set the relevant fields of context mask to 0. 4723 */ 4724 hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX); 4725 4726 hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN); 4727 4728 hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE); 4729 hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD); 4730 hr_reg_clear(qpc_mask, QPC_IRRL_PSN); 4731 4732 hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL); 4733 4734 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN); 4735 4736 hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG); 4737 4738 hr_reg_clear(qpc_mask, QPC_CHECK_FLG); 4739 4740 hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD); 4741 4742 return 0; 4743 } 4744 4745 static int alloc_dip_entry(struct xarray *dip_xa, u32 qpn) 4746 { 4747 struct hns_roce_dip *hr_dip; 4748 int ret; 4749 4750 hr_dip = xa_load(dip_xa, qpn); 4751 if (hr_dip) 4752 return 0; 4753 4754 hr_dip = kzalloc(sizeof(*hr_dip), GFP_KERNEL); 4755 if (!hr_dip) 4756 return -ENOMEM; 4757 4758 ret = xa_err(xa_store(dip_xa, qpn, hr_dip, GFP_KERNEL)); 4759 if (ret) 4760 kfree(hr_dip); 4761 4762 return ret; 4763 } 4764 4765 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4766 u32 *dip_idx) 4767 { 4768 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4769 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4770 struct xarray *dip_xa = &hr_dev->qp_table.dip_xa; 4771 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4772 struct hns_roce_dip *hr_dip; 4773 unsigned long idx; 4774 int ret = 0; 4775 4776 ret = alloc_dip_entry(dip_xa, ibqp->qp_num); 4777 if (ret) 4778 return ret; 4779 4780 xa_lock(dip_xa); 4781 4782 xa_for_each(dip_xa, idx, hr_dip) { 4783 if (hr_dip->qp_cnt && 4784 !memcmp(grh->dgid.raw, hr_dip->dgid, GID_LEN_V2)) { 4785 *dip_idx = hr_dip->dip_idx; 4786 hr_dip->qp_cnt++; 4787 hr_qp->dip = hr_dip; 4788 goto out; 4789 } 4790 } 4791 4792 /* If no dgid is found, a new dip and a mapping between dgid and 4793 * dip_idx will be created. 4794 */ 4795 xa_for_each(dip_xa, idx, hr_dip) { 4796 if (hr_dip->qp_cnt) 4797 continue; 4798 4799 *dip_idx = idx; 4800 memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4801 hr_dip->dip_idx = idx; 4802 hr_dip->qp_cnt++; 4803 hr_qp->dip = hr_dip; 4804 break; 4805 } 4806 4807 /* This should never happen. */ 4808 if (WARN_ON_ONCE(!hr_qp->dip)) 4809 ret = -ENOSPC; 4810 4811 out: 4812 xa_unlock(dip_xa); 4813 return ret; 4814 } 4815 4816 enum { 4817 CONG_DCQCN, 4818 CONG_WINDOW, 4819 }; 4820 4821 enum { 4822 UNSUPPORT_CONG_LEVEL, 4823 SUPPORT_CONG_LEVEL, 4824 }; 4825 4826 enum { 4827 CONG_LDCP, 4828 CONG_HC3, 4829 }; 4830 4831 enum { 4832 DIP_INVALID, 4833 DIP_VALID, 4834 }; 4835 4836 enum { 4837 WND_LIMIT, 4838 WND_UNLIMIT, 4839 }; 4840 4841 static int check_cong_type(struct ib_qp *ibqp, 4842 struct hns_roce_congestion_algorithm *cong_alg) 4843 { 4844 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4845 4846 /* different congestion types match different configurations */ 4847 switch (hr_qp->cong_type) { 4848 case CONG_TYPE_DCQCN: 4849 cong_alg->alg_sel = CONG_DCQCN; 4850 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4851 cong_alg->dip_vld = DIP_INVALID; 4852 cong_alg->wnd_mode_sel = WND_LIMIT; 4853 break; 4854 case CONG_TYPE_LDCP: 4855 cong_alg->alg_sel = CONG_WINDOW; 4856 cong_alg->alg_sub_sel = CONG_LDCP; 4857 cong_alg->dip_vld = DIP_INVALID; 4858 cong_alg->wnd_mode_sel = WND_UNLIMIT; 4859 break; 4860 case CONG_TYPE_HC3: 4861 cong_alg->alg_sel = CONG_WINDOW; 4862 cong_alg->alg_sub_sel = CONG_HC3; 4863 cong_alg->dip_vld = DIP_INVALID; 4864 cong_alg->wnd_mode_sel = WND_LIMIT; 4865 break; 4866 case CONG_TYPE_DIP: 4867 cong_alg->alg_sel = CONG_DCQCN; 4868 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4869 cong_alg->dip_vld = DIP_VALID; 4870 cong_alg->wnd_mode_sel = WND_LIMIT; 4871 break; 4872 default: 4873 hr_qp->cong_type = CONG_TYPE_DCQCN; 4874 cong_alg->alg_sel = CONG_DCQCN; 4875 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4876 cong_alg->dip_vld = DIP_INVALID; 4877 cong_alg->wnd_mode_sel = WND_LIMIT; 4878 break; 4879 } 4880 4881 return 0; 4882 } 4883 4884 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4885 struct hns_roce_v2_qp_context *context, 4886 struct hns_roce_v2_qp_context *qpc_mask) 4887 { 4888 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4889 struct hns_roce_congestion_algorithm cong_field; 4890 struct ib_device *ibdev = ibqp->device; 4891 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 4892 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4893 u32 dip_idx = 0; 4894 int ret; 4895 4896 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 || 4897 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE) 4898 return 0; 4899 4900 ret = check_cong_type(ibqp, &cong_field); 4901 if (ret) 4902 return ret; 4903 4904 hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id + 4905 hr_qp->cong_type * HNS_ROCE_CONG_SIZE); 4906 hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID); 4907 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel); 4908 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL); 4909 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL, 4910 cong_field.alg_sub_sel); 4911 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL); 4912 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld); 4913 hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD); 4914 hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN, 4915 cong_field.wnd_mode_sel); 4916 hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN); 4917 4918 /* if dip is disabled, there is no need to set dip idx */ 4919 if (cong_field.dip_vld == 0) 4920 return 0; 4921 4922 ret = get_dip_ctx_idx(ibqp, attr, &dip_idx); 4923 if (ret) { 4924 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret); 4925 return ret; 4926 } 4927 4928 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx); 4929 hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0); 4930 4931 return 0; 4932 } 4933 4934 static int hns_roce_hw_v2_get_dscp(struct hns_roce_dev *hr_dev, u8 dscp, 4935 u8 *tc_mode, u8 *priority) 4936 { 4937 struct hns_roce_v2_priv *priv = hr_dev->priv; 4938 struct hnae3_handle *handle = priv->handle; 4939 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 4940 4941 if (!ops->get_dscp_prio) 4942 return -EOPNOTSUPP; 4943 4944 return ops->get_dscp_prio(handle, dscp, tc_mode, priority); 4945 } 4946 4947 bool check_sl_valid(struct hns_roce_dev *hr_dev, u8 sl) 4948 { 4949 u32 max_sl; 4950 4951 max_sl = min_t(u32, MAX_SERVICE_LEVEL, hr_dev->caps.sl_num - 1); 4952 if (unlikely(sl > max_sl)) { 4953 ibdev_err_ratelimited(&hr_dev->ib_dev, 4954 "failed to set SL(%u). Shouldn't be larger than %u.\n", 4955 sl, max_sl); 4956 return false; 4957 } 4958 4959 return true; 4960 } 4961 4962 static int hns_roce_set_sl(struct ib_qp *ibqp, 4963 const struct ib_qp_attr *attr, 4964 struct hns_roce_v2_qp_context *context, 4965 struct hns_roce_v2_qp_context *qpc_mask) 4966 { 4967 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4968 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4969 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4970 struct ib_device *ibdev = &hr_dev->ib_dev; 4971 int ret; 4972 4973 ret = hns_roce_hw_v2_get_dscp(hr_dev, get_tclass(&attr->ah_attr.grh), 4974 &hr_qp->tc_mode, &hr_qp->priority); 4975 if (ret && ret != -EOPNOTSUPP && 4976 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 4977 ibdev_err_ratelimited(ibdev, 4978 "failed to get dscp, ret = %d.\n", ret); 4979 return ret; 4980 } 4981 4982 if (hr_qp->tc_mode == HNAE3_TC_MAP_MODE_DSCP && 4983 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 4984 hr_qp->sl = hr_qp->priority; 4985 else 4986 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 4987 4988 if (!check_sl_valid(hr_dev, hr_qp->sl)) 4989 return -EINVAL; 4990 4991 hr_reg_write(context, QPC_SL, hr_qp->sl); 4992 hr_reg_clear(qpc_mask, QPC_SL); 4993 4994 return 0; 4995 } 4996 4997 static int hns_roce_v2_set_path(struct ib_qp *ibqp, 4998 const struct ib_qp_attr *attr, 4999 int attr_mask, 5000 struct hns_roce_v2_qp_context *context, 5001 struct hns_roce_v2_qp_context *qpc_mask) 5002 { 5003 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 5004 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5005 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5006 struct ib_device *ibdev = &hr_dev->ib_dev; 5007 const struct ib_gid_attr *gid_attr = NULL; 5008 u8 sl = rdma_ah_get_sl(&attr->ah_attr); 5009 int is_roce_protocol; 5010 u16 vlan_id = 0xffff; 5011 bool is_udp = false; 5012 u8 ib_port; 5013 u8 hr_port; 5014 int ret; 5015 5016 /* 5017 * If free_mr_en of qp is set, it means that this qp comes from 5018 * free mr. This qp will perform the loopback operation. 5019 * In the loopback scenario, only sl needs to be set. 5020 */ 5021 if (hr_qp->free_mr_en) { 5022 if (!check_sl_valid(hr_dev, sl)) 5023 return -EINVAL; 5024 hr_reg_write(context, QPC_SL, sl); 5025 hr_reg_clear(qpc_mask, QPC_SL); 5026 hr_qp->sl = sl; 5027 return 0; 5028 } 5029 5030 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1; 5031 hr_port = ib_port - 1; 5032 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) && 5033 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 5034 5035 if (is_roce_protocol) { 5036 gid_attr = attr->ah_attr.grh.sgid_attr; 5037 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL); 5038 if (ret) 5039 return ret; 5040 5041 is_udp = (gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP); 5042 } 5043 5044 /* Only HIP08 needs to set the vlan_en bits in QPC */ 5045 if (vlan_id < VLAN_N_VID && 5046 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5047 hr_reg_enable(context, QPC_RQ_VLAN_EN); 5048 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN); 5049 hr_reg_enable(context, QPC_SQ_VLAN_EN); 5050 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN); 5051 } 5052 5053 hr_reg_write(context, QPC_VLAN_ID, vlan_id); 5054 hr_reg_clear(qpc_mask, QPC_VLAN_ID); 5055 5056 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) { 5057 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n", 5058 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]); 5059 return -EINVAL; 5060 } 5061 5062 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) { 5063 ibdev_err(ibdev, "ah attr is not RDMA roce type\n"); 5064 return -EINVAL; 5065 } 5066 5067 hr_reg_write(context, QPC_UDPSPN, 5068 is_udp ? rdma_get_udp_sport(grh->flow_label, ibqp->qp_num, 5069 attr->dest_qp_num) : 5070 0); 5071 5072 hr_reg_clear(qpc_mask, QPC_UDPSPN); 5073 5074 hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index); 5075 5076 hr_reg_clear(qpc_mask, QPC_GMV_IDX); 5077 5078 hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit); 5079 hr_reg_clear(qpc_mask, QPC_HOPLIMIT); 5080 5081 ret = fill_cong_field(ibqp, attr, context, qpc_mask); 5082 if (ret) 5083 return ret; 5084 5085 hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh)); 5086 hr_reg_clear(qpc_mask, QPC_TC); 5087 5088 hr_reg_write(context, QPC_FL, grh->flow_label); 5089 hr_reg_clear(qpc_mask, QPC_FL); 5090 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 5091 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 5092 5093 return hns_roce_set_sl(ibqp, attr, context, qpc_mask); 5094 } 5095 5096 static bool check_qp_state(enum ib_qp_state cur_state, 5097 enum ib_qp_state new_state) 5098 { 5099 static const bool sm[][IB_QPS_ERR + 1] = { 5100 [IB_QPS_RESET] = { [IB_QPS_RESET] = true, 5101 [IB_QPS_INIT] = true }, 5102 [IB_QPS_INIT] = { [IB_QPS_RESET] = true, 5103 [IB_QPS_INIT] = true, 5104 [IB_QPS_RTR] = true, 5105 [IB_QPS_ERR] = true }, 5106 [IB_QPS_RTR] = { [IB_QPS_RESET] = true, 5107 [IB_QPS_RTS] = true, 5108 [IB_QPS_ERR] = true }, 5109 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, 5110 [IB_QPS_RTS] = true, 5111 [IB_QPS_ERR] = true }, 5112 [IB_QPS_SQD] = {}, 5113 [IB_QPS_SQE] = {}, 5114 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, 5115 [IB_QPS_ERR] = true } 5116 }; 5117 5118 return sm[cur_state][new_state]; 5119 } 5120 5121 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, 5122 const struct ib_qp_attr *attr, 5123 int attr_mask, 5124 enum ib_qp_state cur_state, 5125 enum ib_qp_state new_state, 5126 struct hns_roce_v2_qp_context *context, 5127 struct hns_roce_v2_qp_context *qpc_mask, 5128 struct ib_udata *udata) 5129 { 5130 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5131 int ret = 0; 5132 5133 if (!check_qp_state(cur_state, new_state)) 5134 return -EINVAL; 5135 5136 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 5137 memset(qpc_mask, 0, hr_dev->caps.qpc_sz); 5138 modify_qp_reset_to_init(ibqp, context); 5139 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 5140 modify_qp_init_to_init(ibqp, context, qpc_mask); 5141 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 5142 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, 5143 qpc_mask, udata); 5144 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 5145 ret = modify_qp_rtr_to_rts(ibqp, attr_mask, context, qpc_mask); 5146 } 5147 5148 return ret; 5149 } 5150 5151 static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout) 5152 { 5153 #define QP_ACK_TIMEOUT_MAX_HIP08 20 5154 #define QP_ACK_TIMEOUT_MAX 31 5155 5156 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5157 if (*timeout > QP_ACK_TIMEOUT_MAX_HIP08) { 5158 ibdev_warn(&hr_dev->ib_dev, 5159 "local ACK timeout shall be 0 to 20.\n"); 5160 return false; 5161 } 5162 *timeout += HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08; 5163 } else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08) { 5164 if (*timeout > QP_ACK_TIMEOUT_MAX) { 5165 ibdev_warn(&hr_dev->ib_dev, 5166 "local ACK timeout shall be 0 to 31.\n"); 5167 return false; 5168 } 5169 } 5170 5171 return true; 5172 } 5173 5174 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, 5175 const struct ib_qp_attr *attr, 5176 int attr_mask, 5177 struct hns_roce_v2_qp_context *context, 5178 struct hns_roce_v2_qp_context *qpc_mask) 5179 { 5180 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5181 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5182 int ret = 0; 5183 u8 timeout; 5184 5185 if (attr_mask & IB_QP_AV) { 5186 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context, 5187 qpc_mask); 5188 if (ret) 5189 return ret; 5190 } 5191 5192 if (attr_mask & IB_QP_TIMEOUT) { 5193 timeout = attr->timeout; 5194 if (check_qp_timeout_cfg_range(hr_dev, &timeout)) { 5195 hr_reg_write(context, QPC_AT, timeout); 5196 hr_reg_clear(qpc_mask, QPC_AT); 5197 } 5198 } 5199 5200 if (attr_mask & IB_QP_RETRY_CNT) { 5201 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt); 5202 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT); 5203 5204 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt); 5205 hr_reg_clear(qpc_mask, QPC_RETRY_CNT); 5206 } 5207 5208 if (attr_mask & IB_QP_RNR_RETRY) { 5209 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry); 5210 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT); 5211 5212 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry); 5213 hr_reg_clear(qpc_mask, QPC_RNR_CNT); 5214 } 5215 5216 if (attr_mask & IB_QP_SQ_PSN) { 5217 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn); 5218 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN); 5219 5220 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn); 5221 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN); 5222 5223 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn); 5224 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L); 5225 5226 hr_reg_write(context, QPC_RETRY_MSG_PSN_H, 5227 attr->sq_psn >> RETRY_MSG_PSN_SHIFT); 5228 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H); 5229 5230 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn); 5231 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN); 5232 5233 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn); 5234 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN); 5235 } 5236 5237 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && 5238 attr->max_dest_rd_atomic) { 5239 hr_reg_write(context, QPC_RR_MAX, 5240 fls(attr->max_dest_rd_atomic - 1)); 5241 hr_reg_clear(qpc_mask, QPC_RR_MAX); 5242 } 5243 5244 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { 5245 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1)); 5246 hr_reg_clear(qpc_mask, QPC_SR_MAX); 5247 } 5248 5249 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 5250 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); 5251 5252 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 5253 hr_reg_write(context, QPC_MIN_RNR_TIME, 5254 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ? 5255 HNS_ROCE_RNR_TIMER_10NS : attr->min_rnr_timer); 5256 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME); 5257 } 5258 5259 if (attr_mask & IB_QP_RQ_PSN) { 5260 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn); 5261 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN); 5262 5263 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1); 5264 hr_reg_clear(qpc_mask, QPC_RAQ_PSN); 5265 } 5266 5267 if (attr_mask & IB_QP_QKEY) { 5268 context->qkey_xrcd = cpu_to_le32(attr->qkey); 5269 qpc_mask->qkey_xrcd = 0; 5270 hr_qp->qkey = attr->qkey; 5271 } 5272 5273 return ret; 5274 } 5275 5276 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp, 5277 const struct ib_qp_attr *attr, 5278 int attr_mask) 5279 { 5280 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5281 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5282 5283 if (attr_mask & IB_QP_ACCESS_FLAGS) 5284 hr_qp->atomic_rd_en = attr->qp_access_flags; 5285 5286 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 5287 hr_qp->resp_depth = attr->max_dest_rd_atomic; 5288 if (attr_mask & IB_QP_PORT) { 5289 hr_qp->port = attr->port_num - 1; 5290 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 5291 } 5292 } 5293 5294 static void clear_qp(struct hns_roce_qp *hr_qp) 5295 { 5296 struct ib_qp *ibqp = &hr_qp->ibqp; 5297 5298 if (ibqp->send_cq) 5299 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), 5300 hr_qp->qpn, NULL); 5301 5302 if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq) 5303 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), 5304 hr_qp->qpn, ibqp->srq ? 5305 to_hr_srq(ibqp->srq) : NULL); 5306 5307 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 5308 *hr_qp->rdb.db_record = 0; 5309 5310 hr_qp->rq.head = 0; 5311 hr_qp->rq.tail = 0; 5312 hr_qp->sq.head = 0; 5313 hr_qp->sq.tail = 0; 5314 hr_qp->next_sge = 0; 5315 } 5316 5317 static void v2_set_flushed_fields(struct ib_qp *ibqp, 5318 struct hns_roce_v2_qp_context *context, 5319 struct hns_roce_v2_qp_context *qpc_mask) 5320 { 5321 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5322 unsigned long sq_flag = 0; 5323 unsigned long rq_flag = 0; 5324 5325 if (ibqp->qp_type == IB_QPT_XRC_TGT) 5326 return; 5327 5328 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); 5329 trace_hns_sq_flush_cqe(hr_qp->qpn, hr_qp->sq.head, TRACE_SQ); 5330 hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head); 5331 hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX); 5332 hr_qp->state = IB_QPS_ERR; 5333 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); 5334 5335 if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */ 5336 return; 5337 5338 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag); 5339 trace_hns_rq_flush_cqe(hr_qp->qpn, hr_qp->rq.head, TRACE_RQ); 5340 hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head); 5341 hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX); 5342 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag); 5343 } 5344 5345 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 5346 const struct ib_qp_attr *attr, 5347 int attr_mask, enum ib_qp_state cur_state, 5348 enum ib_qp_state new_state, struct ib_udata *udata) 5349 { 5350 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5351 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5352 struct hns_roce_v2_qp_context ctx[2]; 5353 struct hns_roce_v2_qp_context *context = ctx; 5354 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1; 5355 struct ib_device *ibdev = &hr_dev->ib_dev; 5356 int ret; 5357 5358 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 5359 return -EOPNOTSUPP; 5360 5361 /* 5362 * In v2 engine, software pass context and context mask to hardware 5363 * when modifying qp. If software need modify some fields in context, 5364 * we should set all bits of the relevant fields in context mask to 5365 * 0 at the same time, else set them to 0x1. 5366 */ 5367 memset(context, 0, hr_dev->caps.qpc_sz); 5368 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz); 5369 5370 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state, 5371 new_state, context, qpc_mask, udata); 5372 if (ret) 5373 goto out; 5374 5375 /* When QP state is err, SQ and RQ WQE should be flushed */ 5376 if (new_state == IB_QPS_ERR) 5377 v2_set_flushed_fields(ibqp, context, qpc_mask); 5378 5379 /* Configure the optional fields */ 5380 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context, 5381 qpc_mask); 5382 if (ret) 5383 goto out; 5384 5385 hr_reg_write_bool(context, QPC_INV_CREDIT, 5386 to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC || 5387 ibqp->srq); 5388 hr_reg_clear(qpc_mask, QPC_INV_CREDIT); 5389 5390 /* Every status migrate must change state */ 5391 hr_reg_write(context, QPC_QP_ST, new_state); 5392 hr_reg_clear(qpc_mask, QPC_QP_ST); 5393 5394 /* SW pass context to HW */ 5395 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp); 5396 if (ret) { 5397 ibdev_err_ratelimited(ibdev, "failed to modify QP, ret = %d.\n", ret); 5398 goto out; 5399 } 5400 5401 hr_qp->state = new_state; 5402 5403 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask); 5404 5405 if (new_state == IB_QPS_RESET && !ibqp->uobject) 5406 clear_qp(hr_qp); 5407 5408 out: 5409 return ret; 5410 } 5411 5412 static int to_ib_qp_st(enum hns_roce_v2_qp_state state) 5413 { 5414 static const enum ib_qp_state map[] = { 5415 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET, 5416 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT, 5417 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR, 5418 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS, 5419 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD, 5420 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE, 5421 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR, 5422 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD 5423 }; 5424 5425 return (state < ARRAY_SIZE(map)) ? map[state] : -1; 5426 } 5427 5428 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, u32 qpn, 5429 void *buffer) 5430 { 5431 struct hns_roce_cmd_mailbox *mailbox; 5432 int ret; 5433 5434 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5435 if (IS_ERR(mailbox)) 5436 return PTR_ERR(mailbox); 5437 5438 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_QPC, 5439 qpn); 5440 if (ret) 5441 goto out; 5442 5443 memcpy(buffer, mailbox->buf, hr_dev->caps.qpc_sz); 5444 5445 out: 5446 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5447 return ret; 5448 } 5449 5450 static int hns_roce_v2_query_srqc(struct hns_roce_dev *hr_dev, u32 srqn, 5451 void *buffer) 5452 { 5453 struct hns_roce_srq_context *context; 5454 struct hns_roce_cmd_mailbox *mailbox; 5455 int ret; 5456 5457 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5458 if (IS_ERR(mailbox)) 5459 return PTR_ERR(mailbox); 5460 5461 context = mailbox->buf; 5462 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_SRQC, 5463 srqn); 5464 if (ret) 5465 goto out; 5466 5467 memcpy(buffer, context, sizeof(*context)); 5468 5469 out: 5470 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5471 return ret; 5472 } 5473 5474 static int hns_roce_v2_query_sccc(struct hns_roce_dev *hr_dev, u32 qpn, 5475 void *buffer) 5476 { 5477 struct hns_roce_v2_scc_context *context; 5478 struct hns_roce_cmd_mailbox *mailbox; 5479 int ret; 5480 5481 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5482 if (IS_ERR(mailbox)) 5483 return PTR_ERR(mailbox); 5484 5485 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_SCCC, 5486 qpn); 5487 if (ret) 5488 goto out; 5489 5490 context = mailbox->buf; 5491 memcpy(buffer, context, sizeof(*context)); 5492 5493 out: 5494 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5495 return ret; 5496 } 5497 5498 static u8 get_qp_timeout_attr(struct hns_roce_dev *hr_dev, 5499 struct hns_roce_v2_qp_context *context) 5500 { 5501 u8 timeout; 5502 5503 timeout = (u8)hr_reg_read(context, QPC_AT); 5504 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 5505 timeout -= HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08; 5506 5507 return timeout; 5508 } 5509 5510 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5511 int qp_attr_mask, 5512 struct ib_qp_init_attr *qp_init_attr) 5513 { 5514 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5515 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5516 struct hns_roce_v2_qp_context context = {}; 5517 struct ib_device *ibdev = &hr_dev->ib_dev; 5518 int tmp_qp_state; 5519 int state; 5520 int ret; 5521 5522 memset(qp_attr, 0, sizeof(*qp_attr)); 5523 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5524 5525 mutex_lock(&hr_qp->mutex); 5526 5527 if (hr_qp->state == IB_QPS_RESET) { 5528 qp_attr->qp_state = IB_QPS_RESET; 5529 ret = 0; 5530 goto done; 5531 } 5532 5533 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp->qpn, &context); 5534 if (ret) { 5535 ibdev_err_ratelimited(ibdev, 5536 "failed to query QPC, ret = %d.\n", 5537 ret); 5538 ret = -EINVAL; 5539 goto out; 5540 } 5541 5542 state = hr_reg_read(&context, QPC_QP_ST); 5543 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); 5544 if (tmp_qp_state == -1) { 5545 ibdev_err_ratelimited(ibdev, "Illegal ib_qp_state\n"); 5546 ret = -EINVAL; 5547 goto out; 5548 } 5549 hr_qp->state = (u8)tmp_qp_state; 5550 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; 5551 qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU); 5552 qp_attr->path_mig_state = IB_MIG_ARMED; 5553 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 5554 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 5555 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd); 5556 5557 qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN); 5558 qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN); 5559 qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN); 5560 qp_attr->qp_access_flags = 5561 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) | 5562 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) | 5563 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S); 5564 5565 if (hr_qp->ibqp.qp_type == IB_QPT_RC || 5566 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5567 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) { 5568 struct ib_global_route *grh = 5569 rdma_ah_retrieve_grh(&qp_attr->ah_attr); 5570 5571 rdma_ah_set_sl(&qp_attr->ah_attr, 5572 hr_reg_read(&context, QPC_SL)); 5573 rdma_ah_set_port_num(&qp_attr->ah_attr, hr_qp->port + 1); 5574 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH); 5575 grh->flow_label = hr_reg_read(&context, QPC_FL); 5576 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX); 5577 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT); 5578 grh->traffic_class = hr_reg_read(&context, QPC_TC); 5579 5580 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw)); 5581 } 5582 5583 qp_attr->port_num = hr_qp->port + 1; 5584 qp_attr->sq_draining = 0; 5585 qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX); 5586 qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX); 5587 5588 qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME); 5589 qp_attr->timeout = get_qp_timeout_attr(hr_dev, &context); 5590 qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT); 5591 qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT); 5592 5593 done: 5594 qp_attr->cur_qp_state = qp_attr->qp_state; 5595 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; 5596 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 5597 qp_attr->cap.max_inline_data = hr_qp->max_inline_data; 5598 5599 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; 5600 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; 5601 5602 qp_init_attr->qp_context = ibqp->qp_context; 5603 qp_init_attr->qp_type = ibqp->qp_type; 5604 qp_init_attr->recv_cq = ibqp->recv_cq; 5605 qp_init_attr->send_cq = ibqp->send_cq; 5606 qp_init_attr->srq = ibqp->srq; 5607 qp_init_attr->cap = qp_attr->cap; 5608 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits; 5609 5610 out: 5611 mutex_unlock(&hr_qp->mutex); 5612 return ret; 5613 } 5614 5615 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp) 5616 { 5617 return ((hr_qp->ibqp.qp_type == IB_QPT_RC || 5618 hr_qp->ibqp.qp_type == IB_QPT_UD || 5619 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5620 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) && 5621 hr_qp->state != IB_QPS_RESET); 5622 } 5623 5624 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, 5625 struct hns_roce_qp *hr_qp, 5626 struct ib_udata *udata) 5627 { 5628 struct ib_device *ibdev = &hr_dev->ib_dev; 5629 struct hns_roce_cq *send_cq, *recv_cq; 5630 unsigned long flags; 5631 int ret = 0; 5632 5633 if (modify_qp_is_ok(hr_qp)) { 5634 /* Modify qp to reset before destroying qp */ 5635 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, 5636 hr_qp->state, IB_QPS_RESET, udata); 5637 if (ret) 5638 ibdev_err_ratelimited(ibdev, 5639 "failed to modify QP to RST, ret = %d.\n", 5640 ret); 5641 } 5642 5643 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL; 5644 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL; 5645 5646 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 5647 hns_roce_lock_cqs(send_cq, recv_cq); 5648 5649 if (!udata) { 5650 if (recv_cq) 5651 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, 5652 (hr_qp->ibqp.srq ? 5653 to_hr_srq(hr_qp->ibqp.srq) : 5654 NULL)); 5655 5656 if (send_cq && send_cq != recv_cq) 5657 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); 5658 } 5659 5660 hns_roce_qp_remove(hr_dev, hr_qp); 5661 5662 hns_roce_unlock_cqs(send_cq, recv_cq); 5663 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 5664 5665 return ret; 5666 } 5667 5668 static void put_dip_ctx_idx(struct hns_roce_dev *hr_dev, 5669 struct hns_roce_qp *hr_qp) 5670 { 5671 struct hns_roce_dip *hr_dip = hr_qp->dip; 5672 5673 if (!hr_dip) 5674 return; 5675 5676 xa_lock(&hr_dev->qp_table.dip_xa); 5677 5678 hr_dip->qp_cnt--; 5679 if (!hr_dip->qp_cnt) 5680 memset(hr_dip->dgid, 0, GID_LEN_V2); 5681 5682 xa_unlock(&hr_dev->qp_table.dip_xa); 5683 } 5684 5685 int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) 5686 { 5687 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5688 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5689 unsigned long flags; 5690 int ret; 5691 5692 /* Make sure flush_cqe() is completed */ 5693 spin_lock_irqsave(&hr_qp->flush_lock, flags); 5694 set_bit(HNS_ROCE_STOP_FLUSH_FLAG, &hr_qp->flush_flag); 5695 spin_unlock_irqrestore(&hr_qp->flush_lock, flags); 5696 flush_work(&hr_qp->flush_work.work); 5697 5698 if (hr_qp->cong_type == CONG_TYPE_DIP) 5699 put_dip_ctx_idx(hr_dev, hr_qp); 5700 5701 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata); 5702 if (ret) 5703 ibdev_err_ratelimited(&hr_dev->ib_dev, 5704 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n", 5705 hr_qp->qpn, ret); 5706 5707 hns_roce_qp_destroy(hr_dev, hr_qp, udata); 5708 5709 return 0; 5710 } 5711 5712 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev, 5713 struct hns_roce_qp *hr_qp) 5714 { 5715 struct ib_device *ibdev = &hr_dev->ib_dev; 5716 struct hns_roce_sccc_clr_done *resp; 5717 struct hns_roce_sccc_clr *clr; 5718 struct hns_roce_cmq_desc desc; 5719 int ret, i; 5720 5721 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 5722 return 0; 5723 5724 mutex_lock(&hr_dev->qp_table.scc_mutex); 5725 5726 /* set scc ctx clear done flag */ 5727 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false); 5728 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5729 if (ret) { 5730 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret); 5731 goto out; 5732 } 5733 5734 /* clear scc context */ 5735 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false); 5736 clr = (struct hns_roce_sccc_clr *)desc.data; 5737 clr->qpn = cpu_to_le32(hr_qp->qpn); 5738 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5739 if (ret) { 5740 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret); 5741 goto out; 5742 } 5743 5744 /* query scc context clear is done or not */ 5745 resp = (struct hns_roce_sccc_clr_done *)desc.data; 5746 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) { 5747 hns_roce_cmq_setup_basic_desc(&desc, 5748 HNS_ROCE_OPC_QUERY_SCCC, true); 5749 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5750 if (ret) { 5751 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n", 5752 ret); 5753 goto out; 5754 } 5755 5756 if (resp->clr_done) 5757 goto out; 5758 5759 msleep(20); 5760 } 5761 5762 ibdev_err(ibdev, "query SCC clr done flag overtime.\n"); 5763 ret = -ETIMEDOUT; 5764 5765 out: 5766 mutex_unlock(&hr_dev->qp_table.scc_mutex); 5767 return ret; 5768 } 5769 5770 #define DMA_IDX_SHIFT 3 5771 #define DMA_WQE_SHIFT 3 5772 5773 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq, 5774 struct hns_roce_srq_context *ctx) 5775 { 5776 struct hns_roce_idx_que *idx_que = &srq->idx_que; 5777 struct ib_device *ibdev = srq->ibsrq.device; 5778 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5779 u64 mtts_idx[MTT_MIN_COUNT] = {}; 5780 dma_addr_t dma_handle_idx; 5781 int ret; 5782 5783 /* Get physical address of idx que buf */ 5784 ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx, 5785 ARRAY_SIZE(mtts_idx)); 5786 if (ret) { 5787 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n", 5788 ret); 5789 return ret; 5790 } 5791 5792 dma_handle_idx = hns_roce_get_mtr_ba(&idx_que->mtr); 5793 5794 hr_reg_write(ctx, SRQC_IDX_HOP_NUM, 5795 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt)); 5796 5797 hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT); 5798 hr_reg_write(ctx, SRQC_IDX_BT_BA_H, 5799 upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT)); 5800 5801 hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ, 5802 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift)); 5803 hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ, 5804 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift)); 5805 5806 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L, 5807 to_hr_hw_page_addr(mtts_idx[0])); 5808 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H, 5809 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0]))); 5810 5811 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L, 5812 to_hr_hw_page_addr(mtts_idx[1])); 5813 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H, 5814 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1]))); 5815 5816 return 0; 5817 } 5818 5819 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf) 5820 { 5821 struct ib_device *ibdev = srq->ibsrq.device; 5822 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5823 struct hns_roce_srq_context *ctx = mb_buf; 5824 u64 mtts_wqe[MTT_MIN_COUNT] = {}; 5825 dma_addr_t dma_handle_wqe; 5826 int ret; 5827 5828 memset(ctx, 0, sizeof(*ctx)); 5829 5830 /* Get the physical address of srq buf */ 5831 ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe, 5832 ARRAY_SIZE(mtts_wqe)); 5833 if (ret) { 5834 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n", 5835 ret); 5836 return ret; 5837 } 5838 5839 dma_handle_wqe = hns_roce_get_mtr_ba(&srq->buf_mtr); 5840 5841 hr_reg_write(ctx, SRQC_SRQ_ST, 1); 5842 hr_reg_write_bool(ctx, SRQC_SRQ_TYPE, 5843 srq->ibsrq.srq_type == IB_SRQT_XRC); 5844 hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn); 5845 hr_reg_write(ctx, SRQC_SRQN, srq->srqn); 5846 hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn); 5847 hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn); 5848 hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt)); 5849 hr_reg_write(ctx, SRQC_RQWS, 5850 srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1)); 5851 5852 hr_reg_write(ctx, SRQC_WQE_HOP_NUM, 5853 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num, 5854 srq->wqe_cnt)); 5855 5856 hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT); 5857 hr_reg_write(ctx, SRQC_WQE_BT_BA_H, 5858 upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT)); 5859 5860 hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ, 5861 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift)); 5862 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ, 5863 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift)); 5864 5865 if (srq->cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB) { 5866 hr_reg_enable(ctx, SRQC_DB_RECORD_EN); 5867 hr_reg_write(ctx, SRQC_DB_RECORD_ADDR_L, 5868 lower_32_bits(srq->rdb.dma) >> 1); 5869 hr_reg_write(ctx, SRQC_DB_RECORD_ADDR_H, 5870 upper_32_bits(srq->rdb.dma)); 5871 } 5872 5873 return hns_roce_v2_write_srqc_index_queue(srq, ctx); 5874 } 5875 5876 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq, 5877 struct ib_srq_attr *srq_attr, 5878 enum ib_srq_attr_mask srq_attr_mask, 5879 struct ib_udata *udata) 5880 { 5881 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5882 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5883 struct hns_roce_srq_context *srq_context; 5884 struct hns_roce_srq_context *srqc_mask; 5885 struct hns_roce_cmd_mailbox *mailbox; 5886 int ret = 0; 5887 5888 /* Resizing SRQs is not supported yet */ 5889 if (srq_attr_mask & IB_SRQ_MAX_WR) { 5890 ret = -EOPNOTSUPP; 5891 goto out; 5892 } 5893 5894 if (srq_attr_mask & IB_SRQ_LIMIT) { 5895 if (srq_attr->srq_limit > srq->wqe_cnt) { 5896 ret = -EINVAL; 5897 goto out; 5898 } 5899 5900 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5901 if (IS_ERR(mailbox)) { 5902 ret = PTR_ERR(mailbox); 5903 goto out; 5904 } 5905 5906 srq_context = mailbox->buf; 5907 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1; 5908 5909 memset(srqc_mask, 0xff, sizeof(*srqc_mask)); 5910 5911 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit); 5912 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL); 5913 5914 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 5915 HNS_ROCE_CMD_MODIFY_SRQC, srq->srqn); 5916 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5917 if (ret) 5918 ibdev_err(&hr_dev->ib_dev, 5919 "failed to handle cmd of modifying SRQ, ret = %d.\n", 5920 ret); 5921 } 5922 5923 out: 5924 if (ret) 5925 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_SRQ_MODIFY_ERR_CNT]); 5926 5927 return ret; 5928 } 5929 5930 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr) 5931 { 5932 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5933 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5934 struct hns_roce_srq_context *srq_context; 5935 struct hns_roce_cmd_mailbox *mailbox; 5936 int ret; 5937 5938 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5939 if (IS_ERR(mailbox)) 5940 return PTR_ERR(mailbox); 5941 5942 srq_context = mailbox->buf; 5943 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 5944 HNS_ROCE_CMD_QUERY_SRQC, srq->srqn); 5945 if (ret) { 5946 ibdev_err(&hr_dev->ib_dev, 5947 "failed to process cmd of querying SRQ, ret = %d.\n", 5948 ret); 5949 goto out; 5950 } 5951 5952 attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL); 5953 attr->max_wr = srq->wqe_cnt; 5954 attr->max_sge = srq->max_gs - srq->rsv_sge; 5955 5956 out: 5957 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5958 return ret; 5959 } 5960 5961 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 5962 { 5963 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); 5964 struct hns_roce_v2_cq_context *cq_context; 5965 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 5966 struct hns_roce_v2_cq_context *cqc_mask; 5967 struct hns_roce_cmd_mailbox *mailbox; 5968 int ret; 5969 5970 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5971 ret = PTR_ERR_OR_ZERO(mailbox); 5972 if (ret) 5973 goto err_out; 5974 5975 cq_context = mailbox->buf; 5976 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; 5977 5978 memset(cqc_mask, 0xff, sizeof(*cqc_mask)); 5979 5980 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count); 5981 hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT); 5982 5983 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5984 if (cq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 5985 dev_info(hr_dev->dev, 5986 "cq_period(%u) reached the upper limit, adjusted to 65.\n", 5987 cq_period); 5988 cq_period = HNS_ROCE_MAX_CQ_PERIOD_HIP08; 5989 } 5990 cq_period *= HNS_ROCE_CLOCK_ADJUST; 5991 } 5992 hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period); 5993 hr_reg_clear(cqc_mask, CQC_CQ_PERIOD); 5994 5995 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 5996 HNS_ROCE_CMD_MODIFY_CQC, hr_cq->cqn); 5997 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5998 if (ret) 5999 ibdev_err_ratelimited(&hr_dev->ib_dev, 6000 "failed to process cmd when modifying CQ, ret = %d.\n", 6001 ret); 6002 6003 err_out: 6004 if (ret) 6005 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CQ_MODIFY_ERR_CNT]); 6006 6007 return ret; 6008 } 6009 6010 static int hns_roce_v2_query_cqc(struct hns_roce_dev *hr_dev, u32 cqn, 6011 void *buffer) 6012 { 6013 struct hns_roce_v2_cq_context *context; 6014 struct hns_roce_cmd_mailbox *mailbox; 6015 int ret; 6016 6017 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6018 if (IS_ERR(mailbox)) 6019 return PTR_ERR(mailbox); 6020 6021 context = mailbox->buf; 6022 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 6023 HNS_ROCE_CMD_QUERY_CQC, cqn); 6024 if (ret) { 6025 ibdev_err_ratelimited(&hr_dev->ib_dev, 6026 "failed to process cmd when querying CQ, ret = %d.\n", 6027 ret); 6028 goto err_mailbox; 6029 } 6030 6031 memcpy(buffer, context, sizeof(*context)); 6032 6033 err_mailbox: 6034 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6035 6036 return ret; 6037 } 6038 6039 static int hns_roce_v2_query_mpt(struct hns_roce_dev *hr_dev, u32 key, 6040 void *buffer) 6041 { 6042 struct hns_roce_v2_mpt_entry *context; 6043 struct hns_roce_cmd_mailbox *mailbox; 6044 int ret; 6045 6046 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6047 if (IS_ERR(mailbox)) 6048 return PTR_ERR(mailbox); 6049 6050 context = mailbox->buf; 6051 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_MPT, 6052 key_to_hw_index(key)); 6053 if (ret) { 6054 ibdev_err(&hr_dev->ib_dev, 6055 "failed to process cmd when querying MPT, ret = %d.\n", 6056 ret); 6057 goto err_mailbox; 6058 } 6059 6060 memcpy(buffer, context, sizeof(*context)); 6061 6062 err_mailbox: 6063 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6064 6065 return ret; 6066 } 6067 6068 static void dump_aeqe_log(struct hns_roce_work *irq_work) 6069 { 6070 struct hns_roce_dev *hr_dev = irq_work->hr_dev; 6071 struct ib_device *ibdev = &hr_dev->ib_dev; 6072 6073 switch (irq_work->event_type) { 6074 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 6075 ibdev_info(ibdev, "path migrated succeeded.\n"); 6076 break; 6077 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 6078 ibdev_warn(ibdev, "path migration failed.\n"); 6079 break; 6080 case HNS_ROCE_EVENT_TYPE_COMM_EST: 6081 break; 6082 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 6083 ibdev_dbg(ibdev, "send queue drained.\n"); 6084 break; 6085 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 6086 ibdev_err(ibdev, "local work queue 0x%x catast error, sub_event type is: %d\n", 6087 irq_work->queue_num, irq_work->sub_type); 6088 break; 6089 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 6090 ibdev_err(ibdev, "invalid request local work queue 0x%x error.\n", 6091 irq_work->queue_num); 6092 break; 6093 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 6094 ibdev_err(ibdev, "local access violation work queue 0x%x error, sub_event type is: %d\n", 6095 irq_work->queue_num, irq_work->sub_type); 6096 break; 6097 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 6098 ibdev_dbg(ibdev, "SRQ limit reach.\n"); 6099 break; 6100 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 6101 ibdev_dbg(ibdev, "SRQ last wqe reach.\n"); 6102 break; 6103 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 6104 ibdev_err(ibdev, "SRQ catas error.\n"); 6105 break; 6106 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 6107 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num); 6108 break; 6109 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 6110 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num); 6111 break; 6112 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 6113 ibdev_warn(ibdev, "DB overflow.\n"); 6114 break; 6115 case HNS_ROCE_EVENT_TYPE_MB: 6116 break; 6117 case HNS_ROCE_EVENT_TYPE_FLR: 6118 ibdev_warn(ibdev, "function level reset.\n"); 6119 break; 6120 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 6121 ibdev_err(ibdev, "xrc domain violation error.\n"); 6122 break; 6123 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 6124 ibdev_err(ibdev, "invalid xrceth error.\n"); 6125 break; 6126 default: 6127 ibdev_info(ibdev, "Undefined event %d.\n", 6128 irq_work->event_type); 6129 break; 6130 } 6131 } 6132 6133 static void hns_roce_irq_work_handle(struct work_struct *work) 6134 { 6135 struct hns_roce_work *irq_work = 6136 container_of(work, struct hns_roce_work, work); 6137 struct hns_roce_dev *hr_dev = irq_work->hr_dev; 6138 int event_type = irq_work->event_type; 6139 u32 queue_num = irq_work->queue_num; 6140 6141 switch (event_type) { 6142 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 6143 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 6144 case HNS_ROCE_EVENT_TYPE_COMM_EST: 6145 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 6146 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 6147 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 6148 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 6149 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 6150 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 6151 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 6152 hns_roce_qp_event(hr_dev, queue_num, event_type); 6153 break; 6154 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 6155 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 6156 hns_roce_srq_event(hr_dev, queue_num, event_type); 6157 break; 6158 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 6159 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 6160 hns_roce_cq_event(hr_dev, queue_num, event_type); 6161 break; 6162 default: 6163 break; 6164 } 6165 6166 dump_aeqe_log(irq_work); 6167 6168 kfree(irq_work); 6169 } 6170 6171 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev, 6172 struct hns_roce_eq *eq, u32 queue_num) 6173 { 6174 struct hns_roce_work *irq_work; 6175 6176 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC); 6177 if (!irq_work) 6178 return; 6179 6180 INIT_WORK(&irq_work->work, hns_roce_irq_work_handle); 6181 irq_work->hr_dev = hr_dev; 6182 irq_work->event_type = eq->event_type; 6183 irq_work->sub_type = eq->sub_type; 6184 irq_work->queue_num = queue_num; 6185 queue_work(hr_dev->irq_workq, &irq_work->work); 6186 } 6187 6188 static void update_eq_db(struct hns_roce_eq *eq) 6189 { 6190 struct hns_roce_dev *hr_dev = eq->hr_dev; 6191 struct hns_roce_v2_db eq_db = {}; 6192 6193 if (eq->type_flag == HNS_ROCE_AEQ) { 6194 hr_reg_write(&eq_db, EQ_DB_CMD, 6195 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 6196 HNS_ROCE_EQ_DB_CMD_AEQ : 6197 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); 6198 } else { 6199 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn); 6200 6201 hr_reg_write(&eq_db, EQ_DB_CMD, 6202 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 6203 HNS_ROCE_EQ_DB_CMD_CEQ : 6204 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); 6205 } 6206 6207 hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index); 6208 6209 hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg); 6210 } 6211 6212 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 6213 { 6214 struct hns_roce_aeqe *aeqe; 6215 6216 aeqe = hns_roce_buf_offset(eq->mtr.kmem, 6217 (eq->cons_index & (eq->entries - 1)) * 6218 eq->eqe_size); 6219 6220 return (hr_reg_read(aeqe, AEQE_OWNER) ^ 6221 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; 6222 } 6223 6224 static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 6225 struct hns_roce_eq *eq) 6226 { 6227 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq); 6228 irqreturn_t aeqe_found = IRQ_NONE; 6229 int num_aeqes = 0; 6230 int event_type; 6231 u32 queue_num; 6232 int sub_type; 6233 6234 while (aeqe && num_aeqes < HNS_AEQ_POLLING_BUDGET) { 6235 /* Make sure we read AEQ entry after we have checked the 6236 * ownership bit 6237 */ 6238 dma_rmb(); 6239 6240 event_type = hr_reg_read(aeqe, AEQE_EVENT_TYPE); 6241 sub_type = hr_reg_read(aeqe, AEQE_SUB_TYPE); 6242 queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM); 6243 6244 switch (event_type) { 6245 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 6246 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 6247 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 6248 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 6249 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 6250 hns_roce_flush_cqe(hr_dev, queue_num); 6251 break; 6252 case HNS_ROCE_EVENT_TYPE_MB: 6253 hns_roce_cmd_event(hr_dev, 6254 le16_to_cpu(aeqe->event.cmd.token), 6255 aeqe->event.cmd.status, 6256 le64_to_cpu(aeqe->event.cmd.out_param)); 6257 break; 6258 default: 6259 break; 6260 } 6261 6262 eq->event_type = event_type; 6263 eq->sub_type = sub_type; 6264 ++eq->cons_index; 6265 aeqe_found = IRQ_HANDLED; 6266 trace_hns_ae_info(event_type, aeqe, eq->eqe_size); 6267 6268 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_AEQE_CNT]); 6269 6270 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num); 6271 6272 aeqe = next_aeqe_sw_v2(eq); 6273 ++num_aeqes; 6274 } 6275 6276 update_eq_db(eq); 6277 6278 return IRQ_RETVAL(aeqe_found); 6279 } 6280 6281 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 6282 { 6283 struct hns_roce_ceqe *ceqe; 6284 6285 ceqe = hns_roce_buf_offset(eq->mtr.kmem, 6286 (eq->cons_index & (eq->entries - 1)) * 6287 eq->eqe_size); 6288 6289 return (hr_reg_read(ceqe, CEQE_OWNER) ^ 6290 !!(eq->cons_index & eq->entries)) ? ceqe : NULL; 6291 } 6292 6293 static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_eq *eq) 6294 { 6295 queue_work(system_bh_wq, &eq->work); 6296 6297 return IRQ_HANDLED; 6298 } 6299 6300 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 6301 { 6302 struct hns_roce_eq *eq = eq_ptr; 6303 struct hns_roce_dev *hr_dev = eq->hr_dev; 6304 irqreturn_t int_work; 6305 6306 if (eq->type_flag == HNS_ROCE_CEQ) 6307 /* Completion event interrupt */ 6308 int_work = hns_roce_v2_ceq_int(eq); 6309 else 6310 /* Asynchronous event interrupt */ 6311 int_work = hns_roce_v2_aeq_int(hr_dev, eq); 6312 6313 return IRQ_RETVAL(int_work); 6314 } 6315 6316 static irqreturn_t abnormal_interrupt_basic(struct hns_roce_dev *hr_dev, 6317 u32 int_st) 6318 { 6319 struct pci_dev *pdev = hr_dev->pci_dev; 6320 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 6321 const struct hnae3_ae_ops *ops = ae_dev->ops; 6322 enum hnae3_reset_type reset_type; 6323 irqreturn_t int_work = IRQ_NONE; 6324 u32 int_en; 6325 6326 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); 6327 6328 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { 6329 dev_err(hr_dev->dev, "AEQ overflow!\n"); 6330 6331 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, 6332 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S); 6333 6334 reset_type = hr_dev->is_vf ? 6335 HNAE3_VF_FUNC_RESET : HNAE3_FUNC_RESET; 6336 6337 /* Set reset level for reset_event() */ 6338 if (ops->set_default_reset_request) 6339 ops->set_default_reset_request(ae_dev, reset_type); 6340 if (ops->reset_event) 6341 ops->reset_event(pdev, NULL); 6342 6343 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 6344 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 6345 6346 int_work = IRQ_HANDLED; 6347 } else { 6348 dev_err(hr_dev->dev, "there is no basic abn irq found.\n"); 6349 } 6350 6351 return IRQ_RETVAL(int_work); 6352 } 6353 6354 static int fmea_ram_ecc_query(struct hns_roce_dev *hr_dev, 6355 struct fmea_ram_ecc *ecc_info) 6356 { 6357 struct hns_roce_cmq_desc desc; 6358 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6359 int ret; 6360 6361 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_QUERY_RAM_ECC, true); 6362 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6363 if (ret) 6364 return ret; 6365 6366 ecc_info->is_ecc_err = hr_reg_read(req, QUERY_RAM_ECC_1BIT_ERR); 6367 ecc_info->res_type = hr_reg_read(req, QUERY_RAM_ECC_RES_TYPE); 6368 ecc_info->index = hr_reg_read(req, QUERY_RAM_ECC_TAG); 6369 6370 return 0; 6371 } 6372 6373 static int fmea_recover_gmv(struct hns_roce_dev *hr_dev, u32 idx) 6374 { 6375 struct hns_roce_cmq_desc desc; 6376 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6377 u32 addr_upper; 6378 u32 addr_low; 6379 int ret; 6380 6381 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, true); 6382 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6383 6384 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6385 if (ret) { 6386 dev_err(hr_dev->dev, 6387 "failed to execute cmd to read gmv, ret = %d.\n", ret); 6388 return ret; 6389 } 6390 6391 addr_low = hr_reg_read(req, CFG_GMV_BT_BA_L); 6392 addr_upper = hr_reg_read(req, CFG_GMV_BT_BA_H); 6393 6394 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 6395 hr_reg_write(req, CFG_GMV_BT_BA_L, addr_low); 6396 hr_reg_write(req, CFG_GMV_BT_BA_H, addr_upper); 6397 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6398 6399 return hns_roce_cmq_send(hr_dev, &desc, 1); 6400 } 6401 6402 static u64 fmea_get_ram_res_addr(u32 res_type, __le64 *data) 6403 { 6404 if (res_type == ECC_RESOURCE_QPC_TIMER || 6405 res_type == ECC_RESOURCE_CQC_TIMER || 6406 res_type == ECC_RESOURCE_SCCC) 6407 return le64_to_cpu(*data); 6408 6409 return le64_to_cpu(*data) << HNS_HW_PAGE_SHIFT; 6410 } 6411 6412 static int fmea_recover_others(struct hns_roce_dev *hr_dev, u32 res_type, 6413 u32 index) 6414 { 6415 u8 write_bt0_op = fmea_ram_res[res_type].write_bt0_op; 6416 u8 read_bt0_op = fmea_ram_res[res_type].read_bt0_op; 6417 struct hns_roce_cmd_mailbox *mailbox; 6418 u64 addr; 6419 int ret; 6420 6421 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6422 if (IS_ERR(mailbox)) 6423 return PTR_ERR(mailbox); 6424 6425 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, read_bt0_op, index); 6426 if (ret) { 6427 dev_err(hr_dev->dev, 6428 "failed to execute cmd to read fmea ram, ret = %d.\n", 6429 ret); 6430 goto out; 6431 } 6432 6433 addr = fmea_get_ram_res_addr(res_type, mailbox->buf); 6434 6435 ret = hns_roce_cmd_mbox(hr_dev, addr, 0, write_bt0_op, index); 6436 if (ret) 6437 dev_err(hr_dev->dev, 6438 "failed to execute cmd to write fmea ram, ret = %d.\n", 6439 ret); 6440 6441 out: 6442 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6443 return ret; 6444 } 6445 6446 static void fmea_ram_ecc_recover(struct hns_roce_dev *hr_dev, 6447 struct fmea_ram_ecc *ecc_info) 6448 { 6449 u32 res_type = ecc_info->res_type; 6450 u32 index = ecc_info->index; 6451 int ret; 6452 6453 BUILD_BUG_ON(ARRAY_SIZE(fmea_ram_res) != ECC_RESOURCE_COUNT); 6454 6455 if (res_type >= ECC_RESOURCE_COUNT) { 6456 dev_err(hr_dev->dev, "unsupported fmea ram ecc type %u.\n", 6457 res_type); 6458 return; 6459 } 6460 6461 if (res_type == ECC_RESOURCE_GMV) 6462 ret = fmea_recover_gmv(hr_dev, index); 6463 else 6464 ret = fmea_recover_others(hr_dev, res_type, index); 6465 if (ret) 6466 dev_err(hr_dev->dev, 6467 "failed to recover %s, index = %u, ret = %d.\n", 6468 fmea_ram_res[res_type].name, index, ret); 6469 } 6470 6471 static void fmea_ram_ecc_work(struct work_struct *ecc_work) 6472 { 6473 struct hns_roce_dev *hr_dev = 6474 container_of(ecc_work, struct hns_roce_dev, ecc_work); 6475 struct fmea_ram_ecc ecc_info = {}; 6476 6477 if (fmea_ram_ecc_query(hr_dev, &ecc_info)) { 6478 dev_err(hr_dev->dev, "failed to query fmea ram ecc.\n"); 6479 return; 6480 } 6481 6482 if (!ecc_info.is_ecc_err) { 6483 dev_err(hr_dev->dev, "there is no fmea ram ecc err found.\n"); 6484 return; 6485 } 6486 6487 fmea_ram_ecc_recover(hr_dev, &ecc_info); 6488 } 6489 6490 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 6491 { 6492 struct hns_roce_dev *hr_dev = dev_id; 6493 irqreturn_t int_work = IRQ_NONE; 6494 u32 int_st; 6495 6496 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); 6497 6498 if (int_st) { 6499 int_work = abnormal_interrupt_basic(hr_dev, int_st); 6500 } else if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 6501 queue_work(hr_dev->irq_workq, &hr_dev->ecc_work); 6502 int_work = IRQ_HANDLED; 6503 } else { 6504 dev_err(hr_dev->dev, "there is no abnormal irq found.\n"); 6505 } 6506 6507 return IRQ_RETVAL(int_work); 6508 } 6509 6510 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 6511 int eq_num, u32 enable_flag) 6512 { 6513 int i; 6514 6515 for (i = 0; i < eq_num; i++) 6516 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 6517 i * EQ_REG_OFFSET, enable_flag); 6518 6519 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag); 6520 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag); 6521 } 6522 6523 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6524 { 6525 hns_roce_mtr_destroy(hr_dev, &eq->mtr); 6526 } 6527 6528 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, 6529 struct hns_roce_eq *eq) 6530 { 6531 struct device *dev = hr_dev->dev; 6532 int eqn = eq->eqn; 6533 int ret; 6534 u8 cmd; 6535 6536 if (eqn < hr_dev->caps.num_comp_vectors) 6537 cmd = HNS_ROCE_CMD_DESTROY_CEQC; 6538 else 6539 cmd = HNS_ROCE_CMD_DESTROY_AEQC; 6540 6541 ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M); 6542 if (ret) 6543 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn); 6544 6545 free_eq_buf(hr_dev, eq); 6546 } 6547 6548 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6549 { 6550 eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; 6551 eq->cons_index = 0; 6552 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; 6553 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; 6554 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; 6555 eq->shift = ilog2((unsigned int)eq->entries); 6556 } 6557 6558 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, 6559 void *mb_buf) 6560 { 6561 u64 eqe_ba[MTT_MIN_COUNT] = { 0 }; 6562 struct hns_roce_eq_context *eqc; 6563 u64 bt_ba = 0; 6564 int ret; 6565 6566 eqc = mb_buf; 6567 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); 6568 6569 init_eq_config(hr_dev, eq); 6570 6571 /* if not multi-hop, eqe buffer only use one trunk */ 6572 ret = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, 6573 ARRAY_SIZE(eqe_ba)); 6574 if (ret) { 6575 dev_err(hr_dev->dev, "failed to find EQE mtr, ret = %d\n", ret); 6576 return ret; 6577 } 6578 6579 bt_ba = hns_roce_get_mtr_ba(&eq->mtr); 6580 6581 hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID); 6582 hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num); 6583 hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore); 6584 hr_reg_write(eqc, EQC_COALESCE, eq->coalesce); 6585 hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st); 6586 hr_reg_write(eqc, EQC_EQN, eq->eqn); 6587 hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT); 6588 hr_reg_write(eqc, EQC_EQE_BA_PG_SZ, 6589 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift)); 6590 hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ, 6591 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift)); 6592 hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX); 6593 hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt); 6594 6595 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6596 if (eq->eq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 6597 dev_info(hr_dev->dev, "eq_period(%u) reached the upper limit, adjusted to 65.\n", 6598 eq->eq_period); 6599 eq->eq_period = HNS_ROCE_MAX_EQ_PERIOD; 6600 } 6601 eq->eq_period *= HNS_ROCE_CLOCK_ADJUST; 6602 } 6603 6604 hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period); 6605 hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER); 6606 hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3); 6607 hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35); 6608 hr_reg_write(eqc, EQC_SHIFT, eq->shift); 6609 hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX); 6610 hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12); 6611 hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28); 6612 hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60); 6613 hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX); 6614 hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12); 6615 hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44); 6616 hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE); 6617 6618 return 0; 6619 } 6620 6621 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6622 { 6623 struct hns_roce_buf_attr buf_attr = {}; 6624 int err; 6625 6626 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0) 6627 eq->hop_num = 0; 6628 else 6629 eq->hop_num = hr_dev->caps.eqe_hop_num; 6630 6631 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT; 6632 buf_attr.region[0].size = eq->entries * eq->eqe_size; 6633 buf_attr.region[0].hopnum = eq->hop_num; 6634 buf_attr.region_count = 1; 6635 6636 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr, 6637 hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL, 6638 0); 6639 if (err) 6640 dev_err(hr_dev->dev, "failed to alloc EQE mtr, err %d\n", err); 6641 6642 return err; 6643 } 6644 6645 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, 6646 struct hns_roce_eq *eq, u8 eq_cmd) 6647 { 6648 struct hns_roce_cmd_mailbox *mailbox; 6649 int ret; 6650 6651 /* Allocate mailbox memory */ 6652 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6653 if (IS_ERR(mailbox)) 6654 return PTR_ERR(mailbox); 6655 6656 ret = alloc_eq_buf(hr_dev, eq); 6657 if (ret) 6658 goto free_cmd_mbox; 6659 6660 ret = config_eqc(hr_dev, eq, mailbox->buf); 6661 if (ret) 6662 goto err_cmd_mbox; 6663 6664 ret = hns_roce_create_hw_ctx(hr_dev, mailbox, eq_cmd, eq->eqn); 6665 if (ret) { 6666 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n"); 6667 goto err_cmd_mbox; 6668 } 6669 6670 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6671 6672 return 0; 6673 6674 err_cmd_mbox: 6675 free_eq_buf(hr_dev, eq); 6676 6677 free_cmd_mbox: 6678 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6679 6680 return ret; 6681 } 6682 6683 static void hns_roce_ceq_work(struct work_struct *work) 6684 { 6685 struct hns_roce_eq *eq = from_work(eq, work, work); 6686 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq); 6687 struct hns_roce_dev *hr_dev = eq->hr_dev; 6688 int ceqe_num = 0; 6689 u32 cqn; 6690 6691 while (ceqe && ceqe_num < hr_dev->caps.ceqe_depth) { 6692 /* Make sure we read CEQ entry after we have checked the 6693 * ownership bit 6694 */ 6695 dma_rmb(); 6696 6697 cqn = hr_reg_read(ceqe, CEQE_CQN); 6698 6699 hns_roce_cq_completion(hr_dev, cqn); 6700 6701 ++eq->cons_index; 6702 ++ceqe_num; 6703 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CEQE_CNT]); 6704 6705 ceqe = next_ceqe_sw_v2(eq); 6706 } 6707 6708 update_eq_db(eq); 6709 } 6710 6711 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num, 6712 int comp_num, int aeq_num, int other_num) 6713 { 6714 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6715 int i, j; 6716 int ret; 6717 6718 for (i = 0; i < irq_num; i++) { 6719 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, 6720 GFP_KERNEL); 6721 if (!hr_dev->irq_names[i]) { 6722 ret = -ENOMEM; 6723 goto err_kzalloc_failed; 6724 } 6725 } 6726 6727 /* irq contains: abnormal + AEQ + CEQ */ 6728 for (j = 0; j < other_num; j++) 6729 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6730 "hns-%s-abn-%d", pci_name(hr_dev->pci_dev), j); 6731 6732 for (j = other_num; j < (other_num + aeq_num); j++) 6733 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6734 "hns-%s-aeq-%d", pci_name(hr_dev->pci_dev), j - other_num); 6735 6736 for (j = (other_num + aeq_num); j < irq_num; j++) 6737 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6738 "hns-%s-ceq-%d", pci_name(hr_dev->pci_dev), 6739 j - other_num - aeq_num); 6740 6741 for (j = 0; j < irq_num; j++) { 6742 if (j < other_num) { 6743 ret = request_irq(hr_dev->irq[j], 6744 hns_roce_v2_msix_interrupt_abn, 6745 0, hr_dev->irq_names[j], hr_dev); 6746 } else if (j < (other_num + comp_num)) { 6747 INIT_WORK(&eq_table->eq[j - other_num].work, 6748 hns_roce_ceq_work); 6749 ret = request_irq(eq_table->eq[j - other_num].irq, 6750 hns_roce_v2_msix_interrupt_eq, 6751 0, hr_dev->irq_names[j + aeq_num], 6752 &eq_table->eq[j - other_num]); 6753 } else { 6754 ret = request_irq(eq_table->eq[j - other_num].irq, 6755 hns_roce_v2_msix_interrupt_eq, 6756 0, hr_dev->irq_names[j - comp_num], 6757 &eq_table->eq[j - other_num]); 6758 } 6759 6760 if (ret) { 6761 dev_err(hr_dev->dev, "request irq error!\n"); 6762 goto err_request_failed; 6763 } 6764 } 6765 6766 return 0; 6767 6768 err_request_failed: 6769 for (j -= 1; j >= 0; j--) { 6770 if (j < other_num) { 6771 free_irq(hr_dev->irq[j], hr_dev); 6772 continue; 6773 } 6774 free_irq(eq_table->eq[j - other_num].irq, 6775 &eq_table->eq[j - other_num]); 6776 if (j < other_num + comp_num) 6777 cancel_work_sync(&eq_table->eq[j - other_num].work); 6778 } 6779 6780 err_kzalloc_failed: 6781 for (i -= 1; i >= 0; i--) 6782 kfree(hr_dev->irq_names[i]); 6783 6784 return ret; 6785 } 6786 6787 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev) 6788 { 6789 int irq_num; 6790 int eq_num; 6791 int i; 6792 6793 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6794 irq_num = eq_num + hr_dev->caps.num_other_vectors; 6795 6796 for (i = 0; i < hr_dev->caps.num_other_vectors; i++) 6797 free_irq(hr_dev->irq[i], hr_dev); 6798 6799 for (i = 0; i < eq_num; i++) { 6800 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]); 6801 if (i < hr_dev->caps.num_comp_vectors) 6802 cancel_work_sync(&hr_dev->eq_table.eq[i].work); 6803 } 6804 6805 for (i = 0; i < irq_num; i++) 6806 kfree(hr_dev->irq_names[i]); 6807 } 6808 6809 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 6810 { 6811 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6812 struct device *dev = hr_dev->dev; 6813 struct hns_roce_eq *eq; 6814 int other_num; 6815 int comp_num; 6816 int aeq_num; 6817 int irq_num; 6818 int eq_num; 6819 u8 eq_cmd; 6820 int ret; 6821 int i; 6822 6823 if (hr_dev->caps.aeqe_depth < HNS_AEQ_POLLING_BUDGET) 6824 return -EINVAL; 6825 6826 other_num = hr_dev->caps.num_other_vectors; 6827 comp_num = hr_dev->caps.num_comp_vectors; 6828 aeq_num = hr_dev->caps.num_aeq_vectors; 6829 6830 eq_num = comp_num + aeq_num; 6831 irq_num = eq_num + other_num; 6832 6833 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL); 6834 if (!eq_table->eq) 6835 return -ENOMEM; 6836 6837 /* create eq */ 6838 for (i = 0; i < eq_num; i++) { 6839 eq = &eq_table->eq[i]; 6840 eq->hr_dev = hr_dev; 6841 eq->eqn = i; 6842 if (i < comp_num) { 6843 /* CEQ */ 6844 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; 6845 eq->type_flag = HNS_ROCE_CEQ; 6846 eq->entries = hr_dev->caps.ceqe_depth; 6847 eq->eqe_size = hr_dev->caps.ceqe_size; 6848 eq->irq = hr_dev->irq[i + other_num + aeq_num]; 6849 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; 6850 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; 6851 } else { 6852 /* AEQ */ 6853 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; 6854 eq->type_flag = HNS_ROCE_AEQ; 6855 eq->entries = hr_dev->caps.aeqe_depth; 6856 eq->eqe_size = hr_dev->caps.aeqe_size; 6857 eq->irq = hr_dev->irq[i - comp_num + other_num]; 6858 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; 6859 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; 6860 } 6861 6862 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); 6863 if (ret) { 6864 dev_err(dev, "failed to create eq.\n"); 6865 goto err_create_eq_fail; 6866 } 6867 } 6868 6869 INIT_WORK(&hr_dev->ecc_work, fmea_ram_ecc_work); 6870 6871 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0); 6872 if (!hr_dev->irq_workq) { 6873 dev_err(dev, "failed to create irq workqueue.\n"); 6874 ret = -ENOMEM; 6875 goto err_create_eq_fail; 6876 } 6877 6878 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num, 6879 other_num); 6880 if (ret) { 6881 dev_err(dev, "failed to request irq.\n"); 6882 goto err_request_irq_fail; 6883 } 6884 6885 /* enable irq */ 6886 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); 6887 6888 return 0; 6889 6890 err_request_irq_fail: 6891 destroy_workqueue(hr_dev->irq_workq); 6892 6893 err_create_eq_fail: 6894 for (i -= 1; i >= 0; i--) 6895 hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]); 6896 kfree(eq_table->eq); 6897 6898 return ret; 6899 } 6900 6901 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 6902 { 6903 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6904 int eq_num; 6905 int i; 6906 6907 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6908 6909 /* Disable irq */ 6910 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 6911 6912 __hns_roce_free_irq(hr_dev); 6913 destroy_workqueue(hr_dev->irq_workq); 6914 6915 for (i = 0; i < eq_num; i++) 6916 hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]); 6917 6918 kfree(eq_table->eq); 6919 } 6920 6921 static const struct ib_device_ops hns_roce_v2_dev_ops = { 6922 .destroy_qp = hns_roce_v2_destroy_qp, 6923 .modify_cq = hns_roce_v2_modify_cq, 6924 .poll_cq = hns_roce_v2_poll_cq, 6925 .post_recv = hns_roce_v2_post_recv, 6926 .post_send = hns_roce_v2_post_send, 6927 .query_qp = hns_roce_v2_query_qp, 6928 .req_notify_cq = hns_roce_v2_req_notify_cq, 6929 }; 6930 6931 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = { 6932 .modify_srq = hns_roce_v2_modify_srq, 6933 .post_srq_recv = hns_roce_v2_post_srq_recv, 6934 .query_srq = hns_roce_v2_query_srq, 6935 }; 6936 6937 static const struct hns_roce_hw hns_roce_hw_v2 = { 6938 .cmq_init = hns_roce_v2_cmq_init, 6939 .cmq_exit = hns_roce_v2_cmq_exit, 6940 .hw_profile = hns_roce_v2_profile, 6941 .hw_init = hns_roce_v2_init, 6942 .hw_exit = hns_roce_v2_exit, 6943 .post_mbox = v2_post_mbox, 6944 .poll_mbox_done = v2_poll_mbox_done, 6945 .chk_mbox_avail = v2_chk_mbox_is_avail, 6946 .set_gid = hns_roce_v2_set_gid, 6947 .set_mac = hns_roce_v2_set_mac, 6948 .write_mtpt = hns_roce_v2_write_mtpt, 6949 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, 6950 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt, 6951 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt, 6952 .write_cqc = hns_roce_v2_write_cqc, 6953 .set_hem = hns_roce_v2_set_hem, 6954 .clear_hem = hns_roce_v2_clear_hem, 6955 .modify_qp = hns_roce_v2_modify_qp, 6956 .dereg_mr = hns_roce_v2_dereg_mr, 6957 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init, 6958 .init_eq = hns_roce_v2_init_eq_table, 6959 .cleanup_eq = hns_roce_v2_cleanup_eq_table, 6960 .write_srqc = hns_roce_v2_write_srqc, 6961 .query_cqc = hns_roce_v2_query_cqc, 6962 .query_qpc = hns_roce_v2_query_qpc, 6963 .query_mpt = hns_roce_v2_query_mpt, 6964 .query_srqc = hns_roce_v2_query_srqc, 6965 .query_sccc = hns_roce_v2_query_sccc, 6966 .query_hw_counter = hns_roce_hw_v2_query_counter, 6967 .get_dscp = hns_roce_hw_v2_get_dscp, 6968 .hns_roce_dev_ops = &hns_roce_v2_dev_ops, 6969 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops, 6970 }; 6971 6972 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { 6973 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 6974 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 6975 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 6976 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 6977 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 6978 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 6979 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 6980 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 6981 /* required last entry */ 6982 {0, } 6983 }; 6984 6985 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl); 6986 6987 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, 6988 struct hnae3_handle *handle) 6989 { 6990 struct hns_roce_v2_priv *priv = hr_dev->priv; 6991 const struct pci_device_id *id; 6992 int i; 6993 6994 hr_dev->pci_dev = handle->pdev; 6995 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev); 6996 hr_dev->is_vf = id->driver_data; 6997 hr_dev->dev = &handle->pdev->dev; 6998 hr_dev->hw = &hns_roce_hw_v2; 6999 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; 7000 hr_dev->odb_offset = hr_dev->sdb_offset; 7001 7002 /* Get info from NIC driver. */ 7003 hr_dev->reg_base = handle->rinfo.roce_io_base; 7004 hr_dev->mem_base = handle->rinfo.roce_mem_base; 7005 hr_dev->caps.num_ports = 1; 7006 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; 7007 hr_dev->iboe.phy_port[0] = 0; 7008 7009 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, 7010 hr_dev->iboe.netdevs[0]->dev_addr); 7011 7012 for (i = 0; i < handle->rinfo.num_vectors; i++) 7013 hr_dev->irq[i] = pci_irq_vector(handle->pdev, 7014 i + handle->rinfo.base_vector); 7015 7016 /* cmd issue mode: 0 is poll, 1 is event */ 7017 hr_dev->cmd_mod = 1; 7018 hr_dev->loop_idc = 0; 7019 7020 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle); 7021 priv->handle = handle; 7022 } 7023 7024 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 7025 { 7026 struct hns_roce_dev *hr_dev; 7027 int ret; 7028 7029 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev); 7030 if (!hr_dev) 7031 return -ENOMEM; 7032 7033 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL); 7034 if (!hr_dev->priv) { 7035 ret = -ENOMEM; 7036 goto error_failed_kzalloc; 7037 } 7038 7039 hns_roce_hw_v2_get_cfg(hr_dev, handle); 7040 7041 ret = hns_roce_init(hr_dev); 7042 if (ret) { 7043 dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); 7044 goto error_failed_roce_init; 7045 } 7046 7047 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 7048 ret = free_mr_init(hr_dev); 7049 if (ret) { 7050 dev_err(hr_dev->dev, "failed to init free mr!\n"); 7051 goto error_failed_free_mr_init; 7052 } 7053 } 7054 7055 handle->priv = hr_dev; 7056 7057 return 0; 7058 7059 error_failed_free_mr_init: 7060 hns_roce_exit(hr_dev); 7061 7062 error_failed_roce_init: 7063 kfree(hr_dev->priv); 7064 7065 error_failed_kzalloc: 7066 ib_dealloc_device(&hr_dev->ib_dev); 7067 7068 return ret; 7069 } 7070 7071 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 7072 bool reset) 7073 { 7074 struct hns_roce_dev *hr_dev = handle->priv; 7075 7076 if (!hr_dev) 7077 return; 7078 7079 handle->priv = NULL; 7080 7081 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT; 7082 hns_roce_handle_device_err(hr_dev); 7083 7084 hns_roce_exit(hr_dev); 7085 kfree(hr_dev->priv); 7086 ib_dealloc_device(&hr_dev->ib_dev); 7087 } 7088 7089 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 7090 { 7091 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 7092 const struct pci_device_id *id; 7093 struct device *dev = &handle->pdev->dev; 7094 int ret; 7095 7096 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT; 7097 7098 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) { 7099 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 7100 goto reset_chk_err; 7101 } 7102 7103 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev); 7104 if (!id) 7105 return 0; 7106 7107 if (id->driver_data && handle->pdev->revision == PCI_REVISION_ID_HIP08) 7108 return 0; 7109 7110 ret = __hns_roce_hw_v2_init_instance(handle); 7111 if (ret) { 7112 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 7113 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret); 7114 if (ops->ae_dev_resetting(handle) || 7115 ops->get_hw_reset_stat(handle)) 7116 goto reset_chk_err; 7117 else 7118 return ret; 7119 } 7120 7121 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED; 7122 7123 return 0; 7124 7125 reset_chk_err: 7126 dev_err(dev, "Device is busy in resetting state.\n" 7127 "please retry later.\n"); 7128 7129 return -EBUSY; 7130 } 7131 7132 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 7133 bool reset) 7134 { 7135 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) 7136 return; 7137 7138 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT; 7139 7140 __hns_roce_hw_v2_uninit_instance(handle, reset); 7141 7142 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 7143 } 7144 7145 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle) 7146 { 7147 struct hns_roce_dev *hr_dev; 7148 7149 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) { 7150 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 7151 return 0; 7152 } 7153 7154 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN; 7155 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 7156 7157 hr_dev = handle->priv; 7158 if (!hr_dev) 7159 return 0; 7160 7161 hr_dev->active = false; 7162 hr_dev->dis_db = true; 7163 7164 rdma_user_mmap_disassociate(&hr_dev->ib_dev); 7165 7166 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN; 7167 7168 return 0; 7169 } 7170 7171 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle) 7172 { 7173 struct device *dev = &handle->pdev->dev; 7174 int ret; 7175 7176 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN, 7177 &handle->rinfo.state)) { 7178 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 7179 return 0; 7180 } 7181 7182 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT; 7183 7184 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n"); 7185 ret = __hns_roce_hw_v2_init_instance(handle); 7186 if (ret) { 7187 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify 7188 * callback function, RoCE Engine reinitialize. If RoCE reinit 7189 * failed, we should inform NIC driver. 7190 */ 7191 handle->priv = NULL; 7192 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret); 7193 } else { 7194 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 7195 dev_info(dev, "reset done, RoCE client reinit finished.\n"); 7196 } 7197 7198 return ret; 7199 } 7200 7201 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle) 7202 { 7203 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state)) 7204 return 0; 7205 7206 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT; 7207 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n"); 7208 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY); 7209 __hns_roce_hw_v2_uninit_instance(handle, false); 7210 7211 return 0; 7212 } 7213 7214 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle, 7215 enum hnae3_reset_notify_type type) 7216 { 7217 int ret = 0; 7218 7219 switch (type) { 7220 case HNAE3_DOWN_CLIENT: 7221 ret = hns_roce_hw_v2_reset_notify_down(handle); 7222 break; 7223 case HNAE3_INIT_CLIENT: 7224 ret = hns_roce_hw_v2_reset_notify_init(handle); 7225 break; 7226 case HNAE3_UNINIT_CLIENT: 7227 ret = hns_roce_hw_v2_reset_notify_uninit(handle); 7228 break; 7229 default: 7230 break; 7231 } 7232 7233 return ret; 7234 } 7235 7236 static void hns_roce_hw_v2_link_status_change(struct hnae3_handle *handle, 7237 bool linkup) 7238 { 7239 struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv; 7240 struct net_device *netdev = handle->rinfo.netdev; 7241 7242 if (linkup || !hr_dev) 7243 return; 7244 7245 ib_dispatch_port_state_event(&hr_dev->ib_dev, netdev); 7246 } 7247 7248 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 7249 .init_instance = hns_roce_hw_v2_init_instance, 7250 .uninit_instance = hns_roce_hw_v2_uninit_instance, 7251 .link_status_change = hns_roce_hw_v2_link_status_change, 7252 .reset_notify = hns_roce_hw_v2_reset_notify, 7253 }; 7254 7255 static struct hnae3_client hns_roce_hw_v2_client = { 7256 .name = "hns_roce_hw_v2", 7257 .type = HNAE3_CLIENT_ROCE, 7258 .ops = &hns_roce_hw_v2_ops, 7259 }; 7260 7261 static int __init hns_roce_hw_v2_init(void) 7262 { 7263 hns_roce_init_debugfs(); 7264 return hnae3_register_client(&hns_roce_hw_v2_client); 7265 } 7266 7267 static void __exit hns_roce_hw_v2_exit(void) 7268 { 7269 hnae3_unregister_client(&hns_roce_hw_v2_client); 7270 hns_roce_cleanup_debugfs(); 7271 } 7272 7273 module_init(hns_roce_hw_v2_init); 7274 module_exit(hns_roce_hw_v2_exit); 7275 7276 MODULE_LICENSE("Dual BSD/GPL"); 7277 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 7278 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 7279 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); 7280 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); 7281