1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * GPADC driver for sunxi platforms (D1, T113-S3 and R329) 4 * Copyright (c) 2023 Maksim Kiselev <bigunclemax@gmail.com> 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/clk.h> 9 #include <linux/completion.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/mod_devicetable.h> 13 #include <linux/module.h> 14 #include <linux/platform_device.h> 15 #include <linux/property.h> 16 #include <linux/reset.h> 17 18 #include <linux/iio/adc-helpers.h> 19 #include <linux/iio/iio.h> 20 21 #define SUN20I_GPADC_DRIVER_NAME "sun20i-gpadc" 22 23 /* Register map definition */ 24 #define SUN20I_GPADC_SR 0x00 25 #define SUN20I_GPADC_CTRL 0x04 26 #define SUN20I_GPADC_CS_EN 0x08 27 #define SUN20I_GPADC_FIFO_INTC 0x0c 28 #define SUN20I_GPADC_FIFO_INTS 0x10 29 #define SUN20I_GPADC_FIFO_DATA 0X14 30 #define SUN20I_GPADC_CB_DATA 0X18 31 #define SUN20I_GPADC_DATAL_INTC 0x20 32 #define SUN20I_GPADC_DATAH_INTC 0x24 33 #define SUN20I_GPADC_DATA_INTC 0x28 34 #define SUN20I_GPADC_DATAL_INTS 0x30 35 #define SUN20I_GPADC_DATAH_INTS 0x34 36 #define SUN20I_GPADC_DATA_INTS 0x38 37 #define SUN20I_GPADC_CH_CMP_DATA(x) (0x40 + (x) * 4) 38 #define SUN20I_GPADC_CH_DATA(x) (0x80 + (x) * 4) 39 40 #define SUN20I_GPADC_CTRL_ADC_AUTOCALI_EN_MASK BIT(23) 41 #define SUN20I_GPADC_CTRL_WORK_MODE_MASK GENMASK(19, 18) 42 #define SUN20I_GPADC_CTRL_ADC_EN_MASK BIT(16) 43 #define SUN20I_GPADC_CS_EN_ADC_CH(x) BIT(x) 44 #define SUN20I_GPADC_DATA_INTC_CH_DATA_IRQ_EN(x) BIT(x) 45 46 #define SUN20I_GPADC_WORK_MODE_SINGLE 0 47 48 struct sun20i_gpadc_iio { 49 void __iomem *regs; 50 struct completion completion; 51 int last_channel; 52 /* 53 * Lock to protect the device state during a potential concurrent 54 * read access from userspace. Reading a raw value requires a sequence 55 * of register writes, then a wait for a completion callback, 56 * and finally a register read, during which userspace could issue 57 * another read request. This lock protects a read access from 58 * ocurring before another one has finished. 59 */ 60 struct mutex lock; 61 }; 62 63 static int sun20i_gpadc_adc_read(struct sun20i_gpadc_iio *info, 64 struct iio_chan_spec const *chan, int *val) 65 { 66 u32 ctrl; 67 int ret = IIO_VAL_INT; 68 69 mutex_lock(&info->lock); 70 71 reinit_completion(&info->completion); 72 73 if (info->last_channel != chan->channel) { 74 info->last_channel = chan->channel; 75 76 /* enable the analog input channel */ 77 writel(SUN20I_GPADC_CS_EN_ADC_CH(chan->channel), 78 info->regs + SUN20I_GPADC_CS_EN); 79 80 /* enable the data irq for input channel */ 81 writel(SUN20I_GPADC_DATA_INTC_CH_DATA_IRQ_EN(chan->channel), 82 info->regs + SUN20I_GPADC_DATA_INTC); 83 } 84 85 /* enable the ADC function */ 86 ctrl = readl(info->regs + SUN20I_GPADC_CTRL); 87 ctrl |= FIELD_PREP(SUN20I_GPADC_CTRL_ADC_EN_MASK, 1); 88 writel(ctrl, info->regs + SUN20I_GPADC_CTRL); 89 90 /* 91 * According to the datasheet maximum acquire time(TACQ) can be 92 * (65535+1)/24Mhz and conversion time(CONV_TIME) is always constant 93 * and equal to 14/24Mhz, so (TACQ+CONV_TIME) <= 2.73125ms. 94 * A 10ms delay should be enough to make sure an interrupt occurs in 95 * normal conditions. If it doesn't occur, then there is a timeout. 96 */ 97 if (!wait_for_completion_timeout(&info->completion, msecs_to_jiffies(10))) { 98 ret = -ETIMEDOUT; 99 goto err_unlock; 100 } 101 102 /* read the ADC data */ 103 *val = readl(info->regs + SUN20I_GPADC_CH_DATA(chan->channel)); 104 105 err_unlock: 106 mutex_unlock(&info->lock); 107 108 return ret; 109 } 110 111 static int sun20i_gpadc_read_raw(struct iio_dev *indio_dev, 112 struct iio_chan_spec const *chan, int *val, 113 int *val2, long mask) 114 { 115 struct sun20i_gpadc_iio *info = iio_priv(indio_dev); 116 117 switch (mask) { 118 case IIO_CHAN_INFO_RAW: 119 return sun20i_gpadc_adc_read(info, chan, val); 120 case IIO_CHAN_INFO_SCALE: 121 /* value in mv = 1800mV / 4096 raw */ 122 *val = 1800; 123 *val2 = 12; 124 return IIO_VAL_FRACTIONAL_LOG2; 125 default: 126 return -EINVAL; 127 } 128 } 129 130 static irqreturn_t sun20i_gpadc_irq_handler(int irq, void *data) 131 { 132 struct sun20i_gpadc_iio *info = data; 133 134 /* clear data interrupt status register */ 135 writel(GENMASK(31, 0), info->regs + SUN20I_GPADC_DATA_INTS); 136 137 complete(&info->completion); 138 139 return IRQ_HANDLED; 140 } 141 142 static const struct iio_info sun20i_gpadc_iio_info = { 143 .read_raw = sun20i_gpadc_read_raw, 144 }; 145 146 static void sun20i_gpadc_reset_assert(void *data) 147 { 148 struct reset_control *rst = data; 149 150 reset_control_assert(rst); 151 } 152 153 static const struct iio_chan_spec sun20i_gpadc_chan_template = { 154 .type = IIO_VOLTAGE, 155 .indexed = 1, 156 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 157 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), 158 }; 159 160 static int sun20i_gpadc_alloc_channels(struct iio_dev *indio_dev, 161 struct device *dev) 162 { 163 int num_channels; 164 struct iio_chan_spec *channels; 165 166 num_channels = devm_iio_adc_device_alloc_chaninfo_se(dev, 167 &sun20i_gpadc_chan_template, -1, &channels); 168 if (num_channels < 0) 169 return num_channels; 170 171 indio_dev->channels = channels; 172 indio_dev->num_channels = num_channels; 173 174 return 0; 175 } 176 177 static int sun20i_gpadc_probe(struct platform_device *pdev) 178 { 179 struct device *dev = &pdev->dev; 180 struct iio_dev *indio_dev; 181 struct sun20i_gpadc_iio *info; 182 struct reset_control *rst; 183 struct clk *clk; 184 int irq; 185 int ret; 186 187 indio_dev = devm_iio_device_alloc(dev, sizeof(*info)); 188 if (!indio_dev) 189 return -ENOMEM; 190 191 info = iio_priv(indio_dev); 192 info->last_channel = -1; 193 194 mutex_init(&info->lock); 195 init_completion(&info->completion); 196 197 ret = sun20i_gpadc_alloc_channels(indio_dev, dev); 198 if (ret) 199 return ret; 200 201 indio_dev->info = &sun20i_gpadc_iio_info; 202 indio_dev->name = SUN20I_GPADC_DRIVER_NAME; 203 204 info->regs = devm_platform_ioremap_resource(pdev, 0); 205 if (IS_ERR(info->regs)) 206 return PTR_ERR(info->regs); 207 208 clk = devm_clk_get_enabled(dev, NULL); 209 if (IS_ERR(clk)) 210 return dev_err_probe(dev, PTR_ERR(clk), "failed to enable bus clock\n"); 211 212 rst = devm_reset_control_get_exclusive(dev, NULL); 213 if (IS_ERR(rst)) 214 return dev_err_probe(dev, PTR_ERR(rst), "failed to get reset control\n"); 215 216 ret = reset_control_deassert(rst); 217 if (ret) 218 return dev_err_probe(dev, ret, "failed to deassert reset\n"); 219 220 ret = devm_add_action_or_reset(dev, sun20i_gpadc_reset_assert, rst); 221 if (ret) 222 return ret; 223 224 irq = platform_get_irq(pdev, 0); 225 if (irq < 0) 226 return irq; 227 228 ret = devm_request_irq(dev, irq, sun20i_gpadc_irq_handler, 0, 229 dev_name(dev), info); 230 if (ret) 231 return dev_err_probe(dev, ret, "failed requesting irq %d\n", irq); 232 233 writel(FIELD_PREP(SUN20I_GPADC_CTRL_ADC_AUTOCALI_EN_MASK, 1) | 234 FIELD_PREP(SUN20I_GPADC_CTRL_WORK_MODE_MASK, SUN20I_GPADC_WORK_MODE_SINGLE), 235 info->regs + SUN20I_GPADC_CTRL); 236 237 ret = devm_iio_device_register(dev, indio_dev); 238 if (ret) 239 return dev_err_probe(dev, ret, "could not register the device\n"); 240 241 return 0; 242 } 243 244 static const struct of_device_id sun20i_gpadc_of_id[] = { 245 { .compatible = "allwinner,sun20i-d1-gpadc" }, 246 { } 247 }; 248 MODULE_DEVICE_TABLE(of, sun20i_gpadc_of_id); 249 250 static struct platform_driver sun20i_gpadc_driver = { 251 .driver = { 252 .name = SUN20I_GPADC_DRIVER_NAME, 253 .of_match_table = sun20i_gpadc_of_id, 254 }, 255 .probe = sun20i_gpadc_probe, 256 }; 257 module_platform_driver(sun20i_gpadc_driver); 258 259 MODULE_DESCRIPTION("ADC driver for sunxi platforms"); 260 MODULE_AUTHOR("Maksim Kiselev <bigunclemax@gmail.com>"); 261 MODULE_LICENSE("GPL"); 262 MODULE_IMPORT_NS("IIO_DRIVER"); 263