1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * iio/adc/max1363.c 4 * Copyright (C) 2008-2010 Jonathan Cameron 5 * 6 * based on linux/drivers/i2c/chips/max123x 7 * Copyright (C) 2002-2004 Stefan Eletzhofer 8 * 9 * based on linux/drivers/acron/char/pcf8583.c 10 * Copyright (C) 2000 Russell King 11 * 12 * Driver for max1363 and similar chips. 13 */ 14 15 #include <linux/interrupt.h> 16 #include <linux/cleanup.h> 17 #include <linux/device.h> 18 #include <linux/kernel.h> 19 #include <linux/sysfs.h> 20 #include <linux/list.h> 21 #include <linux/i2c.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/slab.h> 24 #include <linux/err.h> 25 #include <linux/module.h> 26 #include <linux/mod_devicetable.h> 27 #include <linux/property.h> 28 #include <linux/unaligned.h> 29 30 #include <linux/iio/iio.h> 31 #include <linux/iio/sysfs.h> 32 #include <linux/iio/events.h> 33 #include <linux/iio/buffer.h> 34 #include <linux/iio/kfifo_buf.h> 35 #include <linux/iio/trigger_consumer.h> 36 #include <linux/iio/triggered_buffer.h> 37 38 #define MAX1363_SETUP_BYTE(a) ((a) | 0x80) 39 40 /* There is a fair bit more defined here than currently 41 * used, but the intention is to support everything these 42 * chips do in the long run */ 43 44 /* see data sheets */ 45 /* max1363 and max1236, max1237, max1238, max1239 */ 46 #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD 0x00 47 #define MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF 0x20 48 #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT 0x40 49 #define MAX1363_SETUP_AIN3_IS_REF_REF_IS_INT 0x60 50 #define MAX1363_SETUP_POWER_UP_INT_REF 0x10 51 #define MAX1363_SETUP_POWER_DOWN_INT_REF 0x00 52 53 /* think about including max11600 etc - more settings */ 54 #define MAX1363_SETUP_EXT_CLOCK 0x08 55 #define MAX1363_SETUP_INT_CLOCK 0x00 56 #define MAX1363_SETUP_UNIPOLAR 0x00 57 #define MAX1363_SETUP_BIPOLAR 0x04 58 #define MAX1363_SETUP_RESET 0x00 59 #define MAX1363_SETUP_NORESET 0x02 60 /* max1363 only - though don't care on others. 61 * For now monitor modes are not implemented as the relevant 62 * line is not connected on my test board. 63 * The definitions are here as I intend to add this soon. 64 */ 65 #define MAX1363_SETUP_MONITOR_SETUP 0x01 66 67 /* Specific to the max1363 */ 68 #define MAX1363_MON_RESET_CHAN(a) (1 << ((a) + 4)) 69 #define MAX1363_MON_INT_ENABLE 0x01 70 71 /* defined for readability reasons */ 72 /* All chips */ 73 #define MAX1363_CONFIG_BYTE(a) ((a)) 74 75 #define MAX1363_CONFIG_SE 0x01 76 #define MAX1363_CONFIG_DE 0x00 77 #define MAX1363_CONFIG_SCAN_TO_CS 0x00 78 #define MAX1363_CONFIG_SCAN_SINGLE_8 0x20 79 #define MAX1363_CONFIG_SCAN_MONITOR_MODE 0x40 80 #define MAX1363_CONFIG_SCAN_SINGLE_1 0x60 81 /* max123{6-9} only */ 82 #define MAX1236_SCAN_MID_TO_CHANNEL 0x40 83 84 /* max1363 only - merely part of channel selects or don't care for others */ 85 #define MAX1363_CONFIG_EN_MON_MODE_READ 0x18 86 87 #define MAX1363_CHANNEL_SEL(a) ((a) << 1) 88 89 /* max1363 strictly 0x06 - but doesn't matter */ 90 #define MAX1363_CHANNEL_SEL_MASK 0x1E 91 #define MAX1363_SCAN_MASK 0x60 92 #define MAX1363_SE_DE_MASK 0x01 93 94 #define MAX1363_MAX_CHANNELS 25 95 /** 96 * struct max1363_mode - scan mode information 97 * @conf: The corresponding value of the configuration register 98 * @modemask: Bit mask corresponding to channels enabled in this mode 99 */ 100 struct max1363_mode { 101 int8_t conf; 102 DECLARE_BITMAP(modemask, MAX1363_MAX_CHANNELS); 103 }; 104 105 /* This must be maintained along side the max1363_mode_table in max1363_core */ 106 enum max1363_modes { 107 /* Single read of a single channel */ 108 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11, 109 /* Differential single read */ 110 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11, 111 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10, 112 /* Scan to channel and mid to channel where overlapping */ 113 s0to1, s0to2, s2to3, s0to3, s0to4, s0to5, s0to6, 114 s6to7, s0to7, s6to8, s0to8, s6to9, 115 s0to9, s6to10, s0to10, s6to11, s0to11, 116 /* Differential scan to channel and mid to channel where overlapping */ 117 d0m1to2m3, d0m1to4m5, d0m1to6m7, d6m7to8m9, 118 d0m1to8m9, d6m7to10m11, d0m1to10m11, d1m0to3m2, 119 d1m0to5m4, d1m0to7m6, d7m6to9m8, d1m0to9m8, 120 d7m6to11m10, d1m0to11m10, 121 }; 122 123 /** 124 * struct max1363_chip_info - chip specifc information 125 * @info: iio core function callbacks structure 126 * @channels: channel specification 127 * @num_channels: number of channels 128 * @mode_list: array of available scan modes 129 * @default_mode: the scan mode in which the chip starts up 130 * @int_vref_mv: the internal reference voltage 131 * @num_modes: number of modes 132 * @bits: accuracy of the adc in bits 133 */ 134 struct max1363_chip_info { 135 const struct iio_info *info; 136 const struct iio_chan_spec *channels; 137 int num_channels; 138 const enum max1363_modes *mode_list; 139 enum max1363_modes default_mode; 140 u16 int_vref_mv; 141 u8 num_modes; 142 u8 bits; 143 }; 144 145 /** 146 * struct max1363_state - driver instance specific data 147 * @client: i2c_client 148 * @setupbyte: cache of current device setup byte 149 * @configbyte: cache of current device config byte 150 * @chip_info: chip model specific constants, available modes, etc. 151 * @current_mode: the scan mode of this chip 152 * @requestedmask: a valid requested set of channels 153 * @lock: lock to ensure state is consistent 154 * @monitor_on: whether monitor mode is enabled 155 * @monitor_speed: parameter corresponding to device monitor speed setting 156 * @mask_high: bitmask for enabled high thresholds 157 * @mask_low: bitmask for enabled low thresholds 158 * @thresh_high: high threshold values 159 * @thresh_low: low threshold values 160 * @vref: Reference voltage regulator 161 * @vref_uv: Actual (external or internal) reference voltage 162 * @send: function used to send data to the chip 163 * @recv: function used to receive data from the chip 164 * @data: buffer to store channel data and timestamp 165 */ 166 struct max1363_state { 167 struct i2c_client *client; 168 u8 setupbyte; 169 u8 configbyte; 170 const struct max1363_chip_info *chip_info; 171 const struct max1363_mode *current_mode; 172 u32 requestedmask; 173 struct mutex lock; 174 175 /* Using monitor modes and buffer at the same time is 176 currently not supported */ 177 bool monitor_on; 178 unsigned int monitor_speed:3; 179 u8 mask_high; 180 u8 mask_low; 181 /* 4x unipolar first then the fours bipolar ones */ 182 s16 thresh_high[8]; 183 s16 thresh_low[8]; 184 struct regulator *vref; 185 u32 vref_uv; 186 int (*send)(const struct i2c_client *client, 187 const char *buf, int count); 188 int (*recv)(const struct i2c_client *client, 189 char *buf, int count); 190 struct { 191 u8 buf[MAX1363_MAX_CHANNELS * 2]; 192 aligned_s64 ts; 193 } data; 194 }; 195 196 #define MAX1363_MODE_SINGLE(_num, _mask) { \ 197 .conf = MAX1363_CHANNEL_SEL(_num) \ 198 | MAX1363_CONFIG_SCAN_SINGLE_1 \ 199 | MAX1363_CONFIG_SE, \ 200 .modemask[0] = _mask, \ 201 } 202 203 #define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \ 204 .conf = MAX1363_CHANNEL_SEL(_num) \ 205 | MAX1363_CONFIG_SCAN_TO_CS \ 206 | MAX1363_CONFIG_SE, \ 207 .modemask[0] = _mask, \ 208 } 209 210 /* note not available for max1363 hence naming */ 211 #define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \ 212 .conf = MAX1363_CHANNEL_SEL(_num) \ 213 | MAX1236_SCAN_MID_TO_CHANNEL \ 214 | MAX1363_CONFIG_SE, \ 215 .modemask[0] = _mask \ 216 } 217 218 #define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \ 219 .conf = MAX1363_CHANNEL_SEL(_nump) \ 220 | MAX1363_CONFIG_SCAN_SINGLE_1 \ 221 | MAX1363_CONFIG_DE, \ 222 .modemask[0] = _mask \ 223 } 224 225 /* Can't think how to automate naming so specify for now */ 226 #define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \ 227 .conf = MAX1363_CHANNEL_SEL(_num) \ 228 | MAX1363_CONFIG_SCAN_TO_CS \ 229 | MAX1363_CONFIG_DE, \ 230 .modemask[0] = _mask \ 231 } 232 233 /* note only available for max1363 hence naming */ 234 #define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \ 235 .conf = MAX1363_CHANNEL_SEL(_num) \ 236 | MAX1236_SCAN_MID_TO_CHANNEL \ 237 | MAX1363_CONFIG_SE, \ 238 .modemask[0] = _mask \ 239 } 240 241 static const struct max1363_mode max1363_mode_table[] = { 242 /* All of the single channel options first */ 243 MAX1363_MODE_SINGLE(0, 1 << 0), 244 MAX1363_MODE_SINGLE(1, 1 << 1), 245 MAX1363_MODE_SINGLE(2, 1 << 2), 246 MAX1363_MODE_SINGLE(3, 1 << 3), 247 MAX1363_MODE_SINGLE(4, 1 << 4), 248 MAX1363_MODE_SINGLE(5, 1 << 5), 249 MAX1363_MODE_SINGLE(6, 1 << 6), 250 MAX1363_MODE_SINGLE(7, 1 << 7), 251 MAX1363_MODE_SINGLE(8, 1 << 8), 252 MAX1363_MODE_SINGLE(9, 1 << 9), 253 MAX1363_MODE_SINGLE(10, 1 << 10), 254 MAX1363_MODE_SINGLE(11, 1 << 11), 255 256 MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12), 257 MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13), 258 MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14), 259 MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15), 260 MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16), 261 MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17), 262 MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18), 263 MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19), 264 MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20), 265 MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21), 266 MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22), 267 MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23), 268 269 /* The multichannel scans next */ 270 MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003), 271 MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007), 272 MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C), 273 MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F), 274 MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F), 275 MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F), 276 MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F), 277 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0), 278 MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF), 279 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0), 280 MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF), 281 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0), 282 MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF), 283 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0), 284 MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF), 285 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0), 286 MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF), 287 288 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000), 289 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000), 290 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000), 291 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000), 292 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000), 293 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000), 294 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000), 295 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000), 296 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000), 297 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000), 298 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000), 299 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000), 300 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000), 301 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000), 302 }; 303 304 static const struct max1363_mode 305 *max1363_match_mode(const unsigned long *mask, 306 const struct max1363_chip_info *ci) 307 { 308 int i; 309 if (mask) 310 for (i = 0; i < ci->num_modes; i++) 311 if (bitmap_subset(mask, 312 max1363_mode_table[ci->mode_list[i]]. 313 modemask, 314 MAX1363_MAX_CHANNELS)) 315 return &max1363_mode_table[ci->mode_list[i]]; 316 return NULL; 317 } 318 319 static int max1363_smbus_send(const struct i2c_client *client, const char *buf, 320 int count) 321 { 322 int i, err; 323 324 for (i = err = 0; err == 0 && i < count; ++i) 325 err = i2c_smbus_write_byte(client, buf[i]); 326 327 return err ? err : count; 328 } 329 330 static int max1363_smbus_recv(const struct i2c_client *client, char *buf, 331 int count) 332 { 333 int i, ret; 334 335 for (i = 0; i < count; ++i) { 336 ret = i2c_smbus_read_byte(client); 337 if (ret < 0) 338 return ret; 339 buf[i] = ret; 340 } 341 342 return count; 343 } 344 345 static int max1363_write_basic_config(struct max1363_state *st) 346 { 347 u8 tx_buf[2] = { st->setupbyte, st->configbyte }; 348 349 return st->send(st->client, tx_buf, 2); 350 } 351 352 static int max1363_set_scan_mode(struct max1363_state *st) 353 { 354 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK 355 | MAX1363_SCAN_MASK 356 | MAX1363_SE_DE_MASK); 357 st->configbyte |= st->current_mode->conf; 358 359 return max1363_write_basic_config(st); 360 } 361 362 static int max1363_read_single_chan(struct iio_dev *indio_dev, 363 struct iio_chan_spec const *chan, 364 int *val, 365 long m) 366 { 367 s32 data; 368 u8 rxbuf[2]; 369 struct max1363_state *st = iio_priv(indio_dev); 370 struct i2c_client *client = st->client; 371 372 guard(mutex)(&st->lock); 373 374 /* 375 * If monitor mode is enabled, the method for reading a single 376 * channel will have to be rather different and has not yet 377 * been implemented. 378 * 379 * Also, cannot read directly if buffered capture enabled. 380 */ 381 if (st->monitor_on) 382 return -EBUSY; 383 384 /* Check to see if current scan mode is correct */ 385 if (st->current_mode != &max1363_mode_table[chan->address]) { 386 int ret; 387 388 /* Update scan mode if needed */ 389 st->current_mode = &max1363_mode_table[chan->address]; 390 ret = max1363_set_scan_mode(st); 391 if (ret < 0) 392 return ret; 393 } 394 if (st->chip_info->bits != 8) { 395 /* Get reading */ 396 data = st->recv(client, rxbuf, 2); 397 if (data < 0) 398 return data; 399 400 data = get_unaligned_be16(rxbuf) & 401 ((1 << st->chip_info->bits) - 1); 402 } else { 403 /* Get reading */ 404 data = st->recv(client, rxbuf, 1); 405 if (data < 0) 406 return data; 407 408 data = rxbuf[0]; 409 } 410 *val = data; 411 412 return 0; 413 } 414 415 static int max1363_read_raw(struct iio_dev *indio_dev, 416 struct iio_chan_spec const *chan, 417 int *val, 418 int *val2, 419 long m) 420 { 421 struct max1363_state *st = iio_priv(indio_dev); 422 int ret; 423 424 switch (m) { 425 case IIO_CHAN_INFO_RAW: 426 if (!iio_device_claim_direct(indio_dev)) 427 return -EBUSY; 428 429 ret = max1363_read_single_chan(indio_dev, chan, val, m); 430 iio_device_release_direct(indio_dev); 431 if (ret < 0) 432 return ret; 433 return IIO_VAL_INT; 434 case IIO_CHAN_INFO_SCALE: 435 *val = st->vref_uv / 1000; 436 *val2 = st->chip_info->bits; 437 return IIO_VAL_FRACTIONAL_LOG2; 438 default: 439 return -EINVAL; 440 } 441 return 0; 442 } 443 444 /* Applies to max1363 */ 445 static const enum max1363_modes max1363_mode_list[] = { 446 _s0, _s1, _s2, _s3, 447 s0to1, s0to2, s0to3, 448 d0m1, d2m3, d1m0, d3m2, 449 d0m1to2m3, d1m0to3m2, 450 }; 451 452 static const struct iio_event_spec max1363_events[] = { 453 { 454 .type = IIO_EV_TYPE_THRESH, 455 .dir = IIO_EV_DIR_RISING, 456 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 457 BIT(IIO_EV_INFO_ENABLE), 458 }, { 459 .type = IIO_EV_TYPE_THRESH, 460 .dir = IIO_EV_DIR_FALLING, 461 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 462 BIT(IIO_EV_INFO_ENABLE), 463 }, 464 }; 465 466 #define MAX1363_CHAN_U(num, addr, si, bits, ev_spec, num_ev_spec) \ 467 { \ 468 .type = IIO_VOLTAGE, \ 469 .indexed = 1, \ 470 .channel = num, \ 471 .address = addr, \ 472 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 473 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 474 .datasheet_name = "AIN"#num, \ 475 .scan_type = { \ 476 .sign = 'u', \ 477 .realbits = bits, \ 478 .storagebits = (bits > 8) ? 16 : 8, \ 479 .endianness = IIO_BE, \ 480 }, \ 481 .scan_index = si, \ 482 .event_spec = ev_spec, \ 483 .num_event_specs = num_ev_spec, \ 484 } 485 486 /* bipolar channel */ 487 #define MAX1363_CHAN_B(num, num2, addr, si, bits, ev_spec, num_ev_spec) \ 488 { \ 489 .type = IIO_VOLTAGE, \ 490 .differential = 1, \ 491 .indexed = 1, \ 492 .channel = num, \ 493 .channel2 = num2, \ 494 .address = addr, \ 495 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 496 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 497 .datasheet_name = "AIN"#num"-AIN"#num2, \ 498 .scan_type = { \ 499 .sign = 's', \ 500 .realbits = bits, \ 501 .storagebits = (bits > 8) ? 16 : 8, \ 502 .endianness = IIO_BE, \ 503 }, \ 504 .scan_index = si, \ 505 .event_spec = ev_spec, \ 506 .num_event_specs = num_ev_spec, \ 507 } 508 509 #define MAX1363_4X_CHANS(bits, ev_spec, num_ev_spec) { \ 510 MAX1363_CHAN_U(0, _s0, 0, bits, ev_spec, num_ev_spec), \ 511 MAX1363_CHAN_U(1, _s1, 1, bits, ev_spec, num_ev_spec), \ 512 MAX1363_CHAN_U(2, _s2, 2, bits, ev_spec, num_ev_spec), \ 513 MAX1363_CHAN_U(3, _s3, 3, bits, ev_spec, num_ev_spec), \ 514 MAX1363_CHAN_B(0, 1, d0m1, 4, bits, ev_spec, num_ev_spec), \ 515 MAX1363_CHAN_B(2, 3, d2m3, 5, bits, ev_spec, num_ev_spec), \ 516 MAX1363_CHAN_B(1, 0, d1m0, 6, bits, ev_spec, num_ev_spec), \ 517 MAX1363_CHAN_B(3, 2, d3m2, 7, bits, ev_spec, num_ev_spec), \ 518 IIO_CHAN_SOFT_TIMESTAMP(8) \ 519 } 520 521 static const struct iio_chan_spec max1036_channels[] = 522 MAX1363_4X_CHANS(8, NULL, 0); 523 static const struct iio_chan_spec max1136_channels[] = 524 MAX1363_4X_CHANS(10, NULL, 0); 525 static const struct iio_chan_spec max1236_channels[] = 526 MAX1363_4X_CHANS(12, NULL, 0); 527 static const struct iio_chan_spec max1361_channels[] = 528 MAX1363_4X_CHANS(10, max1363_events, ARRAY_SIZE(max1363_events)); 529 static const struct iio_chan_spec max1363_channels[] = 530 MAX1363_4X_CHANS(12, max1363_events, ARRAY_SIZE(max1363_events)); 531 532 /* Applies to max1236, max1237 */ 533 static const enum max1363_modes max1236_mode_list[] = { 534 _s0, _s1, _s2, _s3, 535 s0to1, s0to2, s0to3, 536 d0m1, d2m3, d1m0, d3m2, 537 d0m1to2m3, d1m0to3m2, 538 s2to3, 539 }; 540 541 /* Applies to max1238, max1239 */ 542 static const enum max1363_modes max1238_mode_list[] = { 543 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11, 544 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, 545 s0to7, s0to8, s0to9, s0to10, s0to11, 546 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11, 547 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10, 548 d0m1to2m3, d0m1to4m5, d0m1to6m7, d0m1to8m9, d0m1to10m11, 549 d1m0to3m2, d1m0to5m4, d1m0to7m6, d1m0to9m8, d1m0to11m10, 550 s6to7, s6to8, s6to9, s6to10, s6to11, 551 d6m7to8m9, d6m7to10m11, d7m6to9m8, d7m6to11m10, 552 }; 553 554 #define MAX1363_12X_CHANS(bits) { \ 555 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \ 556 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \ 557 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \ 558 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \ 559 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \ 560 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \ 561 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \ 562 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \ 563 MAX1363_CHAN_U(8, _s8, 8, bits, NULL, 0), \ 564 MAX1363_CHAN_U(9, _s9, 9, bits, NULL, 0), \ 565 MAX1363_CHAN_U(10, _s10, 10, bits, NULL, 0), \ 566 MAX1363_CHAN_U(11, _s11, 11, bits, NULL, 0), \ 567 MAX1363_CHAN_B(0, 1, d0m1, 12, bits, NULL, 0), \ 568 MAX1363_CHAN_B(2, 3, d2m3, 13, bits, NULL, 0), \ 569 MAX1363_CHAN_B(4, 5, d4m5, 14, bits, NULL, 0), \ 570 MAX1363_CHAN_B(6, 7, d6m7, 15, bits, NULL, 0), \ 571 MAX1363_CHAN_B(8, 9, d8m9, 16, bits, NULL, 0), \ 572 MAX1363_CHAN_B(10, 11, d10m11, 17, bits, NULL, 0), \ 573 MAX1363_CHAN_B(1, 0, d1m0, 18, bits, NULL, 0), \ 574 MAX1363_CHAN_B(3, 2, d3m2, 19, bits, NULL, 0), \ 575 MAX1363_CHAN_B(5, 4, d5m4, 20, bits, NULL, 0), \ 576 MAX1363_CHAN_B(7, 6, d7m6, 21, bits, NULL, 0), \ 577 MAX1363_CHAN_B(9, 8, d9m8, 22, bits, NULL, 0), \ 578 MAX1363_CHAN_B(11, 10, d11m10, 23, bits, NULL, 0), \ 579 IIO_CHAN_SOFT_TIMESTAMP(24) \ 580 } 581 static const struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8); 582 static const struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10); 583 static const struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12); 584 585 static const enum max1363_modes max11607_mode_list[] = { 586 _s0, _s1, _s2, _s3, 587 s0to1, s0to2, s0to3, 588 s2to3, 589 d0m1, d2m3, d1m0, d3m2, 590 d0m1to2m3, d1m0to3m2, 591 }; 592 593 static const enum max1363_modes max11608_mode_list[] = { 594 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, 595 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s0to7, 596 s6to7, 597 d0m1, d2m3, d4m5, d6m7, 598 d1m0, d3m2, d5m4, d7m6, 599 d0m1to2m3, d0m1to4m5, d0m1to6m7, 600 d1m0to3m2, d1m0to5m4, d1m0to7m6, 601 }; 602 603 #define MAX1363_8X_CHANS(bits) { \ 604 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \ 605 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \ 606 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \ 607 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \ 608 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \ 609 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \ 610 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \ 611 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \ 612 MAX1363_CHAN_B(0, 1, d0m1, 8, bits, NULL, 0), \ 613 MAX1363_CHAN_B(2, 3, d2m3, 9, bits, NULL, 0), \ 614 MAX1363_CHAN_B(4, 5, d4m5, 10, bits, NULL, 0), \ 615 MAX1363_CHAN_B(6, 7, d6m7, 11, bits, NULL, 0), \ 616 MAX1363_CHAN_B(1, 0, d1m0, 12, bits, NULL, 0), \ 617 MAX1363_CHAN_B(3, 2, d3m2, 13, bits, NULL, 0), \ 618 MAX1363_CHAN_B(5, 4, d5m4, 14, bits, NULL, 0), \ 619 MAX1363_CHAN_B(7, 6, d7m6, 15, bits, NULL, 0), \ 620 IIO_CHAN_SOFT_TIMESTAMP(16) \ 621 } 622 static const struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8); 623 static const struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10); 624 static const struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12); 625 626 static const enum max1363_modes max11644_mode_list[] = { 627 _s0, _s1, s0to1, d0m1, d1m0, 628 }; 629 630 #define MAX1363_2X_CHANS(bits) { \ 631 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \ 632 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \ 633 MAX1363_CHAN_B(0, 1, d0m1, 2, bits, NULL, 0), \ 634 MAX1363_CHAN_B(1, 0, d1m0, 3, bits, NULL, 0), \ 635 IIO_CHAN_SOFT_TIMESTAMP(4) \ 636 } 637 638 static const struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10); 639 static const struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12); 640 641 enum { max1361, 642 max1362, 643 max1363, 644 max1364, 645 max1036, 646 max1037, 647 max1038, 648 max1039, 649 max1136, 650 max1137, 651 max1138, 652 max1139, 653 max1236, 654 max1237, 655 max1238, 656 max1239, 657 max11600, 658 max11601, 659 max11602, 660 max11603, 661 max11604, 662 max11605, 663 max11606, 664 max11607, 665 max11608, 666 max11609, 667 max11610, 668 max11611, 669 max11612, 670 max11613, 671 max11614, 672 max11615, 673 max11616, 674 max11617, 675 max11644, 676 max11645, 677 max11646, 678 max11647 679 }; 680 681 static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600, 682 8300, 4200, 2000, 1000 }; 683 684 static ssize_t max1363_monitor_show_freq(struct device *dev, 685 struct device_attribute *attr, 686 char *buf) 687 { 688 struct max1363_state *st = iio_priv(dev_to_iio_dev(dev)); 689 return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]); 690 } 691 692 static ssize_t max1363_monitor_store_freq(struct device *dev, 693 struct device_attribute *attr, 694 const char *buf, 695 size_t len) 696 { 697 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 698 struct max1363_state *st = iio_priv(indio_dev); 699 int i, ret; 700 unsigned long val; 701 bool found = false; 702 703 ret = kstrtoul(buf, 10, &val); 704 if (ret) 705 return -EINVAL; 706 for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++) 707 if (val == max1363_monitor_speeds[i]) { 708 found = true; 709 break; 710 } 711 if (!found) 712 return -EINVAL; 713 714 scoped_guard(mutex, &st->lock) 715 st->monitor_speed = i; 716 717 return 0; 718 } 719 720 static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR, 721 max1363_monitor_show_freq, 722 max1363_monitor_store_freq); 723 724 static IIO_CONST_ATTR(sampling_frequency_available, 725 "133000 665000 33300 16600 8300 4200 2000 1000"); 726 727 static int max1363_read_thresh(struct iio_dev *indio_dev, 728 const struct iio_chan_spec *chan, enum iio_event_type type, 729 enum iio_event_direction dir, enum iio_event_info info, int *val, 730 int *val2) 731 { 732 struct max1363_state *st = iio_priv(indio_dev); 733 if (dir == IIO_EV_DIR_FALLING) 734 *val = st->thresh_low[chan->channel]; 735 else 736 *val = st->thresh_high[chan->channel]; 737 return IIO_VAL_INT; 738 } 739 740 static int max1363_write_thresh(struct iio_dev *indio_dev, 741 const struct iio_chan_spec *chan, enum iio_event_type type, 742 enum iio_event_direction dir, enum iio_event_info info, int val, 743 int val2) 744 { 745 struct max1363_state *st = iio_priv(indio_dev); 746 /* make it handle signed correctly as well */ 747 switch (st->chip_info->bits) { 748 case 10: 749 if (val > 0x3FF) 750 return -EINVAL; 751 break; 752 case 12: 753 if (val > 0xFFF) 754 return -EINVAL; 755 break; 756 } 757 758 switch (dir) { 759 case IIO_EV_DIR_FALLING: 760 st->thresh_low[chan->channel] = val; 761 break; 762 case IIO_EV_DIR_RISING: 763 st->thresh_high[chan->channel] = val; 764 break; 765 default: 766 return -EINVAL; 767 } 768 769 return 0; 770 } 771 772 static const u64 max1363_event_codes[] = { 773 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0, 774 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING), 775 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1, 776 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING), 777 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2, 778 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING), 779 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3, 780 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING), 781 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0, 782 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING), 783 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1, 784 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING), 785 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2, 786 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING), 787 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3, 788 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING), 789 }; 790 791 static irqreturn_t max1363_event_handler(int irq, void *private) 792 { 793 struct iio_dev *indio_dev = private; 794 struct max1363_state *st = iio_priv(indio_dev); 795 s64 timestamp = iio_get_time_ns(indio_dev); 796 unsigned long mask, loc; 797 u8 rx; 798 u8 tx[2] = { st->setupbyte, 799 MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 }; 800 801 st->recv(st->client, &rx, 1); 802 mask = rx; 803 for_each_set_bit(loc, &mask, 8) 804 iio_push_event(indio_dev, max1363_event_codes[loc], timestamp); 805 st->send(st->client, tx, 2); 806 807 return IRQ_HANDLED; 808 } 809 810 static int max1363_read_event_config(struct iio_dev *indio_dev, 811 const struct iio_chan_spec *chan, enum iio_event_type type, 812 enum iio_event_direction dir) 813 { 814 struct max1363_state *st = iio_priv(indio_dev); 815 int val; 816 int number = chan->channel; 817 818 guard(mutex)(&st->lock); 819 if (dir == IIO_EV_DIR_FALLING) 820 val = (1 << number) & st->mask_low; 821 else 822 val = (1 << number) & st->mask_high; 823 824 return val; 825 } 826 827 static int max1363_monitor_mode_update(struct max1363_state *st, int enabled) 828 { 829 int ret, i = 3, j; 830 unsigned long numelements; 831 int len; 832 const long *modemask; 833 834 if (!enabled) { 835 /* transition to buffered capture is not currently supported */ 836 st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP; 837 st->configbyte &= ~MAX1363_SCAN_MASK; 838 st->monitor_on = false; 839 return max1363_write_basic_config(st); 840 } 841 842 /* Ensure we are in the relevant mode */ 843 st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP; 844 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK 845 | MAX1363_SCAN_MASK 846 | MAX1363_SE_DE_MASK); 847 st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE; 848 if ((st->mask_low | st->mask_high) & 0x0F) { 849 st->configbyte |= max1363_mode_table[s0to3].conf; 850 modemask = max1363_mode_table[s0to3].modemask; 851 } else if ((st->mask_low | st->mask_high) & 0x30) { 852 st->configbyte |= max1363_mode_table[d0m1to2m3].conf; 853 modemask = max1363_mode_table[d0m1to2m3].modemask; 854 } else { 855 st->configbyte |= max1363_mode_table[d1m0to3m2].conf; 856 modemask = max1363_mode_table[d1m0to3m2].modemask; 857 } 858 numelements = bitmap_weight(modemask, MAX1363_MAX_CHANNELS); 859 len = 3 * numelements + 3; 860 u8 *tx_buf __free(kfree) = kmalloc(len, GFP_KERNEL); 861 if (!tx_buf) 862 return -ENOMEM; 863 864 tx_buf[0] = st->configbyte; 865 tx_buf[1] = st->setupbyte; 866 tx_buf[2] = (st->monitor_speed << 1); 867 868 /* 869 * So we need to do yet another bit of nefarious scan mode 870 * setup to match what we need. 871 */ 872 for (j = 0; j < 8; j++) 873 if (test_bit(j, modemask)) { 874 /* Establish the mode is in the scan */ 875 if (st->mask_low & (1 << j)) { 876 tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF; 877 tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0; 878 } else if (j < 4) { 879 tx_buf[i] = 0; 880 tx_buf[i + 1] = 0; 881 } else { 882 tx_buf[i] = 0x80; 883 tx_buf[i + 1] = 0; 884 } 885 if (st->mask_high & (1 << j)) { 886 tx_buf[i + 1] |= 887 (st->thresh_high[j] >> 8) & 0x0F; 888 tx_buf[i + 2] = st->thresh_high[j] & 0xFF; 889 } else if (j < 4) { 890 tx_buf[i + 1] |= 0x0F; 891 tx_buf[i + 2] = 0xFF; 892 } else { 893 tx_buf[i + 1] |= 0x07; 894 tx_buf[i + 2] = 0xFF; 895 } 896 i += 3; 897 } 898 899 900 ret = st->send(st->client, tx_buf, len); 901 if (ret < 0) 902 return ret; 903 if (ret != len) 904 return -EIO; 905 906 /* 907 * Now that we hopefully have sensible thresholds in place it is 908 * time to turn the interrupts on. 909 * It is unclear from the data sheet if this should be necessary 910 * (i.e. whether monitor mode setup is atomic) but it appears to 911 * be in practice. 912 */ 913 tx_buf[0] = st->setupbyte; 914 tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0; 915 ret = st->send(st->client, tx_buf, 2); 916 if (ret < 0) 917 return ret; 918 if (ret != 2) 919 return -EIO; 920 921 st->monitor_on = true; 922 923 return 0; 924 } 925 926 /* 927 * To keep this manageable we always use one of 3 scan modes. 928 * Scan 0...3, 0-1,2-3 and 1-0,3-2 929 */ 930 931 static inline int __max1363_check_event_mask(int thismask, int checkmask) 932 { 933 int ret = 0; 934 /* Is it unipolar */ 935 if (thismask < 4) { 936 if (checkmask & ~0x0F) { 937 ret = -EBUSY; 938 goto error_ret; 939 } 940 } else if (thismask < 6) { 941 if (checkmask & ~0x30) { 942 ret = -EBUSY; 943 goto error_ret; 944 } 945 } else if (checkmask & ~0xC0) 946 ret = -EBUSY; 947 error_ret: 948 return ret; 949 } 950 951 static int __max1363_write_event_config(struct max1363_state *st, 952 const struct iio_chan_spec *chan, 953 enum iio_event_direction dir, bool state) 954 { 955 int number = chan->channel; 956 u16 unifiedmask; 957 int ret; 958 959 guard(mutex)(&st->lock); 960 961 unifiedmask = st->mask_low | st->mask_high; 962 if (dir == IIO_EV_DIR_FALLING) { 963 964 if (state == 0) 965 st->mask_low &= ~(1 << number); 966 else { 967 ret = __max1363_check_event_mask((1 << number), 968 unifiedmask); 969 if (ret) 970 return ret; 971 st->mask_low |= (1 << number); 972 } 973 } else { 974 if (state == 0) 975 st->mask_high &= ~(1 << number); 976 else { 977 ret = __max1363_check_event_mask((1 << number), 978 unifiedmask); 979 if (ret) 980 return ret; 981 st->mask_high |= (1 << number); 982 } 983 } 984 985 return 0; 986 987 } 988 static int max1363_write_event_config(struct iio_dev *indio_dev, 989 const struct iio_chan_spec *chan, enum iio_event_type type, 990 enum iio_event_direction dir, bool state) 991 { 992 struct max1363_state *st = iio_priv(indio_dev); 993 int ret; 994 995 if (!iio_device_claim_direct(indio_dev)) 996 return -EBUSY; 997 998 ret = __max1363_write_event_config(st, chan, dir, state); 999 iio_device_release_direct(indio_dev); 1000 max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low)); 1001 1002 return ret; 1003 } 1004 1005 /* 1006 * As with scan_elements, only certain sets of these can 1007 * be combined. 1008 */ 1009 static struct attribute *max1363_event_attributes[] = { 1010 &iio_dev_attr_sampling_frequency.dev_attr.attr, 1011 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 1012 NULL, 1013 }; 1014 1015 static const struct attribute_group max1363_event_attribute_group = { 1016 .attrs = max1363_event_attributes, 1017 }; 1018 1019 static int max1363_update_scan_mode(struct iio_dev *indio_dev, 1020 const unsigned long *scan_mask) 1021 { 1022 struct max1363_state *st = iio_priv(indio_dev); 1023 1024 /* 1025 * Need to figure out the current mode based upon the requested 1026 * scan mask in iio_dev 1027 */ 1028 st->current_mode = max1363_match_mode(scan_mask, st->chip_info); 1029 if (!st->current_mode) 1030 return -EINVAL; 1031 max1363_set_scan_mode(st); 1032 return 0; 1033 } 1034 1035 static const struct iio_info max1238_info = { 1036 .read_raw = &max1363_read_raw, 1037 .update_scan_mode = &max1363_update_scan_mode, 1038 }; 1039 1040 static const struct iio_info max1363_info = { 1041 .read_event_value = &max1363_read_thresh, 1042 .write_event_value = &max1363_write_thresh, 1043 .read_event_config = &max1363_read_event_config, 1044 .write_event_config = &max1363_write_event_config, 1045 .read_raw = &max1363_read_raw, 1046 .update_scan_mode = &max1363_update_scan_mode, 1047 .event_attrs = &max1363_event_attribute_group, 1048 }; 1049 1050 /* max1363 and max1368 tested - rest from data sheet */ 1051 static const struct max1363_chip_info max1363_chip_info_tbl[] = { 1052 [max1361] = { 1053 .bits = 10, 1054 .int_vref_mv = 2048, 1055 .mode_list = max1363_mode_list, 1056 .num_modes = ARRAY_SIZE(max1363_mode_list), 1057 .default_mode = s0to3, 1058 .channels = max1361_channels, 1059 .num_channels = ARRAY_SIZE(max1361_channels), 1060 .info = &max1363_info, 1061 }, 1062 [max1362] = { 1063 .bits = 10, 1064 .int_vref_mv = 4096, 1065 .mode_list = max1363_mode_list, 1066 .num_modes = ARRAY_SIZE(max1363_mode_list), 1067 .default_mode = s0to3, 1068 .channels = max1361_channels, 1069 .num_channels = ARRAY_SIZE(max1361_channels), 1070 .info = &max1363_info, 1071 }, 1072 [max1363] = { 1073 .bits = 12, 1074 .int_vref_mv = 2048, 1075 .mode_list = max1363_mode_list, 1076 .num_modes = ARRAY_SIZE(max1363_mode_list), 1077 .default_mode = s0to3, 1078 .channels = max1363_channels, 1079 .num_channels = ARRAY_SIZE(max1363_channels), 1080 .info = &max1363_info, 1081 }, 1082 [max1364] = { 1083 .bits = 12, 1084 .int_vref_mv = 4096, 1085 .mode_list = max1363_mode_list, 1086 .num_modes = ARRAY_SIZE(max1363_mode_list), 1087 .default_mode = s0to3, 1088 .channels = max1363_channels, 1089 .num_channels = ARRAY_SIZE(max1363_channels), 1090 .info = &max1363_info, 1091 }, 1092 [max1036] = { 1093 .bits = 8, 1094 .int_vref_mv = 4096, 1095 .mode_list = max1236_mode_list, 1096 .num_modes = ARRAY_SIZE(max1236_mode_list), 1097 .default_mode = s0to3, 1098 .info = &max1238_info, 1099 .channels = max1036_channels, 1100 .num_channels = ARRAY_SIZE(max1036_channels), 1101 }, 1102 [max1037] = { 1103 .bits = 8, 1104 .int_vref_mv = 2048, 1105 .mode_list = max1236_mode_list, 1106 .num_modes = ARRAY_SIZE(max1236_mode_list), 1107 .default_mode = s0to3, 1108 .info = &max1238_info, 1109 .channels = max1036_channels, 1110 .num_channels = ARRAY_SIZE(max1036_channels), 1111 }, 1112 [max1038] = { 1113 .bits = 8, 1114 .int_vref_mv = 4096, 1115 .mode_list = max1238_mode_list, 1116 .num_modes = ARRAY_SIZE(max1238_mode_list), 1117 .default_mode = s0to11, 1118 .info = &max1238_info, 1119 .channels = max1038_channels, 1120 .num_channels = ARRAY_SIZE(max1038_channels), 1121 }, 1122 [max1039] = { 1123 .bits = 8, 1124 .int_vref_mv = 2048, 1125 .mode_list = max1238_mode_list, 1126 .num_modes = ARRAY_SIZE(max1238_mode_list), 1127 .default_mode = s0to11, 1128 .info = &max1238_info, 1129 .channels = max1038_channels, 1130 .num_channels = ARRAY_SIZE(max1038_channels), 1131 }, 1132 [max1136] = { 1133 .bits = 10, 1134 .int_vref_mv = 4096, 1135 .mode_list = max1236_mode_list, 1136 .num_modes = ARRAY_SIZE(max1236_mode_list), 1137 .default_mode = s0to3, 1138 .info = &max1238_info, 1139 .channels = max1136_channels, 1140 .num_channels = ARRAY_SIZE(max1136_channels), 1141 }, 1142 [max1137] = { 1143 .bits = 10, 1144 .int_vref_mv = 2048, 1145 .mode_list = max1236_mode_list, 1146 .num_modes = ARRAY_SIZE(max1236_mode_list), 1147 .default_mode = s0to3, 1148 .info = &max1238_info, 1149 .channels = max1136_channels, 1150 .num_channels = ARRAY_SIZE(max1136_channels), 1151 }, 1152 [max1138] = { 1153 .bits = 10, 1154 .int_vref_mv = 4096, 1155 .mode_list = max1238_mode_list, 1156 .num_modes = ARRAY_SIZE(max1238_mode_list), 1157 .default_mode = s0to11, 1158 .info = &max1238_info, 1159 .channels = max1138_channels, 1160 .num_channels = ARRAY_SIZE(max1138_channels), 1161 }, 1162 [max1139] = { 1163 .bits = 10, 1164 .int_vref_mv = 2048, 1165 .mode_list = max1238_mode_list, 1166 .num_modes = ARRAY_SIZE(max1238_mode_list), 1167 .default_mode = s0to11, 1168 .info = &max1238_info, 1169 .channels = max1138_channels, 1170 .num_channels = ARRAY_SIZE(max1138_channels), 1171 }, 1172 [max1236] = { 1173 .bits = 12, 1174 .int_vref_mv = 4096, 1175 .mode_list = max1236_mode_list, 1176 .num_modes = ARRAY_SIZE(max1236_mode_list), 1177 .default_mode = s0to3, 1178 .info = &max1238_info, 1179 .channels = max1236_channels, 1180 .num_channels = ARRAY_SIZE(max1236_channels), 1181 }, 1182 [max1237] = { 1183 .bits = 12, 1184 .int_vref_mv = 2048, 1185 .mode_list = max1236_mode_list, 1186 .num_modes = ARRAY_SIZE(max1236_mode_list), 1187 .default_mode = s0to3, 1188 .info = &max1238_info, 1189 .channels = max1236_channels, 1190 .num_channels = ARRAY_SIZE(max1236_channels), 1191 }, 1192 [max1238] = { 1193 .bits = 12, 1194 .int_vref_mv = 4096, 1195 .mode_list = max1238_mode_list, 1196 .num_modes = ARRAY_SIZE(max1238_mode_list), 1197 .default_mode = s0to11, 1198 .info = &max1238_info, 1199 .channels = max1238_channels, 1200 .num_channels = ARRAY_SIZE(max1238_channels), 1201 }, 1202 [max1239] = { 1203 .bits = 12, 1204 .int_vref_mv = 2048, 1205 .mode_list = max1238_mode_list, 1206 .num_modes = ARRAY_SIZE(max1238_mode_list), 1207 .default_mode = s0to11, 1208 .info = &max1238_info, 1209 .channels = max1238_channels, 1210 .num_channels = ARRAY_SIZE(max1238_channels), 1211 }, 1212 [max11600] = { 1213 .bits = 8, 1214 .int_vref_mv = 4096, 1215 .mode_list = max11607_mode_list, 1216 .num_modes = ARRAY_SIZE(max11607_mode_list), 1217 .default_mode = s0to3, 1218 .info = &max1238_info, 1219 .channels = max1036_channels, 1220 .num_channels = ARRAY_SIZE(max1036_channels), 1221 }, 1222 [max11601] = { 1223 .bits = 8, 1224 .int_vref_mv = 2048, 1225 .mode_list = max11607_mode_list, 1226 .num_modes = ARRAY_SIZE(max11607_mode_list), 1227 .default_mode = s0to3, 1228 .info = &max1238_info, 1229 .channels = max1036_channels, 1230 .num_channels = ARRAY_SIZE(max1036_channels), 1231 }, 1232 [max11602] = { 1233 .bits = 8, 1234 .int_vref_mv = 4096, 1235 .mode_list = max11608_mode_list, 1236 .num_modes = ARRAY_SIZE(max11608_mode_list), 1237 .default_mode = s0to7, 1238 .info = &max1238_info, 1239 .channels = max11602_channels, 1240 .num_channels = ARRAY_SIZE(max11602_channels), 1241 }, 1242 [max11603] = { 1243 .bits = 8, 1244 .int_vref_mv = 2048, 1245 .mode_list = max11608_mode_list, 1246 .num_modes = ARRAY_SIZE(max11608_mode_list), 1247 .default_mode = s0to7, 1248 .info = &max1238_info, 1249 .channels = max11602_channels, 1250 .num_channels = ARRAY_SIZE(max11602_channels), 1251 }, 1252 [max11604] = { 1253 .bits = 8, 1254 .int_vref_mv = 4096, 1255 .mode_list = max1238_mode_list, 1256 .num_modes = ARRAY_SIZE(max1238_mode_list), 1257 .default_mode = s0to11, 1258 .info = &max1238_info, 1259 .channels = max1038_channels, 1260 .num_channels = ARRAY_SIZE(max1038_channels), 1261 }, 1262 [max11605] = { 1263 .bits = 8, 1264 .int_vref_mv = 2048, 1265 .mode_list = max1238_mode_list, 1266 .num_modes = ARRAY_SIZE(max1238_mode_list), 1267 .default_mode = s0to11, 1268 .info = &max1238_info, 1269 .channels = max1038_channels, 1270 .num_channels = ARRAY_SIZE(max1038_channels), 1271 }, 1272 [max11606] = { 1273 .bits = 10, 1274 .int_vref_mv = 4096, 1275 .mode_list = max11607_mode_list, 1276 .num_modes = ARRAY_SIZE(max11607_mode_list), 1277 .default_mode = s0to3, 1278 .info = &max1238_info, 1279 .channels = max1136_channels, 1280 .num_channels = ARRAY_SIZE(max1136_channels), 1281 }, 1282 [max11607] = { 1283 .bits = 10, 1284 .int_vref_mv = 2048, 1285 .mode_list = max11607_mode_list, 1286 .num_modes = ARRAY_SIZE(max11607_mode_list), 1287 .default_mode = s0to3, 1288 .info = &max1238_info, 1289 .channels = max1136_channels, 1290 .num_channels = ARRAY_SIZE(max1136_channels), 1291 }, 1292 [max11608] = { 1293 .bits = 10, 1294 .int_vref_mv = 4096, 1295 .mode_list = max11608_mode_list, 1296 .num_modes = ARRAY_SIZE(max11608_mode_list), 1297 .default_mode = s0to7, 1298 .info = &max1238_info, 1299 .channels = max11608_channels, 1300 .num_channels = ARRAY_SIZE(max11608_channels), 1301 }, 1302 [max11609] = { 1303 .bits = 10, 1304 .int_vref_mv = 2048, 1305 .mode_list = max11608_mode_list, 1306 .num_modes = ARRAY_SIZE(max11608_mode_list), 1307 .default_mode = s0to7, 1308 .info = &max1238_info, 1309 .channels = max11608_channels, 1310 .num_channels = ARRAY_SIZE(max11608_channels), 1311 }, 1312 [max11610] = { 1313 .bits = 10, 1314 .int_vref_mv = 4096, 1315 .mode_list = max1238_mode_list, 1316 .num_modes = ARRAY_SIZE(max1238_mode_list), 1317 .default_mode = s0to11, 1318 .info = &max1238_info, 1319 .channels = max1138_channels, 1320 .num_channels = ARRAY_SIZE(max1138_channels), 1321 }, 1322 [max11611] = { 1323 .bits = 10, 1324 .int_vref_mv = 2048, 1325 .mode_list = max1238_mode_list, 1326 .num_modes = ARRAY_SIZE(max1238_mode_list), 1327 .default_mode = s0to11, 1328 .info = &max1238_info, 1329 .channels = max1138_channels, 1330 .num_channels = ARRAY_SIZE(max1138_channels), 1331 }, 1332 [max11612] = { 1333 .bits = 12, 1334 .int_vref_mv = 4096, 1335 .mode_list = max11607_mode_list, 1336 .num_modes = ARRAY_SIZE(max11607_mode_list), 1337 .default_mode = s0to3, 1338 .info = &max1238_info, 1339 .channels = max1363_channels, 1340 .num_channels = ARRAY_SIZE(max1363_channels), 1341 }, 1342 [max11613] = { 1343 .bits = 12, 1344 .int_vref_mv = 2048, 1345 .mode_list = max11607_mode_list, 1346 .num_modes = ARRAY_SIZE(max11607_mode_list), 1347 .default_mode = s0to3, 1348 .info = &max1238_info, 1349 .channels = max1363_channels, 1350 .num_channels = ARRAY_SIZE(max1363_channels), 1351 }, 1352 [max11614] = { 1353 .bits = 12, 1354 .int_vref_mv = 4096, 1355 .mode_list = max11608_mode_list, 1356 .num_modes = ARRAY_SIZE(max11608_mode_list), 1357 .default_mode = s0to7, 1358 .info = &max1238_info, 1359 .channels = max11614_channels, 1360 .num_channels = ARRAY_SIZE(max11614_channels), 1361 }, 1362 [max11615] = { 1363 .bits = 12, 1364 .int_vref_mv = 2048, 1365 .mode_list = max11608_mode_list, 1366 .num_modes = ARRAY_SIZE(max11608_mode_list), 1367 .default_mode = s0to7, 1368 .info = &max1238_info, 1369 .channels = max11614_channels, 1370 .num_channels = ARRAY_SIZE(max11614_channels), 1371 }, 1372 [max11616] = { 1373 .bits = 12, 1374 .int_vref_mv = 4096, 1375 .mode_list = max1238_mode_list, 1376 .num_modes = ARRAY_SIZE(max1238_mode_list), 1377 .default_mode = s0to11, 1378 .info = &max1238_info, 1379 .channels = max1238_channels, 1380 .num_channels = ARRAY_SIZE(max1238_channels), 1381 }, 1382 [max11617] = { 1383 .bits = 12, 1384 .int_vref_mv = 2048, 1385 .mode_list = max1238_mode_list, 1386 .num_modes = ARRAY_SIZE(max1238_mode_list), 1387 .default_mode = s0to11, 1388 .info = &max1238_info, 1389 .channels = max1238_channels, 1390 .num_channels = ARRAY_SIZE(max1238_channels), 1391 }, 1392 [max11644] = { 1393 .bits = 12, 1394 .int_vref_mv = 4096, 1395 .mode_list = max11644_mode_list, 1396 .num_modes = ARRAY_SIZE(max11644_mode_list), 1397 .default_mode = s0to1, 1398 .info = &max1238_info, 1399 .channels = max11644_channels, 1400 .num_channels = ARRAY_SIZE(max11644_channels), 1401 }, 1402 [max11645] = { 1403 .bits = 12, 1404 .int_vref_mv = 2048, 1405 .mode_list = max11644_mode_list, 1406 .num_modes = ARRAY_SIZE(max11644_mode_list), 1407 .default_mode = s0to1, 1408 .info = &max1238_info, 1409 .channels = max11644_channels, 1410 .num_channels = ARRAY_SIZE(max11644_channels), 1411 }, 1412 [max11646] = { 1413 .bits = 10, 1414 .int_vref_mv = 4096, 1415 .mode_list = max11644_mode_list, 1416 .num_modes = ARRAY_SIZE(max11644_mode_list), 1417 .default_mode = s0to1, 1418 .info = &max1238_info, 1419 .channels = max11646_channels, 1420 .num_channels = ARRAY_SIZE(max11646_channels), 1421 }, 1422 [max11647] = { 1423 .bits = 10, 1424 .int_vref_mv = 2048, 1425 .mode_list = max11644_mode_list, 1426 .num_modes = ARRAY_SIZE(max11644_mode_list), 1427 .default_mode = s0to1, 1428 .info = &max1238_info, 1429 .channels = max11646_channels, 1430 .num_channels = ARRAY_SIZE(max11646_channels), 1431 }, 1432 }; 1433 1434 static int max1363_initial_setup(struct max1363_state *st) 1435 { 1436 st->setupbyte = MAX1363_SETUP_INT_CLOCK 1437 | MAX1363_SETUP_UNIPOLAR 1438 | MAX1363_SETUP_NORESET; 1439 1440 if (st->vref) 1441 st->setupbyte |= MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF; 1442 else 1443 st->setupbyte |= MAX1363_SETUP_POWER_UP_INT_REF 1444 | MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT; 1445 1446 /* Set scan mode writes the config anyway so wait until then */ 1447 st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte); 1448 st->current_mode = &max1363_mode_table[st->chip_info->default_mode]; 1449 st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte); 1450 1451 return max1363_set_scan_mode(st); 1452 } 1453 1454 static int max1363_alloc_scan_masks(struct iio_dev *indio_dev) 1455 { 1456 struct max1363_state *st = iio_priv(indio_dev); 1457 unsigned long *masks; 1458 int i; 1459 1460 masks = devm_kzalloc(&indio_dev->dev, 1461 array3_size(BITS_TO_LONGS(MAX1363_MAX_CHANNELS), 1462 sizeof(long), 1463 st->chip_info->num_modes + 1), 1464 GFP_KERNEL); 1465 if (!masks) 1466 return -ENOMEM; 1467 1468 for (i = 0; i < st->chip_info->num_modes; i++) 1469 bitmap_copy(masks + BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*i, 1470 max1363_mode_table[st->chip_info->mode_list[i]] 1471 .modemask, MAX1363_MAX_CHANNELS); 1472 1473 indio_dev->available_scan_masks = masks; 1474 1475 return 0; 1476 } 1477 1478 static irqreturn_t max1363_trigger_handler(int irq, void *p) 1479 { 1480 struct iio_poll_func *pf = p; 1481 struct iio_dev *indio_dev = pf->indio_dev; 1482 struct max1363_state *st = iio_priv(indio_dev); 1483 int b_sent; 1484 unsigned long numvals = bitmap_weight(st->current_mode->modemask, 1485 MAX1363_MAX_CHANNELS); 1486 1487 /* Monitor mode prevents reading. Whilst not currently implemented 1488 * might as well have this test in here in the meantime as it does 1489 * no harm. 1490 */ 1491 if (numvals == 0) 1492 goto done; 1493 1494 if (st->chip_info->bits != 8) 1495 b_sent = st->recv(st->client, st->data.buf, numvals * 2); 1496 else 1497 b_sent = st->recv(st->client, st->data.buf, numvals); 1498 if (b_sent < 0) 1499 goto done; 1500 1501 iio_push_to_buffers_with_ts(indio_dev, &st->data, sizeof(st->data), 1502 iio_get_time_ns(indio_dev)); 1503 1504 done: 1505 iio_trigger_notify_done(indio_dev->trig); 1506 1507 return IRQ_HANDLED; 1508 } 1509 1510 #define MAX1363_COMPATIBLE(of_compatible, cfg) { \ 1511 .compatible = of_compatible, \ 1512 .data = &max1363_chip_info_tbl[cfg], \ 1513 } 1514 1515 static const struct of_device_id max1363_of_match[] = { 1516 MAX1363_COMPATIBLE("maxim,max1361", max1361), 1517 MAX1363_COMPATIBLE("maxim,max1362", max1362), 1518 MAX1363_COMPATIBLE("maxim,max1363", max1363), 1519 MAX1363_COMPATIBLE("maxim,max1364", max1364), 1520 MAX1363_COMPATIBLE("maxim,max1036", max1036), 1521 MAX1363_COMPATIBLE("maxim,max1037", max1037), 1522 MAX1363_COMPATIBLE("maxim,max1038", max1038), 1523 MAX1363_COMPATIBLE("maxim,max1039", max1039), 1524 MAX1363_COMPATIBLE("maxim,max1136", max1136), 1525 MAX1363_COMPATIBLE("maxim,max1137", max1137), 1526 MAX1363_COMPATIBLE("maxim,max1138", max1138), 1527 MAX1363_COMPATIBLE("maxim,max1139", max1139), 1528 MAX1363_COMPATIBLE("maxim,max1236", max1236), 1529 MAX1363_COMPATIBLE("maxim,max1237", max1237), 1530 MAX1363_COMPATIBLE("maxim,max1238", max1238), 1531 MAX1363_COMPATIBLE("maxim,max1239", max1239), 1532 MAX1363_COMPATIBLE("maxim,max11600", max11600), 1533 MAX1363_COMPATIBLE("maxim,max11601", max11601), 1534 MAX1363_COMPATIBLE("maxim,max11602", max11602), 1535 MAX1363_COMPATIBLE("maxim,max11603", max11603), 1536 MAX1363_COMPATIBLE("maxim,max11604", max11604), 1537 MAX1363_COMPATIBLE("maxim,max11605", max11605), 1538 MAX1363_COMPATIBLE("maxim,max11606", max11606), 1539 MAX1363_COMPATIBLE("maxim,max11607", max11607), 1540 MAX1363_COMPATIBLE("maxim,max11608", max11608), 1541 MAX1363_COMPATIBLE("maxim,max11609", max11609), 1542 MAX1363_COMPATIBLE("maxim,max11610", max11610), 1543 MAX1363_COMPATIBLE("maxim,max11611", max11611), 1544 MAX1363_COMPATIBLE("maxim,max11612", max11612), 1545 MAX1363_COMPATIBLE("maxim,max11613", max11613), 1546 MAX1363_COMPATIBLE("maxim,max11614", max11614), 1547 MAX1363_COMPATIBLE("maxim,max11615", max11615), 1548 MAX1363_COMPATIBLE("maxim,max11616", max11616), 1549 MAX1363_COMPATIBLE("maxim,max11617", max11617), 1550 MAX1363_COMPATIBLE("maxim,max11644", max11644), 1551 MAX1363_COMPATIBLE("maxim,max11645", max11645), 1552 MAX1363_COMPATIBLE("maxim,max11646", max11646), 1553 MAX1363_COMPATIBLE("maxim,max11647", max11647), 1554 { } 1555 }; 1556 MODULE_DEVICE_TABLE(of, max1363_of_match); 1557 1558 static int max1363_probe(struct i2c_client *client) 1559 { 1560 const struct i2c_device_id *id = i2c_client_get_device_id(client); 1561 int ret; 1562 struct max1363_state *st; 1563 struct iio_dev *indio_dev; 1564 1565 indio_dev = devm_iio_device_alloc(&client->dev, 1566 sizeof(struct max1363_state)); 1567 if (!indio_dev) 1568 return -ENOMEM; 1569 1570 st = iio_priv(indio_dev); 1571 1572 mutex_init(&st->lock); 1573 ret = devm_regulator_get_enable(&client->dev, "vcc"); 1574 if (ret) 1575 return ret; 1576 1577 st->chip_info = i2c_get_match_data(client); 1578 st->client = client; 1579 1580 ret = devm_regulator_get_enable_read_voltage(&client->dev, "vref"); 1581 if (ret < 0 && ret != -ENODEV) 1582 return ret; 1583 1584 1585 st->vref_uv = ret == -ENODEV ? st->chip_info->int_vref_mv * 1000 : ret; 1586 1587 if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1588 st->send = i2c_master_send; 1589 st->recv = i2c_master_recv; 1590 } else if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE) 1591 && st->chip_info->bits == 8) { 1592 st->send = max1363_smbus_send; 1593 st->recv = max1363_smbus_recv; 1594 } else { 1595 return -EOPNOTSUPP; 1596 } 1597 1598 ret = max1363_alloc_scan_masks(indio_dev); 1599 if (ret) 1600 return ret; 1601 1602 indio_dev->name = id->name; 1603 indio_dev->channels = st->chip_info->channels; 1604 indio_dev->num_channels = st->chip_info->num_channels; 1605 indio_dev->info = st->chip_info->info; 1606 indio_dev->modes = INDIO_DIRECT_MODE; 1607 ret = max1363_initial_setup(st); 1608 if (ret < 0) 1609 return ret; 1610 1611 ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL, 1612 &max1363_trigger_handler, NULL); 1613 if (ret) 1614 return ret; 1615 1616 if (client->irq) { 1617 ret = devm_request_threaded_irq(&client->dev, st->client->irq, 1618 NULL, 1619 &max1363_event_handler, 1620 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 1621 "max1363_event", 1622 indio_dev); 1623 1624 if (ret) 1625 return ret; 1626 } 1627 1628 return devm_iio_device_register(&client->dev, indio_dev); 1629 } 1630 1631 #define MAX1363_ID_TABLE(_name, cfg) { \ 1632 .name = _name, \ 1633 .driver_data = (kernel_ulong_t)&max1363_chip_info_tbl[cfg], \ 1634 } 1635 1636 static const struct i2c_device_id max1363_id[] = { 1637 MAX1363_ID_TABLE("max1361", max1361), 1638 MAX1363_ID_TABLE("max1362", max1362), 1639 MAX1363_ID_TABLE("max1363", max1363), 1640 MAX1363_ID_TABLE("max1364", max1364), 1641 MAX1363_ID_TABLE("max1036", max1036), 1642 MAX1363_ID_TABLE("max1037", max1037), 1643 MAX1363_ID_TABLE("max1038", max1038), 1644 MAX1363_ID_TABLE("max1039", max1039), 1645 MAX1363_ID_TABLE("max1136", max1136), 1646 MAX1363_ID_TABLE("max1137", max1137), 1647 MAX1363_ID_TABLE("max1138", max1138), 1648 MAX1363_ID_TABLE("max1139", max1139), 1649 MAX1363_ID_TABLE("max1236", max1236), 1650 MAX1363_ID_TABLE("max1237", max1237), 1651 MAX1363_ID_TABLE("max1238", max1238), 1652 MAX1363_ID_TABLE("max1239", max1239), 1653 MAX1363_ID_TABLE("max11600", max11600), 1654 MAX1363_ID_TABLE("max11601", max11601), 1655 MAX1363_ID_TABLE("max11602", max11602), 1656 MAX1363_ID_TABLE("max11603", max11603), 1657 MAX1363_ID_TABLE("max11604", max11604), 1658 MAX1363_ID_TABLE("max11605", max11605), 1659 MAX1363_ID_TABLE("max11606", max11606), 1660 MAX1363_ID_TABLE("max11607", max11607), 1661 MAX1363_ID_TABLE("max11608", max11608), 1662 MAX1363_ID_TABLE("max11609", max11609), 1663 MAX1363_ID_TABLE("max11610", max11610), 1664 MAX1363_ID_TABLE("max11611", max11611), 1665 MAX1363_ID_TABLE("max11612", max11612), 1666 MAX1363_ID_TABLE("max11613", max11613), 1667 MAX1363_ID_TABLE("max11614", max11614), 1668 MAX1363_ID_TABLE("max11615", max11615), 1669 MAX1363_ID_TABLE("max11616", max11616), 1670 MAX1363_ID_TABLE("max11617", max11617), 1671 MAX1363_ID_TABLE("max11644", max11644), 1672 MAX1363_ID_TABLE("max11645", max11645), 1673 MAX1363_ID_TABLE("max11646", max11646), 1674 MAX1363_ID_TABLE("max11647", max11647), 1675 { } 1676 }; 1677 1678 MODULE_DEVICE_TABLE(i2c, max1363_id); 1679 1680 static struct i2c_driver max1363_driver = { 1681 .driver = { 1682 .name = "max1363", 1683 .of_match_table = max1363_of_match, 1684 }, 1685 .probe = max1363_probe, 1686 .id_table = max1363_id, 1687 }; 1688 module_i2c_driver(max1363_driver); 1689 1690 MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>"); 1691 MODULE_DESCRIPTION("Maxim 1363 ADC"); 1692 MODULE_LICENSE("GPL v2"); 1693