1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Atmel ADC driver for SAMA5D2 devices and compatible. 4 * 5 * Copyright (C) 2015 Atmel, 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7 * 2021 Microchip Technology, Inc. and its subsidiaries 8 * 2021 Eugen Hristev <eugen.hristev@microchip.com> 9 */ 10 11 #include <linux/bitops.h> 12 #include <linux/cleanup.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/dmaengine.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/platform_device.h> 22 #include <linux/property.h> 23 #include <linux/sched.h> 24 #include <linux/units.h> 25 #include <linux/wait.h> 26 #include <linux/iio/iio.h> 27 #include <linux/iio/sysfs.h> 28 #include <linux/iio/buffer.h> 29 #include <linux/iio/trigger.h> 30 #include <linux/iio/trigger_consumer.h> 31 #include <linux/iio/triggered_buffer.h> 32 #include <linux/nvmem-consumer.h> 33 #include <linux/pinctrl/consumer.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/regulator/consumer.h> 36 37 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h> 38 39 struct at91_adc_reg_layout { 40 /* Control Register */ 41 u16 CR; 42 /* Software Reset */ 43 #define AT91_SAMA5D2_CR_SWRST BIT(0) 44 /* Start Conversion */ 45 #define AT91_SAMA5D2_CR_START BIT(1) 46 /* Touchscreen Calibration */ 47 #define AT91_SAMA5D2_CR_TSCALIB BIT(2) 48 /* Comparison Restart */ 49 #define AT91_SAMA5D2_CR_CMPRST BIT(4) 50 51 /* Mode Register */ 52 u16 MR; 53 /* Trigger Selection */ 54 #define AT91_SAMA5D2_MR_TRGSEL(v) ((v) << 1) 55 /* ADTRG */ 56 #define AT91_SAMA5D2_MR_TRGSEL_TRIG0 0 57 /* TIOA0 */ 58 #define AT91_SAMA5D2_MR_TRGSEL_TRIG1 1 59 /* TIOA1 */ 60 #define AT91_SAMA5D2_MR_TRGSEL_TRIG2 2 61 /* TIOA2 */ 62 #define AT91_SAMA5D2_MR_TRGSEL_TRIG3 3 63 /* PWM event line 0 */ 64 #define AT91_SAMA5D2_MR_TRGSEL_TRIG4 4 65 /* PWM event line 1 */ 66 #define AT91_SAMA5D2_MR_TRGSEL_TRIG5 5 67 /* TIOA3 */ 68 #define AT91_SAMA5D2_MR_TRGSEL_TRIG6 6 69 /* RTCOUT0 */ 70 #define AT91_SAMA5D2_MR_TRGSEL_TRIG7 7 71 /* Sleep Mode */ 72 #define AT91_SAMA5D2_MR_SLEEP BIT(5) 73 /* Fast Wake Up */ 74 #define AT91_SAMA5D2_MR_FWUP BIT(6) 75 /* Prescaler Rate Selection */ 76 #define AT91_SAMA5D2_MR_PRESCAL(v) ((v) << AT91_SAMA5D2_MR_PRESCAL_OFFSET) 77 #define AT91_SAMA5D2_MR_PRESCAL_OFFSET 8 78 #define AT91_SAMA5D2_MR_PRESCAL_MAX 0xff 79 #define AT91_SAMA5D2_MR_PRESCAL_MASK GENMASK(15, 8) 80 /* Startup Time */ 81 #define AT91_SAMA5D2_MR_STARTUP(v) ((v) << 16) 82 #define AT91_SAMA5D2_MR_STARTUP_MASK GENMASK(19, 16) 83 /* Minimum startup time for temperature sensor */ 84 #define AT91_SAMA5D2_MR_STARTUP_TS_MIN (50) 85 /* Analog Change */ 86 #define AT91_SAMA5D2_MR_ANACH BIT(23) 87 /* Tracking Time */ 88 #define AT91_SAMA5D2_MR_TRACKTIM(v) ((v) << 24) 89 #define AT91_SAMA5D2_MR_TRACKTIM_TS 6 90 #define AT91_SAMA5D2_MR_TRACKTIM_MAX 0xf 91 /* Transfer Time */ 92 #define AT91_SAMA5D2_MR_TRANSFER(v) ((v) << 28) 93 #define AT91_SAMA5D2_MR_TRANSFER_MAX 0x3 94 /* Use Sequence Enable */ 95 #define AT91_SAMA5D2_MR_USEQ BIT(31) 96 97 /* Channel Sequence Register 1 */ 98 u16 SEQR1; 99 /* Channel Sequence Register 2 */ 100 u16 SEQR2; 101 /* Channel Enable Register */ 102 u16 CHER; 103 /* Channel Disable Register */ 104 u16 CHDR; 105 /* Channel Status Register */ 106 u16 CHSR; 107 /* Last Converted Data Register */ 108 u16 LCDR; 109 /* Interrupt Enable Register */ 110 u16 IER; 111 /* Interrupt Enable Register - TS X measurement ready */ 112 #define AT91_SAMA5D2_IER_XRDY BIT(20) 113 /* Interrupt Enable Register - TS Y measurement ready */ 114 #define AT91_SAMA5D2_IER_YRDY BIT(21) 115 /* Interrupt Enable Register - TS pressure measurement ready */ 116 #define AT91_SAMA5D2_IER_PRDY BIT(22) 117 /* Interrupt Enable Register - Data ready */ 118 #define AT91_SAMA5D2_IER_DRDY BIT(24) 119 /* Interrupt Enable Register - general overrun error */ 120 #define AT91_SAMA5D2_IER_GOVRE BIT(25) 121 /* Interrupt Enable Register - Pen detect */ 122 #define AT91_SAMA5D2_IER_PEN BIT(29) 123 /* Interrupt Enable Register - No pen detect */ 124 #define AT91_SAMA5D2_IER_NOPEN BIT(30) 125 126 /* Interrupt Disable Register */ 127 u16 IDR; 128 /* Interrupt Mask Register */ 129 u16 IMR; 130 /* Interrupt Status Register */ 131 u16 ISR; 132 /* End of Conversion Interrupt Enable Register */ 133 u16 EOC_IER; 134 /* End of Conversion Interrupt Disable Register */ 135 u16 EOC_IDR; 136 /* End of Conversion Interrupt Mask Register */ 137 u16 EOC_IMR; 138 /* End of Conversion Interrupt Status Register */ 139 u16 EOC_ISR; 140 /* Interrupt Status Register - Pen touching sense status */ 141 #define AT91_SAMA5D2_ISR_PENS BIT(31) 142 /* Last Channel Trigger Mode Register */ 143 u16 LCTMR; 144 /* Last Channel Compare Window Register */ 145 u16 LCCWR; 146 /* Overrun Status Register */ 147 u16 OVER; 148 /* Extended Mode Register */ 149 u16 EMR; 150 /* Extended Mode Register - Oversampling rate */ 151 #define AT91_SAMA5D2_EMR_OSR(V, M) (((V) << 16) & (M)) 152 #define AT91_SAMA5D2_EMR_OSR_1SAMPLES 0 153 #define AT91_SAMA5D2_EMR_OSR_4SAMPLES 1 154 #define AT91_SAMA5D2_EMR_OSR_16SAMPLES 2 155 #define AT91_SAMA5D2_EMR_OSR_64SAMPLES 3 156 #define AT91_SAMA5D2_EMR_OSR_256SAMPLES 4 157 158 /* Extended Mode Register - TRACKX */ 159 #define AT91_SAMA5D2_TRACKX_MASK GENMASK(23, 22) 160 #define AT91_SAMA5D2_TRACKX(x) (((x) << 22) & \ 161 AT91_SAMA5D2_TRACKX_MASK) 162 /* TRACKX for temperature sensor. */ 163 #define AT91_SAMA5D2_TRACKX_TS (1) 164 165 /* Extended Mode Register - Averaging on single trigger event */ 166 #define AT91_SAMA5D2_EMR_ASTE(V) ((V) << 20) 167 168 /* Compare Window Register */ 169 u16 CWR; 170 /* Channel Gain Register */ 171 u16 CGR; 172 /* Channel Offset Register */ 173 u16 COR; 174 /* Channel Offset Register differential offset - constant, not a register */ 175 u16 COR_diff_offset; 176 /* Analog Control Register */ 177 u16 ACR; 178 /* Analog Control Register - Pen detect sensitivity mask */ 179 #define AT91_SAMA5D2_ACR_PENDETSENS_MASK GENMASK(1, 0) 180 /* Analog Control Register - Source last channel */ 181 #define AT91_SAMA5D2_ACR_SRCLCH BIT(16) 182 183 /* Touchscreen Mode Register */ 184 u16 TSMR; 185 /* Touchscreen Mode Register - No touch mode */ 186 #define AT91_SAMA5D2_TSMR_TSMODE_NONE 0 187 /* Touchscreen Mode Register - 4 wire screen, no pressure measurement */ 188 #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_NO_PRESS 1 189 /* Touchscreen Mode Register - 4 wire screen, pressure measurement */ 190 #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS 2 191 /* Touchscreen Mode Register - 5 wire screen */ 192 #define AT91_SAMA5D2_TSMR_TSMODE_5WIRE 3 193 /* Touchscreen Mode Register - Average samples mask */ 194 #define AT91_SAMA5D2_TSMR_TSAV_MASK GENMASK(5, 4) 195 /* Touchscreen Mode Register - Average samples */ 196 #define AT91_SAMA5D2_TSMR_TSAV(x) ((x) << 4) 197 /* Touchscreen Mode Register - Touch/trigger frequency ratio mask */ 198 #define AT91_SAMA5D2_TSMR_TSFREQ_MASK GENMASK(11, 8) 199 /* Touchscreen Mode Register - Touch/trigger frequency ratio */ 200 #define AT91_SAMA5D2_TSMR_TSFREQ(x) ((x) << 8) 201 /* Touchscreen Mode Register - Pen Debounce Time mask */ 202 #define AT91_SAMA5D2_TSMR_PENDBC_MASK GENMASK(31, 28) 203 /* Touchscreen Mode Register - Pen Debounce Time */ 204 #define AT91_SAMA5D2_TSMR_PENDBC(x) ((x) << 28) 205 /* Touchscreen Mode Register - No DMA for touch measurements */ 206 #define AT91_SAMA5D2_TSMR_NOTSDMA BIT(22) 207 /* Touchscreen Mode Register - Disable pen detection */ 208 #define AT91_SAMA5D2_TSMR_PENDET_DIS (0 << 24) 209 /* Touchscreen Mode Register - Enable pen detection */ 210 #define AT91_SAMA5D2_TSMR_PENDET_ENA BIT(24) 211 212 /* Touchscreen X Position Register */ 213 u16 XPOSR; 214 /* Touchscreen Y Position Register */ 215 u16 YPOSR; 216 /* Touchscreen Pressure Register */ 217 u16 PRESSR; 218 /* Trigger Register */ 219 u16 TRGR; 220 /* Mask for TRGMOD field of TRGR register */ 221 #define AT91_SAMA5D2_TRGR_TRGMOD_MASK GENMASK(2, 0) 222 /* No trigger, only software trigger can start conversions */ 223 #define AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER 0 224 /* Trigger Mode external trigger rising edge */ 225 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE 1 226 /* Trigger Mode external trigger falling edge */ 227 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL 2 228 /* Trigger Mode external trigger any edge */ 229 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY 3 230 /* Trigger Mode internal periodic */ 231 #define AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC 5 232 /* Trigger Mode - trigger period mask */ 233 #define AT91_SAMA5D2_TRGR_TRGPER_MASK GENMASK(31, 16) 234 /* Trigger Mode - trigger period */ 235 #define AT91_SAMA5D2_TRGR_TRGPER(x) ((x) << 16) 236 237 /* Correction Select Register */ 238 u16 COSR; 239 /* Correction Value Register */ 240 u16 CVR; 241 /* Channel Error Correction Register */ 242 u16 CECR; 243 /* Write Protection Mode Register */ 244 u16 WPMR; 245 /* Write Protection Status Register */ 246 u16 WPSR; 247 /* Version Register */ 248 u16 VERSION; 249 /* Temperature Sensor Mode Register */ 250 u16 TEMPMR; 251 /* Temperature Sensor Mode - Temperature sensor on */ 252 #define AT91_SAMA5D2_TEMPMR_TEMPON BIT(0) 253 }; 254 255 static const struct at91_adc_reg_layout sama5d2_layout = { 256 .CR = 0x00, 257 .MR = 0x04, 258 .SEQR1 = 0x08, 259 .SEQR2 = 0x0c, 260 .CHER = 0x10, 261 .CHDR = 0x14, 262 .CHSR = 0x18, 263 .LCDR = 0x20, 264 .IER = 0x24, 265 .IDR = 0x28, 266 .IMR = 0x2c, 267 .ISR = 0x30, 268 .LCTMR = 0x34, 269 .LCCWR = 0x38, 270 .OVER = 0x3c, 271 .EMR = 0x40, 272 .CWR = 0x44, 273 .CGR = 0x48, 274 .COR = 0x4c, 275 .COR_diff_offset = 16, 276 .ACR = 0x94, 277 .TSMR = 0xb0, 278 .XPOSR = 0xb4, 279 .YPOSR = 0xb8, 280 .PRESSR = 0xbc, 281 .TRGR = 0xc0, 282 .COSR = 0xd0, 283 .CVR = 0xd4, 284 .CECR = 0xd8, 285 .WPMR = 0xe4, 286 .WPSR = 0xe8, 287 .VERSION = 0xfc, 288 }; 289 290 static const struct at91_adc_reg_layout sama7g5_layout = { 291 .CR = 0x00, 292 .MR = 0x04, 293 .SEQR1 = 0x08, 294 .SEQR2 = 0x0c, 295 .CHER = 0x10, 296 .CHDR = 0x14, 297 .CHSR = 0x18, 298 .LCDR = 0x20, 299 .IER = 0x24, 300 .IDR = 0x28, 301 .IMR = 0x2c, 302 .ISR = 0x30, 303 .EOC_IER = 0x34, 304 .EOC_IDR = 0x38, 305 .EOC_IMR = 0x3c, 306 .EOC_ISR = 0x40, 307 .TEMPMR = 0x44, 308 .OVER = 0x4c, 309 .EMR = 0x50, 310 .CWR = 0x54, 311 .COR = 0x5c, 312 .COR_diff_offset = 0, 313 .ACR = 0xe0, 314 .TRGR = 0x100, 315 .COSR = 0x104, 316 .CVR = 0x108, 317 .CECR = 0x10c, 318 .WPMR = 0x118, 319 .WPSR = 0x11c, 320 .VERSION = 0x130, 321 }; 322 323 #define AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */ 324 #define AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US 200 325 326 #define AT91_SAMA5D2_XYZ_MASK GENMASK(11, 0) 327 328 #define AT91_SAMA5D2_MAX_POS_BITS 12 329 330 #define AT91_HWFIFO_MAX_SIZE_STR "128" 331 #define AT91_HWFIFO_MAX_SIZE 128 332 333 #define AT91_SAMA_CHAN_SINGLE(index, num, addr, rbits) \ 334 { \ 335 .type = IIO_VOLTAGE, \ 336 .channel = num, \ 337 .address = addr, \ 338 .scan_index = index, \ 339 .scan_type = { \ 340 .sign = 'u', \ 341 .realbits = rbits, \ 342 .storagebits = 16, \ 343 }, \ 344 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 345 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 346 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ 347 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 348 .info_mask_shared_by_all_available = \ 349 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 350 .datasheet_name = "CH"#num, \ 351 .indexed = 1, \ 352 } 353 354 #define AT91_SAMA5D2_CHAN_SINGLE(index, num, addr) \ 355 AT91_SAMA_CHAN_SINGLE(index, num, addr, 14) 356 357 #define AT91_SAMA7G5_CHAN_SINGLE(index, num, addr) \ 358 AT91_SAMA_CHAN_SINGLE(index, num, addr, 16) 359 360 #define AT91_SAMA_CHAN_DIFF(index, num, num2, addr, rbits) \ 361 { \ 362 .type = IIO_VOLTAGE, \ 363 .differential = 1, \ 364 .channel = num, \ 365 .channel2 = num2, \ 366 .address = addr, \ 367 .scan_index = index, \ 368 .scan_type = { \ 369 .sign = 's', \ 370 .realbits = rbits, \ 371 .storagebits = 16, \ 372 }, \ 373 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 374 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 375 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ 376 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 377 .info_mask_shared_by_all_available = \ 378 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 379 .datasheet_name = "CH"#num"-CH"#num2, \ 380 .indexed = 1, \ 381 } 382 383 #define AT91_SAMA5D2_CHAN_DIFF(index, num, num2, addr) \ 384 AT91_SAMA_CHAN_DIFF(index, num, num2, addr, 14) 385 386 #define AT91_SAMA7G5_CHAN_DIFF(index, num, num2, addr) \ 387 AT91_SAMA_CHAN_DIFF(index, num, num2, addr, 16) 388 389 #define AT91_SAMA5D2_CHAN_TOUCH(num, name, mod) \ 390 { \ 391 .type = IIO_POSITIONRELATIVE, \ 392 .modified = 1, \ 393 .channel = num, \ 394 .channel2 = mod, \ 395 .scan_index = num, \ 396 .scan_type = { \ 397 .sign = 'u', \ 398 .realbits = 12, \ 399 .storagebits = 16, \ 400 }, \ 401 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 402 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ 403 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 404 .info_mask_shared_by_all_available = \ 405 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 406 .datasheet_name = name, \ 407 } 408 #define AT91_SAMA5D2_CHAN_PRESSURE(num, name) \ 409 { \ 410 .type = IIO_PRESSURE, \ 411 .channel = num, \ 412 .scan_index = num, \ 413 .scan_type = { \ 414 .sign = 'u', \ 415 .realbits = 12, \ 416 .storagebits = 16, \ 417 }, \ 418 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 419 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ 420 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 421 .info_mask_shared_by_all_available = \ 422 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 423 .datasheet_name = name, \ 424 } 425 426 #define AT91_SAMA5D2_CHAN_TEMP(num, name, addr) \ 427 { \ 428 .type = IIO_TEMP, \ 429 .channel = num, \ 430 .address = addr, \ 431 .scan_index = num, \ 432 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \ 433 .info_mask_shared_by_all = \ 434 BIT(IIO_CHAN_INFO_PROCESSED) | \ 435 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 436 .info_mask_shared_by_all_available = \ 437 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 438 .datasheet_name = name, \ 439 } 440 441 #define at91_adc_readl(st, reg) \ 442 readl_relaxed((st)->base + (st)->soc_info.platform->layout->reg) 443 #define at91_adc_read_chan(st, reg) \ 444 readl_relaxed((st)->base + reg) 445 #define at91_adc_writel(st, reg, val) \ 446 writel_relaxed(val, (st)->base + (st)->soc_info.platform->layout->reg) 447 448 /** 449 * struct at91_adc_platform - at91-sama5d2 platform information struct 450 * @layout: pointer to the reg layout struct 451 * @adc_channels: pointer to an array of channels for registering in 452 * the iio subsystem 453 * @nr_channels: number of physical channels available 454 * @touch_chan_x: index of the touchscreen X channel 455 * @touch_chan_y: index of the touchscreen Y channel 456 * @touch_chan_p: index of the touchscreen P channel 457 * @max_channels: number of total channels 458 * @max_index: highest channel index (highest index may be higher 459 * than the total channel number) 460 * @hw_trig_cnt: number of possible hardware triggers 461 * @osr_mask: oversampling ratio bitmask on EMR register 462 * @oversampling_avail: available oversampling values 463 * @oversampling_avail_no: number of available oversampling values 464 * @chan_realbits: realbits for registered channels 465 * @temp_chan: temperature channel index 466 * @temp_sensor: temperature sensor supported 467 */ 468 struct at91_adc_platform { 469 const struct at91_adc_reg_layout *layout; 470 const struct iio_chan_spec (*adc_channels)[]; 471 unsigned int nr_channels; 472 unsigned int touch_chan_x; 473 unsigned int touch_chan_y; 474 unsigned int touch_chan_p; 475 unsigned int max_channels; 476 unsigned int max_index; 477 unsigned int hw_trig_cnt; 478 unsigned int osr_mask; 479 unsigned int oversampling_avail[5]; 480 unsigned int oversampling_avail_no; 481 unsigned int chan_realbits; 482 unsigned int temp_chan; 483 bool temp_sensor; 484 }; 485 486 /** 487 * struct at91_adc_temp_sensor_clb - at91-sama5d2 temperature sensor 488 * calibration data structure 489 * @p1: P1 calibration temperature 490 * @p4: P4 calibration voltage 491 * @p6: P6 calibration voltage 492 */ 493 struct at91_adc_temp_sensor_clb { 494 u32 p1; 495 u32 p4; 496 u32 p6; 497 }; 498 499 /** 500 * enum at91_adc_ts_clb_idx - calibration indexes in NVMEM buffer 501 * @AT91_ADC_TS_CLB_IDX_P1: index for P1 502 * @AT91_ADC_TS_CLB_IDX_P4: index for P4 503 * @AT91_ADC_TS_CLB_IDX_P6: index for P6 504 * @AT91_ADC_TS_CLB_IDX_MAX: max index for temperature calibration packet in OTP 505 */ 506 enum at91_adc_ts_clb_idx { 507 AT91_ADC_TS_CLB_IDX_P1 = 2, 508 AT91_ADC_TS_CLB_IDX_P4 = 5, 509 AT91_ADC_TS_CLB_IDX_P6 = 7, 510 AT91_ADC_TS_CLB_IDX_MAX = 19, 511 }; 512 513 /* Temperature sensor calibration - Vtemp voltage sensitivity to temperature. */ 514 #define AT91_ADC_TS_VTEMP_DT (2080U) 515 516 /** 517 * struct at91_adc_soc_info - at91-sama5d2 soc information struct 518 * @startup_time: device startup time 519 * @min_sample_rate: minimum sample rate in Hz 520 * @max_sample_rate: maximum sample rate in Hz 521 * @platform: pointer to the platform structure 522 * @temp_sensor_clb: temperature sensor calibration data structure 523 */ 524 struct at91_adc_soc_info { 525 unsigned startup_time; 526 unsigned min_sample_rate; 527 unsigned max_sample_rate; 528 const struct at91_adc_platform *platform; 529 struct at91_adc_temp_sensor_clb temp_sensor_clb; 530 }; 531 532 struct at91_adc_trigger { 533 char *name; 534 unsigned int trgmod_value; 535 unsigned int edge_type; 536 bool hw_trig; 537 }; 538 539 /** 540 * struct at91_adc_dma - at91-sama5d2 dma information struct 541 * @dma_chan: the dma channel acquired 542 * @rx_buf: dma coherent allocated area 543 * @rx_dma_buf: dma handler for the buffer 544 * @phys_addr: physical address of the ADC base register 545 * @buf_idx: index inside the dma buffer where reading was last done 546 * @rx_buf_sz: size of buffer used by DMA operation 547 * @watermark: number of conversions to copy before DMA triggers irq 548 * @dma_ts: hold the start timestamp of dma operation 549 */ 550 struct at91_adc_dma { 551 struct dma_chan *dma_chan; 552 u8 *rx_buf; 553 dma_addr_t rx_dma_buf; 554 phys_addr_t phys_addr; 555 int buf_idx; 556 int rx_buf_sz; 557 int watermark; 558 s64 dma_ts; 559 }; 560 561 /** 562 * struct at91_adc_touch - at91-sama5d2 touchscreen information struct 563 * @sample_period_val: the value for periodic trigger interval 564 * @touching: is the pen touching the screen or not 565 * @x_pos: temporary placeholder for pressure computation 566 * @channels_bitmask: bitmask with the touchscreen channels enabled 567 * @workq: workqueue for buffer data pushing 568 */ 569 struct at91_adc_touch { 570 u16 sample_period_val; 571 bool touching; 572 u16 x_pos; 573 unsigned long channels_bitmask; 574 struct work_struct workq; 575 }; 576 577 /** 578 * struct at91_adc_temp - at91-sama5d2 temperature information structure 579 * @sample_period_val: sample period value 580 * @saved_sample_rate: saved sample rate 581 * @saved_oversampling: saved oversampling 582 */ 583 struct at91_adc_temp { 584 u16 sample_period_val; 585 u16 saved_sample_rate; 586 u16 saved_oversampling; 587 }; 588 589 struct at91_adc_state { 590 void __iomem *base; 591 int irq; 592 struct clk *per_clk; 593 struct regulator *reg; 594 struct regulator *vref; 595 int vref_uv; 596 unsigned int current_sample_rate; 597 struct iio_trigger *trig; 598 const struct at91_adc_trigger *selected_trig; 599 const struct iio_chan_spec *chan; 600 bool conversion_done; 601 u32 conversion_value; 602 unsigned int oversampling_ratio; 603 struct at91_adc_soc_info soc_info; 604 wait_queue_head_t wq_data_available; 605 struct at91_adc_dma dma_st; 606 struct at91_adc_touch touch_st; 607 struct at91_adc_temp temp_st; 608 struct iio_dev *indio_dev; 609 struct device *dev; 610 /* We assume 32 channels for now, has to be increased if needed. */ 611 IIO_DECLARE_BUFFER_WITH_TS(u16, buffer, 32); 612 /* 613 * lock to prevent concurrent 'single conversion' requests through 614 * sysfs. 615 */ 616 struct mutex lock; 617 }; 618 619 static const struct at91_adc_trigger at91_adc_trigger_list[] = { 620 { 621 .name = "external_rising", 622 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE, 623 .edge_type = IRQ_TYPE_EDGE_RISING, 624 .hw_trig = true, 625 }, 626 { 627 .name = "external_falling", 628 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL, 629 .edge_type = IRQ_TYPE_EDGE_FALLING, 630 .hw_trig = true, 631 }, 632 { 633 .name = "external_any", 634 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY, 635 .edge_type = IRQ_TYPE_EDGE_BOTH, 636 .hw_trig = true, 637 }, 638 { 639 .name = "software", 640 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER, 641 .edge_type = IRQ_TYPE_NONE, 642 .hw_trig = false, 643 }, 644 }; 645 646 static const struct iio_chan_spec at91_sama5d2_adc_channels[] = { 647 AT91_SAMA5D2_CHAN_SINGLE(0, 0, 0x50), 648 AT91_SAMA5D2_CHAN_SINGLE(1, 1, 0x54), 649 AT91_SAMA5D2_CHAN_SINGLE(2, 2, 0x58), 650 AT91_SAMA5D2_CHAN_SINGLE(3, 3, 0x5c), 651 AT91_SAMA5D2_CHAN_SINGLE(4, 4, 0x60), 652 AT91_SAMA5D2_CHAN_SINGLE(5, 5, 0x64), 653 AT91_SAMA5D2_CHAN_SINGLE(6, 6, 0x68), 654 AT91_SAMA5D2_CHAN_SINGLE(7, 7, 0x6c), 655 AT91_SAMA5D2_CHAN_SINGLE(8, 8, 0x70), 656 AT91_SAMA5D2_CHAN_SINGLE(9, 9, 0x74), 657 AT91_SAMA5D2_CHAN_SINGLE(10, 10, 0x78), 658 AT91_SAMA5D2_CHAN_SINGLE(11, 11, 0x7c), 659 /* original ABI has the differential channels with a gap in between */ 660 AT91_SAMA5D2_CHAN_DIFF(12, 0, 1, 0x50), 661 AT91_SAMA5D2_CHAN_DIFF(14, 2, 3, 0x58), 662 AT91_SAMA5D2_CHAN_DIFF(16, 4, 5, 0x60), 663 AT91_SAMA5D2_CHAN_DIFF(18, 6, 7, 0x68), 664 AT91_SAMA5D2_CHAN_DIFF(20, 8, 9, 0x70), 665 AT91_SAMA5D2_CHAN_DIFF(22, 10, 11, 0x78), 666 IIO_CHAN_SOFT_TIMESTAMP(23), 667 AT91_SAMA5D2_CHAN_TOUCH(24, "x", IIO_MOD_X), 668 AT91_SAMA5D2_CHAN_TOUCH(25, "y", IIO_MOD_Y), 669 AT91_SAMA5D2_CHAN_PRESSURE(26, "pressure"), 670 }; 671 672 static const struct iio_chan_spec at91_sama7g5_adc_channels[] = { 673 AT91_SAMA7G5_CHAN_SINGLE(0, 0, 0x60), 674 AT91_SAMA7G5_CHAN_SINGLE(1, 1, 0x64), 675 AT91_SAMA7G5_CHAN_SINGLE(2, 2, 0x68), 676 AT91_SAMA7G5_CHAN_SINGLE(3, 3, 0x6c), 677 AT91_SAMA7G5_CHAN_SINGLE(4, 4, 0x70), 678 AT91_SAMA7G5_CHAN_SINGLE(5, 5, 0x74), 679 AT91_SAMA7G5_CHAN_SINGLE(6, 6, 0x78), 680 AT91_SAMA7G5_CHAN_SINGLE(7, 7, 0x7c), 681 AT91_SAMA7G5_CHAN_SINGLE(8, 8, 0x80), 682 AT91_SAMA7G5_CHAN_SINGLE(9, 9, 0x84), 683 AT91_SAMA7G5_CHAN_SINGLE(10, 10, 0x88), 684 AT91_SAMA7G5_CHAN_SINGLE(11, 11, 0x8c), 685 AT91_SAMA7G5_CHAN_SINGLE(12, 12, 0x90), 686 AT91_SAMA7G5_CHAN_SINGLE(13, 13, 0x94), 687 AT91_SAMA7G5_CHAN_SINGLE(14, 14, 0x98), 688 AT91_SAMA7G5_CHAN_SINGLE(15, 15, 0x9c), 689 AT91_SAMA7G5_CHAN_DIFF(16, 0, 1, 0x60), 690 AT91_SAMA7G5_CHAN_DIFF(17, 2, 3, 0x68), 691 AT91_SAMA7G5_CHAN_DIFF(18, 4, 5, 0x70), 692 AT91_SAMA7G5_CHAN_DIFF(19, 6, 7, 0x78), 693 AT91_SAMA7G5_CHAN_DIFF(20, 8, 9, 0x80), 694 AT91_SAMA7G5_CHAN_DIFF(21, 10, 11, 0x88), 695 AT91_SAMA7G5_CHAN_DIFF(22, 12, 13, 0x90), 696 AT91_SAMA7G5_CHAN_DIFF(23, 14, 15, 0x98), 697 IIO_CHAN_SOFT_TIMESTAMP(24), 698 AT91_SAMA5D2_CHAN_TEMP(AT91_SAMA7G5_ADC_TEMP_CHANNEL, "temp", 0xdc), 699 }; 700 701 static const struct at91_adc_platform sama5d2_platform = { 702 .layout = &sama5d2_layout, 703 .adc_channels = &at91_sama5d2_adc_channels, 704 #define AT91_SAMA5D2_SINGLE_CHAN_CNT 12 705 #define AT91_SAMA5D2_DIFF_CHAN_CNT 6 706 .nr_channels = AT91_SAMA5D2_SINGLE_CHAN_CNT + 707 AT91_SAMA5D2_DIFF_CHAN_CNT, 708 #define AT91_SAMA5D2_TOUCH_X_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \ 709 AT91_SAMA5D2_DIFF_CHAN_CNT * 2) 710 .touch_chan_x = AT91_SAMA5D2_TOUCH_X_CHAN_IDX, 711 #define AT91_SAMA5D2_TOUCH_Y_CHAN_IDX (AT91_SAMA5D2_TOUCH_X_CHAN_IDX + 1) 712 .touch_chan_y = AT91_SAMA5D2_TOUCH_Y_CHAN_IDX, 713 #define AT91_SAMA5D2_TOUCH_P_CHAN_IDX (AT91_SAMA5D2_TOUCH_Y_CHAN_IDX + 1) 714 .touch_chan_p = AT91_SAMA5D2_TOUCH_P_CHAN_IDX, 715 #define AT91_SAMA5D2_MAX_CHAN_IDX AT91_SAMA5D2_TOUCH_P_CHAN_IDX 716 .max_channels = ARRAY_SIZE(at91_sama5d2_adc_channels), 717 .max_index = AT91_SAMA5D2_MAX_CHAN_IDX, 718 #define AT91_SAMA5D2_HW_TRIG_CNT 3 719 .hw_trig_cnt = AT91_SAMA5D2_HW_TRIG_CNT, 720 .osr_mask = GENMASK(17, 16), 721 .oversampling_avail = { 1, 4, 16, }, 722 .oversampling_avail_no = 3, 723 .chan_realbits = 14, 724 }; 725 726 static const struct at91_adc_platform sama7g5_platform = { 727 .layout = &sama7g5_layout, 728 .adc_channels = &at91_sama7g5_adc_channels, 729 #define AT91_SAMA7G5_SINGLE_CHAN_CNT 16 730 #define AT91_SAMA7G5_DIFF_CHAN_CNT 8 731 #define AT91_SAMA7G5_TEMP_CHAN_CNT 1 732 .nr_channels = AT91_SAMA7G5_SINGLE_CHAN_CNT + 733 AT91_SAMA7G5_DIFF_CHAN_CNT + 734 AT91_SAMA7G5_TEMP_CHAN_CNT, 735 #define AT91_SAMA7G5_MAX_CHAN_IDX (AT91_SAMA7G5_SINGLE_CHAN_CNT + \ 736 AT91_SAMA7G5_DIFF_CHAN_CNT + \ 737 AT91_SAMA7G5_TEMP_CHAN_CNT) 738 .max_channels = ARRAY_SIZE(at91_sama7g5_adc_channels), 739 .max_index = AT91_SAMA7G5_MAX_CHAN_IDX, 740 #define AT91_SAMA7G5_HW_TRIG_CNT 3 741 .hw_trig_cnt = AT91_SAMA7G5_HW_TRIG_CNT, 742 .osr_mask = GENMASK(18, 16), 743 .oversampling_avail = { 1, 4, 16, 64, 256, }, 744 .oversampling_avail_no = 5, 745 .chan_realbits = 16, 746 .temp_sensor = true, 747 .temp_chan = AT91_SAMA7G5_ADC_TEMP_CHANNEL, 748 }; 749 750 static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan) 751 { 752 int i; 753 754 for (i = 0; i < indio_dev->num_channels; i++) { 755 if (indio_dev->channels[i].scan_index == chan) 756 return i; 757 } 758 return -EINVAL; 759 } 760 761 static inline struct iio_chan_spec const * 762 at91_adc_chan_get(struct iio_dev *indio_dev, int chan) 763 { 764 int index = at91_adc_chan_xlate(indio_dev, chan); 765 766 if (index < 0) 767 return NULL; 768 return indio_dev->channels + index; 769 } 770 771 static inline int at91_adc_fwnode_xlate(struct iio_dev *indio_dev, 772 const struct fwnode_reference_args *iiospec) 773 { 774 return at91_adc_chan_xlate(indio_dev, iiospec->args[0]); 775 } 776 777 static unsigned int at91_adc_active_scan_mask_to_reg(struct iio_dev *indio_dev) 778 { 779 u32 mask = 0; 780 u8 bit; 781 struct at91_adc_state *st = iio_priv(indio_dev); 782 783 for_each_set_bit(bit, indio_dev->active_scan_mask, 784 indio_dev->num_channels) { 785 struct iio_chan_spec const *chan = 786 at91_adc_chan_get(indio_dev, bit); 787 mask |= BIT(chan->channel); 788 } 789 790 return mask & GENMASK(st->soc_info.platform->nr_channels, 0); 791 } 792 793 static void at91_adc_cor(struct at91_adc_state *st, 794 struct iio_chan_spec const *chan) 795 { 796 u32 cor, cur_cor; 797 798 cor = BIT(chan->channel) | BIT(chan->channel2); 799 800 cur_cor = at91_adc_readl(st, COR); 801 cor <<= st->soc_info.platform->layout->COR_diff_offset; 802 if (chan->differential) 803 at91_adc_writel(st, COR, cur_cor | cor); 804 else 805 at91_adc_writel(st, COR, cur_cor & ~cor); 806 } 807 808 static void at91_adc_irq_status(struct at91_adc_state *st, u32 *status, 809 u32 *eoc) 810 { 811 *status = at91_adc_readl(st, ISR); 812 if (st->soc_info.platform->layout->EOC_ISR) 813 *eoc = at91_adc_readl(st, EOC_ISR); 814 else 815 *eoc = *status; 816 } 817 818 static void at91_adc_irq_mask(struct at91_adc_state *st, u32 *status, u32 *eoc) 819 { 820 *status = at91_adc_readl(st, IMR); 821 if (st->soc_info.platform->layout->EOC_IMR) 822 *eoc = at91_adc_readl(st, EOC_IMR); 823 else 824 *eoc = *status; 825 } 826 827 static void at91_adc_eoc_dis(struct at91_adc_state *st, unsigned int channel) 828 { 829 /* 830 * On some products having the EOC bits in a separate register, 831 * errata recommends not writing this register (EOC_IDR). 832 * On products having the EOC bits in the IDR register, it's fine to write it. 833 */ 834 if (!st->soc_info.platform->layout->EOC_IDR) 835 at91_adc_writel(st, IDR, BIT(channel)); 836 } 837 838 static void at91_adc_eoc_ena(struct at91_adc_state *st, unsigned int channel) 839 { 840 if (!st->soc_info.platform->layout->EOC_IDR) 841 at91_adc_writel(st, IER, BIT(channel)); 842 else 843 at91_adc_writel(st, EOC_IER, BIT(channel)); 844 } 845 846 static int at91_adc_config_emr(struct at91_adc_state *st, 847 u32 oversampling_ratio, u32 trackx) 848 { 849 /* configure the extended mode register */ 850 unsigned int emr, osr; 851 unsigned int osr_mask = st->soc_info.platform->osr_mask; 852 int i, ret; 853 854 /* Check against supported oversampling values. */ 855 for (i = 0; i < st->soc_info.platform->oversampling_avail_no; i++) { 856 if (oversampling_ratio == st->soc_info.platform->oversampling_avail[i]) 857 break; 858 } 859 if (i == st->soc_info.platform->oversampling_avail_no) 860 return -EINVAL; 861 862 /* select oversampling ratio from configuration */ 863 switch (oversampling_ratio) { 864 case 1: 865 osr = AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_1SAMPLES, 866 osr_mask); 867 break; 868 case 4: 869 osr = AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_4SAMPLES, 870 osr_mask); 871 break; 872 case 16: 873 osr = AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_16SAMPLES, 874 osr_mask); 875 break; 876 case 64: 877 osr = AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_64SAMPLES, 878 osr_mask); 879 break; 880 case 256: 881 osr = AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_256SAMPLES, 882 osr_mask); 883 break; 884 } 885 886 ret = pm_runtime_resume_and_get(st->dev); 887 if (ret < 0) 888 return ret; 889 890 emr = at91_adc_readl(st, EMR); 891 /* select oversampling per single trigger event */ 892 emr |= AT91_SAMA5D2_EMR_ASTE(1); 893 /* delete leftover content if it's the case */ 894 emr &= ~(osr_mask | AT91_SAMA5D2_TRACKX_MASK); 895 /* Update osr and trackx. */ 896 emr |= osr | AT91_SAMA5D2_TRACKX(trackx); 897 at91_adc_writel(st, EMR, emr); 898 899 pm_runtime_mark_last_busy(st->dev); 900 pm_runtime_put_autosuspend(st->dev); 901 902 st->oversampling_ratio = oversampling_ratio; 903 904 return 0; 905 } 906 907 static int at91_adc_adjust_val_osr(struct at91_adc_state *st, int *val) 908 { 909 int nbits, diff; 910 911 if (st->oversampling_ratio == 1) 912 nbits = 12; 913 else if (st->oversampling_ratio == 4) 914 nbits = 13; 915 else if (st->oversampling_ratio == 16) 916 nbits = 14; 917 else if (st->oversampling_ratio == 64) 918 nbits = 15; 919 else if (st->oversampling_ratio == 256) 920 nbits = 16; 921 else 922 /* Should not happen. */ 923 return -EINVAL; 924 925 /* 926 * We have nbits of real data and channel is registered as 927 * st->soc_info.platform->chan_realbits, so shift left diff bits. 928 */ 929 diff = st->soc_info.platform->chan_realbits - nbits; 930 *val <<= diff; 931 932 return IIO_VAL_INT; 933 } 934 935 static void at91_adc_adjust_val_osr_array(struct at91_adc_state *st, void *buf, 936 int len) 937 { 938 int i = 0, val; 939 u16 *buf_u16 = (u16 *) buf; 940 941 /* 942 * We are converting each two bytes (each sample). 943 * First convert the byte based array to u16, and convert each sample 944 * separately. 945 * Each value is two bytes in an array of chars, so to not shift 946 * more than we need, save the value separately. 947 * len is in bytes, so divide by two to get number of samples. 948 */ 949 while (i < len / 2) { 950 val = buf_u16[i]; 951 at91_adc_adjust_val_osr(st, &val); 952 buf_u16[i] = val; 953 i++; 954 } 955 } 956 957 static int at91_adc_configure_touch(struct at91_adc_state *st, bool state) 958 { 959 u32 clk_khz = st->current_sample_rate / 1000; 960 int i = 0, ret; 961 u16 pendbc; 962 u32 tsmr, acr; 963 964 if (state) { 965 ret = pm_runtime_resume_and_get(st->dev); 966 if (ret < 0) 967 return ret; 968 } else { 969 /* disabling touch IRQs and setting mode to no touch enabled */ 970 at91_adc_writel(st, IDR, 971 AT91_SAMA5D2_IER_PEN | AT91_SAMA5D2_IER_NOPEN); 972 at91_adc_writel(st, TSMR, 0); 973 974 pm_runtime_mark_last_busy(st->dev); 975 pm_runtime_put_autosuspend(st->dev); 976 return 0; 977 } 978 /* 979 * debounce time is in microseconds, we need it in milliseconds to 980 * multiply with kilohertz, so, divide by 1000, but after the multiply. 981 * round up to make sure pendbc is at least 1 982 */ 983 pendbc = round_up(AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US * 984 clk_khz / 1000, 1); 985 986 /* get the required exponent */ 987 while (pendbc >> i++) 988 ; 989 990 pendbc = i; 991 992 tsmr = AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS; 993 994 tsmr |= AT91_SAMA5D2_TSMR_TSAV(2) & AT91_SAMA5D2_TSMR_TSAV_MASK; 995 tsmr |= AT91_SAMA5D2_TSMR_PENDBC(pendbc) & 996 AT91_SAMA5D2_TSMR_PENDBC_MASK; 997 tsmr |= AT91_SAMA5D2_TSMR_NOTSDMA; 998 tsmr |= AT91_SAMA5D2_TSMR_PENDET_ENA; 999 tsmr |= AT91_SAMA5D2_TSMR_TSFREQ(2) & AT91_SAMA5D2_TSMR_TSFREQ_MASK; 1000 1001 at91_adc_writel(st, TSMR, tsmr); 1002 1003 acr = at91_adc_readl(st, ACR); 1004 acr &= ~AT91_SAMA5D2_ACR_PENDETSENS_MASK; 1005 acr |= 0x02 & AT91_SAMA5D2_ACR_PENDETSENS_MASK; 1006 at91_adc_writel(st, ACR, acr); 1007 1008 /* Sample Period Time = (TRGPER + 1) / ADCClock */ 1009 st->touch_st.sample_period_val = 1010 round_up((AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US * 1011 clk_khz / 1000) - 1, 1); 1012 /* enable pen detect IRQ */ 1013 at91_adc_writel(st, IER, AT91_SAMA5D2_IER_PEN); 1014 1015 return 0; 1016 } 1017 1018 static u16 at91_adc_touch_pos(struct at91_adc_state *st, int reg) 1019 { 1020 u32 val = 0; 1021 u32 scale, result, pos; 1022 1023 /* 1024 * to obtain the actual position we must divide by scale 1025 * and multiply with max, where 1026 * max = 2^AT91_SAMA5D2_MAX_POS_BITS - 1 1027 */ 1028 /* first half of register is the x or y, second half is the scale */ 1029 if (reg == st->soc_info.platform->layout->XPOSR) 1030 val = at91_adc_readl(st, XPOSR); 1031 else if (reg == st->soc_info.platform->layout->YPOSR) 1032 val = at91_adc_readl(st, YPOSR); 1033 1034 if (!val) 1035 dev_dbg(&st->indio_dev->dev, "pos is 0\n"); 1036 1037 pos = val & AT91_SAMA5D2_XYZ_MASK; 1038 result = (pos << AT91_SAMA5D2_MAX_POS_BITS) - pos; 1039 scale = (val >> 16) & AT91_SAMA5D2_XYZ_MASK; 1040 if (scale == 0) { 1041 dev_err(&st->indio_dev->dev, "scale is 0\n"); 1042 return 0; 1043 } 1044 result /= scale; 1045 1046 return result; 1047 } 1048 1049 static u16 at91_adc_touch_x_pos(struct at91_adc_state *st) 1050 { 1051 st->touch_st.x_pos = at91_adc_touch_pos(st, st->soc_info.platform->layout->XPOSR); 1052 return st->touch_st.x_pos; 1053 } 1054 1055 static u16 at91_adc_touch_y_pos(struct at91_adc_state *st) 1056 { 1057 return at91_adc_touch_pos(st, st->soc_info.platform->layout->YPOSR); 1058 } 1059 1060 static u16 at91_adc_touch_pressure(struct at91_adc_state *st) 1061 { 1062 u32 val; 1063 u32 z1, z2; 1064 u32 pres; 1065 u32 rxp = 1; 1066 u32 factor = 1000; 1067 1068 /* calculate the pressure */ 1069 val = at91_adc_readl(st, PRESSR); 1070 z1 = val & AT91_SAMA5D2_XYZ_MASK; 1071 z2 = (val >> 16) & AT91_SAMA5D2_XYZ_MASK; 1072 1073 if (z1 != 0) 1074 pres = rxp * (st->touch_st.x_pos * factor / 1024) * 1075 (z2 * factor / z1 - factor) / 1076 factor; 1077 else 1078 pres = 0xFFFF; /* no pen contact */ 1079 1080 /* 1081 * The pressure from device grows down, minimum is 0xFFFF, maximum 0x0. 1082 * We compute it this way, but let's return it in the expected way, 1083 * growing from 0 to 0xFFFF. 1084 */ 1085 return 0xFFFF - pres; 1086 } 1087 1088 static int at91_adc_read_position(struct at91_adc_state *st, int chan, u16 *val) 1089 { 1090 *val = 0; 1091 if (!st->touch_st.touching) 1092 return -ENODATA; 1093 if (chan == st->soc_info.platform->touch_chan_x) 1094 *val = at91_adc_touch_x_pos(st); 1095 else if (chan == st->soc_info.platform->touch_chan_y) 1096 *val = at91_adc_touch_y_pos(st); 1097 else 1098 return -ENODATA; 1099 1100 return IIO_VAL_INT; 1101 } 1102 1103 static int at91_adc_read_pressure(struct at91_adc_state *st, int chan, u16 *val) 1104 { 1105 *val = 0; 1106 if (!st->touch_st.touching) 1107 return -ENODATA; 1108 if (chan == st->soc_info.platform->touch_chan_p) 1109 *val = at91_adc_touch_pressure(st); 1110 else 1111 return -ENODATA; 1112 1113 return IIO_VAL_INT; 1114 } 1115 1116 static void at91_adc_configure_trigger_registers(struct at91_adc_state *st, 1117 bool state) 1118 { 1119 u32 status = at91_adc_readl(st, TRGR); 1120 1121 /* clear TRGMOD */ 1122 status &= ~AT91_SAMA5D2_TRGR_TRGMOD_MASK; 1123 1124 if (state) 1125 status |= st->selected_trig->trgmod_value; 1126 1127 /* set/unset hw trigger */ 1128 at91_adc_writel(st, TRGR, status); 1129 } 1130 1131 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) 1132 { 1133 struct iio_dev *indio = iio_trigger_get_drvdata(trig); 1134 struct at91_adc_state *st = iio_priv(indio); 1135 int ret; 1136 1137 if (state) { 1138 ret = pm_runtime_resume_and_get(st->dev); 1139 if (ret < 0) 1140 return ret; 1141 } 1142 1143 at91_adc_configure_trigger_registers(st, state); 1144 1145 if (!state) { 1146 pm_runtime_mark_last_busy(st->dev); 1147 pm_runtime_put_autosuspend(st->dev); 1148 } 1149 1150 return 0; 1151 } 1152 1153 static void at91_adc_reenable_trigger(struct iio_trigger *trig) 1154 { 1155 struct iio_dev *indio = iio_trigger_get_drvdata(trig); 1156 struct at91_adc_state *st = iio_priv(indio); 1157 1158 /* if we are using DMA, we must not reenable irq after each trigger */ 1159 if (st->dma_st.dma_chan) 1160 return; 1161 1162 enable_irq(st->irq); 1163 1164 /* Needed to ACK the DRDY interruption */ 1165 at91_adc_readl(st, LCDR); 1166 } 1167 1168 static const struct iio_trigger_ops at91_adc_trigger_ops = { 1169 .set_trigger_state = &at91_adc_configure_trigger, 1170 .reenable = &at91_adc_reenable_trigger, 1171 .validate_device = iio_trigger_validate_own_device, 1172 }; 1173 1174 static int at91_adc_dma_size_done(struct at91_adc_state *st) 1175 { 1176 struct dma_tx_state state; 1177 enum dma_status status; 1178 int i, size; 1179 1180 status = dmaengine_tx_status(st->dma_st.dma_chan, 1181 st->dma_st.dma_chan->cookie, 1182 &state); 1183 if (status != DMA_IN_PROGRESS) 1184 return 0; 1185 1186 /* Transferred length is size in bytes from end of buffer */ 1187 i = st->dma_st.rx_buf_sz - state.residue; 1188 1189 /* Return available bytes */ 1190 if (i >= st->dma_st.buf_idx) 1191 size = i - st->dma_st.buf_idx; 1192 else 1193 size = st->dma_st.rx_buf_sz + i - st->dma_st.buf_idx; 1194 return size; 1195 } 1196 1197 static void at91_dma_buffer_done(void *data) 1198 { 1199 struct iio_dev *indio_dev = data; 1200 1201 iio_trigger_poll_nested(indio_dev->trig); 1202 } 1203 1204 static int at91_adc_dma_start(struct iio_dev *indio_dev) 1205 { 1206 struct at91_adc_state *st = iio_priv(indio_dev); 1207 struct dma_async_tx_descriptor *desc; 1208 dma_cookie_t cookie; 1209 int ret; 1210 u8 bit; 1211 1212 if (!st->dma_st.dma_chan) 1213 return 0; 1214 1215 /* we start a new DMA, so set buffer index to start */ 1216 st->dma_st.buf_idx = 0; 1217 1218 /* 1219 * compute buffer size w.r.t. watermark and enabled channels. 1220 * scan_bytes is aligned so we need an exact size for DMA 1221 */ 1222 st->dma_st.rx_buf_sz = 0; 1223 1224 for_each_set_bit(bit, indio_dev->active_scan_mask, 1225 indio_dev->num_channels) { 1226 struct iio_chan_spec const *chan = 1227 at91_adc_chan_get(indio_dev, bit); 1228 1229 if (!chan) 1230 continue; 1231 1232 st->dma_st.rx_buf_sz += chan->scan_type.storagebits / 8; 1233 } 1234 st->dma_st.rx_buf_sz *= st->dma_st.watermark; 1235 1236 /* Prepare a DMA cyclic transaction */ 1237 desc = dmaengine_prep_dma_cyclic(st->dma_st.dma_chan, 1238 st->dma_st.rx_dma_buf, 1239 st->dma_st.rx_buf_sz, 1240 st->dma_st.rx_buf_sz / 2, 1241 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 1242 1243 if (!desc) { 1244 dev_err(&indio_dev->dev, "cannot prepare DMA cyclic\n"); 1245 return -EBUSY; 1246 } 1247 1248 desc->callback = at91_dma_buffer_done; 1249 desc->callback_param = indio_dev; 1250 1251 cookie = dmaengine_submit(desc); 1252 ret = dma_submit_error(cookie); 1253 if (ret) { 1254 dev_err(&indio_dev->dev, "cannot submit DMA cyclic\n"); 1255 dmaengine_terminate_async(st->dma_st.dma_chan); 1256 return ret; 1257 } 1258 1259 /* enable general overrun error signaling */ 1260 at91_adc_writel(st, IER, AT91_SAMA5D2_IER_GOVRE); 1261 /* Issue pending DMA requests */ 1262 dma_async_issue_pending(st->dma_st.dma_chan); 1263 1264 /* consider current time as DMA start time for timestamps */ 1265 st->dma_st.dma_ts = iio_get_time_ns(indio_dev); 1266 1267 dev_dbg(&indio_dev->dev, "DMA cyclic started\n"); 1268 1269 return 0; 1270 } 1271 1272 static bool at91_adc_buffer_check_use_irq(struct iio_dev *indio, 1273 struct at91_adc_state *st) 1274 { 1275 /* if using DMA, we do not use our own IRQ (we use DMA-controller) */ 1276 if (st->dma_st.dma_chan) 1277 return false; 1278 /* if the trigger is not ours, then it has its own IRQ */ 1279 if (iio_trigger_validate_own_device(indio->trig, indio)) 1280 return false; 1281 return true; 1282 } 1283 1284 static bool at91_adc_current_chan_is_touch(struct iio_dev *indio_dev) 1285 { 1286 struct at91_adc_state *st = iio_priv(indio_dev); 1287 1288 return !!bitmap_subset(indio_dev->active_scan_mask, 1289 &st->touch_st.channels_bitmask, 1290 st->soc_info.platform->max_index + 1); 1291 } 1292 1293 static int at91_adc_buffer_prepare(struct iio_dev *indio_dev) 1294 { 1295 int ret; 1296 u8 bit; 1297 struct at91_adc_state *st = iio_priv(indio_dev); 1298 1299 /* check if we are enabling triggered buffer or the touchscreen */ 1300 if (at91_adc_current_chan_is_touch(indio_dev)) 1301 return at91_adc_configure_touch(st, true); 1302 1303 /* if we are not in triggered mode, we cannot enable the buffer. */ 1304 if (!(iio_device_get_current_mode(indio_dev) & INDIO_ALL_TRIGGERED_MODES)) 1305 return -EINVAL; 1306 1307 ret = pm_runtime_resume_and_get(st->dev); 1308 if (ret < 0) 1309 return ret; 1310 1311 /* we continue with the triggered buffer */ 1312 ret = at91_adc_dma_start(indio_dev); 1313 if (ret) { 1314 dev_err(&indio_dev->dev, "buffer prepare failed\n"); 1315 goto pm_runtime_put; 1316 } 1317 1318 for_each_set_bit(bit, indio_dev->active_scan_mask, 1319 indio_dev->num_channels) { 1320 struct iio_chan_spec const *chan = 1321 at91_adc_chan_get(indio_dev, bit); 1322 if (!chan) 1323 continue; 1324 /* these channel types cannot be handled by this trigger */ 1325 if (chan->type == IIO_POSITIONRELATIVE || 1326 chan->type == IIO_PRESSURE || 1327 chan->type == IIO_TEMP) 1328 continue; 1329 1330 at91_adc_cor(st, chan); 1331 1332 at91_adc_writel(st, CHER, BIT(chan->channel)); 1333 } 1334 1335 if (at91_adc_buffer_check_use_irq(indio_dev, st)) 1336 at91_adc_writel(st, IER, AT91_SAMA5D2_IER_DRDY); 1337 1338 pm_runtime_put: 1339 pm_runtime_mark_last_busy(st->dev); 1340 pm_runtime_put_autosuspend(st->dev); 1341 return ret; 1342 } 1343 1344 static int at91_adc_buffer_postdisable(struct iio_dev *indio_dev) 1345 { 1346 struct at91_adc_state *st = iio_priv(indio_dev); 1347 int ret; 1348 u8 bit; 1349 1350 /* check if we are disabling triggered buffer or the touchscreen */ 1351 if (at91_adc_current_chan_is_touch(indio_dev)) 1352 return at91_adc_configure_touch(st, false); 1353 1354 /* if we are not in triggered mode, nothing to do here */ 1355 if (!(iio_device_get_current_mode(indio_dev) & INDIO_ALL_TRIGGERED_MODES)) 1356 return -EINVAL; 1357 1358 ret = pm_runtime_resume_and_get(st->dev); 1359 if (ret < 0) 1360 return ret; 1361 1362 /* 1363 * For each enable channel we must disable it in hardware. 1364 * In the case of DMA, we must read the last converted value 1365 * to clear EOC status and not get a possible interrupt later. 1366 * This value is being read by DMA from LCDR anyway, so it's not lost. 1367 */ 1368 for_each_set_bit(bit, indio_dev->active_scan_mask, 1369 indio_dev->num_channels) { 1370 struct iio_chan_spec const *chan = 1371 at91_adc_chan_get(indio_dev, bit); 1372 1373 if (!chan) 1374 continue; 1375 /* these channel types are virtual, no need to do anything */ 1376 if (chan->type == IIO_POSITIONRELATIVE || 1377 chan->type == IIO_PRESSURE || 1378 chan->type == IIO_TEMP) 1379 continue; 1380 1381 at91_adc_writel(st, CHDR, BIT(chan->channel)); 1382 1383 if (st->dma_st.dma_chan) 1384 at91_adc_read_chan(st, chan->address); 1385 } 1386 1387 if (at91_adc_buffer_check_use_irq(indio_dev, st)) 1388 at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_DRDY); 1389 1390 /* read overflow register to clear possible overflow status */ 1391 at91_adc_readl(st, OVER); 1392 1393 /* if we are using DMA we must clear registers and end DMA */ 1394 if (st->dma_st.dma_chan) 1395 dmaengine_terminate_sync(st->dma_st.dma_chan); 1396 1397 pm_runtime_mark_last_busy(st->dev); 1398 pm_runtime_put_autosuspend(st->dev); 1399 1400 return 0; 1401 } 1402 1403 static const struct iio_buffer_setup_ops at91_buffer_setup_ops = { 1404 .postdisable = &at91_adc_buffer_postdisable, 1405 }; 1406 1407 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *indio, 1408 char *trigger_name) 1409 { 1410 struct iio_trigger *trig; 1411 int ret; 1412 1413 trig = devm_iio_trigger_alloc(&indio->dev, "%s-dev%d-%s", indio->name, 1414 iio_device_id(indio), trigger_name); 1415 if (!trig) 1416 return ERR_PTR(-ENOMEM); 1417 1418 trig->dev.parent = indio->dev.parent; 1419 iio_trigger_set_drvdata(trig, indio); 1420 trig->ops = &at91_adc_trigger_ops; 1421 1422 ret = devm_iio_trigger_register(&indio->dev, trig); 1423 if (ret) 1424 return ERR_PTR(ret); 1425 1426 return trig; 1427 } 1428 1429 static void at91_adc_trigger_handler_nodma(struct iio_dev *indio_dev, 1430 struct iio_poll_func *pf) 1431 { 1432 struct at91_adc_state *st = iio_priv(indio_dev); 1433 int i = 0; 1434 int val; 1435 u8 bit; 1436 u32 mask = at91_adc_active_scan_mask_to_reg(indio_dev); 1437 unsigned int timeout = 50; 1438 u32 status, imr, eoc = 0, eoc_imr; 1439 1440 /* 1441 * Check if the conversion is ready. If not, wait a little bit, and 1442 * in case of timeout exit with an error. 1443 */ 1444 while (((eoc & mask) != mask) && timeout) { 1445 at91_adc_irq_status(st, &status, &eoc); 1446 at91_adc_irq_mask(st, &imr, &eoc_imr); 1447 usleep_range(50, 100); 1448 timeout--; 1449 } 1450 1451 /* Cannot read data, not ready. Continue without reporting data */ 1452 if (!timeout) 1453 return; 1454 1455 for_each_set_bit(bit, indio_dev->active_scan_mask, 1456 indio_dev->num_channels) { 1457 struct iio_chan_spec const *chan = 1458 at91_adc_chan_get(indio_dev, bit); 1459 1460 if (!chan) 1461 continue; 1462 /* 1463 * Our external trigger only supports the voltage channels. 1464 * In case someone requested a different type of channel 1465 * just put zeroes to buffer. 1466 * This should not happen because we check the scan mode 1467 * and scan mask when we enable the buffer, and we don't allow 1468 * the buffer to start with a mixed mask (voltage and something 1469 * else). 1470 * Thus, emit a warning. 1471 */ 1472 if (chan->type == IIO_VOLTAGE) { 1473 val = at91_adc_read_chan(st, chan->address); 1474 at91_adc_adjust_val_osr(st, &val); 1475 st->buffer[i] = val; 1476 } else { 1477 st->buffer[i] = 0; 1478 WARN(true, "This trigger cannot handle this type of channel"); 1479 } 1480 i++; 1481 } 1482 iio_push_to_buffers_with_timestamp(indio_dev, st->buffer, 1483 pf->timestamp); 1484 } 1485 1486 static void at91_adc_trigger_handler_dma(struct iio_dev *indio_dev) 1487 { 1488 struct at91_adc_state *st = iio_priv(indio_dev); 1489 int transferred_len = at91_adc_dma_size_done(st); 1490 s64 ns = iio_get_time_ns(indio_dev); 1491 s64 interval; 1492 int sample_index = 0, sample_count, sample_size; 1493 1494 u32 status = at91_adc_readl(st, ISR); 1495 /* if we reached this point, we cannot sample faster */ 1496 if (status & AT91_SAMA5D2_IER_GOVRE) 1497 pr_info_ratelimited("%s: conversion overrun detected\n", 1498 indio_dev->name); 1499 1500 sample_size = div_s64(st->dma_st.rx_buf_sz, st->dma_st.watermark); 1501 1502 sample_count = div_s64(transferred_len, sample_size); 1503 1504 /* 1505 * interval between samples is total time since last transfer handling 1506 * divided by the number of samples (total size divided by sample size) 1507 */ 1508 interval = div_s64((ns - st->dma_st.dma_ts), sample_count); 1509 1510 while (transferred_len >= sample_size) { 1511 /* 1512 * for all the values in the current sample, 1513 * adjust the values inside the buffer for oversampling 1514 */ 1515 at91_adc_adjust_val_osr_array(st, 1516 &st->dma_st.rx_buf[st->dma_st.buf_idx], 1517 sample_size); 1518 1519 iio_push_to_buffers_with_timestamp(indio_dev, 1520 (st->dma_st.rx_buf + st->dma_st.buf_idx), 1521 (st->dma_st.dma_ts + interval * sample_index)); 1522 /* adjust remaining length */ 1523 transferred_len -= sample_size; 1524 /* adjust buffer index */ 1525 st->dma_st.buf_idx += sample_size; 1526 /* in case of reaching end of buffer, reset index */ 1527 if (st->dma_st.buf_idx >= st->dma_st.rx_buf_sz) 1528 st->dma_st.buf_idx = 0; 1529 sample_index++; 1530 } 1531 /* adjust saved time for next transfer handling */ 1532 st->dma_st.dma_ts = iio_get_time_ns(indio_dev); 1533 } 1534 1535 static irqreturn_t at91_adc_trigger_handler(int irq, void *p) 1536 { 1537 struct iio_poll_func *pf = p; 1538 struct iio_dev *indio_dev = pf->indio_dev; 1539 struct at91_adc_state *st = iio_priv(indio_dev); 1540 1541 /* 1542 * If it's not our trigger, start a conversion now, as we are 1543 * actually polling the trigger now. 1544 */ 1545 if (iio_trigger_validate_own_device(indio_dev->trig, indio_dev)) 1546 at91_adc_writel(st, CR, AT91_SAMA5D2_CR_START); 1547 1548 if (st->dma_st.dma_chan) 1549 at91_adc_trigger_handler_dma(indio_dev); 1550 else 1551 at91_adc_trigger_handler_nodma(indio_dev, pf); 1552 1553 iio_trigger_notify_done(indio_dev->trig); 1554 1555 return IRQ_HANDLED; 1556 } 1557 1558 static unsigned at91_adc_startup_time(unsigned startup_time_min, 1559 unsigned adc_clk_khz) 1560 { 1561 static const unsigned int startup_lookup[] = { 1562 0, 8, 16, 24, 1563 64, 80, 96, 112, 1564 512, 576, 640, 704, 1565 768, 832, 896, 960 1566 }; 1567 unsigned ticks_min, i; 1568 1569 /* 1570 * Since the adc frequency is checked before, there is no reason 1571 * to not meet the startup time constraint. 1572 */ 1573 1574 ticks_min = startup_time_min * adc_clk_khz / 1000; 1575 for (i = 0; i < ARRAY_SIZE(startup_lookup); i++) 1576 if (startup_lookup[i] > ticks_min) 1577 break; 1578 1579 return i; 1580 } 1581 1582 static void at91_adc_setup_samp_freq(struct iio_dev *indio_dev, unsigned freq, 1583 unsigned int startup_time, 1584 unsigned int tracktim) 1585 { 1586 struct at91_adc_state *st = iio_priv(indio_dev); 1587 unsigned f_per, prescal, startup, mr; 1588 int ret; 1589 1590 f_per = clk_get_rate(st->per_clk); 1591 prescal = (f_per / (2 * freq)) - 1; 1592 1593 startup = at91_adc_startup_time(startup_time, freq / 1000); 1594 1595 ret = pm_runtime_resume_and_get(st->dev); 1596 if (ret < 0) 1597 return; 1598 1599 mr = at91_adc_readl(st, MR); 1600 mr &= ~(AT91_SAMA5D2_MR_STARTUP_MASK | AT91_SAMA5D2_MR_PRESCAL_MASK); 1601 mr |= AT91_SAMA5D2_MR_STARTUP(startup); 1602 mr |= AT91_SAMA5D2_MR_PRESCAL(prescal); 1603 mr |= AT91_SAMA5D2_MR_TRACKTIM(tracktim); 1604 at91_adc_writel(st, MR, mr); 1605 1606 pm_runtime_mark_last_busy(st->dev); 1607 pm_runtime_put_autosuspend(st->dev); 1608 1609 dev_dbg(&indio_dev->dev, "freq: %u, startup: %u, prescal: %u, tracktim=%u\n", 1610 freq, startup, prescal, tracktim); 1611 st->current_sample_rate = freq; 1612 } 1613 1614 static inline unsigned at91_adc_get_sample_freq(struct at91_adc_state *st) 1615 { 1616 return st->current_sample_rate; 1617 } 1618 1619 static void at91_adc_touch_data_handler(struct iio_dev *indio_dev) 1620 { 1621 struct at91_adc_state *st = iio_priv(indio_dev); 1622 u8 bit; 1623 u16 val; 1624 int i = 0; 1625 1626 for_each_set_bit(bit, indio_dev->active_scan_mask, 1627 st->soc_info.platform->max_index + 1) { 1628 struct iio_chan_spec const *chan = 1629 at91_adc_chan_get(indio_dev, bit); 1630 1631 if (chan->type == IIO_POSITIONRELATIVE) 1632 at91_adc_read_position(st, chan->channel, &val); 1633 else if (chan->type == IIO_PRESSURE) 1634 at91_adc_read_pressure(st, chan->channel, &val); 1635 else 1636 continue; 1637 st->buffer[i] = val; 1638 i++; 1639 } 1640 /* 1641 * Schedule work to push to buffers. 1642 * This is intended to push to the callback buffer that another driver 1643 * registered. We are still in a handler from our IRQ. If we push 1644 * directly, it means the other driver has it's callback called 1645 * from our IRQ context. Which is something we better avoid. 1646 * Let's schedule it after our IRQ is completed. 1647 */ 1648 schedule_work(&st->touch_st.workq); 1649 } 1650 1651 static void at91_adc_pen_detect_interrupt(struct at91_adc_state *st) 1652 { 1653 at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_PEN); 1654 at91_adc_writel(st, IER, AT91_SAMA5D2_IER_NOPEN | 1655 AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY | 1656 AT91_SAMA5D2_IER_PRDY); 1657 at91_adc_writel(st, TRGR, AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC | 1658 AT91_SAMA5D2_TRGR_TRGPER(st->touch_st.sample_period_val)); 1659 st->touch_st.touching = true; 1660 } 1661 1662 static void at91_adc_no_pen_detect_interrupt(struct iio_dev *indio_dev) 1663 { 1664 struct at91_adc_state *st = iio_priv(indio_dev); 1665 1666 at91_adc_writel(st, TRGR, AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER); 1667 at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_NOPEN | 1668 AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY | 1669 AT91_SAMA5D2_IER_PRDY); 1670 st->touch_st.touching = false; 1671 1672 at91_adc_touch_data_handler(indio_dev); 1673 1674 at91_adc_writel(st, IER, AT91_SAMA5D2_IER_PEN); 1675 } 1676 1677 static void at91_adc_workq_handler(struct work_struct *workq) 1678 { 1679 struct at91_adc_touch *touch_st = container_of(workq, 1680 struct at91_adc_touch, workq); 1681 struct at91_adc_state *st = container_of(touch_st, 1682 struct at91_adc_state, touch_st); 1683 struct iio_dev *indio_dev = st->indio_dev; 1684 1685 iio_push_to_buffers(indio_dev, st->buffer); 1686 } 1687 1688 static irqreturn_t at91_adc_interrupt(int irq, void *private) 1689 { 1690 struct iio_dev *indio = private; 1691 struct at91_adc_state *st = iio_priv(indio); 1692 u32 status, eoc, imr, eoc_imr; 1693 u32 rdy_mask = AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY | 1694 AT91_SAMA5D2_IER_PRDY; 1695 1696 at91_adc_irq_status(st, &status, &eoc); 1697 at91_adc_irq_mask(st, &imr, &eoc_imr); 1698 1699 if (!(status & imr) && !(eoc & eoc_imr)) 1700 return IRQ_NONE; 1701 if (status & AT91_SAMA5D2_IER_PEN) { 1702 /* pen detected IRQ */ 1703 at91_adc_pen_detect_interrupt(st); 1704 } else if ((status & AT91_SAMA5D2_IER_NOPEN)) { 1705 /* nopen detected IRQ */ 1706 at91_adc_no_pen_detect_interrupt(indio); 1707 } else if ((status & AT91_SAMA5D2_ISR_PENS) && 1708 ((status & rdy_mask) == rdy_mask)) { 1709 /* periodic trigger IRQ - during pen sense */ 1710 at91_adc_touch_data_handler(indio); 1711 } else if (status & AT91_SAMA5D2_ISR_PENS) { 1712 /* 1713 * touching, but the measurements are not ready yet. 1714 * read and ignore. 1715 */ 1716 status = at91_adc_readl(st, XPOSR); 1717 status = at91_adc_readl(st, YPOSR); 1718 status = at91_adc_readl(st, PRESSR); 1719 } else if (iio_buffer_enabled(indio) && 1720 (status & AT91_SAMA5D2_IER_DRDY)) { 1721 /* triggered buffer without DMA */ 1722 disable_irq_nosync(irq); 1723 iio_trigger_poll(indio->trig); 1724 } else if (iio_buffer_enabled(indio) && st->dma_st.dma_chan) { 1725 /* triggered buffer with DMA - should not happen */ 1726 disable_irq_nosync(irq); 1727 WARN(true, "Unexpected irq occurred\n"); 1728 } else if (!iio_buffer_enabled(indio)) { 1729 /* software requested conversion */ 1730 st->conversion_value = at91_adc_read_chan(st, st->chan->address); 1731 st->conversion_done = true; 1732 wake_up_interruptible(&st->wq_data_available); 1733 } 1734 return IRQ_HANDLED; 1735 } 1736 1737 /* This needs to be called with direct mode claimed and st->lock locked. */ 1738 static int at91_adc_read_info_raw(struct iio_dev *indio_dev, 1739 struct iio_chan_spec const *chan, int *val) 1740 { 1741 struct at91_adc_state *st = iio_priv(indio_dev); 1742 u16 tmp_val; 1743 int ret; 1744 1745 ret = pm_runtime_resume_and_get(st->dev); 1746 if (ret < 0) 1747 return ret; 1748 1749 /* 1750 * Keep in mind that we cannot use software trigger or touchscreen 1751 * if external trigger is enabled 1752 */ 1753 if (chan->type == IIO_POSITIONRELATIVE) { 1754 ret = at91_adc_read_position(st, chan->channel, 1755 &tmp_val); 1756 *val = tmp_val; 1757 if (ret > 0) 1758 ret = at91_adc_adjust_val_osr(st, val); 1759 1760 goto pm_runtime_put; 1761 } 1762 if (chan->type == IIO_PRESSURE) { 1763 ret = at91_adc_read_pressure(st, chan->channel, 1764 &tmp_val); 1765 *val = tmp_val; 1766 if (ret > 0) 1767 ret = at91_adc_adjust_val_osr(st, val); 1768 1769 goto pm_runtime_put; 1770 } 1771 1772 /* in this case we have a voltage or temperature channel */ 1773 1774 st->chan = chan; 1775 1776 at91_adc_cor(st, chan); 1777 at91_adc_writel(st, CHER, BIT(chan->channel)); 1778 /* 1779 * TEMPMR.TEMPON needs to update after CHER otherwise if none 1780 * of the channels are enabled and TEMPMR.TEMPON = 1 will 1781 * trigger DRDY interruption while preparing for temperature read. 1782 */ 1783 if (chan->type == IIO_TEMP) 1784 at91_adc_writel(st, TEMPMR, AT91_SAMA5D2_TEMPMR_TEMPON); 1785 at91_adc_eoc_ena(st, chan->channel); 1786 at91_adc_writel(st, CR, AT91_SAMA5D2_CR_START); 1787 1788 ret = wait_event_interruptible_timeout(st->wq_data_available, 1789 st->conversion_done, 1790 msecs_to_jiffies(1000)); 1791 if (ret == 0) 1792 ret = -ETIMEDOUT; 1793 1794 if (ret > 0) { 1795 *val = st->conversion_value; 1796 ret = at91_adc_adjust_val_osr(st, val); 1797 if (chan->scan_type.sign == 's') 1798 *val = sign_extend32(*val, 1799 chan->scan_type.realbits - 1); 1800 st->conversion_done = false; 1801 } 1802 1803 at91_adc_eoc_dis(st, st->chan->channel); 1804 if (chan->type == IIO_TEMP) 1805 at91_adc_writel(st, TEMPMR, 0U); 1806 at91_adc_writel(st, CHDR, BIT(chan->channel)); 1807 1808 /* Needed to ACK the DRDY interruption */ 1809 at91_adc_readl(st, LCDR); 1810 1811 pm_runtime_put: 1812 pm_runtime_mark_last_busy(st->dev); 1813 pm_runtime_put_autosuspend(st->dev); 1814 return ret; 1815 } 1816 1817 static int at91_adc_read_info_locked(struct iio_dev *indio_dev, 1818 struct iio_chan_spec const *chan, int *val) 1819 { 1820 struct at91_adc_state *st = iio_priv(indio_dev); 1821 1822 guard(mutex)(&st->lock); 1823 1824 return at91_adc_read_info_raw(indio_dev, chan, val); 1825 } 1826 1827 static void at91_adc_temp_sensor_configure(struct at91_adc_state *st, 1828 bool start) 1829 { 1830 u32 sample_rate, oversampling_ratio; 1831 u32 startup_time, tracktim, trackx; 1832 1833 if (start) { 1834 /* 1835 * Configure the sensor for best accuracy: 10MHz frequency, 1836 * oversampling rate of 256, tracktim=0xf and trackx=1. 1837 */ 1838 sample_rate = 10 * MEGA; 1839 oversampling_ratio = 256; 1840 startup_time = AT91_SAMA5D2_MR_STARTUP_TS_MIN; 1841 tracktim = AT91_SAMA5D2_MR_TRACKTIM_TS; 1842 trackx = AT91_SAMA5D2_TRACKX_TS; 1843 1844 st->temp_st.saved_sample_rate = st->current_sample_rate; 1845 st->temp_st.saved_oversampling = st->oversampling_ratio; 1846 } else { 1847 /* Go back to previous settings. */ 1848 sample_rate = st->temp_st.saved_sample_rate; 1849 oversampling_ratio = st->temp_st.saved_oversampling; 1850 startup_time = st->soc_info.startup_time; 1851 tracktim = 0; 1852 trackx = 0; 1853 } 1854 1855 at91_adc_setup_samp_freq(st->indio_dev, sample_rate, startup_time, 1856 tracktim); 1857 at91_adc_config_emr(st, oversampling_ratio, trackx); 1858 } 1859 1860 static int at91_adc_read_temp(struct iio_dev *indio_dev, 1861 struct iio_chan_spec const *chan, int *val) 1862 { 1863 struct at91_adc_state *st = iio_priv(indio_dev); 1864 struct at91_adc_temp_sensor_clb *clb = &st->soc_info.temp_sensor_clb; 1865 u64 div1, div2; 1866 u32 tmp; 1867 int ret, vbg, vtemp; 1868 1869 guard(mutex)(&st->lock); 1870 1871 ret = pm_runtime_resume_and_get(st->dev); 1872 if (ret < 0) 1873 return ret; 1874 1875 at91_adc_temp_sensor_configure(st, true); 1876 1877 /* Read VBG. */ 1878 tmp = at91_adc_readl(st, ACR); 1879 tmp |= AT91_SAMA5D2_ACR_SRCLCH; 1880 at91_adc_writel(st, ACR, tmp); 1881 ret = at91_adc_read_info_raw(indio_dev, chan, &vbg); 1882 if (ret < 0) 1883 goto restore_config; 1884 1885 /* Read VTEMP. */ 1886 tmp &= ~AT91_SAMA5D2_ACR_SRCLCH; 1887 at91_adc_writel(st, ACR, tmp); 1888 ret = at91_adc_read_info_raw(indio_dev, chan, &vtemp); 1889 1890 restore_config: 1891 /* Revert previous settings. */ 1892 at91_adc_temp_sensor_configure(st, false); 1893 pm_runtime_mark_last_busy(st->dev); 1894 pm_runtime_put_autosuspend(st->dev); 1895 if (ret < 0) 1896 return ret; 1897 1898 /* 1899 * Temp[milli] = p1[milli] + (vtemp * clb->p6 - clb->p4 * vbg)/ 1900 * (vbg * AT91_ADC_TS_VTEMP_DT) 1901 */ 1902 div1 = DIV_ROUND_CLOSEST_ULL(((u64)vtemp * clb->p6), vbg); 1903 div1 = DIV_ROUND_CLOSEST_ULL((div1 * 1000), AT91_ADC_TS_VTEMP_DT); 1904 div2 = DIV_ROUND_CLOSEST_ULL((u64)clb->p4, AT91_ADC_TS_VTEMP_DT); 1905 div2 *= 1000; 1906 *val = clb->p1 + (int)div1 - (int)div2; 1907 1908 return ret; 1909 } 1910 1911 static int at91_adc_read_raw(struct iio_dev *indio_dev, 1912 struct iio_chan_spec const *chan, 1913 int *val, int *val2, long mask) 1914 { 1915 struct at91_adc_state *st = iio_priv(indio_dev); 1916 int ret; 1917 1918 switch (mask) { 1919 case IIO_CHAN_INFO_RAW: 1920 if (!iio_device_claim_direct(indio_dev)) 1921 return -EBUSY; 1922 1923 ret = at91_adc_read_info_locked(indio_dev, chan, val); 1924 iio_device_release_direct(indio_dev); 1925 return ret; 1926 1927 case IIO_CHAN_INFO_SCALE: 1928 *val = st->vref_uv / 1000; 1929 if (chan->differential) 1930 *val *= 2; 1931 *val2 = chan->scan_type.realbits; 1932 return IIO_VAL_FRACTIONAL_LOG2; 1933 1934 case IIO_CHAN_INFO_PROCESSED: 1935 if (chan->type != IIO_TEMP) 1936 return -EINVAL; 1937 if (!iio_device_claim_direct(indio_dev)) 1938 return -EBUSY; 1939 1940 ret = at91_adc_read_temp(indio_dev, chan, val); 1941 iio_device_release_direct(indio_dev); 1942 1943 return ret; 1944 1945 case IIO_CHAN_INFO_SAMP_FREQ: 1946 *val = at91_adc_get_sample_freq(st); 1947 return IIO_VAL_INT; 1948 1949 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1950 *val = st->oversampling_ratio; 1951 return IIO_VAL_INT; 1952 1953 default: 1954 return -EINVAL; 1955 } 1956 } 1957 1958 static int at91_adc_write_raw(struct iio_dev *indio_dev, 1959 struct iio_chan_spec const *chan, 1960 int val, int val2, long mask) 1961 { 1962 struct at91_adc_state *st = iio_priv(indio_dev); 1963 int ret; 1964 1965 switch (mask) { 1966 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1967 /* if no change, optimize out */ 1968 if (val == st->oversampling_ratio) 1969 return 0; 1970 1971 if (!iio_device_claim_direct(indio_dev)) 1972 return -EBUSY; 1973 mutex_lock(&st->lock); 1974 /* update ratio */ 1975 ret = at91_adc_config_emr(st, val, 0); 1976 mutex_unlock(&st->lock); 1977 iio_device_release_direct(indio_dev); 1978 return ret; 1979 case IIO_CHAN_INFO_SAMP_FREQ: 1980 if (val < st->soc_info.min_sample_rate || 1981 val > st->soc_info.max_sample_rate) 1982 return -EINVAL; 1983 1984 if (!iio_device_claim_direct(indio_dev)) 1985 return -EBUSY; 1986 mutex_lock(&st->lock); 1987 at91_adc_setup_samp_freq(indio_dev, val, 1988 st->soc_info.startup_time, 0); 1989 mutex_unlock(&st->lock); 1990 iio_device_release_direct(indio_dev); 1991 return 0; 1992 default: 1993 return -EINVAL; 1994 } 1995 } 1996 1997 static int at91_adc_read_avail(struct iio_dev *indio_dev, 1998 struct iio_chan_spec const *chan, 1999 const int **vals, int *type, int *length, 2000 long mask) 2001 { 2002 struct at91_adc_state *st = iio_priv(indio_dev); 2003 2004 switch (mask) { 2005 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 2006 *vals = (int *)st->soc_info.platform->oversampling_avail; 2007 *type = IIO_VAL_INT; 2008 *length = st->soc_info.platform->oversampling_avail_no; 2009 return IIO_AVAIL_LIST; 2010 default: 2011 return -EINVAL; 2012 } 2013 } 2014 2015 static void at91_adc_dma_init(struct at91_adc_state *st) 2016 { 2017 struct device *dev = &st->indio_dev->dev; 2018 struct dma_slave_config config = {0}; 2019 /* we have 2 bytes for each channel */ 2020 unsigned int sample_size = st->soc_info.platform->nr_channels * 2; 2021 /* 2022 * We make the buffer double the size of the fifo, 2023 * such that DMA uses one half of the buffer (full fifo size) 2024 * and the software uses the other half to read/write. 2025 */ 2026 unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE * 2027 sample_size * 2, PAGE_SIZE); 2028 2029 if (st->dma_st.dma_chan) 2030 return; 2031 2032 st->dma_st.dma_chan = dma_request_chan(dev, "rx"); 2033 if (IS_ERR(st->dma_st.dma_chan)) { 2034 dev_info(dev, "can't get DMA channel\n"); 2035 st->dma_st.dma_chan = NULL; 2036 goto dma_exit; 2037 } 2038 2039 st->dma_st.rx_buf = dma_alloc_coherent(st->dma_st.dma_chan->device->dev, 2040 pages * PAGE_SIZE, 2041 &st->dma_st.rx_dma_buf, 2042 GFP_KERNEL); 2043 if (!st->dma_st.rx_buf) { 2044 dev_info(dev, "can't allocate coherent DMA area\n"); 2045 goto dma_chan_disable; 2046 } 2047 2048 /* Configure DMA channel to read data register */ 2049 config.direction = DMA_DEV_TO_MEM; 2050 config.src_addr = (phys_addr_t)(st->dma_st.phys_addr 2051 + st->soc_info.platform->layout->LCDR); 2052 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 2053 config.src_maxburst = 1; 2054 config.dst_maxburst = 1; 2055 2056 if (dmaengine_slave_config(st->dma_st.dma_chan, &config)) { 2057 dev_info(dev, "can't configure DMA slave\n"); 2058 goto dma_free_area; 2059 } 2060 2061 dev_info(dev, "using %s for rx DMA transfers\n", 2062 dma_chan_name(st->dma_st.dma_chan)); 2063 2064 return; 2065 2066 dma_free_area: 2067 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE, 2068 st->dma_st.rx_buf, st->dma_st.rx_dma_buf); 2069 dma_chan_disable: 2070 dma_release_channel(st->dma_st.dma_chan); 2071 st->dma_st.dma_chan = NULL; 2072 dma_exit: 2073 dev_info(dev, "continuing without DMA support\n"); 2074 } 2075 2076 static void at91_adc_dma_disable(struct at91_adc_state *st) 2077 { 2078 struct device *dev = &st->indio_dev->dev; 2079 /* we have 2 bytes for each channel */ 2080 unsigned int sample_size = st->soc_info.platform->nr_channels * 2; 2081 unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE * 2082 sample_size * 2, PAGE_SIZE); 2083 2084 /* if we are not using DMA, just return */ 2085 if (!st->dma_st.dma_chan) 2086 return; 2087 2088 /* wait for all transactions to be terminated first*/ 2089 dmaengine_terminate_sync(st->dma_st.dma_chan); 2090 2091 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE, 2092 st->dma_st.rx_buf, st->dma_st.rx_dma_buf); 2093 dma_release_channel(st->dma_st.dma_chan); 2094 st->dma_st.dma_chan = NULL; 2095 2096 dev_info(dev, "continuing without DMA support\n"); 2097 } 2098 2099 static int at91_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val) 2100 { 2101 struct at91_adc_state *st = iio_priv(indio_dev); 2102 int ret; 2103 2104 if (val > AT91_HWFIFO_MAX_SIZE) 2105 val = AT91_HWFIFO_MAX_SIZE; 2106 2107 if (!st->selected_trig->hw_trig) { 2108 dev_dbg(&indio_dev->dev, "we need hw trigger for DMA\n"); 2109 return 0; 2110 } 2111 2112 dev_dbg(&indio_dev->dev, "new watermark is %u\n", val); 2113 st->dma_st.watermark = val; 2114 2115 /* 2116 * The logic here is: if we have watermark 1, it means we do 2117 * each conversion with it's own IRQ, thus we don't need DMA. 2118 * If the watermark is higher, we do DMA to do all the transfers in bulk 2119 */ 2120 2121 if (val == 1) 2122 at91_adc_dma_disable(st); 2123 else if (val > 1) 2124 at91_adc_dma_init(st); 2125 2126 /* 2127 * We can start the DMA only after setting the watermark and 2128 * having the DMA initialization completed 2129 */ 2130 ret = at91_adc_buffer_prepare(indio_dev); 2131 if (ret) 2132 at91_adc_dma_disable(st); 2133 2134 return ret; 2135 } 2136 2137 static int at91_adc_update_scan_mode(struct iio_dev *indio_dev, 2138 const unsigned long *scan_mask) 2139 { 2140 struct at91_adc_state *st = iio_priv(indio_dev); 2141 2142 if (bitmap_subset(scan_mask, &st->touch_st.channels_bitmask, 2143 st->soc_info.platform->max_index + 1)) 2144 return 0; 2145 /* 2146 * if the new bitmap is a combination of touchscreen and regular 2147 * channels, then we are not fine 2148 */ 2149 if (bitmap_intersects(&st->touch_st.channels_bitmask, scan_mask, 2150 st->soc_info.platform->max_index + 1)) 2151 return -EINVAL; 2152 return 0; 2153 } 2154 2155 static void at91_adc_hw_init(struct iio_dev *indio_dev) 2156 { 2157 struct at91_adc_state *st = iio_priv(indio_dev); 2158 2159 at91_adc_writel(st, CR, AT91_SAMA5D2_CR_SWRST); 2160 if (st->soc_info.platform->layout->EOC_IDR) 2161 at91_adc_writel(st, EOC_IDR, 0xffffffff); 2162 at91_adc_writel(st, IDR, 0xffffffff); 2163 /* 2164 * Transfer field must be set to 2 according to the datasheet and 2165 * allows different analog settings for each channel. 2166 */ 2167 at91_adc_writel(st, MR, 2168 AT91_SAMA5D2_MR_TRANSFER(2) | AT91_SAMA5D2_MR_ANACH); 2169 2170 at91_adc_setup_samp_freq(indio_dev, st->soc_info.min_sample_rate, 2171 st->soc_info.startup_time, 0); 2172 2173 /* configure extended mode register */ 2174 at91_adc_config_emr(st, st->oversampling_ratio, 0); 2175 } 2176 2177 static ssize_t at91_adc_get_fifo_state(struct device *dev, 2178 struct device_attribute *attr, char *buf) 2179 { 2180 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 2181 struct at91_adc_state *st = iio_priv(indio_dev); 2182 2183 return sysfs_emit(buf, "%d\n", !!st->dma_st.dma_chan); 2184 } 2185 2186 static ssize_t at91_adc_get_watermark(struct device *dev, 2187 struct device_attribute *attr, char *buf) 2188 { 2189 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 2190 struct at91_adc_state *st = iio_priv(indio_dev); 2191 2192 return sysfs_emit(buf, "%d\n", st->dma_st.watermark); 2193 } 2194 2195 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444, 2196 at91_adc_get_fifo_state, NULL, 0); 2197 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444, 2198 at91_adc_get_watermark, NULL, 0); 2199 2200 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_min, "2"); 2201 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_max, AT91_HWFIFO_MAX_SIZE_STR); 2202 2203 static const struct iio_dev_attr *at91_adc_fifo_attributes[] = { 2204 &iio_dev_attr_hwfifo_watermark_min, 2205 &iio_dev_attr_hwfifo_watermark_max, 2206 &iio_dev_attr_hwfifo_watermark, 2207 &iio_dev_attr_hwfifo_enabled, 2208 NULL, 2209 }; 2210 2211 static const struct iio_info at91_adc_info = { 2212 .read_avail = &at91_adc_read_avail, 2213 .read_raw = &at91_adc_read_raw, 2214 .write_raw = &at91_adc_write_raw, 2215 .update_scan_mode = &at91_adc_update_scan_mode, 2216 .fwnode_xlate = &at91_adc_fwnode_xlate, 2217 .hwfifo_set_watermark = &at91_adc_set_watermark, 2218 }; 2219 2220 static int at91_adc_buffer_and_trigger_init(struct device *dev, 2221 struct iio_dev *indio) 2222 { 2223 struct at91_adc_state *st = iio_priv(indio); 2224 const struct iio_dev_attr **fifo_attrs; 2225 int ret; 2226 2227 if (st->selected_trig->hw_trig) 2228 fifo_attrs = at91_adc_fifo_attributes; 2229 else 2230 fifo_attrs = NULL; 2231 2232 ret = devm_iio_triggered_buffer_setup_ext(&indio->dev, indio, 2233 &iio_pollfunc_store_time, &at91_adc_trigger_handler, 2234 IIO_BUFFER_DIRECTION_IN, &at91_buffer_setup_ops, fifo_attrs); 2235 if (ret < 0) { 2236 dev_err(dev, "couldn't initialize the buffer.\n"); 2237 return ret; 2238 } 2239 2240 if (!st->selected_trig->hw_trig) 2241 return 0; 2242 2243 st->trig = at91_adc_allocate_trigger(indio, st->selected_trig->name); 2244 if (IS_ERR(st->trig)) { 2245 dev_err(dev, "could not allocate trigger\n"); 2246 return PTR_ERR(st->trig); 2247 } 2248 2249 /* 2250 * Initially the iio buffer has a length of 2 and 2251 * a watermark of 1 2252 */ 2253 st->dma_st.watermark = 1; 2254 2255 return 0; 2256 } 2257 2258 static int at91_adc_temp_sensor_init(struct at91_adc_state *st, 2259 struct device *dev) 2260 { 2261 struct at91_adc_temp_sensor_clb *clb = &st->soc_info.temp_sensor_clb; 2262 struct nvmem_cell *temp_calib; 2263 u32 *buf; 2264 size_t len; 2265 int ret = 0; 2266 2267 if (!st->soc_info.platform->temp_sensor) 2268 return 0; 2269 2270 /* Get the calibration data from NVMEM. */ 2271 temp_calib = devm_nvmem_cell_get(dev, "temperature_calib"); 2272 if (IS_ERR(temp_calib)) { 2273 ret = PTR_ERR(temp_calib); 2274 if (ret != -ENOENT) 2275 dev_err(dev, "Failed to get temperature_calib cell!\n"); 2276 return ret; 2277 } 2278 2279 buf = nvmem_cell_read(temp_calib, &len); 2280 if (IS_ERR(buf)) { 2281 dev_err(dev, "Failed to read calibration data!\n"); 2282 return PTR_ERR(buf); 2283 } 2284 if (len < AT91_ADC_TS_CLB_IDX_MAX * 4) { 2285 dev_err(dev, "Invalid calibration data!\n"); 2286 ret = -EINVAL; 2287 goto free_buf; 2288 } 2289 2290 /* Store calibration data for later use. */ 2291 clb->p1 = buf[AT91_ADC_TS_CLB_IDX_P1]; 2292 clb->p4 = buf[AT91_ADC_TS_CLB_IDX_P4]; 2293 clb->p6 = buf[AT91_ADC_TS_CLB_IDX_P6]; 2294 2295 /* 2296 * We prepare here the conversion to milli to avoid doing it on hotpath. 2297 */ 2298 clb->p1 = clb->p1 * 1000; 2299 2300 free_buf: 2301 kfree(buf); 2302 return ret; 2303 } 2304 2305 static int at91_adc_probe(struct platform_device *pdev) 2306 { 2307 struct device *dev = &pdev->dev; 2308 struct iio_dev *indio_dev; 2309 struct at91_adc_state *st; 2310 struct resource *res; 2311 int ret, i, num_channels; 2312 u32 edge_type = IRQ_TYPE_NONE; 2313 2314 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st)); 2315 if (!indio_dev) 2316 return -ENOMEM; 2317 2318 st = iio_priv(indio_dev); 2319 st->indio_dev = indio_dev; 2320 2321 st->soc_info.platform = device_get_match_data(dev); 2322 2323 ret = at91_adc_temp_sensor_init(st, &pdev->dev); 2324 /* Don't register temperature channel if initialization failed. */ 2325 if (ret) 2326 num_channels = st->soc_info.platform->max_channels - 1; 2327 else 2328 num_channels = st->soc_info.platform->max_channels; 2329 2330 indio_dev->name = dev_name(&pdev->dev); 2331 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE; 2332 indio_dev->info = &at91_adc_info; 2333 indio_dev->channels = *st->soc_info.platform->adc_channels; 2334 indio_dev->num_channels = num_channels; 2335 2336 bitmap_set(&st->touch_st.channels_bitmask, 2337 st->soc_info.platform->touch_chan_x, 1); 2338 bitmap_set(&st->touch_st.channels_bitmask, 2339 st->soc_info.platform->touch_chan_y, 1); 2340 bitmap_set(&st->touch_st.channels_bitmask, 2341 st->soc_info.platform->touch_chan_p, 1); 2342 2343 st->oversampling_ratio = 1; 2344 2345 ret = device_property_read_u32(dev, "atmel,min-sample-rate-hz", 2346 &st->soc_info.min_sample_rate); 2347 if (ret) { 2348 dev_err(&pdev->dev, 2349 "invalid or missing value for atmel,min-sample-rate-hz\n"); 2350 return ret; 2351 } 2352 2353 ret = device_property_read_u32(dev, "atmel,max-sample-rate-hz", 2354 &st->soc_info.max_sample_rate); 2355 if (ret) { 2356 dev_err(&pdev->dev, 2357 "invalid or missing value for atmel,max-sample-rate-hz\n"); 2358 return ret; 2359 } 2360 2361 ret = device_property_read_u32(dev, "atmel,startup-time-ms", 2362 &st->soc_info.startup_time); 2363 if (ret) { 2364 dev_err(&pdev->dev, 2365 "invalid or missing value for atmel,startup-time-ms\n"); 2366 return ret; 2367 } 2368 2369 ret = device_property_read_u32(dev, "atmel,trigger-edge-type", 2370 &edge_type); 2371 if (ret) { 2372 dev_dbg(&pdev->dev, 2373 "atmel,trigger-edge-type not specified, only software trigger available\n"); 2374 } 2375 2376 st->selected_trig = NULL; 2377 2378 /* find the right trigger, or no trigger at all */ 2379 for (i = 0; i < st->soc_info.platform->hw_trig_cnt + 1; i++) 2380 if (at91_adc_trigger_list[i].edge_type == edge_type) { 2381 st->selected_trig = &at91_adc_trigger_list[i]; 2382 break; 2383 } 2384 2385 if (!st->selected_trig) { 2386 dev_err(&pdev->dev, "invalid external trigger edge value\n"); 2387 return -EINVAL; 2388 } 2389 2390 init_waitqueue_head(&st->wq_data_available); 2391 mutex_init(&st->lock); 2392 INIT_WORK(&st->touch_st.workq, at91_adc_workq_handler); 2393 2394 st->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2395 if (IS_ERR(st->base)) 2396 return PTR_ERR(st->base); 2397 2398 /* if we plan to use DMA, we need the physical address of the regs */ 2399 st->dma_st.phys_addr = res->start; 2400 2401 st->irq = platform_get_irq(pdev, 0); 2402 if (st->irq < 0) 2403 return st->irq; 2404 2405 st->per_clk = devm_clk_get(&pdev->dev, "adc_clk"); 2406 if (IS_ERR(st->per_clk)) 2407 return PTR_ERR(st->per_clk); 2408 2409 st->reg = devm_regulator_get(&pdev->dev, "vddana"); 2410 if (IS_ERR(st->reg)) 2411 return PTR_ERR(st->reg); 2412 2413 st->vref = devm_regulator_get(&pdev->dev, "vref"); 2414 if (IS_ERR(st->vref)) 2415 return PTR_ERR(st->vref); 2416 2417 ret = devm_request_irq(&pdev->dev, st->irq, at91_adc_interrupt, 0, 2418 pdev->dev.driver->name, indio_dev); 2419 if (ret) 2420 return ret; 2421 2422 ret = regulator_enable(st->reg); 2423 if (ret) 2424 return ret; 2425 2426 ret = regulator_enable(st->vref); 2427 if (ret) 2428 goto reg_disable; 2429 2430 st->vref_uv = regulator_get_voltage(st->vref); 2431 if (st->vref_uv <= 0) { 2432 ret = -EINVAL; 2433 goto vref_disable; 2434 } 2435 2436 ret = clk_prepare_enable(st->per_clk); 2437 if (ret) 2438 goto vref_disable; 2439 2440 platform_set_drvdata(pdev, indio_dev); 2441 st->dev = &pdev->dev; 2442 pm_runtime_set_autosuspend_delay(st->dev, 500); 2443 pm_runtime_use_autosuspend(st->dev); 2444 pm_runtime_set_active(st->dev); 2445 pm_runtime_enable(st->dev); 2446 pm_runtime_get_noresume(st->dev); 2447 2448 at91_adc_hw_init(indio_dev); 2449 2450 ret = at91_adc_buffer_and_trigger_init(&pdev->dev, indio_dev); 2451 if (ret < 0) 2452 goto err_pm_disable; 2453 2454 if (dma_coerce_mask_and_coherent(&indio_dev->dev, DMA_BIT_MASK(32))) 2455 dev_info(&pdev->dev, "cannot set DMA mask to 32-bit\n"); 2456 2457 ret = iio_device_register(indio_dev); 2458 if (ret < 0) 2459 goto dma_disable; 2460 2461 if (st->selected_trig->hw_trig) 2462 dev_info(&pdev->dev, "setting up trigger as %s\n", 2463 st->selected_trig->name); 2464 2465 dev_info(&pdev->dev, "version: %x\n", 2466 readl_relaxed(st->base + st->soc_info.platform->layout->VERSION)); 2467 2468 pm_runtime_mark_last_busy(st->dev); 2469 pm_runtime_put_autosuspend(st->dev); 2470 2471 return 0; 2472 2473 dma_disable: 2474 at91_adc_dma_disable(st); 2475 err_pm_disable: 2476 pm_runtime_put_noidle(st->dev); 2477 pm_runtime_disable(st->dev); 2478 pm_runtime_set_suspended(st->dev); 2479 pm_runtime_dont_use_autosuspend(st->dev); 2480 clk_disable_unprepare(st->per_clk); 2481 vref_disable: 2482 regulator_disable(st->vref); 2483 reg_disable: 2484 regulator_disable(st->reg); 2485 return ret; 2486 } 2487 2488 static void at91_adc_remove(struct platform_device *pdev) 2489 { 2490 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 2491 struct at91_adc_state *st = iio_priv(indio_dev); 2492 2493 iio_device_unregister(indio_dev); 2494 2495 at91_adc_dma_disable(st); 2496 2497 pm_runtime_disable(st->dev); 2498 pm_runtime_set_suspended(st->dev); 2499 clk_disable_unprepare(st->per_clk); 2500 2501 regulator_disable(st->vref); 2502 regulator_disable(st->reg); 2503 } 2504 2505 static int at91_adc_suspend(struct device *dev) 2506 { 2507 struct iio_dev *indio_dev = dev_get_drvdata(dev); 2508 struct at91_adc_state *st = iio_priv(indio_dev); 2509 int ret; 2510 2511 ret = pm_runtime_resume_and_get(st->dev); 2512 if (ret < 0) 2513 return ret; 2514 2515 if (iio_buffer_enabled(indio_dev)) 2516 at91_adc_buffer_postdisable(indio_dev); 2517 2518 /* 2519 * Do a sofware reset of the ADC before we go to suspend. 2520 * this will ensure that all pins are free from being muxed by the ADC 2521 * and can be used by for other devices. 2522 * Otherwise, ADC will hog them and we can't go to suspend mode. 2523 */ 2524 at91_adc_writel(st, CR, AT91_SAMA5D2_CR_SWRST); 2525 2526 pm_runtime_mark_last_busy(st->dev); 2527 pm_runtime_put_noidle(st->dev); 2528 clk_disable_unprepare(st->per_clk); 2529 regulator_disable(st->vref); 2530 regulator_disable(st->reg); 2531 2532 return pinctrl_pm_select_sleep_state(dev); 2533 } 2534 2535 static int at91_adc_resume(struct device *dev) 2536 { 2537 struct iio_dev *indio_dev = dev_get_drvdata(dev); 2538 struct at91_adc_state *st = iio_priv(indio_dev); 2539 int ret; 2540 2541 ret = pinctrl_pm_select_default_state(dev); 2542 if (ret) 2543 goto resume_failed; 2544 2545 ret = regulator_enable(st->reg); 2546 if (ret) 2547 goto resume_failed; 2548 2549 ret = regulator_enable(st->vref); 2550 if (ret) 2551 goto reg_disable_resume; 2552 2553 ret = clk_prepare_enable(st->per_clk); 2554 if (ret) 2555 goto vref_disable_resume; 2556 2557 pm_runtime_get_noresume(st->dev); 2558 2559 at91_adc_hw_init(indio_dev); 2560 2561 /* reconfiguring trigger hardware state */ 2562 if (iio_buffer_enabled(indio_dev)) { 2563 ret = at91_adc_buffer_prepare(indio_dev); 2564 if (ret) 2565 goto pm_runtime_put; 2566 2567 at91_adc_configure_trigger_registers(st, true); 2568 } 2569 2570 pm_runtime_mark_last_busy(st->dev); 2571 pm_runtime_put_autosuspend(st->dev); 2572 2573 return 0; 2574 2575 pm_runtime_put: 2576 pm_runtime_mark_last_busy(st->dev); 2577 pm_runtime_put_noidle(st->dev); 2578 clk_disable_unprepare(st->per_clk); 2579 vref_disable_resume: 2580 regulator_disable(st->vref); 2581 reg_disable_resume: 2582 regulator_disable(st->reg); 2583 resume_failed: 2584 dev_err(&indio_dev->dev, "failed to resume\n"); 2585 return ret; 2586 } 2587 2588 static int at91_adc_runtime_suspend(struct device *dev) 2589 { 2590 struct iio_dev *indio_dev = dev_get_drvdata(dev); 2591 struct at91_adc_state *st = iio_priv(indio_dev); 2592 2593 clk_disable(st->per_clk); 2594 2595 return 0; 2596 } 2597 2598 static int at91_adc_runtime_resume(struct device *dev) 2599 { 2600 struct iio_dev *indio_dev = dev_get_drvdata(dev); 2601 struct at91_adc_state *st = iio_priv(indio_dev); 2602 2603 return clk_enable(st->per_clk); 2604 } 2605 2606 static const struct dev_pm_ops at91_adc_pm_ops = { 2607 SYSTEM_SLEEP_PM_OPS(at91_adc_suspend, at91_adc_resume) 2608 RUNTIME_PM_OPS(at91_adc_runtime_suspend, at91_adc_runtime_resume, 2609 NULL) 2610 }; 2611 2612 static const struct of_device_id at91_adc_dt_match[] = { 2613 { 2614 .compatible = "atmel,sama5d2-adc", 2615 .data = (const void *)&sama5d2_platform, 2616 }, { 2617 .compatible = "microchip,sama7g5-adc", 2618 .data = (const void *)&sama7g5_platform, 2619 }, { 2620 /* sentinel */ 2621 } 2622 }; 2623 MODULE_DEVICE_TABLE(of, at91_adc_dt_match); 2624 2625 static struct platform_driver at91_adc_driver = { 2626 .probe = at91_adc_probe, 2627 .remove = at91_adc_remove, 2628 .driver = { 2629 .name = "at91-sama5d2_adc", 2630 .of_match_table = at91_adc_dt_match, 2631 .pm = pm_ptr(&at91_adc_pm_ops), 2632 }, 2633 }; 2634 module_platform_driver(at91_adc_driver) 2635 2636 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@microchip.com>"); 2637 MODULE_AUTHOR("Eugen Hristev <eugen.hristev@microchip.com"); 2638 MODULE_DESCRIPTION("Atmel AT91 SAMA5D2 ADC"); 2639 MODULE_LICENSE("GPL v2"); 2640