1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * AD7124 SPI ADC driver 4 * 5 * Copyright 2018 Analog Devices Inc. 6 */ 7 #include <linux/bitfield.h> 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/device.h> 12 #include <linux/err.h> 13 #include <linux/interrupt.h> 14 #include <linux/kernel.h> 15 #include <linux/kfifo.h> 16 #include <linux/module.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/property.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/spi/spi.h> 21 22 #include <linux/iio/iio.h> 23 #include <linux/iio/adc/ad_sigma_delta.h> 24 #include <linux/iio/sysfs.h> 25 26 /* AD7124 registers */ 27 #define AD7124_COMMS 0x00 28 #define AD7124_STATUS 0x00 29 #define AD7124_ADC_CONTROL 0x01 30 #define AD7124_DATA 0x02 31 #define AD7124_IO_CONTROL_1 0x03 32 #define AD7124_IO_CONTROL_2 0x04 33 #define AD7124_ID 0x05 34 #define AD7124_ERROR 0x06 35 #define AD7124_ERROR_EN 0x07 36 #define AD7124_MCLK_COUNT 0x08 37 #define AD7124_CHANNEL(x) (0x09 + (x)) 38 #define AD7124_CONFIG(x) (0x19 + (x)) 39 #define AD7124_FILTER(x) (0x21 + (x)) 40 #define AD7124_OFFSET(x) (0x29 + (x)) 41 #define AD7124_GAIN(x) (0x31 + (x)) 42 43 /* AD7124_STATUS */ 44 #define AD7124_STATUS_POR_FLAG BIT(4) 45 46 /* AD7124_ADC_CONTROL */ 47 #define AD7124_ADC_CONTROL_MODE GENMASK(5, 2) 48 #define AD7124_ADC_CONTROL_MODE_CONTINUOUS 0 49 #define AD7124_ADC_CONTROL_MODE_SINGLE 1 50 #define AD7124_ADC_CONTROL_MODE_STANDBY 2 51 #define AD7124_ADC_CONTROL_MODE_POWERDOWN 3 52 #define AD7124_ADC_CONTROL_MODE_IDLE 4 53 #define AD7124_ADC_CONTROL_MODE_INT_OFFSET_CALIB 5 /* Internal Zero-Scale Calibration */ 54 #define AD7124_ADC_CONTROL_MODE_INT_GAIN_CALIB 6 /* Internal Full-Scale Calibration */ 55 #define AD7124_ADC_CONTROL_MODE_SYS_OFFSET_CALIB 7 /* System Zero-Scale Calibration */ 56 #define AD7124_ADC_CONTROL_MODE_SYS_GAIN_CALIB 8 /* System Full-Scale Calibration */ 57 #define AD7124_ADC_CONTROL_POWER_MODE GENMASK(7, 6) 58 #define AD7124_ADC_CONTROL_POWER_MODE_LOW 0 59 #define AD7124_ADC_CONTROL_POWER_MODE_MID 1 60 #define AD7124_ADC_CONTROL_POWER_MODE_FULL 2 61 #define AD7124_ADC_CONTROL_REF_EN BIT(8) 62 #define AD7124_ADC_CONTROL_DATA_STATUS BIT(10) 63 64 /* AD7124_ID */ 65 #define AD7124_ID_SILICON_REVISION GENMASK(3, 0) 66 #define AD7124_ID_DEVICE_ID GENMASK(7, 4) 67 #define AD7124_ID_DEVICE_ID_AD7124_4 0x0 68 #define AD7124_ID_DEVICE_ID_AD7124_8 0x1 69 70 /* AD7124_CHANNEL_X */ 71 #define AD7124_CHANNEL_ENABLE BIT(15) 72 #define AD7124_CHANNEL_SETUP GENMASK(14, 12) 73 #define AD7124_CHANNEL_AINP GENMASK(9, 5) 74 #define AD7124_CHANNEL_AINM GENMASK(4, 0) 75 #define AD7124_CHANNEL_AINx_TEMPSENSOR 16 76 #define AD7124_CHANNEL_AINx_AVSS 17 77 78 /* AD7124_CONFIG_X */ 79 #define AD7124_CONFIG_BIPOLAR BIT(11) 80 #define AD7124_CONFIG_IN_BUFF GENMASK(6, 5) 81 #define AD7124_CONFIG_AIN_BUFP BIT(6) 82 #define AD7124_CONFIG_AIN_BUFM BIT(5) 83 #define AD7124_CONFIG_REF_SEL GENMASK(4, 3) 84 #define AD7124_CONFIG_PGA GENMASK(2, 0) 85 86 /* AD7124_FILTER_X */ 87 #define AD7124_FILTER_FS GENMASK(10, 0) 88 #define AD7124_FILTER_FILTER GENMASK(23, 21) 89 #define AD7124_FILTER_FILTER_SINC4 0 90 #define AD7124_FILTER_FILTER_SINC3 2 91 92 #define AD7124_MAX_CONFIGS 8 93 #define AD7124_MAX_CHANNELS 16 94 95 /* AD7124 input sources */ 96 97 enum ad7124_ids { 98 ID_AD7124_4, 99 ID_AD7124_8, 100 }; 101 102 enum ad7124_ref_sel { 103 AD7124_REFIN1, 104 AD7124_REFIN2, 105 AD7124_INT_REF, 106 AD7124_AVDD_REF, 107 }; 108 109 enum ad7124_power_mode { 110 AD7124_LOW_POWER, 111 AD7124_MID_POWER, 112 AD7124_FULL_POWER, 113 }; 114 115 static const unsigned int ad7124_gain[8] = { 116 1, 2, 4, 8, 16, 32, 64, 128 117 }; 118 119 static const unsigned int ad7124_reg_size[] = { 120 1, 2, 3, 3, 2, 1, 3, 3, 1, 2, 2, 2, 2, 121 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 122 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 123 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 124 3, 3, 3, 3, 3 125 }; 126 127 static const int ad7124_master_clk_freq_hz[3] = { 128 [AD7124_LOW_POWER] = 76800, 129 [AD7124_MID_POWER] = 153600, 130 [AD7124_FULL_POWER] = 614400, 131 }; 132 133 static const char * const ad7124_ref_names[] = { 134 [AD7124_REFIN1] = "refin1", 135 [AD7124_REFIN2] = "refin2", 136 [AD7124_INT_REF] = "int", 137 [AD7124_AVDD_REF] = "avdd", 138 }; 139 140 struct ad7124_chip_info { 141 const char *name; 142 unsigned int chip_id; 143 unsigned int num_inputs; 144 }; 145 146 struct ad7124_channel_config { 147 bool live; 148 unsigned int cfg_slot; 149 /* 150 * Following fields are used to compare for equality. If you 151 * make adaptations in it, you most likely also have to adapt 152 * ad7124_find_similar_live_cfg(), too. 153 */ 154 struct_group(config_props, 155 enum ad7124_ref_sel refsel; 156 bool bipolar; 157 bool buf_positive; 158 bool buf_negative; 159 unsigned int vref_mv; 160 unsigned int pga_bits; 161 unsigned int odr; 162 unsigned int odr_sel_bits; 163 unsigned int filter_type; 164 unsigned int calibration_offset; 165 unsigned int calibration_gain; 166 ); 167 }; 168 169 struct ad7124_channel { 170 unsigned int nr; 171 struct ad7124_channel_config cfg; 172 unsigned int ain; 173 unsigned int slot; 174 u8 syscalib_mode; 175 }; 176 177 struct ad7124_state { 178 const struct ad7124_chip_info *chip_info; 179 struct ad_sigma_delta sd; 180 struct ad7124_channel *channels; 181 struct regulator *vref[4]; 182 struct clk *mclk; 183 unsigned int adc_control; 184 unsigned int num_channels; 185 struct mutex cfgs_lock; /* lock for configs access */ 186 unsigned long cfg_slots_status; /* bitmap with slot status (1 means it is used) */ 187 188 /* 189 * Stores the power-on reset value for the GAIN(x) registers which are 190 * needed for measurements at gain 1 (i.e. CONFIG(x).PGA == 0) 191 */ 192 unsigned int gain_default; 193 DECLARE_KFIFO(live_cfgs_fifo, struct ad7124_channel_config *, AD7124_MAX_CONFIGS); 194 }; 195 196 static struct ad7124_chip_info ad7124_chip_info_tbl[] = { 197 [ID_AD7124_4] = { 198 .name = "ad7124-4", 199 .chip_id = AD7124_ID_DEVICE_ID_AD7124_4, 200 .num_inputs = 8, 201 }, 202 [ID_AD7124_8] = { 203 .name = "ad7124-8", 204 .chip_id = AD7124_ID_DEVICE_ID_AD7124_8, 205 .num_inputs = 16, 206 }, 207 }; 208 209 static int ad7124_find_closest_match(const int *array, 210 unsigned int size, int val) 211 { 212 int i, idx; 213 unsigned int diff_new, diff_old; 214 215 diff_old = U32_MAX; 216 idx = 0; 217 218 for (i = 0; i < size; i++) { 219 diff_new = abs(val - array[i]); 220 if (diff_new < diff_old) { 221 diff_old = diff_new; 222 idx = i; 223 } 224 } 225 226 return idx; 227 } 228 229 static int ad7124_spi_write_mask(struct ad7124_state *st, 230 unsigned int addr, 231 unsigned long mask, 232 unsigned int val, 233 unsigned int bytes) 234 { 235 unsigned int readval; 236 int ret; 237 238 ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval); 239 if (ret < 0) 240 return ret; 241 242 readval &= ~mask; 243 readval |= val; 244 245 return ad_sd_write_reg(&st->sd, addr, bytes, readval); 246 } 247 248 static int ad7124_set_mode(struct ad_sigma_delta *sd, 249 enum ad_sigma_delta_mode mode) 250 { 251 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); 252 253 st->adc_control &= ~AD7124_ADC_CONTROL_MODE; 254 st->adc_control |= FIELD_PREP(AD7124_ADC_CONTROL_MODE, mode); 255 256 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control); 257 } 258 259 static void ad7124_set_channel_odr(struct ad7124_state *st, unsigned int channel, unsigned int odr) 260 { 261 unsigned int fclk, odr_sel_bits; 262 263 fclk = clk_get_rate(st->mclk); 264 /* 265 * FS[10:0] = fCLK / (fADC x 32) where: 266 * fADC is the output data rate 267 * fCLK is the master clock frequency 268 * FS[10:0] are the bits in the filter register 269 * FS[10:0] can have a value from 1 to 2047 270 */ 271 odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32); 272 if (odr_sel_bits < 1) 273 odr_sel_bits = 1; 274 else if (odr_sel_bits > 2047) 275 odr_sel_bits = 2047; 276 277 if (odr_sel_bits != st->channels[channel].cfg.odr_sel_bits) 278 st->channels[channel].cfg.live = false; 279 280 /* fADC = fCLK / (FS[10:0] x 32) */ 281 st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32); 282 st->channels[channel].cfg.odr_sel_bits = odr_sel_bits; 283 } 284 285 static int ad7124_get_3db_filter_freq(struct ad7124_state *st, 286 unsigned int channel) 287 { 288 unsigned int fadc; 289 290 fadc = st->channels[channel].cfg.odr; 291 292 switch (st->channels[channel].cfg.filter_type) { 293 case AD7124_FILTER_FILTER_SINC3: 294 return DIV_ROUND_CLOSEST(fadc * 272, 1000); 295 case AD7124_FILTER_FILTER_SINC4: 296 return DIV_ROUND_CLOSEST(fadc * 230, 1000); 297 default: 298 return -EINVAL; 299 } 300 } 301 302 static struct ad7124_channel_config *ad7124_find_similar_live_cfg(struct ad7124_state *st, 303 struct ad7124_channel_config *cfg) 304 { 305 struct ad7124_channel_config *cfg_aux; 306 int i; 307 308 /* 309 * This is just to make sure that the comparison is adapted after 310 * struct ad7124_channel_config was changed. 311 */ 312 static_assert(sizeof_field(struct ad7124_channel_config, config_props) == 313 sizeof(struct { 314 enum ad7124_ref_sel refsel; 315 bool bipolar; 316 bool buf_positive; 317 bool buf_negative; 318 unsigned int vref_mv; 319 unsigned int pga_bits; 320 unsigned int odr; 321 unsigned int odr_sel_bits; 322 unsigned int filter_type; 323 unsigned int calibration_offset; 324 unsigned int calibration_gain; 325 })); 326 327 for (i = 0; i < st->num_channels; i++) { 328 cfg_aux = &st->channels[i].cfg; 329 330 if (cfg_aux->live && 331 cfg->refsel == cfg_aux->refsel && 332 cfg->bipolar == cfg_aux->bipolar && 333 cfg->buf_positive == cfg_aux->buf_positive && 334 cfg->buf_negative == cfg_aux->buf_negative && 335 cfg->vref_mv == cfg_aux->vref_mv && 336 cfg->pga_bits == cfg_aux->pga_bits && 337 cfg->odr == cfg_aux->odr && 338 cfg->odr_sel_bits == cfg_aux->odr_sel_bits && 339 cfg->filter_type == cfg_aux->filter_type && 340 cfg->calibration_offset == cfg_aux->calibration_offset && 341 cfg->calibration_gain == cfg_aux->calibration_gain) 342 return cfg_aux; 343 } 344 345 return NULL; 346 } 347 348 static int ad7124_find_free_config_slot(struct ad7124_state *st) 349 { 350 unsigned int free_cfg_slot; 351 352 free_cfg_slot = find_first_zero_bit(&st->cfg_slots_status, AD7124_MAX_CONFIGS); 353 if (free_cfg_slot == AD7124_MAX_CONFIGS) 354 return -1; 355 356 return free_cfg_slot; 357 } 358 359 /* Only called during probe, so dev_err_probe() can be used */ 360 static int ad7124_init_config_vref(struct ad7124_state *st, struct ad7124_channel_config *cfg) 361 { 362 struct device *dev = &st->sd.spi->dev; 363 unsigned int refsel = cfg->refsel; 364 365 switch (refsel) { 366 case AD7124_REFIN1: 367 case AD7124_REFIN2: 368 case AD7124_AVDD_REF: 369 if (IS_ERR(st->vref[refsel])) 370 return dev_err_probe(dev, PTR_ERR(st->vref[refsel]), 371 "Error, trying to use external voltage reference without a %s regulator.\n", 372 ad7124_ref_names[refsel]); 373 374 cfg->vref_mv = regulator_get_voltage(st->vref[refsel]); 375 /* Conversion from uV to mV */ 376 cfg->vref_mv /= 1000; 377 return 0; 378 case AD7124_INT_REF: 379 cfg->vref_mv = 2500; 380 st->adc_control |= AD7124_ADC_CONTROL_REF_EN; 381 return 0; 382 default: 383 return dev_err_probe(dev, -EINVAL, "Invalid reference %d\n", refsel); 384 } 385 } 386 387 static int ad7124_write_config(struct ad7124_state *st, struct ad7124_channel_config *cfg, 388 unsigned int cfg_slot) 389 { 390 unsigned int tmp; 391 unsigned int val; 392 int ret; 393 394 cfg->cfg_slot = cfg_slot; 395 396 ret = ad_sd_write_reg(&st->sd, AD7124_OFFSET(cfg->cfg_slot), 3, cfg->calibration_offset); 397 if (ret) 398 return ret; 399 400 ret = ad_sd_write_reg(&st->sd, AD7124_GAIN(cfg->cfg_slot), 3, cfg->calibration_gain); 401 if (ret) 402 return ret; 403 404 val = FIELD_PREP(AD7124_CONFIG_BIPOLAR, cfg->bipolar) | 405 FIELD_PREP(AD7124_CONFIG_REF_SEL, cfg->refsel) | 406 (cfg->buf_positive ? AD7124_CONFIG_AIN_BUFP : 0) | 407 (cfg->buf_negative ? AD7124_CONFIG_AIN_BUFM : 0) | 408 FIELD_PREP(AD7124_CONFIG_PGA, cfg->pga_bits); 409 410 ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(cfg->cfg_slot), 2, val); 411 if (ret < 0) 412 return ret; 413 414 tmp = FIELD_PREP(AD7124_FILTER_FILTER, cfg->filter_type) | 415 FIELD_PREP(AD7124_FILTER_FS, cfg->odr_sel_bits); 416 return ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot), 417 AD7124_FILTER_FILTER | AD7124_FILTER_FS, 418 tmp, 3); 419 } 420 421 static struct ad7124_channel_config *ad7124_pop_config(struct ad7124_state *st) 422 { 423 struct ad7124_channel_config *lru_cfg; 424 struct ad7124_channel_config *cfg; 425 int ret; 426 int i; 427 428 /* 429 * Pop least recently used config from the fifo 430 * in order to make room for the new one 431 */ 432 ret = kfifo_get(&st->live_cfgs_fifo, &lru_cfg); 433 if (ret <= 0) 434 return NULL; 435 436 lru_cfg->live = false; 437 438 /* mark slot as free */ 439 assign_bit(lru_cfg->cfg_slot, &st->cfg_slots_status, 0); 440 441 /* invalidate all other configs that pointed to this one */ 442 for (i = 0; i < st->num_channels; i++) { 443 cfg = &st->channels[i].cfg; 444 445 if (cfg->cfg_slot == lru_cfg->cfg_slot) 446 cfg->live = false; 447 } 448 449 return lru_cfg; 450 } 451 452 static int ad7124_push_config(struct ad7124_state *st, struct ad7124_channel_config *cfg) 453 { 454 struct ad7124_channel_config *lru_cfg; 455 int free_cfg_slot; 456 457 free_cfg_slot = ad7124_find_free_config_slot(st); 458 if (free_cfg_slot >= 0) { 459 /* push the new config in configs queue */ 460 kfifo_put(&st->live_cfgs_fifo, cfg); 461 } else { 462 /* pop one config to make room for the new one */ 463 lru_cfg = ad7124_pop_config(st); 464 if (!lru_cfg) 465 return -EINVAL; 466 467 /* push the new config in configs queue */ 468 free_cfg_slot = lru_cfg->cfg_slot; 469 kfifo_put(&st->live_cfgs_fifo, cfg); 470 } 471 472 /* mark slot as used */ 473 assign_bit(free_cfg_slot, &st->cfg_slots_status, 1); 474 475 return ad7124_write_config(st, cfg, free_cfg_slot); 476 } 477 478 static int ad7124_enable_channel(struct ad7124_state *st, struct ad7124_channel *ch) 479 { 480 ch->cfg.live = true; 481 return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(ch->nr), 2, ch->ain | 482 FIELD_PREP(AD7124_CHANNEL_SETUP, ch->cfg.cfg_slot) | 483 AD7124_CHANNEL_ENABLE); 484 } 485 486 static int ad7124_prepare_read(struct ad7124_state *st, int address) 487 { 488 struct ad7124_channel_config *cfg = &st->channels[address].cfg; 489 struct ad7124_channel_config *live_cfg; 490 491 /* 492 * Before doing any reads assign the channel a configuration. 493 * Check if channel's config is on the device 494 */ 495 if (!cfg->live) { 496 /* check if config matches another one */ 497 live_cfg = ad7124_find_similar_live_cfg(st, cfg); 498 if (!live_cfg) 499 ad7124_push_config(st, cfg); 500 else 501 cfg->cfg_slot = live_cfg->cfg_slot; 502 } 503 504 /* point channel to the config slot and enable */ 505 return ad7124_enable_channel(st, &st->channels[address]); 506 } 507 508 static int __ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel) 509 { 510 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); 511 512 return ad7124_prepare_read(st, channel); 513 } 514 515 static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel) 516 { 517 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); 518 int ret; 519 520 mutex_lock(&st->cfgs_lock); 521 ret = __ad7124_set_channel(sd, channel); 522 mutex_unlock(&st->cfgs_lock); 523 524 return ret; 525 } 526 527 static int ad7124_append_status(struct ad_sigma_delta *sd, bool append) 528 { 529 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); 530 unsigned int adc_control = st->adc_control; 531 int ret; 532 533 if (append) 534 adc_control |= AD7124_ADC_CONTROL_DATA_STATUS; 535 else 536 adc_control &= ~AD7124_ADC_CONTROL_DATA_STATUS; 537 538 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, adc_control); 539 if (ret < 0) 540 return ret; 541 542 st->adc_control = adc_control; 543 544 return 0; 545 } 546 547 static int ad7124_disable_one(struct ad_sigma_delta *sd, unsigned int chan) 548 { 549 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); 550 551 /* The relevant thing here is that AD7124_CHANNEL_ENABLE is cleared. */ 552 return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(chan), 2, 0); 553 } 554 555 static int ad7124_disable_all(struct ad_sigma_delta *sd) 556 { 557 int ret; 558 int i; 559 560 for (i = 0; i < 16; i++) { 561 ret = ad7124_disable_one(sd, i); 562 if (ret < 0) 563 return ret; 564 } 565 566 return 0; 567 } 568 569 static const struct ad_sigma_delta_info ad7124_sigma_delta_info = { 570 .set_channel = ad7124_set_channel, 571 .append_status = ad7124_append_status, 572 .disable_all = ad7124_disable_all, 573 .disable_one = ad7124_disable_one, 574 .set_mode = ad7124_set_mode, 575 .has_registers = true, 576 .addr_shift = 0, 577 .read_mask = BIT(6), 578 .status_ch_mask = GENMASK(3, 0), 579 .data_reg = AD7124_DATA, 580 .num_slots = 8, 581 .irq_flags = IRQF_TRIGGER_FALLING, 582 .num_resetclks = 64, 583 }; 584 585 static int ad7124_read_raw(struct iio_dev *indio_dev, 586 struct iio_chan_spec const *chan, 587 int *val, int *val2, long info) 588 { 589 struct ad7124_state *st = iio_priv(indio_dev); 590 int idx, ret; 591 592 switch (info) { 593 case IIO_CHAN_INFO_RAW: 594 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val); 595 if (ret < 0) 596 return ret; 597 598 return IIO_VAL_INT; 599 case IIO_CHAN_INFO_SCALE: 600 switch (chan->type) { 601 case IIO_VOLTAGE: 602 mutex_lock(&st->cfgs_lock); 603 604 idx = st->channels[chan->address].cfg.pga_bits; 605 *val = st->channels[chan->address].cfg.vref_mv; 606 if (st->channels[chan->address].cfg.bipolar) 607 *val2 = chan->scan_type.realbits - 1 + idx; 608 else 609 *val2 = chan->scan_type.realbits + idx; 610 611 mutex_unlock(&st->cfgs_lock); 612 return IIO_VAL_FRACTIONAL_LOG2; 613 614 case IIO_TEMP: 615 /* 616 * According to the data sheet 617 * Temperature (°C) 618 * = ((Conversion − 0x800000)/13584) − 272.5 619 * = (Conversion − 0x800000 - 13584 * 272.5) / 13584 620 * = (Conversion − 12090248) / 13584 621 * So scale with 1000/13584 to yield °mC. Reduce by 8 to 622 * 125/1698. 623 */ 624 *val = 125; 625 *val2 = 1698; 626 return IIO_VAL_FRACTIONAL; 627 628 default: 629 return -EINVAL; 630 } 631 632 case IIO_CHAN_INFO_OFFSET: 633 switch (chan->type) { 634 case IIO_VOLTAGE: 635 mutex_lock(&st->cfgs_lock); 636 if (st->channels[chan->address].cfg.bipolar) 637 *val = -(1 << (chan->scan_type.realbits - 1)); 638 else 639 *val = 0; 640 641 mutex_unlock(&st->cfgs_lock); 642 return IIO_VAL_INT; 643 644 case IIO_TEMP: 645 /* see calculation above */ 646 *val = -12090248; 647 return IIO_VAL_INT; 648 649 default: 650 return -EINVAL; 651 } 652 653 case IIO_CHAN_INFO_SAMP_FREQ: 654 mutex_lock(&st->cfgs_lock); 655 *val = st->channels[chan->address].cfg.odr; 656 mutex_unlock(&st->cfgs_lock); 657 658 return IIO_VAL_INT; 659 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 660 mutex_lock(&st->cfgs_lock); 661 *val = ad7124_get_3db_filter_freq(st, chan->scan_index); 662 mutex_unlock(&st->cfgs_lock); 663 664 return IIO_VAL_INT; 665 default: 666 return -EINVAL; 667 } 668 } 669 670 static int ad7124_write_raw(struct iio_dev *indio_dev, 671 struct iio_chan_spec const *chan, 672 int val, int val2, long info) 673 { 674 struct ad7124_state *st = iio_priv(indio_dev); 675 unsigned int res, gain, full_scale, vref; 676 int ret = 0; 677 678 mutex_lock(&st->cfgs_lock); 679 680 switch (info) { 681 case IIO_CHAN_INFO_SAMP_FREQ: 682 if (val2 != 0 || val == 0) { 683 ret = -EINVAL; 684 break; 685 } 686 687 ad7124_set_channel_odr(st, chan->address, val); 688 break; 689 case IIO_CHAN_INFO_SCALE: 690 if (val != 0) { 691 ret = -EINVAL; 692 break; 693 } 694 695 if (st->channels[chan->address].cfg.bipolar) 696 full_scale = 1 << (chan->scan_type.realbits - 1); 697 else 698 full_scale = 1 << chan->scan_type.realbits; 699 700 vref = st->channels[chan->address].cfg.vref_mv * 1000000LL; 701 res = DIV_ROUND_CLOSEST(vref, full_scale); 702 gain = DIV_ROUND_CLOSEST(res, val2); 703 res = ad7124_find_closest_match(ad7124_gain, ARRAY_SIZE(ad7124_gain), gain); 704 705 if (st->channels[chan->address].cfg.pga_bits != res) 706 st->channels[chan->address].cfg.live = false; 707 708 st->channels[chan->address].cfg.pga_bits = res; 709 break; 710 default: 711 ret = -EINVAL; 712 } 713 714 mutex_unlock(&st->cfgs_lock); 715 return ret; 716 } 717 718 static int ad7124_reg_access(struct iio_dev *indio_dev, 719 unsigned int reg, 720 unsigned int writeval, 721 unsigned int *readval) 722 { 723 struct ad7124_state *st = iio_priv(indio_dev); 724 int ret; 725 726 if (reg >= ARRAY_SIZE(ad7124_reg_size)) 727 return -EINVAL; 728 729 if (readval) 730 ret = ad_sd_read_reg(&st->sd, reg, ad7124_reg_size[reg], 731 readval); 732 else 733 ret = ad_sd_write_reg(&st->sd, reg, ad7124_reg_size[reg], 734 writeval); 735 736 return ret; 737 } 738 739 static IIO_CONST_ATTR(in_voltage_scale_available, 740 "0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023"); 741 742 static struct attribute *ad7124_attributes[] = { 743 &iio_const_attr_in_voltage_scale_available.dev_attr.attr, 744 NULL, 745 }; 746 747 static const struct attribute_group ad7124_attrs_group = { 748 .attrs = ad7124_attributes, 749 }; 750 751 static int ad7124_update_scan_mode(struct iio_dev *indio_dev, 752 const unsigned long *scan_mask) 753 { 754 struct ad7124_state *st = iio_priv(indio_dev); 755 bool bit_set; 756 int ret; 757 int i; 758 759 mutex_lock(&st->cfgs_lock); 760 for (i = 0; i < st->num_channels; i++) { 761 bit_set = test_bit(i, scan_mask); 762 if (bit_set) 763 ret = __ad7124_set_channel(&st->sd, i); 764 else 765 ret = ad7124_spi_write_mask(st, AD7124_CHANNEL(i), AD7124_CHANNEL_ENABLE, 766 0, 2); 767 if (ret < 0) { 768 mutex_unlock(&st->cfgs_lock); 769 770 return ret; 771 } 772 } 773 774 mutex_unlock(&st->cfgs_lock); 775 776 return 0; 777 } 778 779 static const struct iio_info ad7124_info = { 780 .read_raw = ad7124_read_raw, 781 .write_raw = ad7124_write_raw, 782 .debugfs_reg_access = &ad7124_reg_access, 783 .validate_trigger = ad_sd_validate_trigger, 784 .update_scan_mode = ad7124_update_scan_mode, 785 .attrs = &ad7124_attrs_group, 786 }; 787 788 /* Only called during probe, so dev_err_probe() can be used */ 789 static int ad7124_soft_reset(struct ad7124_state *st) 790 { 791 struct device *dev = &st->sd.spi->dev; 792 unsigned int readval, timeout; 793 int ret; 794 795 ret = ad_sd_reset(&st->sd); 796 if (ret < 0) 797 return ret; 798 799 fsleep(200); 800 timeout = 100; 801 do { 802 ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval); 803 if (ret < 0) 804 return dev_err_probe(dev, ret, "Error reading status register\n"); 805 806 if (!(readval & AD7124_STATUS_POR_FLAG)) 807 break; 808 809 /* The AD7124 requires typically 2ms to power up and settle */ 810 usleep_range(100, 2000); 811 } while (--timeout); 812 813 if (readval & AD7124_STATUS_POR_FLAG) 814 return dev_err_probe(dev, -EIO, "Soft reset failed\n"); 815 816 ret = ad_sd_read_reg(&st->sd, AD7124_GAIN(0), 3, &st->gain_default); 817 if (ret < 0) 818 return dev_err_probe(dev, ret, "Error reading gain register\n"); 819 820 dev_dbg(dev, "Reset value of GAIN register is 0x%x\n", st->gain_default); 821 822 return 0; 823 } 824 825 static int ad7124_check_chip_id(struct ad7124_state *st) 826 { 827 struct device *dev = &st->sd.spi->dev; 828 unsigned int readval, chip_id, silicon_rev; 829 int ret; 830 831 ret = ad_sd_read_reg(&st->sd, AD7124_ID, 1, &readval); 832 if (ret < 0) 833 return dev_err_probe(dev, ret, "Failure to read ID register\n"); 834 835 chip_id = FIELD_GET(AD7124_ID_DEVICE_ID, readval); 836 silicon_rev = FIELD_GET(AD7124_ID_SILICON_REVISION, readval); 837 838 if (chip_id != st->chip_info->chip_id) 839 return dev_err_probe(dev, -ENODEV, 840 "Chip ID mismatch: expected %u, got %u\n", 841 st->chip_info->chip_id, chip_id); 842 843 if (silicon_rev == 0) 844 return dev_err_probe(dev, -ENODEV, 845 "Silicon revision empty. Chip may not be present\n"); 846 847 return 0; 848 } 849 850 enum { 851 AD7124_SYSCALIB_ZERO_SCALE, 852 AD7124_SYSCALIB_FULL_SCALE, 853 }; 854 855 static int ad7124_syscalib_locked(struct ad7124_state *st, const struct iio_chan_spec *chan) 856 { 857 struct device *dev = &st->sd.spi->dev; 858 struct ad7124_channel *ch = &st->channels[chan->channel]; 859 int ret; 860 861 if (ch->syscalib_mode == AD7124_SYSCALIB_ZERO_SCALE) { 862 ch->cfg.calibration_offset = 0x800000; 863 864 ret = ad_sd_calibrate(&st->sd, AD7124_ADC_CONTROL_MODE_SYS_OFFSET_CALIB, 865 chan->address); 866 if (ret < 0) 867 return ret; 868 869 ret = ad_sd_read_reg(&st->sd, AD7124_OFFSET(ch->cfg.cfg_slot), 3, 870 &ch->cfg.calibration_offset); 871 if (ret < 0) 872 return ret; 873 874 dev_dbg(dev, "offset for channel %d after zero-scale calibration: 0x%x\n", 875 chan->channel, ch->cfg.calibration_offset); 876 } else { 877 ch->cfg.calibration_gain = st->gain_default; 878 879 ret = ad_sd_calibrate(&st->sd, AD7124_ADC_CONTROL_MODE_SYS_GAIN_CALIB, 880 chan->address); 881 if (ret < 0) 882 return ret; 883 884 ret = ad_sd_read_reg(&st->sd, AD7124_GAIN(ch->cfg.cfg_slot), 3, 885 &ch->cfg.calibration_gain); 886 if (ret < 0) 887 return ret; 888 889 dev_dbg(dev, "gain for channel %d after full-scale calibration: 0x%x\n", 890 chan->channel, ch->cfg.calibration_gain); 891 } 892 893 return 0; 894 } 895 896 static ssize_t ad7124_write_syscalib(struct iio_dev *indio_dev, 897 uintptr_t private, 898 const struct iio_chan_spec *chan, 899 const char *buf, size_t len) 900 { 901 struct ad7124_state *st = iio_priv(indio_dev); 902 bool sys_calib; 903 int ret; 904 905 ret = kstrtobool(buf, &sys_calib); 906 if (ret) 907 return ret; 908 909 if (!sys_calib) 910 return len; 911 912 if (!iio_device_claim_direct(indio_dev)) 913 return -EBUSY; 914 915 ret = ad7124_syscalib_locked(st, chan); 916 917 iio_device_release_direct(indio_dev); 918 919 return ret ?: len; 920 } 921 922 static const char * const ad7124_syscalib_modes[] = { 923 [AD7124_SYSCALIB_ZERO_SCALE] = "zero_scale", 924 [AD7124_SYSCALIB_FULL_SCALE] = "full_scale", 925 }; 926 927 static int ad7124_set_syscalib_mode(struct iio_dev *indio_dev, 928 const struct iio_chan_spec *chan, 929 unsigned int mode) 930 { 931 struct ad7124_state *st = iio_priv(indio_dev); 932 933 st->channels[chan->channel].syscalib_mode = mode; 934 935 return 0; 936 } 937 938 static int ad7124_get_syscalib_mode(struct iio_dev *indio_dev, 939 const struct iio_chan_spec *chan) 940 { 941 struct ad7124_state *st = iio_priv(indio_dev); 942 943 return st->channels[chan->channel].syscalib_mode; 944 } 945 946 static const struct iio_enum ad7124_syscalib_mode_enum = { 947 .items = ad7124_syscalib_modes, 948 .num_items = ARRAY_SIZE(ad7124_syscalib_modes), 949 .set = ad7124_set_syscalib_mode, 950 .get = ad7124_get_syscalib_mode 951 }; 952 953 static const struct iio_chan_spec_ext_info ad7124_calibsys_ext_info[] = { 954 { 955 .name = "sys_calibration", 956 .write = ad7124_write_syscalib, 957 .shared = IIO_SEPARATE, 958 }, 959 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE, 960 &ad7124_syscalib_mode_enum), 961 IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE, 962 &ad7124_syscalib_mode_enum), 963 { } 964 }; 965 966 static const struct iio_chan_spec ad7124_channel_template = { 967 .type = IIO_VOLTAGE, 968 .indexed = 1, 969 .differential = 1, 970 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 971 BIT(IIO_CHAN_INFO_SCALE) | 972 BIT(IIO_CHAN_INFO_OFFSET) | 973 BIT(IIO_CHAN_INFO_SAMP_FREQ) | 974 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), 975 .scan_type = { 976 .sign = 'u', 977 .realbits = 24, 978 .storagebits = 32, 979 .endianness = IIO_BE, 980 }, 981 .ext_info = ad7124_calibsys_ext_info, 982 }; 983 984 /* 985 * Input specifiers 8 - 15 are explicitly reserved for ad7124-4 986 * while they are fine for ad7124-8. Values above 31 don't fit 987 * into the register field and so are invalid for sure. 988 */ 989 static bool ad7124_valid_input_select(unsigned int ain, const struct ad7124_chip_info *info) 990 { 991 if (ain >= info->num_inputs && ain < 16) 992 return false; 993 994 return ain <= FIELD_MAX(AD7124_CHANNEL_AINM); 995 } 996 997 static int ad7124_parse_channel_config(struct iio_dev *indio_dev, 998 struct device *dev) 999 { 1000 struct ad7124_state *st = iio_priv(indio_dev); 1001 struct ad7124_channel_config *cfg; 1002 struct ad7124_channel *channels; 1003 struct iio_chan_spec *chan; 1004 unsigned int ain[2], channel = 0, tmp; 1005 unsigned int num_channels; 1006 int ret; 1007 1008 num_channels = device_get_child_node_count(dev); 1009 1010 /* 1011 * The driver assigns each logical channel defined in the device tree 1012 * statically one channel register. So only accept 16 such logical 1013 * channels to not treat CONFIG_0 (i.e. the register following 1014 * CHANNEL_15) as an additional channel register. The driver could be 1015 * improved to lift this limitation. 1016 */ 1017 if (num_channels > AD7124_MAX_CHANNELS) 1018 return dev_err_probe(dev, -EINVAL, "Too many channels defined\n"); 1019 1020 /* Add one for temperature */ 1021 st->num_channels = min(num_channels + 1, AD7124_MAX_CHANNELS); 1022 1023 chan = devm_kcalloc(dev, st->num_channels, 1024 sizeof(*chan), GFP_KERNEL); 1025 if (!chan) 1026 return -ENOMEM; 1027 1028 channels = devm_kcalloc(dev, st->num_channels, sizeof(*channels), 1029 GFP_KERNEL); 1030 if (!channels) 1031 return -ENOMEM; 1032 1033 indio_dev->channels = chan; 1034 indio_dev->num_channels = st->num_channels; 1035 st->channels = channels; 1036 1037 device_for_each_child_node_scoped(dev, child) { 1038 ret = fwnode_property_read_u32(child, "reg", &channel); 1039 if (ret) 1040 return dev_err_probe(dev, ret, 1041 "Failed to parse reg property of %pfwP\n", child); 1042 1043 if (channel >= num_channels) 1044 return dev_err_probe(dev, -EINVAL, 1045 "Channel index >= number of channels in %pfwP\n", child); 1046 1047 ret = fwnode_property_read_u32_array(child, "diff-channels", 1048 ain, 2); 1049 if (ret) 1050 return dev_err_probe(dev, ret, 1051 "Failed to parse diff-channels property of %pfwP\n", child); 1052 1053 if (!ad7124_valid_input_select(ain[0], st->chip_info) || 1054 !ad7124_valid_input_select(ain[1], st->chip_info)) 1055 return dev_err_probe(dev, -EINVAL, 1056 "diff-channels property of %pfwP contains invalid data\n", child); 1057 1058 st->channels[channel].nr = channel; 1059 st->channels[channel].ain = FIELD_PREP(AD7124_CHANNEL_AINP, ain[0]) | 1060 FIELD_PREP(AD7124_CHANNEL_AINM, ain[1]); 1061 1062 cfg = &st->channels[channel].cfg; 1063 cfg->bipolar = fwnode_property_read_bool(child, "bipolar"); 1064 1065 ret = fwnode_property_read_u32(child, "adi,reference-select", &tmp); 1066 if (ret) 1067 cfg->refsel = AD7124_INT_REF; 1068 else 1069 cfg->refsel = tmp; 1070 1071 cfg->buf_positive = 1072 fwnode_property_read_bool(child, "adi,buffered-positive"); 1073 cfg->buf_negative = 1074 fwnode_property_read_bool(child, "adi,buffered-negative"); 1075 1076 chan[channel] = ad7124_channel_template; 1077 chan[channel].address = channel; 1078 chan[channel].scan_index = channel; 1079 chan[channel].channel = ain[0]; 1080 chan[channel].channel2 = ain[1]; 1081 } 1082 1083 if (num_channels < AD7124_MAX_CHANNELS) { 1084 st->channels[num_channels] = (struct ad7124_channel) { 1085 .nr = num_channels, 1086 .ain = FIELD_PREP(AD7124_CHANNEL_AINP, AD7124_CHANNEL_AINx_TEMPSENSOR) | 1087 FIELD_PREP(AD7124_CHANNEL_AINM, AD7124_CHANNEL_AINx_AVSS), 1088 .cfg = { 1089 .bipolar = true, 1090 }, 1091 }; 1092 1093 chan[num_channels] = (struct iio_chan_spec) { 1094 .type = IIO_TEMP, 1095 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 1096 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET) | 1097 BIT(IIO_CHAN_INFO_SAMP_FREQ), 1098 .scan_type = { 1099 /* 1100 * You might find it strange that a bipolar 1101 * measurement yields an unsigned value, but 1102 * this matches the device's manual. 1103 */ 1104 .sign = 'u', 1105 .realbits = 24, 1106 .storagebits = 32, 1107 .endianness = IIO_BE, 1108 }, 1109 .address = num_channels, 1110 .scan_index = num_channels, 1111 }; 1112 } 1113 1114 return 0; 1115 } 1116 1117 static int ad7124_setup(struct ad7124_state *st) 1118 { 1119 struct device *dev = &st->sd.spi->dev; 1120 unsigned int fclk, power_mode; 1121 int i, ret; 1122 1123 fclk = clk_get_rate(st->mclk); 1124 if (!fclk) 1125 return dev_err_probe(dev, -EINVAL, "Failed to get mclk rate\n"); 1126 1127 /* The power mode changes the master clock frequency */ 1128 power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz, 1129 ARRAY_SIZE(ad7124_master_clk_freq_hz), 1130 fclk); 1131 if (fclk != ad7124_master_clk_freq_hz[power_mode]) { 1132 ret = clk_set_rate(st->mclk, fclk); 1133 if (ret) 1134 return dev_err_probe(dev, ret, "Failed to set mclk rate\n"); 1135 } 1136 1137 /* Set the power mode */ 1138 st->adc_control &= ~AD7124_ADC_CONTROL_POWER_MODE; 1139 st->adc_control |= FIELD_PREP(AD7124_ADC_CONTROL_POWER_MODE, power_mode); 1140 1141 st->adc_control &= ~AD7124_ADC_CONTROL_MODE; 1142 st->adc_control |= FIELD_PREP(AD7124_ADC_CONTROL_MODE, AD_SD_MODE_IDLE); 1143 1144 mutex_init(&st->cfgs_lock); 1145 INIT_KFIFO(st->live_cfgs_fifo); 1146 for (i = 0; i < st->num_channels; i++) { 1147 1148 ret = ad7124_init_config_vref(st, &st->channels[i].cfg); 1149 if (ret < 0) 1150 return ret; 1151 1152 /* 1153 * 9.38 SPS is the minimum output data rate supported 1154 * regardless of the selected power mode. Round it up to 10 and 1155 * set all channels to this default value. 1156 */ 1157 ad7124_set_channel_odr(st, i, 10); 1158 } 1159 1160 ad7124_disable_all(&st->sd); 1161 1162 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control); 1163 if (ret < 0) 1164 return dev_err_probe(dev, ret, "Failed to setup CONTROL register\n"); 1165 1166 return ret; 1167 } 1168 1169 static int __ad7124_calibrate_all(struct ad7124_state *st, struct iio_dev *indio_dev) 1170 { 1171 struct device *dev = &st->sd.spi->dev; 1172 int ret, i; 1173 1174 for (i = 0; i < st->num_channels; i++) { 1175 1176 if (indio_dev->channels[i].type != IIO_VOLTAGE) 1177 continue; 1178 1179 /* 1180 * For calibration the OFFSET register should hold its reset default 1181 * value. For the GAIN register there is no such requirement but 1182 * for gain 1 it should hold the reset default value, too. So to 1183 * simplify matters use the reset default value for both. 1184 */ 1185 st->channels[i].cfg.calibration_offset = 0x800000; 1186 st->channels[i].cfg.calibration_gain = st->gain_default; 1187 1188 /* 1189 * Full-scale calibration isn't supported at gain 1, so skip in 1190 * that case. Note that untypically full-scale calibration has 1191 * to happen before zero-scale calibration. This only applies to 1192 * the internal calibration. For system calibration it's as 1193 * usual: first zero-scale then full-scale calibration. 1194 */ 1195 if (st->channels[i].cfg.pga_bits > 0) { 1196 ret = ad_sd_calibrate(&st->sd, AD7124_ADC_CONTROL_MODE_INT_GAIN_CALIB, i); 1197 if (ret < 0) 1198 return ret; 1199 1200 /* 1201 * read out the resulting value of GAIN 1202 * after full-scale calibration because the next 1203 * ad_sd_calibrate() call overwrites this via 1204 * ad_sigma_delta_set_channel() -> ad7124_set_channel() 1205 * ... -> ad7124_enable_channel(). 1206 */ 1207 ret = ad_sd_read_reg(&st->sd, AD7124_GAIN(st->channels[i].cfg.cfg_slot), 3, 1208 &st->channels[i].cfg.calibration_gain); 1209 if (ret < 0) 1210 return ret; 1211 } 1212 1213 ret = ad_sd_calibrate(&st->sd, AD7124_ADC_CONTROL_MODE_INT_OFFSET_CALIB, i); 1214 if (ret < 0) 1215 return ret; 1216 1217 ret = ad_sd_read_reg(&st->sd, AD7124_OFFSET(st->channels[i].cfg.cfg_slot), 3, 1218 &st->channels[i].cfg.calibration_offset); 1219 if (ret < 0) 1220 return ret; 1221 1222 dev_dbg(dev, "offset and gain for channel %d = 0x%x + 0x%x\n", i, 1223 st->channels[i].cfg.calibration_offset, 1224 st->channels[i].cfg.calibration_gain); 1225 } 1226 1227 return 0; 1228 } 1229 1230 static int ad7124_calibrate_all(struct ad7124_state *st, struct iio_dev *indio_dev) 1231 { 1232 int ret; 1233 unsigned int adc_control = st->adc_control; 1234 1235 /* 1236 * Calibration isn't supported at full power, so speed down a bit. 1237 * Setting .adc_control is enough here because the control register is 1238 * written as part of ad_sd_calibrate() -> ad_sigma_delta_set_mode(). 1239 * The resulting calibration is then also valid for high-speed, so just 1240 * restore adc_control afterwards. 1241 */ 1242 if (FIELD_GET(AD7124_ADC_CONTROL_POWER_MODE, adc_control) >= AD7124_FULL_POWER) { 1243 st->adc_control &= ~AD7124_ADC_CONTROL_POWER_MODE; 1244 st->adc_control |= FIELD_PREP(AD7124_ADC_CONTROL_POWER_MODE, AD7124_MID_POWER); 1245 } 1246 1247 ret = __ad7124_calibrate_all(st, indio_dev); 1248 1249 st->adc_control = adc_control; 1250 1251 return ret; 1252 } 1253 1254 static void ad7124_reg_disable(void *r) 1255 { 1256 regulator_disable(r); 1257 } 1258 1259 static int ad7124_probe(struct spi_device *spi) 1260 { 1261 const struct ad7124_chip_info *info; 1262 struct device *dev = &spi->dev; 1263 struct ad7124_state *st; 1264 struct iio_dev *indio_dev; 1265 int i, ret; 1266 1267 info = spi_get_device_match_data(spi); 1268 if (!info) 1269 return dev_err_probe(dev, -ENODEV, "Failed to get match data\n"); 1270 1271 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1272 if (!indio_dev) 1273 return -ENOMEM; 1274 1275 st = iio_priv(indio_dev); 1276 1277 st->chip_info = info; 1278 1279 indio_dev->name = st->chip_info->name; 1280 indio_dev->modes = INDIO_DIRECT_MODE; 1281 indio_dev->info = &ad7124_info; 1282 1283 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info); 1284 if (ret < 0) 1285 return ret; 1286 1287 ret = ad7124_parse_channel_config(indio_dev, &spi->dev); 1288 if (ret < 0) 1289 return ret; 1290 1291 for (i = 0; i < ARRAY_SIZE(st->vref); i++) { 1292 if (i == AD7124_INT_REF) 1293 continue; 1294 1295 st->vref[i] = devm_regulator_get_optional(&spi->dev, 1296 ad7124_ref_names[i]); 1297 if (PTR_ERR(st->vref[i]) == -ENODEV) 1298 continue; 1299 else if (IS_ERR(st->vref[i])) 1300 return PTR_ERR(st->vref[i]); 1301 1302 ret = regulator_enable(st->vref[i]); 1303 if (ret) 1304 return dev_err_probe(dev, ret, "Failed to enable regulator #%d\n", i); 1305 1306 ret = devm_add_action_or_reset(&spi->dev, ad7124_reg_disable, 1307 st->vref[i]); 1308 if (ret) 1309 return dev_err_probe(dev, ret, "Failed to register disable handler for regulator #%d\n", i); 1310 } 1311 1312 st->mclk = devm_clk_get_enabled(&spi->dev, "mclk"); 1313 if (IS_ERR(st->mclk)) 1314 return dev_err_probe(dev, PTR_ERR(st->mclk), "Failed to get mclk\n"); 1315 1316 ret = ad7124_soft_reset(st); 1317 if (ret < 0) 1318 return ret; 1319 1320 ret = ad7124_check_chip_id(st); 1321 if (ret) 1322 return ret; 1323 1324 ret = ad7124_setup(st); 1325 if (ret < 0) 1326 return ret; 1327 1328 ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev); 1329 if (ret < 0) 1330 return dev_err_probe(dev, ret, "Failed to setup triggers\n"); 1331 1332 ret = ad7124_calibrate_all(st, indio_dev); 1333 if (ret) 1334 return ret; 1335 1336 ret = devm_iio_device_register(&spi->dev, indio_dev); 1337 if (ret < 0) 1338 return dev_err_probe(dev, ret, "Failed to register iio device\n"); 1339 1340 return 0; 1341 } 1342 1343 static const struct of_device_id ad7124_of_match[] = { 1344 { .compatible = "adi,ad7124-4", 1345 .data = &ad7124_chip_info_tbl[ID_AD7124_4], }, 1346 { .compatible = "adi,ad7124-8", 1347 .data = &ad7124_chip_info_tbl[ID_AD7124_8], }, 1348 { } 1349 }; 1350 MODULE_DEVICE_TABLE(of, ad7124_of_match); 1351 1352 static const struct spi_device_id ad71124_ids[] = { 1353 { "ad7124-4", (kernel_ulong_t)&ad7124_chip_info_tbl[ID_AD7124_4] }, 1354 { "ad7124-8", (kernel_ulong_t)&ad7124_chip_info_tbl[ID_AD7124_8] }, 1355 { } 1356 }; 1357 MODULE_DEVICE_TABLE(spi, ad71124_ids); 1358 1359 static struct spi_driver ad71124_driver = { 1360 .driver = { 1361 .name = "ad7124", 1362 .of_match_table = ad7124_of_match, 1363 }, 1364 .probe = ad7124_probe, 1365 .id_table = ad71124_ids, 1366 }; 1367 module_spi_driver(ad71124_driver); 1368 1369 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>"); 1370 MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver"); 1371 MODULE_LICENSE("GPL"); 1372 MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA"); 1373