1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices AD4851 DAS driver 4 * 5 * Copyright 2024 Analog Devices Inc. 6 */ 7 8 #include <linux/array_size.h> 9 #include <linux/bitfield.h> 10 #include <linux/bits.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/err.h> 14 #include <linux/minmax.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/module.h> 17 #include <linux/mutex.h> 18 #include <linux/pwm.h> 19 #include <linux/regmap.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/spi/spi.h> 22 #include <linux/types.h> 23 #include <linux/unaligned.h> 24 #include <linux/units.h> 25 26 #include <linux/iio/backend.h> 27 #include <linux/iio/iio.h> 28 29 #define AD4851_REG_INTERFACE_CONFIG_A 0x00 30 #define AD4851_REG_INTERFACE_CONFIG_B 0x01 31 #define AD4851_REG_PRODUCT_ID_L 0x04 32 #define AD4851_REG_PRODUCT_ID_H 0x05 33 #define AD4851_REG_DEVICE_CTRL 0x25 34 #define AD4851_REG_PACKET 0x26 35 #define AD4851_REG_OVERSAMPLE 0x27 36 37 #define AD4851_REG_CH_CONFIG_BASE 0x2A 38 #define AD4851_REG_CHX_SOFTSPAN(ch) ((0x12 * (ch)) + AD4851_REG_CH_CONFIG_BASE) 39 #define AD4851_REG_CHX_OFFSET(ch) (AD4851_REG_CHX_SOFTSPAN(ch) + 0x01) 40 #define AD4851_REG_CHX_OFFSET_LSB(ch) AD4851_REG_CHX_OFFSET(ch) 41 #define AD4851_REG_CHX_OFFSET_MID(ch) (AD4851_REG_CHX_OFFSET_LSB(ch) + 0x01) 42 #define AD4851_REG_CHX_OFFSET_MSB(ch) (AD4851_REG_CHX_OFFSET_MID(ch) + 0x01) 43 #define AD4851_REG_CHX_GAIN(ch) (AD4851_REG_CHX_OFFSET(ch) + 0x03) 44 #define AD4851_REG_CHX_GAIN_LSB(ch) AD4851_REG_CHX_GAIN(ch) 45 #define AD4851_REG_CHX_GAIN_MSB(ch) (AD4851_REG_CHX_GAIN(ch) + 0x01) 46 #define AD4851_REG_CHX_PHASE(ch) (AD4851_REG_CHX_GAIN(ch) + 0x02) 47 #define AD4851_REG_CHX_PHASE_LSB(ch) AD4851_REG_CHX_PHASE(ch) 48 #define AD4851_REG_CHX_PHASE_MSB(ch) (AD4851_REG_CHX_PHASE_LSB(ch) + 0x01) 49 50 #define AD4851_REG_TESTPAT_0(c) (0x38 + (c) * 0x12) 51 #define AD4851_REG_TESTPAT_1(c) (0x39 + (c) * 0x12) 52 #define AD4851_REG_TESTPAT_2(c) (0x3A + (c) * 0x12) 53 #define AD4851_REG_TESTPAT_3(c) (0x3B + (c) * 0x12) 54 55 #define AD4851_SW_RESET (BIT(7) | BIT(0)) 56 #define AD4851_SDO_ENABLE BIT(4) 57 #define AD4851_SINGLE_INSTRUCTION BIT(7) 58 #define AD4851_REFBUF BIT(2) 59 #define AD4851_REFSEL BIT(1) 60 #define AD4851_ECHO_CLOCK_MODE BIT(0) 61 62 #define AD4851_PACKET_FORMAT_0 0 63 #define AD4851_PACKET_FORMAT_1 1 64 #define AD4851_PACKET_FORMAT_MASK GENMASK(1, 0) 65 66 #define AD4851_OS_EN_MSK BIT(7) 67 #define AD4851_OS_RATIO_MSK GENMASK(3, 0) 68 69 #define AD4851_TEST_PAT BIT(2) 70 71 #define AD4858_PACKET_SIZE_20 0 72 #define AD4858_PACKET_SIZE_24 1 73 #define AD4858_PACKET_SIZE_32 2 74 75 #define AD4857_PACKET_SIZE_16 0 76 #define AD4857_PACKET_SIZE_24 1 77 78 #define AD4851_TESTPAT_0_DEFAULT 0x2A 79 #define AD4851_TESTPAT_1_DEFAULT 0x3C 80 #define AD4851_TESTPAT_2_DEFAULT 0xCE 81 #define AD4851_TESTPAT_3_DEFAULT(c) (0x0A + (0x10 * (c))) 82 83 #define AD4851_SOFTSPAN_0V_2V5 0 84 #define AD4851_SOFTSPAN_N2V5_2V5 1 85 #define AD4851_SOFTSPAN_0V_5V 2 86 #define AD4851_SOFTSPAN_N5V_5V 3 87 #define AD4851_SOFTSPAN_0V_6V25 4 88 #define AD4851_SOFTSPAN_N6V25_6V25 5 89 #define AD4851_SOFTSPAN_0V_10V 6 90 #define AD4851_SOFTSPAN_N10V_10V 7 91 #define AD4851_SOFTSPAN_0V_12V5 8 92 #define AD4851_SOFTSPAN_N12V5_12V5 9 93 #define AD4851_SOFTSPAN_0V_20V 10 94 #define AD4851_SOFTSPAN_N20V_20V 11 95 #define AD4851_SOFTSPAN_0V_25V 12 96 #define AD4851_SOFTSPAN_N25V_25V 13 97 #define AD4851_SOFTSPAN_0V_40V 14 98 #define AD4851_SOFTSPAN_N40V_40V 15 99 100 #define AD4851_MAX_LANES 8 101 #define AD4851_MAX_IODELAY 32 102 103 #define AD4851_T_CNVH_NS 40 104 #define AD4851_T_CNVH_NS_MARGIN 10 105 106 #define AD4841_MAX_SCALE_AVAIL 8 107 108 #define AD4851_MAX_CH_NR 8 109 #define AD4851_CH_START 0 110 111 struct ad4851_scale { 112 unsigned int scale_val; 113 u8 reg_val; 114 }; 115 116 static const struct ad4851_scale ad4851_scale_table_unipolar[] = { 117 { 2500, 0x0 }, 118 { 5000, 0x2 }, 119 { 6250, 0x4 }, 120 { 10000, 0x6 }, 121 { 12500, 0x8 }, 122 { 20000, 0xA }, 123 { 25000, 0xC }, 124 { 40000, 0xE }, 125 }; 126 127 static const struct ad4851_scale ad4851_scale_table_bipolar[] = { 128 { 5000, 0x1 }, 129 { 10000, 0x3 }, 130 { 12500, 0x5 }, 131 { 20000, 0x7 }, 132 { 25000, 0x9 }, 133 { 40000, 0xB }, 134 { 50000, 0xD }, 135 { 80000, 0xF }, 136 }; 137 138 static const unsigned int ad4851_scale_avail_unipolar[] = { 139 2500, 140 5000, 141 6250, 142 10000, 143 12500, 144 20000, 145 25000, 146 40000, 147 }; 148 149 static const unsigned int ad4851_scale_avail_bipolar[] = { 150 5000, 151 10000, 152 12500, 153 20000, 154 25000, 155 40000, 156 50000, 157 80000, 158 }; 159 160 struct ad4851_chip_info { 161 const char *name; 162 unsigned int product_id; 163 int num_scales; 164 unsigned long max_sample_rate_hz; 165 unsigned int resolution; 166 unsigned int max_channels; 167 int (*parse_channels)(struct iio_dev *indio_dev); 168 }; 169 170 enum { 171 AD4851_SCAN_TYPE_NORMAL, 172 AD4851_SCAN_TYPE_RESOLUTION_BOOST, 173 }; 174 175 struct ad4851_state { 176 struct spi_device *spi; 177 struct pwm_device *cnv; 178 struct iio_backend *back; 179 /* 180 * Synchronize access to members the of driver state, and ensure 181 * atomicity of consecutive regmap operations. 182 */ 183 struct mutex lock; 184 struct regmap *regmap; 185 const struct ad4851_chip_info *info; 186 struct gpio_desc *pd_gpio; 187 bool resolution_boost_enabled; 188 unsigned long cnv_trigger_rate_hz; 189 unsigned int osr; 190 bool vrefbuf_en; 191 bool vrefio_en; 192 bool bipolar_ch[AD4851_MAX_CH_NR]; 193 unsigned int scales_unipolar[AD4841_MAX_SCALE_AVAIL][2]; 194 unsigned int scales_bipolar[AD4841_MAX_SCALE_AVAIL][2]; 195 }; 196 197 static int ad4851_reg_access(struct iio_dev *indio_dev, 198 unsigned int reg, 199 unsigned int writeval, 200 unsigned int *readval) 201 { 202 struct ad4851_state *st = iio_priv(indio_dev); 203 204 if (readval) 205 return regmap_read(st->regmap, reg, readval); 206 207 return regmap_write(st->regmap, reg, writeval); 208 } 209 210 static int ad4851_set_sampling_freq(struct ad4851_state *st, unsigned int freq) 211 { 212 struct pwm_state cnv_state = { 213 .duty_cycle = AD4851_T_CNVH_NS + AD4851_T_CNVH_NS_MARGIN, 214 .enabled = true, 215 }; 216 int ret; 217 218 freq = clamp(freq, 1, st->info->max_sample_rate_hz); 219 220 cnv_state.period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, freq); 221 222 ret = pwm_apply_might_sleep(st->cnv, &cnv_state); 223 if (ret) 224 return ret; 225 226 st->cnv_trigger_rate_hz = freq; 227 228 return 0; 229 } 230 231 static const int ad4851_oversampling_ratios[] = { 232 1, 2, 4, 8, 16, 32, 64, 128, 233 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 234 65536, 235 }; 236 237 static int ad4851_osr_to_regval(unsigned int ratio) 238 { 239 int i; 240 241 for (i = 1; i < ARRAY_SIZE(ad4851_oversampling_ratios); i++) 242 if (ratio == ad4851_oversampling_ratios[i]) 243 return i - 1; 244 245 return -EINVAL; 246 } 247 248 static int __ad4851_get_scale(struct iio_dev *indio_dev, int scale_tbl, 249 unsigned int *val, unsigned int *val2) 250 { 251 const struct iio_scan_type *scan_type; 252 unsigned int tmp; 253 254 scan_type = iio_get_current_scan_type(indio_dev, &indio_dev->channels[0]); 255 if (IS_ERR(scan_type)) 256 return PTR_ERR(scan_type); 257 258 tmp = ((u64)scale_tbl * MICRO) >> scan_type->realbits; 259 *val = tmp / MICRO; 260 *val2 = tmp % MICRO; 261 262 return 0; 263 } 264 265 static int ad4851_scale_fill(struct iio_dev *indio_dev) 266 { 267 struct ad4851_state *st = iio_priv(indio_dev); 268 unsigned int i, val1, val2; 269 int ret; 270 271 for (i = 0; i < ARRAY_SIZE(ad4851_scale_avail_unipolar); i++) { 272 ret = __ad4851_get_scale(indio_dev, 273 ad4851_scale_avail_unipolar[i], 274 &val1, &val2); 275 if (ret) 276 return ret; 277 278 st->scales_unipolar[i][0] = val1; 279 st->scales_unipolar[i][1] = val2; 280 } 281 282 for (i = 0; i < ARRAY_SIZE(ad4851_scale_avail_bipolar); i++) { 283 ret = __ad4851_get_scale(indio_dev, 284 ad4851_scale_avail_bipolar[i], 285 &val1, &val2); 286 if (ret) 287 return ret; 288 289 st->scales_bipolar[i][0] = val1; 290 st->scales_bipolar[i][1] = val2; 291 } 292 293 return 0; 294 } 295 296 static int ad4851_set_oversampling_ratio(struct iio_dev *indio_dev, 297 const struct iio_chan_spec *chan, 298 unsigned int osr) 299 { 300 struct ad4851_state *st = iio_priv(indio_dev); 301 int val, ret; 302 303 guard(mutex)(&st->lock); 304 305 if (osr == 1) { 306 ret = regmap_clear_bits(st->regmap, AD4851_REG_OVERSAMPLE, 307 AD4851_OS_EN_MSK); 308 if (ret) 309 return ret; 310 } else { 311 val = ad4851_osr_to_regval(osr); 312 if (val < 0) 313 return -EINVAL; 314 315 ret = regmap_update_bits(st->regmap, AD4851_REG_OVERSAMPLE, 316 AD4851_OS_EN_MSK | 317 AD4851_OS_RATIO_MSK, 318 FIELD_PREP(AD4851_OS_EN_MSK, 1) | 319 FIELD_PREP(AD4851_OS_RATIO_MSK, val)); 320 if (ret) 321 return ret; 322 } 323 324 ret = iio_backend_oversampling_ratio_set(st->back, osr); 325 if (ret) 326 return ret; 327 328 switch (st->info->resolution) { 329 case 20: 330 switch (osr) { 331 case 0: 332 return -EINVAL; 333 case 1: 334 val = 20; 335 break; 336 default: 337 val = 24; 338 break; 339 } 340 break; 341 case 16: 342 val = 16; 343 break; 344 default: 345 return -EINVAL; 346 } 347 348 ret = iio_backend_data_size_set(st->back, val); 349 if (ret) 350 return ret; 351 352 if (osr == 1 || st->info->resolution == 16) { 353 ret = regmap_clear_bits(st->regmap, AD4851_REG_PACKET, 354 AD4851_PACKET_FORMAT_MASK); 355 if (ret) 356 return ret; 357 358 st->resolution_boost_enabled = false; 359 } else { 360 ret = regmap_update_bits(st->regmap, AD4851_REG_PACKET, 361 AD4851_PACKET_FORMAT_MASK, 362 FIELD_PREP(AD4851_PACKET_FORMAT_MASK, 1)); 363 if (ret) 364 return ret; 365 366 st->resolution_boost_enabled = true; 367 } 368 369 if (st->osr != osr) { 370 ret = ad4851_scale_fill(indio_dev); 371 if (ret) 372 return ret; 373 374 st->osr = osr; 375 } 376 377 return 0; 378 } 379 380 static int ad4851_get_oversampling_ratio(struct ad4851_state *st, unsigned int *val) 381 { 382 unsigned int osr; 383 int ret; 384 385 guard(mutex)(&st->lock); 386 387 ret = regmap_read(st->regmap, AD4851_REG_OVERSAMPLE, &osr); 388 if (ret) 389 return ret; 390 391 if (!FIELD_GET(AD4851_OS_EN_MSK, osr)) 392 *val = 1; 393 else 394 *val = ad4851_oversampling_ratios[FIELD_GET(AD4851_OS_RATIO_MSK, osr) + 1]; 395 396 st->osr = *val; 397 398 return IIO_VAL_INT; 399 } 400 401 static void ad4851_pwm_disable(void *data) 402 { 403 pwm_disable(data); 404 } 405 406 static int ad4851_setup(struct ad4851_state *st) 407 { 408 unsigned int product_id; 409 int ret; 410 411 if (st->pd_gpio) { 412 /* To initiate a global reset, bring the PD pin high twice */ 413 gpiod_set_value(st->pd_gpio, 1); 414 fsleep(1); 415 gpiod_set_value(st->pd_gpio, 0); 416 fsleep(1); 417 gpiod_set_value(st->pd_gpio, 1); 418 fsleep(1); 419 gpiod_set_value(st->pd_gpio, 0); 420 fsleep(1000); 421 } else { 422 ret = regmap_set_bits(st->regmap, AD4851_REG_INTERFACE_CONFIG_A, 423 AD4851_SW_RESET); 424 if (ret) 425 return ret; 426 } 427 428 if (st->vrefbuf_en) { 429 ret = regmap_set_bits(st->regmap, AD4851_REG_DEVICE_CTRL, 430 AD4851_REFBUF); 431 if (ret) 432 return ret; 433 } 434 435 if (st->vrefio_en) { 436 ret = regmap_set_bits(st->regmap, AD4851_REG_DEVICE_CTRL, 437 AD4851_REFSEL); 438 if (ret) 439 return ret; 440 } 441 442 ret = regmap_write(st->regmap, AD4851_REG_INTERFACE_CONFIG_B, 443 AD4851_SINGLE_INSTRUCTION); 444 if (ret) 445 return ret; 446 447 ret = regmap_write(st->regmap, AD4851_REG_INTERFACE_CONFIG_A, 448 AD4851_SDO_ENABLE); 449 if (ret) 450 return ret; 451 452 ret = regmap_read(st->regmap, AD4851_REG_PRODUCT_ID_L, &product_id); 453 if (ret) 454 return ret; 455 456 if (product_id != st->info->product_id) 457 dev_info(&st->spi->dev, "Unknown product ID: 0x%02X\n", 458 product_id); 459 460 ret = regmap_set_bits(st->regmap, AD4851_REG_DEVICE_CTRL, 461 AD4851_ECHO_CLOCK_MODE); 462 if (ret) 463 return ret; 464 465 return regmap_write(st->regmap, AD4851_REG_PACKET, 0); 466 } 467 468 /* 469 * Find the longest consecutive sequence of false values from field 470 * and return starting index. 471 */ 472 static int ad4851_find_opt(const unsigned long *field, unsigned int start, 473 unsigned int nbits, unsigned int *val) 474 { 475 unsigned int bit = start, end, start_cnt, cnt = 0; 476 477 for_each_clear_bitrange_from(bit, end, field, start + nbits) { 478 if (end - bit > cnt) { 479 cnt = end - bit; 480 start_cnt = bit - start; 481 } 482 } 483 484 if (!cnt) 485 return -ENOENT; 486 487 *val = start_cnt; 488 489 return cnt; 490 } 491 492 static int ad4851_calibrate(struct iio_dev *indio_dev) 493 { 494 struct ad4851_state *st = iio_priv(indio_dev); 495 unsigned int opt_delay, num_lanes, delay, i, s; 496 enum iio_backend_interface_type interface_type; 497 DECLARE_BITMAP(pn_status, AD4851_MAX_LANES * AD4851_MAX_IODELAY); 498 bool status; 499 int c, ret; 500 501 ret = iio_backend_interface_type_get(st->back, &interface_type); 502 if (ret) 503 return ret; 504 505 switch (interface_type) { 506 case IIO_BACKEND_INTERFACE_SERIAL_CMOS: 507 num_lanes = indio_dev->num_channels; 508 break; 509 case IIO_BACKEND_INTERFACE_SERIAL_LVDS: 510 num_lanes = 1; 511 break; 512 default: 513 return -EINVAL; 514 } 515 516 if (st->info->resolution == 16) { 517 ret = iio_backend_data_size_set(st->back, 24); 518 if (ret) 519 return ret; 520 521 ret = regmap_write(st->regmap, AD4851_REG_PACKET, 522 AD4851_TEST_PAT | AD4857_PACKET_SIZE_24); 523 if (ret) 524 return ret; 525 } else { 526 ret = iio_backend_data_size_set(st->back, 32); 527 if (ret) 528 return ret; 529 530 ret = regmap_write(st->regmap, AD4851_REG_PACKET, 531 AD4851_TEST_PAT | AD4858_PACKET_SIZE_32); 532 if (ret) 533 return ret; 534 } 535 536 for (i = 0; i < indio_dev->num_channels; i++) { 537 ret = regmap_write(st->regmap, AD4851_REG_TESTPAT_0(i), 538 AD4851_TESTPAT_0_DEFAULT); 539 if (ret) 540 return ret; 541 542 ret = regmap_write(st->regmap, AD4851_REG_TESTPAT_1(i), 543 AD4851_TESTPAT_1_DEFAULT); 544 if (ret) 545 return ret; 546 547 ret = regmap_write(st->regmap, AD4851_REG_TESTPAT_2(i), 548 AD4851_TESTPAT_2_DEFAULT); 549 if (ret) 550 return ret; 551 552 ret = regmap_write(st->regmap, AD4851_REG_TESTPAT_3(i), 553 AD4851_TESTPAT_3_DEFAULT(i)); 554 if (ret) 555 return ret; 556 557 ret = iio_backend_chan_enable(st->back, 558 indio_dev->channels[i].channel); 559 if (ret) 560 return ret; 561 } 562 563 for (i = 0; i < num_lanes; i++) { 564 for (delay = 0; delay < AD4851_MAX_IODELAY; delay++) { 565 ret = iio_backend_iodelay_set(st->back, i, delay); 566 if (ret) 567 return ret; 568 569 ret = iio_backend_chan_status(st->back, i, &status); 570 if (ret) 571 return ret; 572 573 __assign_bit(i * AD4851_MAX_IODELAY + delay, pn_status, 574 status); 575 } 576 } 577 578 for (i = 0; i < num_lanes; i++) { 579 c = ad4851_find_opt(pn_status, i * AD4851_MAX_IODELAY, 580 AD4851_MAX_IODELAY, &s); 581 if (c < 0) 582 return c; 583 584 opt_delay = s + c / 2; 585 ret = iio_backend_iodelay_set(st->back, i, opt_delay); 586 if (ret) 587 return ret; 588 } 589 590 for (i = 0; i < indio_dev->num_channels; i++) { 591 ret = iio_backend_chan_disable(st->back, i); 592 if (ret) 593 return ret; 594 } 595 596 ret = iio_backend_data_size_set(st->back, 20); 597 if (ret) 598 return ret; 599 600 return regmap_write(st->regmap, AD4851_REG_PACKET, 0); 601 } 602 603 static int ad4851_get_calibscale(struct ad4851_state *st, int ch, int *val, int *val2) 604 { 605 unsigned int reg_val; 606 int gain; 607 int ret; 608 609 guard(mutex)(&st->lock); 610 611 ret = regmap_read(st->regmap, AD4851_REG_CHX_GAIN_MSB(ch), ®_val); 612 if (ret) 613 return ret; 614 615 gain = reg_val << 8; 616 617 ret = regmap_read(st->regmap, AD4851_REG_CHX_GAIN_LSB(ch), ®_val); 618 if (ret) 619 return ret; 620 621 gain |= reg_val; 622 623 *val = gain; 624 *val2 = 15; 625 626 return IIO_VAL_FRACTIONAL_LOG2; 627 } 628 629 static int ad4851_set_calibscale(struct ad4851_state *st, int ch, int val, 630 int val2) 631 { 632 u64 gain; 633 u8 buf[2]; 634 int ret; 635 636 if (val < 0 || val2 < 0) 637 return -EINVAL; 638 639 gain = val * MICRO + val2; 640 gain = DIV_U64_ROUND_CLOSEST(gain * 32768, MICRO); 641 642 put_unaligned_be16(gain, buf); 643 644 guard(mutex)(&st->lock); 645 646 ret = regmap_write(st->regmap, AD4851_REG_CHX_GAIN_MSB(ch), buf[0]); 647 if (ret) 648 return ret; 649 650 return regmap_write(st->regmap, AD4851_REG_CHX_GAIN_LSB(ch), buf[1]); 651 } 652 653 static int ad4851_get_calibbias(struct ad4851_state *st, int ch, int *val) 654 { 655 unsigned int lsb, mid, msb; 656 int ret; 657 658 guard(mutex)(&st->lock); 659 /* 660 * After testing, the bulk_write operations doesn't work as expected 661 * here since the cs needs to be raised after each byte transaction. 662 */ 663 ret = regmap_read(st->regmap, AD4851_REG_CHX_OFFSET_MSB(ch), &msb); 664 if (ret) 665 return ret; 666 667 ret = regmap_read(st->regmap, AD4851_REG_CHX_OFFSET_MID(ch), &mid); 668 if (ret) 669 return ret; 670 671 ret = regmap_read(st->regmap, AD4851_REG_CHX_OFFSET_LSB(ch), &lsb); 672 if (ret) 673 return ret; 674 675 if (st->info->resolution == 16) { 676 *val = msb << 8; 677 *val |= mid; 678 *val = sign_extend32(*val, 15); 679 } else { 680 *val = msb << 12; 681 *val |= mid << 4; 682 *val |= lsb >> 4; 683 *val = sign_extend32(*val, 19); 684 } 685 686 return IIO_VAL_INT; 687 } 688 689 static int ad4851_set_calibbias(struct ad4851_state *st, int ch, int val) 690 { 691 u8 buf[3]; 692 int ret; 693 694 if (val < 0) 695 return -EINVAL; 696 697 if (st->info->resolution == 16) 698 put_unaligned_be16(val, buf); 699 else 700 put_unaligned_be24(val << 4, buf); 701 702 guard(mutex)(&st->lock); 703 /* 704 * After testing, the bulk_write operations doesn't work as expected 705 * here since the cs needs to be raised after each byte transaction. 706 */ 707 ret = regmap_write(st->regmap, AD4851_REG_CHX_OFFSET_LSB(ch), buf[2]); 708 if (ret) 709 return ret; 710 711 ret = regmap_write(st->regmap, AD4851_REG_CHX_OFFSET_MID(ch), buf[1]); 712 if (ret) 713 return ret; 714 715 return regmap_write(st->regmap, AD4851_REG_CHX_OFFSET_MSB(ch), buf[0]); 716 } 717 718 static int ad4851_set_scale(struct iio_dev *indio_dev, 719 const struct iio_chan_spec *chan, int val, int val2) 720 { 721 struct ad4851_state *st = iio_priv(indio_dev); 722 unsigned int scale_val[2]; 723 unsigned int i; 724 const struct ad4851_scale *scale_table; 725 size_t table_size; 726 int ret; 727 728 if (st->bipolar_ch[chan->channel]) { 729 scale_table = ad4851_scale_table_bipolar; 730 table_size = ARRAY_SIZE(ad4851_scale_table_bipolar); 731 } else { 732 scale_table = ad4851_scale_table_unipolar; 733 table_size = ARRAY_SIZE(ad4851_scale_table_unipolar); 734 } 735 736 for (i = 0; i < table_size; i++) { 737 ret = __ad4851_get_scale(indio_dev, scale_table[i].scale_val, 738 &scale_val[0], &scale_val[1]); 739 if (ret) 740 return ret; 741 742 if (scale_val[0] != val || scale_val[1] != val2) 743 continue; 744 745 return regmap_write(st->regmap, 746 AD4851_REG_CHX_SOFTSPAN(chan->channel), 747 scale_table[i].reg_val); 748 } 749 750 return -EINVAL; 751 } 752 753 static int ad4851_get_scale(struct iio_dev *indio_dev, 754 const struct iio_chan_spec *chan, int *val, 755 int *val2) 756 { 757 struct ad4851_state *st = iio_priv(indio_dev); 758 const struct ad4851_scale *scale_table; 759 size_t table_size; 760 u32 softspan_val; 761 int i, ret; 762 763 if (st->bipolar_ch[chan->channel]) { 764 scale_table = ad4851_scale_table_bipolar; 765 table_size = ARRAY_SIZE(ad4851_scale_table_bipolar); 766 } else { 767 scale_table = ad4851_scale_table_unipolar; 768 table_size = ARRAY_SIZE(ad4851_scale_table_unipolar); 769 } 770 771 ret = regmap_read(st->regmap, AD4851_REG_CHX_SOFTSPAN(chan->channel), 772 &softspan_val); 773 if (ret) 774 return ret; 775 776 for (i = 0; i < table_size; i++) { 777 if (softspan_val == scale_table[i].reg_val) 778 break; 779 } 780 781 if (i == table_size) 782 return -EIO; 783 784 ret = __ad4851_get_scale(indio_dev, scale_table[i].scale_val, val, 785 val2); 786 if (ret) 787 return ret; 788 789 return IIO_VAL_INT_PLUS_MICRO; 790 } 791 792 static int ad4851_read_raw(struct iio_dev *indio_dev, 793 const struct iio_chan_spec *chan, 794 int *val, int *val2, long info) 795 { 796 struct ad4851_state *st = iio_priv(indio_dev); 797 798 switch (info) { 799 case IIO_CHAN_INFO_SAMP_FREQ: 800 *val = st->cnv_trigger_rate_hz; 801 *val2 = st->osr; 802 return IIO_VAL_FRACTIONAL; 803 case IIO_CHAN_INFO_CALIBSCALE: 804 return ad4851_get_calibscale(st, chan->channel, val, val2); 805 case IIO_CHAN_INFO_SCALE: 806 return ad4851_get_scale(indio_dev, chan, val, val2); 807 case IIO_CHAN_INFO_CALIBBIAS: 808 return ad4851_get_calibbias(st, chan->channel, val); 809 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 810 return ad4851_get_oversampling_ratio(st, val); 811 default: 812 return -EINVAL; 813 } 814 } 815 816 static int ad4851_write_raw(struct iio_dev *indio_dev, 817 struct iio_chan_spec const *chan, 818 int val, int val2, long info) 819 { 820 struct ad4851_state *st = iio_priv(indio_dev); 821 822 switch (info) { 823 case IIO_CHAN_INFO_SAMP_FREQ: 824 if (val < 0 || val2 < 0) 825 return -EINVAL; 826 return ad4851_set_sampling_freq(st, val * st->osr + val2 * st->osr / MICRO); 827 case IIO_CHAN_INFO_SCALE: 828 return ad4851_set_scale(indio_dev, chan, val, val2); 829 case IIO_CHAN_INFO_CALIBSCALE: 830 return ad4851_set_calibscale(st, chan->channel, val, val2); 831 case IIO_CHAN_INFO_CALIBBIAS: 832 return ad4851_set_calibbias(st, chan->channel, val); 833 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 834 return ad4851_set_oversampling_ratio(indio_dev, chan, val); 835 default: 836 return -EINVAL; 837 } 838 } 839 840 static int ad4851_update_scan_mode(struct iio_dev *indio_dev, 841 const unsigned long *scan_mask) 842 { 843 struct ad4851_state *st = iio_priv(indio_dev); 844 unsigned int c; 845 int ret; 846 847 for (c = 0; c < indio_dev->num_channels; c++) { 848 if (test_bit(c, scan_mask)) 849 ret = iio_backend_chan_enable(st->back, c); 850 else 851 ret = iio_backend_chan_disable(st->back, c); 852 if (ret) 853 return ret; 854 } 855 856 return 0; 857 } 858 859 static int ad4851_read_avail(struct iio_dev *indio_dev, 860 struct iio_chan_spec const *chan, 861 const int **vals, int *type, int *length, 862 long mask) 863 { 864 struct ad4851_state *st = iio_priv(indio_dev); 865 866 switch (mask) { 867 case IIO_CHAN_INFO_SCALE: 868 if (st->bipolar_ch[chan->channel]) { 869 *vals = (const int *)st->scales_bipolar; 870 *type = IIO_VAL_INT_PLUS_MICRO; 871 /* Values are stored in a 2D matrix */ 872 *length = ARRAY_SIZE(ad4851_scale_avail_bipolar) * 2; 873 } else { 874 *vals = (const int *)st->scales_unipolar; 875 *type = IIO_VAL_INT_PLUS_MICRO; 876 /* Values are stored in a 2D matrix */ 877 *length = ARRAY_SIZE(ad4851_scale_avail_unipolar) * 2; 878 } 879 return IIO_AVAIL_LIST; 880 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 881 *vals = ad4851_oversampling_ratios; 882 *length = ARRAY_SIZE(ad4851_oversampling_ratios); 883 *type = IIO_VAL_INT; 884 return IIO_AVAIL_LIST; 885 default: 886 return -EINVAL; 887 } 888 } 889 890 static const struct iio_scan_type ad4851_scan_type_20_u[] = { 891 [AD4851_SCAN_TYPE_NORMAL] = { 892 .sign = 'u', 893 .realbits = 20, 894 .storagebits = 32, 895 }, 896 [AD4851_SCAN_TYPE_RESOLUTION_BOOST] = { 897 .sign = 'u', 898 .realbits = 24, 899 .storagebits = 32, 900 }, 901 }; 902 903 static const struct iio_scan_type ad4851_scan_type_20_b[] = { 904 [AD4851_SCAN_TYPE_NORMAL] = { 905 .sign = 's', 906 .realbits = 20, 907 .storagebits = 32, 908 }, 909 [AD4851_SCAN_TYPE_RESOLUTION_BOOST] = { 910 .sign = 's', 911 .realbits = 24, 912 .storagebits = 32, 913 }, 914 }; 915 916 static int ad4851_get_current_scan_type(const struct iio_dev *indio_dev, 917 const struct iio_chan_spec *chan) 918 { 919 struct ad4851_state *st = iio_priv(indio_dev); 920 921 return st->resolution_boost_enabled ? AD4851_SCAN_TYPE_RESOLUTION_BOOST 922 : AD4851_SCAN_TYPE_NORMAL; 923 } 924 925 #define AD4851_IIO_CHANNEL \ 926 .type = IIO_VOLTAGE, \ 927 .info_mask_separate = BIT(IIO_CHAN_INFO_CALIBSCALE) | \ 928 BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 929 BIT(IIO_CHAN_INFO_SCALE), \ 930 .info_mask_separate_available = BIT(IIO_CHAN_INFO_SCALE), \ 931 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 932 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 933 .info_mask_shared_by_all_available = \ 934 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 935 .indexed = 1 936 937 /* 938 * In case of AD4858_IIO_CHANNEL the scan_type is handled dynamically during the 939 * parse_channels function. 940 */ 941 #define AD4858_IIO_CHANNEL \ 942 { \ 943 AD4851_IIO_CHANNEL \ 944 } 945 946 #define AD4857_IIO_CHANNEL \ 947 { \ 948 AD4851_IIO_CHANNEL, \ 949 .scan_type = { \ 950 .sign = 'u', \ 951 .realbits = 16, \ 952 .storagebits = 16, \ 953 }, \ 954 } 955 956 static int ad4851_parse_channels_common(struct iio_dev *indio_dev, 957 struct iio_chan_spec **chans, 958 const struct iio_chan_spec ad4851_chan) 959 { 960 struct ad4851_state *st = iio_priv(indio_dev); 961 struct device *dev = &st->spi->dev; 962 struct iio_chan_spec *channels, *chan_start; 963 unsigned int num_channels, reg; 964 unsigned int index = 0; 965 int ret; 966 967 num_channels = device_get_child_node_count(dev); 968 if (num_channels > AD4851_MAX_CH_NR) 969 return dev_err_probe(dev, -EINVAL, "Too many channels: %u\n", 970 num_channels); 971 972 channels = devm_kcalloc(dev, num_channels, sizeof(*channels), GFP_KERNEL); 973 if (!channels) 974 return -ENOMEM; 975 976 chan_start = channels; 977 978 device_for_each_child_node_scoped(dev, child) { 979 ret = fwnode_property_read_u32(child, "reg", ®); 980 if (ret) 981 return dev_err_probe(dev, ret, 982 "Missing channel number\n"); 983 if (reg >= AD4851_MAX_CH_NR) 984 return dev_err_probe(dev, -EINVAL, 985 "Invalid channel number\n"); 986 *channels = ad4851_chan; 987 channels->scan_index = index++; 988 channels->channel = reg; 989 990 if (fwnode_property_present(child, "diff-channels")) { 991 channels->channel2 = reg + st->info->max_channels; 992 channels->differential = 1; 993 } 994 995 st->bipolar_ch[reg] = fwnode_property_read_bool(child, "bipolar"); 996 997 if (st->bipolar_ch[reg]) { 998 channels->scan_type.sign = 's'; 999 } else { 1000 ret = regmap_write(st->regmap, AD4851_REG_CHX_SOFTSPAN(reg), 1001 AD4851_SOFTSPAN_0V_40V); 1002 if (ret) 1003 return ret; 1004 } 1005 1006 channels++; 1007 } 1008 1009 *chans = chan_start; 1010 1011 return num_channels; 1012 } 1013 1014 static int ad4857_parse_channels(struct iio_dev *indio_dev) 1015 { 1016 struct iio_chan_spec *ad4851_channels; 1017 const struct iio_chan_spec ad4851_chan = AD4857_IIO_CHANNEL; 1018 int ret; 1019 1020 ret = ad4851_parse_channels_common(indio_dev, &ad4851_channels, 1021 ad4851_chan); 1022 if (ret < 0) 1023 return ret; 1024 1025 indio_dev->channels = ad4851_channels; 1026 indio_dev->num_channels = ret; 1027 1028 return 0; 1029 } 1030 1031 static int ad4858_parse_channels(struct iio_dev *indio_dev) 1032 { 1033 struct ad4851_state *st = iio_priv(indio_dev); 1034 struct device *dev = &st->spi->dev; 1035 struct iio_chan_spec *ad4851_channels; 1036 const struct iio_chan_spec ad4851_chan = AD4858_IIO_CHANNEL; 1037 int ret, i = 0; 1038 1039 ret = ad4851_parse_channels_common(indio_dev, &ad4851_channels, 1040 ad4851_chan); 1041 if (ret < 0) 1042 return ret; 1043 1044 device_for_each_child_node_scoped(dev, child) { 1045 ad4851_channels[i].has_ext_scan_type = 1; 1046 if (fwnode_property_read_bool(child, "bipolar")) { 1047 ad4851_channels[i].ext_scan_type = ad4851_scan_type_20_b; 1048 ad4851_channels[i].num_ext_scan_type = ARRAY_SIZE(ad4851_scan_type_20_b); 1049 } else { 1050 ad4851_channels[i].ext_scan_type = ad4851_scan_type_20_u; 1051 ad4851_channels[i].num_ext_scan_type = ARRAY_SIZE(ad4851_scan_type_20_u); 1052 } 1053 i++; 1054 } 1055 1056 indio_dev->channels = ad4851_channels; 1057 indio_dev->num_channels = ret; 1058 1059 return 0; 1060 } 1061 1062 /* 1063 * parse_channels() function handles the rest of the channel related attributes 1064 * that are usually are stored in the chip info structure. 1065 */ 1066 static const struct ad4851_chip_info ad4851_info = { 1067 .name = "ad4851", 1068 .product_id = 0x67, 1069 .max_sample_rate_hz = 250 * KILO, 1070 .resolution = 16, 1071 .max_channels = AD4851_MAX_CH_NR, 1072 .parse_channels = ad4857_parse_channels, 1073 }; 1074 1075 static const struct ad4851_chip_info ad4852_info = { 1076 .name = "ad4852", 1077 .product_id = 0x66, 1078 .max_sample_rate_hz = 250 * KILO, 1079 .resolution = 20, 1080 .max_channels = AD4851_MAX_CH_NR, 1081 .parse_channels = ad4858_parse_channels, 1082 }; 1083 1084 static const struct ad4851_chip_info ad4853_info = { 1085 .name = "ad4853", 1086 .product_id = 0x65, 1087 .max_sample_rate_hz = 1 * MEGA, 1088 .resolution = 16, 1089 .max_channels = AD4851_MAX_CH_NR, 1090 .parse_channels = ad4857_parse_channels, 1091 }; 1092 1093 static const struct ad4851_chip_info ad4854_info = { 1094 .name = "ad4854", 1095 .product_id = 0x64, 1096 .max_sample_rate_hz = 1 * MEGA, 1097 .resolution = 20, 1098 .max_channels = AD4851_MAX_CH_NR, 1099 .parse_channels = ad4858_parse_channels, 1100 }; 1101 1102 static const struct ad4851_chip_info ad4855_info = { 1103 .name = "ad4855", 1104 .product_id = 0x63, 1105 .max_sample_rate_hz = 250 * KILO, 1106 .resolution = 16, 1107 .max_channels = AD4851_MAX_CH_NR, 1108 .parse_channels = ad4857_parse_channels, 1109 }; 1110 1111 static const struct ad4851_chip_info ad4856_info = { 1112 .name = "ad4856", 1113 .product_id = 0x62, 1114 .max_sample_rate_hz = 250 * KILO, 1115 .resolution = 20, 1116 .max_channels = AD4851_MAX_CH_NR, 1117 .parse_channels = ad4858_parse_channels, 1118 }; 1119 1120 static const struct ad4851_chip_info ad4857_info = { 1121 .name = "ad4857", 1122 .product_id = 0x61, 1123 .max_sample_rate_hz = 1 * MEGA, 1124 .resolution = 16, 1125 .max_channels = AD4851_MAX_CH_NR, 1126 .parse_channels = ad4857_parse_channels, 1127 }; 1128 1129 static const struct ad4851_chip_info ad4858_info = { 1130 .name = "ad4858", 1131 .product_id = 0x60, 1132 .max_sample_rate_hz = 1 * MEGA, 1133 .resolution = 20, 1134 .max_channels = AD4851_MAX_CH_NR, 1135 .parse_channels = ad4858_parse_channels, 1136 }; 1137 1138 static const struct ad4851_chip_info ad4858i_info = { 1139 .name = "ad4858i", 1140 .product_id = 0x6F, 1141 .max_sample_rate_hz = 1 * MEGA, 1142 .resolution = 20, 1143 .max_channels = AD4851_MAX_CH_NR, 1144 .parse_channels = ad4858_parse_channels, 1145 }; 1146 1147 static const struct iio_info ad4851_iio_info = { 1148 .debugfs_reg_access = ad4851_reg_access, 1149 .read_raw = ad4851_read_raw, 1150 .write_raw = ad4851_write_raw, 1151 .update_scan_mode = ad4851_update_scan_mode, 1152 .get_current_scan_type = ad4851_get_current_scan_type, 1153 .read_avail = ad4851_read_avail, 1154 }; 1155 1156 static const struct regmap_config regmap_config = { 1157 .reg_bits = 16, 1158 .val_bits = 8, 1159 .read_flag_mask = BIT(7), 1160 }; 1161 1162 static const char * const ad4851_power_supplies[] = { 1163 "vcc", "vdd", "vee", "vio", 1164 }; 1165 1166 static int ad4851_probe(struct spi_device *spi) 1167 { 1168 struct iio_dev *indio_dev; 1169 struct device *dev = &spi->dev; 1170 struct ad4851_state *st; 1171 int ret; 1172 1173 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1174 if (!indio_dev) 1175 return -ENOMEM; 1176 1177 st = iio_priv(indio_dev); 1178 st->spi = spi; 1179 1180 ret = devm_mutex_init(dev, &st->lock); 1181 if (ret) 1182 return ret; 1183 1184 ret = devm_regulator_bulk_get_enable(dev, 1185 ARRAY_SIZE(ad4851_power_supplies), 1186 ad4851_power_supplies); 1187 if (ret) 1188 return dev_err_probe(dev, ret, 1189 "failed to get and enable supplies\n"); 1190 1191 ret = devm_regulator_get_enable_optional(dev, "vddh"); 1192 if (ret < 0 && ret != -ENODEV) 1193 return dev_err_probe(dev, ret, "failed to enable vddh voltage\n"); 1194 1195 ret = devm_regulator_get_enable_optional(dev, "vddl"); 1196 if (ret < 0 && ret != -ENODEV) 1197 return dev_err_probe(dev, ret, "failed to enable vddl voltage\n"); 1198 1199 ret = devm_regulator_get_enable_optional(dev, "vrefbuf"); 1200 if (ret < 0 && ret != -ENODEV) 1201 return dev_err_probe(dev, ret, "failed to enable vrefbuf voltage\n"); 1202 1203 st->vrefbuf_en = ret != -ENODEV; 1204 1205 ret = devm_regulator_get_enable_optional(dev, "vrefio"); 1206 if (ret < 0 && ret != -ENODEV) 1207 return dev_err_probe(dev, ret, "failed to enable vrefio voltage\n"); 1208 1209 st->vrefio_en = ret != -ENODEV; 1210 1211 st->pd_gpio = devm_gpiod_get_optional(dev, "pd", GPIOD_OUT_LOW); 1212 if (IS_ERR(st->pd_gpio)) 1213 return dev_err_probe(dev, PTR_ERR(st->pd_gpio), 1214 "Error on requesting pd GPIO\n"); 1215 1216 st->cnv = devm_pwm_get(dev, NULL); 1217 if (IS_ERR(st->cnv)) 1218 return dev_err_probe(dev, PTR_ERR(st->cnv), 1219 "Error on requesting pwm\n"); 1220 1221 st->info = spi_get_device_match_data(spi); 1222 if (!st->info) 1223 return -ENODEV; 1224 1225 st->regmap = devm_regmap_init_spi(spi, ®map_config); 1226 if (IS_ERR(st->regmap)) 1227 return PTR_ERR(st->regmap); 1228 1229 ret = ad4851_set_sampling_freq(st, HZ_PER_MHZ); 1230 if (ret) 1231 return ret; 1232 1233 ret = devm_add_action_or_reset(&st->spi->dev, ad4851_pwm_disable, 1234 st->cnv); 1235 if (ret) 1236 return ret; 1237 1238 ret = ad4851_setup(st); 1239 if (ret) 1240 return ret; 1241 1242 indio_dev->name = st->info->name; 1243 indio_dev->info = &ad4851_iio_info; 1244 indio_dev->modes = INDIO_DIRECT_MODE; 1245 1246 ret = st->info->parse_channels(indio_dev); 1247 if (ret) 1248 return ret; 1249 1250 ret = ad4851_scale_fill(indio_dev); 1251 if (ret) 1252 return ret; 1253 1254 st->back = devm_iio_backend_get(dev, NULL); 1255 if (IS_ERR(st->back)) 1256 return PTR_ERR(st->back); 1257 1258 ret = devm_iio_backend_request_buffer(dev, st->back, indio_dev); 1259 if (ret) 1260 return ret; 1261 1262 ret = devm_iio_backend_enable(dev, st->back); 1263 if (ret) 1264 return ret; 1265 1266 ret = ad4851_calibrate(indio_dev); 1267 if (ret) 1268 return ret; 1269 1270 return devm_iio_device_register(dev, indio_dev); 1271 } 1272 1273 static const struct of_device_id ad4851_of_match[] = { 1274 { .compatible = "adi,ad4851", .data = &ad4851_info, }, 1275 { .compatible = "adi,ad4852", .data = &ad4852_info, }, 1276 { .compatible = "adi,ad4853", .data = &ad4853_info, }, 1277 { .compatible = "adi,ad4854", .data = &ad4854_info, }, 1278 { .compatible = "adi,ad4855", .data = &ad4855_info, }, 1279 { .compatible = "adi,ad4856", .data = &ad4856_info, }, 1280 { .compatible = "adi,ad4857", .data = &ad4857_info, }, 1281 { .compatible = "adi,ad4858", .data = &ad4858_info, }, 1282 { .compatible = "adi,ad4858i", .data = &ad4858i_info, }, 1283 { } 1284 }; 1285 1286 static const struct spi_device_id ad4851_spi_id[] = { 1287 { "ad4851", (kernel_ulong_t)&ad4851_info }, 1288 { "ad4852", (kernel_ulong_t)&ad4852_info }, 1289 { "ad4853", (kernel_ulong_t)&ad4853_info }, 1290 { "ad4854", (kernel_ulong_t)&ad4854_info }, 1291 { "ad4855", (kernel_ulong_t)&ad4855_info }, 1292 { "ad4856", (kernel_ulong_t)&ad4856_info }, 1293 { "ad4857", (kernel_ulong_t)&ad4857_info }, 1294 { "ad4858", (kernel_ulong_t)&ad4858_info }, 1295 { "ad4858i", (kernel_ulong_t)&ad4858i_info }, 1296 { } 1297 }; 1298 MODULE_DEVICE_TABLE(spi, ad4851_spi_id); 1299 1300 static struct spi_driver ad4851_driver = { 1301 .probe = ad4851_probe, 1302 .driver = { 1303 .name = "ad4851", 1304 .of_match_table = ad4851_of_match, 1305 }, 1306 .id_table = ad4851_spi_id, 1307 }; 1308 module_spi_driver(ad4851_driver); 1309 1310 MODULE_AUTHOR("Sergiu Cuciurean <sergiu.cuciurean@analog.com>"); 1311 MODULE_AUTHOR("Dragos Bogdan <dragos.bogdan@analog.com>"); 1312 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com>"); 1313 MODULE_DESCRIPTION("Analog Devices AD4851 DAS driver"); 1314 MODULE_LICENSE("GPL"); 1315 MODULE_IMPORT_NS("IIO_BACKEND"); 1316