1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Murata SCA3300 3-axis industrial accelerometer 4 * 5 * Copyright (c) 2021 Vaisala Oyj. All rights reserved. 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/crc8.h> 10 #include <linux/delay.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/spi/spi.h> 14 15 #include <linux/unaligned.h> 16 17 #include <linux/iio/buffer.h> 18 #include <linux/iio/iio.h> 19 #include <linux/iio/sysfs.h> 20 #include <linux/iio/trigger_consumer.h> 21 #include <linux/iio/triggered_buffer.h> 22 23 #define SCA3300_ALIAS "sca3300" 24 25 #define SCA3300_CRC8_POLYNOMIAL 0x1d 26 27 /* Device mode register */ 28 #define SCA3300_REG_MODE 0xd 29 #define SCA3300_MODE_SW_RESET 0x20 30 31 /* Last register in map */ 32 #define SCA3300_REG_SELBANK 0x1f 33 34 /* Device status and mask */ 35 #define SCA3300_REG_STATUS 0x6 36 #define SCA3300_STATUS_MASK GENMASK(8, 0) 37 38 /* Device ID */ 39 #define SCA3300_REG_WHOAMI 0x10 40 #define SCA3300_WHOAMI_ID 0x51 41 #define SCL3300_WHOAMI_ID 0xC1 42 43 /* Device return status and mask */ 44 #define SCA3300_VALUE_RS_ERROR 0x3 45 #define SCA3300_MASK_RS_STATUS GENMASK(1, 0) 46 47 #define SCL3300_REG_ANG_CTRL 0x0C 48 #define SCL3300_ANG_ENABLE 0x1F 49 50 enum sca3300_scan_indexes { 51 SCA3300_ACC_X = 0, 52 SCA3300_ACC_Y, 53 SCA3300_ACC_Z, 54 SCA3300_TEMP, 55 SCA3300_INCLI_X, 56 SCA3300_INCLI_Y, 57 SCA3300_INCLI_Z, 58 SCA3300_SCAN_MAX 59 }; 60 61 #define SCA3300_ACCEL_CHANNEL(index, reg, axis) { \ 62 .type = IIO_ACCEL, \ 63 .address = reg, \ 64 .modified = 1, \ 65 .channel2 = IIO_MOD_##axis, \ 66 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 67 .info_mask_shared_by_type = \ 68 BIT(IIO_CHAN_INFO_SCALE) | \ 69 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 70 .info_mask_shared_by_type_available = \ 71 BIT(IIO_CHAN_INFO_SCALE) | \ 72 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 73 .scan_index = index, \ 74 .scan_type = { \ 75 .sign = 's', \ 76 .realbits = 16, \ 77 .storagebits = 16, \ 78 .endianness = IIO_CPU, \ 79 }, \ 80 } 81 82 #define SCA3300_INCLI_CHANNEL(index, reg, axis) { \ 83 .type = IIO_INCLI, \ 84 .address = reg, \ 85 .modified = 1, \ 86 .channel2 = IIO_MOD_##axis, \ 87 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 88 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 89 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \ 90 .scan_index = index, \ 91 .scan_type = { \ 92 .sign = 's', \ 93 .realbits = 16, \ 94 .storagebits = 16, \ 95 .endianness = IIO_CPU, \ 96 }, \ 97 } 98 99 #define SCA3300_TEMP_CHANNEL(index, reg) { \ 100 .type = IIO_TEMP, \ 101 .address = reg, \ 102 .scan_index = index, \ 103 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 104 .scan_type = { \ 105 .sign = 's', \ 106 .realbits = 16, \ 107 .storagebits = 16, \ 108 .endianness = IIO_CPU, \ 109 }, \ 110 } 111 112 static const struct iio_chan_spec sca3300_channels[] = { 113 SCA3300_ACCEL_CHANNEL(SCA3300_ACC_X, 0x1, X), 114 SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Y, 0x2, Y), 115 SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Z, 0x3, Z), 116 SCA3300_TEMP_CHANNEL(SCA3300_TEMP, 0x05), 117 IIO_CHAN_SOFT_TIMESTAMP(4), 118 }; 119 120 static const int sca3300_lp_freq[] = {70, 10}; 121 static const int sca3300_lp_freq_map[] = {0, 0, 0, 1}; 122 123 static const int scl3300_lp_freq[] = {40, 70, 10}; 124 static const int scl3300_lp_freq_map[] = {0, 1, 2}; 125 126 static const int sca3300_accel_scale[][2] = {{0, 370}, {0, 741}, {0, 185}}; 127 static const int sca3300_accel_scale_map[] = {0, 1, 2, 2}; 128 129 static const int scl3300_accel_scale[][2] = {{0, 167}, {0, 333}, {0, 83}}; 130 static const int scl3300_accel_scale_map[] = {0, 1, 2}; 131 132 static const int scl3300_incli_scale[][2] = {{0, 5495}}; 133 static const int scl3300_incli_scale_map[] = {0, 0, 0}; 134 135 static const int sca3300_avail_modes_map[] = {0, 1, 2, 3}; 136 static const int scl3300_avail_modes_map[] = {0, 1, 3}; 137 138 static const struct iio_chan_spec scl3300_channels[] = { 139 SCA3300_ACCEL_CHANNEL(SCA3300_ACC_X, 0x1, X), 140 SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Y, 0x2, Y), 141 SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Z, 0x3, Z), 142 SCA3300_TEMP_CHANNEL(SCA3300_TEMP, 0x05), 143 SCA3300_INCLI_CHANNEL(SCA3300_INCLI_X, 0x09, X), 144 SCA3300_INCLI_CHANNEL(SCA3300_INCLI_Y, 0x0A, Y), 145 SCA3300_INCLI_CHANNEL(SCA3300_INCLI_Z, 0x0B, Z), 146 IIO_CHAN_SOFT_TIMESTAMP(7), 147 }; 148 149 static const unsigned long sca3300_scan_masks[] = { 150 BIT(SCA3300_ACC_X) | BIT(SCA3300_ACC_Y) | BIT(SCA3300_ACC_Z) | 151 BIT(SCA3300_TEMP), 152 0 153 }; 154 155 static const unsigned long scl3300_scan_masks[] = { 156 BIT(SCA3300_ACC_X) | BIT(SCA3300_ACC_Y) | BIT(SCA3300_ACC_Z) | 157 BIT(SCA3300_TEMP) | 158 BIT(SCA3300_INCLI_X) | BIT(SCA3300_INCLI_Y) | BIT(SCA3300_INCLI_Z), 159 0 160 }; 161 162 struct sca3300_chip_info { 163 const char *name; 164 const unsigned long *scan_masks; 165 const struct iio_chan_spec *channels; 166 u8 num_channels; 167 u8 num_accel_scales; 168 const int (*accel_scale)[2]; 169 const int *accel_scale_map; 170 const int (*incli_scale)[2]; 171 const int *incli_scale_map; 172 u8 num_incli_scales; 173 u8 num_freqs; 174 const int *freq_table; 175 const int *freq_map; 176 const int *avail_modes_table; 177 u8 num_avail_modes; 178 u8 chip_id; 179 bool angle_supported; 180 }; 181 182 /** 183 * struct sca3300_data - device data 184 * @spi: SPI device structure 185 * @lock: Data buffer lock 186 * @chip: Sensor chip specific information 187 * @txbuf: Transmit buffer 188 * @rxbuf: Receive buffer 189 */ 190 struct sca3300_data { 191 struct spi_device *spi; 192 struct mutex lock; 193 const struct sca3300_chip_info *chip; 194 u8 txbuf[4] __aligned(IIO_DMA_MINALIGN); 195 u8 rxbuf[4]; 196 }; 197 198 static const struct sca3300_chip_info sca3300_chip_tbl[] = { 199 { 200 .name = "sca3300", 201 .scan_masks = sca3300_scan_masks, 202 .channels = sca3300_channels, 203 .num_channels = ARRAY_SIZE(sca3300_channels), 204 .num_accel_scales = ARRAY_SIZE(sca3300_accel_scale)*2, 205 .accel_scale = sca3300_accel_scale, 206 .accel_scale_map = sca3300_accel_scale_map, 207 .num_freqs = ARRAY_SIZE(sca3300_lp_freq), 208 .freq_table = sca3300_lp_freq, 209 .freq_map = sca3300_lp_freq_map, 210 .avail_modes_table = sca3300_avail_modes_map, 211 .num_avail_modes = 4, 212 .chip_id = SCA3300_WHOAMI_ID, 213 .angle_supported = false, 214 }, 215 { 216 .name = "scl3300", 217 .scan_masks = scl3300_scan_masks, 218 .channels = scl3300_channels, 219 .num_channels = ARRAY_SIZE(scl3300_channels), 220 .num_accel_scales = ARRAY_SIZE(scl3300_accel_scale)*2, 221 .accel_scale = scl3300_accel_scale, 222 .accel_scale_map = scl3300_accel_scale_map, 223 .incli_scale = scl3300_incli_scale, 224 .incli_scale_map = scl3300_incli_scale_map, 225 .num_incli_scales = ARRAY_SIZE(scl3300_incli_scale)*2, 226 .num_freqs = ARRAY_SIZE(scl3300_lp_freq), 227 .freq_table = scl3300_lp_freq, 228 .freq_map = scl3300_lp_freq_map, 229 .avail_modes_table = scl3300_avail_modes_map, 230 .num_avail_modes = 3, 231 .chip_id = SCL3300_WHOAMI_ID, 232 .angle_supported = true, 233 }, 234 }; 235 236 DECLARE_CRC8_TABLE(sca3300_crc_table); 237 238 static int sca3300_transfer(struct sca3300_data *sca_data, int *val) 239 { 240 /* Consecutive requests min. 10 us delay (Datasheet section 5.1.2) */ 241 struct spi_delay delay = { .value = 10, .unit = SPI_DELAY_UNIT_USECS }; 242 int32_t ret; 243 int rs; 244 u8 crc; 245 struct spi_transfer xfers[2] = { 246 { 247 .tx_buf = sca_data->txbuf, 248 .len = ARRAY_SIZE(sca_data->txbuf), 249 .delay = delay, 250 .cs_change = 1, 251 }, 252 { 253 .rx_buf = sca_data->rxbuf, 254 .len = ARRAY_SIZE(sca_data->rxbuf), 255 .delay = delay, 256 } 257 }; 258 259 /* inverted crc value as described in device data sheet */ 260 crc = ~crc8(sca3300_crc_table, &sca_data->txbuf[0], 3, CRC8_INIT_VALUE); 261 sca_data->txbuf[3] = crc; 262 263 ret = spi_sync_transfer(sca_data->spi, xfers, ARRAY_SIZE(xfers)); 264 if (ret) { 265 dev_err(&sca_data->spi->dev, 266 "transfer error, error: %d\n", ret); 267 return -EIO; 268 } 269 270 crc = ~crc8(sca3300_crc_table, &sca_data->rxbuf[0], 3, CRC8_INIT_VALUE); 271 if (sca_data->rxbuf[3] != crc) { 272 dev_err(&sca_data->spi->dev, "CRC checksum mismatch"); 273 return -EIO; 274 } 275 276 /* get return status */ 277 rs = sca_data->rxbuf[0] & SCA3300_MASK_RS_STATUS; 278 if (rs == SCA3300_VALUE_RS_ERROR) 279 ret = -EINVAL; 280 281 *val = sign_extend32(get_unaligned_be16(&sca_data->rxbuf[1]), 15); 282 283 return ret; 284 } 285 286 static int sca3300_error_handler(struct sca3300_data *sca_data) 287 { 288 int ret; 289 int val; 290 291 mutex_lock(&sca_data->lock); 292 sca_data->txbuf[0] = SCA3300_REG_STATUS << 2; 293 ret = sca3300_transfer(sca_data, &val); 294 mutex_unlock(&sca_data->lock); 295 /* 296 * Return status error is cleared after reading status register once, 297 * expect EINVAL here. 298 */ 299 if (ret != -EINVAL) { 300 dev_err(&sca_data->spi->dev, 301 "error reading device status: %d\n", ret); 302 return ret; 303 } 304 305 dev_err(&sca_data->spi->dev, "device status: 0x%lx\n", 306 val & SCA3300_STATUS_MASK); 307 308 return 0; 309 } 310 311 static int sca3300_read_reg(struct sca3300_data *sca_data, u8 reg, int *val) 312 { 313 int ret; 314 315 mutex_lock(&sca_data->lock); 316 sca_data->txbuf[0] = reg << 2; 317 ret = sca3300_transfer(sca_data, val); 318 mutex_unlock(&sca_data->lock); 319 if (ret != -EINVAL) 320 return ret; 321 322 return sca3300_error_handler(sca_data); 323 } 324 325 static int sca3300_write_reg(struct sca3300_data *sca_data, u8 reg, int val) 326 { 327 int reg_val = 0; 328 int ret; 329 330 mutex_lock(&sca_data->lock); 331 /* BIT(7) for write operation */ 332 sca_data->txbuf[0] = BIT(7) | (reg << 2); 333 put_unaligned_be16(val, &sca_data->txbuf[1]); 334 ret = sca3300_transfer(sca_data, ®_val); 335 mutex_unlock(&sca_data->lock); 336 if (ret != -EINVAL) 337 return ret; 338 339 return sca3300_error_handler(sca_data); 340 } 341 342 static int sca3300_set_op_mode(struct sca3300_data *sca_data, int index) 343 { 344 if ((index < 0) || (index >= sca_data->chip->num_avail_modes)) 345 return -EINVAL; 346 347 return sca3300_write_reg(sca_data, SCA3300_REG_MODE, 348 sca_data->chip->avail_modes_table[index]); 349 } 350 351 static int sca3300_get_op_mode(struct sca3300_data *sca_data, int *index) 352 { 353 int reg_val; 354 int ret; 355 int i; 356 357 ret = sca3300_read_reg(sca_data, SCA3300_REG_MODE, ®_val); 358 if (ret) 359 return ret; 360 361 for (i = 0; i < sca_data->chip->num_avail_modes; i++) { 362 if (sca_data->chip->avail_modes_table[i] == reg_val) 363 break; 364 } 365 if (i == sca_data->chip->num_avail_modes) 366 return -EINVAL; 367 368 *index = i; 369 return 0; 370 } 371 372 static int sca3300_set_frequency(struct sca3300_data *data, int val) 373 { 374 const struct sca3300_chip_info *chip = data->chip; 375 unsigned int index; 376 int *opmode_scale; 377 int *new_scale; 378 unsigned int i; 379 380 if (sca3300_get_op_mode(data, &index)) 381 return -EINVAL; 382 383 /* 384 * Find a mode in which the requested sampling frequency is available 385 * and the scaling currently set is retained. 386 */ 387 opmode_scale = (int *)chip->accel_scale[chip->accel_scale_map[index]]; 388 for (i = 0; i < chip->num_avail_modes; i++) { 389 new_scale = (int *)chip->accel_scale[chip->accel_scale_map[i]]; 390 if ((val == chip->freq_table[chip->freq_map[i]]) && 391 (opmode_scale[1] == new_scale[1]) && 392 (opmode_scale[0] == new_scale[0])) 393 break; 394 } 395 if (i == chip->num_avail_modes) 396 return -EINVAL; 397 398 return sca3300_set_op_mode(data, i); 399 } 400 401 static int sca3300_write_raw(struct iio_dev *indio_dev, 402 struct iio_chan_spec const *chan, 403 int val, int val2, long mask) 404 { 405 struct sca3300_data *data = iio_priv(indio_dev); 406 int index; 407 int i; 408 409 switch (mask) { 410 case IIO_CHAN_INFO_SCALE: 411 if (chan->type != IIO_ACCEL) 412 return -EINVAL; 413 /* 414 * Letting scale take priority over sampling frequency. 415 * That makes sense given we can only ever end up increasing 416 * the sampling frequency which is unlikely to be a problem. 417 */ 418 for (i = 0; i < data->chip->num_avail_modes; i++) { 419 index = data->chip->accel_scale_map[i]; 420 if ((val == data->chip->accel_scale[index][0]) && 421 (val2 == data->chip->accel_scale[index][1])) 422 return sca3300_set_op_mode(data, i); 423 } 424 return -EINVAL; 425 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 426 return sca3300_set_frequency(data, val); 427 default: 428 return -EINVAL; 429 } 430 } 431 432 static int sca3300_read_raw(struct iio_dev *indio_dev, 433 struct iio_chan_spec const *chan, 434 int *val, int *val2, long mask) 435 { 436 struct sca3300_data *data = iio_priv(indio_dev); 437 int index; 438 int ret; 439 440 switch (mask) { 441 case IIO_CHAN_INFO_RAW: 442 ret = sca3300_read_reg(data, chan->address, val); 443 if (ret) 444 return ret; 445 return IIO_VAL_INT; 446 case IIO_CHAN_INFO_SCALE: 447 ret = sca3300_get_op_mode(data, &index); 448 if (ret) 449 return ret; 450 switch (chan->type) { 451 case IIO_INCLI: 452 index = data->chip->incli_scale_map[index]; 453 *val = data->chip->incli_scale[index][0]; 454 *val2 = data->chip->incli_scale[index][1]; 455 return IIO_VAL_INT_PLUS_MICRO; 456 case IIO_ACCEL: 457 index = data->chip->accel_scale_map[index]; 458 *val = data->chip->accel_scale[index][0]; 459 *val2 = data->chip->accel_scale[index][1]; 460 return IIO_VAL_INT_PLUS_MICRO; 461 default: 462 return -EINVAL; 463 } 464 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 465 ret = sca3300_get_op_mode(data, &index); 466 if (ret) 467 return ret; 468 index = data->chip->freq_map[index]; 469 *val = data->chip->freq_table[index]; 470 return IIO_VAL_INT; 471 default: 472 return -EINVAL; 473 } 474 } 475 476 static irqreturn_t sca3300_trigger_handler(int irq, void *p) 477 { 478 struct iio_poll_func *pf = p; 479 struct iio_dev *indio_dev = pf->indio_dev; 480 struct sca3300_data *data = iio_priv(indio_dev); 481 int bit, ret, val, i = 0; 482 IIO_DECLARE_BUFFER_WITH_TS(s16, channels, SCA3300_SCAN_MAX); 483 484 iio_for_each_active_channel(indio_dev, bit) { 485 ret = sca3300_read_reg(data, indio_dev->channels[bit].address, &val); 486 if (ret) { 487 dev_err_ratelimited(&data->spi->dev, 488 "failed to read register, error: %d\n", ret); 489 /* handled, but bailing out due to errors */ 490 goto out; 491 } 492 channels[i++] = val; 493 } 494 495 iio_push_to_buffers_with_ts(indio_dev, channels, sizeof(channels), 496 iio_get_time_ns(indio_dev)); 497 out: 498 iio_trigger_notify_done(indio_dev->trig); 499 500 return IRQ_HANDLED; 501 } 502 503 /* 504 * sca3300_init - Device init sequence. See datasheet rev 2 section 505 * 4.2 Start-Up Sequence for details. 506 */ 507 static int sca3300_init(struct sca3300_data *sca_data, 508 struct iio_dev *indio_dev) 509 { 510 int value = 0; 511 int ret; 512 int i; 513 514 ret = sca3300_write_reg(sca_data, SCA3300_REG_MODE, 515 SCA3300_MODE_SW_RESET); 516 if (ret) 517 return ret; 518 519 /* 520 * Wait 1ms after SW-reset command. 521 * Wait for the settling of signal paths, 522 * 15ms for SCA3300 and 25ms for SCL3300, 523 */ 524 usleep_range(26e3, 50e3); 525 526 ret = sca3300_read_reg(sca_data, SCA3300_REG_WHOAMI, &value); 527 if (ret) 528 return ret; 529 530 for (i = 0; i < ARRAY_SIZE(sca3300_chip_tbl); i++) { 531 if (sca3300_chip_tbl[i].chip_id == value) 532 break; 533 } 534 if (i == ARRAY_SIZE(sca3300_chip_tbl)) { 535 dev_err(&sca_data->spi->dev, "unknown chip id %x\n", value); 536 return -ENODEV; 537 } 538 539 sca_data->chip = &sca3300_chip_tbl[i]; 540 541 if (sca_data->chip->angle_supported) { 542 ret = sca3300_write_reg(sca_data, SCL3300_REG_ANG_CTRL, 543 SCL3300_ANG_ENABLE); 544 if (ret) 545 return ret; 546 } 547 548 return 0; 549 } 550 551 static int sca3300_debugfs_reg_access(struct iio_dev *indio_dev, 552 unsigned int reg, unsigned int writeval, 553 unsigned int *readval) 554 { 555 struct sca3300_data *data = iio_priv(indio_dev); 556 int value; 557 int ret; 558 559 if (reg > SCA3300_REG_SELBANK) 560 return -EINVAL; 561 562 if (!readval) 563 return sca3300_write_reg(data, reg, writeval); 564 565 ret = sca3300_read_reg(data, reg, &value); 566 if (ret) 567 return ret; 568 569 *readval = value; 570 571 return 0; 572 } 573 574 static int sca3300_read_avail(struct iio_dev *indio_dev, 575 struct iio_chan_spec const *chan, 576 const int **vals, int *type, int *length, 577 long mask) 578 { 579 struct sca3300_data *data = iio_priv(indio_dev); 580 switch (mask) { 581 case IIO_CHAN_INFO_SCALE: 582 switch (chan->type) { 583 case IIO_INCLI: 584 *vals = (const int *)data->chip->incli_scale; 585 *length = data->chip->num_incli_scales; 586 *type = IIO_VAL_INT_PLUS_MICRO; 587 return IIO_AVAIL_LIST; 588 case IIO_ACCEL: 589 *vals = (const int *)data->chip->accel_scale; 590 *length = data->chip->num_accel_scales; 591 *type = IIO_VAL_INT_PLUS_MICRO; 592 return IIO_AVAIL_LIST; 593 default: 594 return -EINVAL; 595 } 596 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 597 *vals = (const int *)data->chip->freq_table; 598 *length = data->chip->num_freqs; 599 *type = IIO_VAL_INT; 600 return IIO_AVAIL_LIST; 601 default: 602 return -EINVAL; 603 } 604 } 605 606 static const struct iio_info sca3300_info = { 607 .read_raw = sca3300_read_raw, 608 .write_raw = sca3300_write_raw, 609 .debugfs_reg_access = &sca3300_debugfs_reg_access, 610 .read_avail = sca3300_read_avail, 611 }; 612 613 static int sca3300_probe(struct spi_device *spi) 614 { 615 struct sca3300_data *sca_data; 616 struct iio_dev *indio_dev; 617 int ret; 618 619 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*sca_data)); 620 if (!indio_dev) 621 return -ENOMEM; 622 623 sca_data = iio_priv(indio_dev); 624 mutex_init(&sca_data->lock); 625 sca_data->spi = spi; 626 627 crc8_populate_msb(sca3300_crc_table, SCA3300_CRC8_POLYNOMIAL); 628 629 indio_dev->info = &sca3300_info; 630 631 ret = sca3300_init(sca_data, indio_dev); 632 if (ret) { 633 dev_err(&spi->dev, "failed to init device, error: %d\n", ret); 634 return ret; 635 } 636 637 indio_dev->name = sca_data->chip->name; 638 indio_dev->modes = INDIO_DIRECT_MODE; 639 indio_dev->channels = sca_data->chip->channels; 640 indio_dev->num_channels = sca_data->chip->num_channels; 641 indio_dev->available_scan_masks = sca_data->chip->scan_masks; 642 643 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, 644 iio_pollfunc_store_time, 645 sca3300_trigger_handler, NULL); 646 if (ret) { 647 dev_err(&spi->dev, 648 "iio triggered buffer setup failed, error: %d\n", ret); 649 return ret; 650 } 651 652 ret = devm_iio_device_register(&spi->dev, indio_dev); 653 if (ret) { 654 dev_err(&spi->dev, "iio device register failed, error: %d\n", 655 ret); 656 } 657 658 return ret; 659 } 660 661 static const struct of_device_id sca3300_dt_ids[] = { 662 { .compatible = "murata,sca3300"}, 663 { .compatible = "murata,scl3300"}, 664 { } 665 }; 666 MODULE_DEVICE_TABLE(of, sca3300_dt_ids); 667 668 static const struct spi_device_id sca3300_ids[] = { 669 { "sca3300" }, 670 { "scl3300" }, 671 { } 672 }; 673 MODULE_DEVICE_TABLE(spi, sca3300_ids); 674 675 static struct spi_driver sca3300_driver = { 676 .driver = { 677 .name = SCA3300_ALIAS, 678 .of_match_table = sca3300_dt_ids, 679 }, 680 .probe = sca3300_probe, 681 .id_table = sca3300_ids, 682 }; 683 module_spi_driver(sca3300_driver); 684 685 MODULE_AUTHOR("Tomas Melin <tomas.melin@vaisala.com>"); 686 MODULE_DESCRIPTION("Murata SCA3300 SPI Accelerometer"); 687 MODULE_LICENSE("GPL v2"); 688