1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MEMSensing digital 3-Axis accelerometer 4 * 5 * MSA311 is a tri-axial, low-g accelerometer with I2C digital output for 6 * sensitivity consumer applications. It has dynamic user-selectable full 7 * scales range of +-2g/+-4g/+-8g/+-16g and allows acceleration measurements 8 * with output data rates from 1Hz to 1000Hz. 9 * 10 * MSA311 is available in an ultra small (2mm x 2mm, height 0.95mm) LGA package 11 * and is guaranteed to operate over -40C to +85C. 12 * 13 * This driver supports following MSA311 features: 14 * - IIO interface 15 * - Different power modes: NORMAL, SUSPEND 16 * - ODR (Output Data Rate) selection 17 * - Scale selection 18 * - IIO triggered buffer 19 * - NEW_DATA interrupt + trigger 20 * 21 * Below features to be done: 22 * - Motion Events: ACTIVE, TAP, ORIENT, FREEFALL 23 * - Low Power mode 24 * 25 * Copyright (c) 2022, SberDevices. All Rights Reserved. 26 * 27 * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru> 28 */ 29 30 #include <linux/i2c.h> 31 #include <linux/mod_devicetable.h> 32 #include <linux/module.h> 33 #include <linux/pm.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/regmap.h> 36 #include <linux/string_choices.h> 37 #include <linux/types.h> 38 #include <linux/units.h> 39 40 #include <linux/iio/buffer.h> 41 #include <linux/iio/iio.h> 42 #include <linux/iio/sysfs.h> 43 #include <linux/iio/trigger.h> 44 #include <linux/iio/trigger_consumer.h> 45 #include <linux/iio/triggered_buffer.h> 46 47 #define MSA311_SOFT_RESET_REG 0x00 48 #define MSA311_PARTID_REG 0x01 49 #define MSA311_ACC_X_REG 0x02 50 #define MSA311_ACC_Y_REG 0x04 51 #define MSA311_ACC_Z_REG 0x06 52 #define MSA311_MOTION_INT_REG 0x09 53 #define MSA311_DATA_INT_REG 0x0A 54 #define MSA311_TAP_ACTIVE_STS_REG 0x0B 55 #define MSA311_ORIENT_STS_REG 0x0C 56 #define MSA311_RANGE_REG 0x0F 57 #define MSA311_ODR_REG 0x10 58 #define MSA311_PWR_MODE_REG 0x11 59 #define MSA311_SWAP_POLARITY_REG 0x12 60 #define MSA311_INT_SET_0_REG 0x16 61 #define MSA311_INT_SET_1_REG 0x17 62 #define MSA311_INT_MAP_0_REG 0x19 63 #define MSA311_INT_MAP_1_REG 0x1A 64 #define MSA311_INT_CONFIG_REG 0x20 65 #define MSA311_INT_LATCH_REG 0x21 66 #define MSA311_FREEFALL_DUR_REG 0x22 67 #define MSA311_FREEFALL_TH_REG 0x23 68 #define MSA311_FREEFALL_HY_REG 0x24 69 #define MSA311_ACTIVE_DUR_REG 0x27 70 #define MSA311_ACTIVE_TH_REG 0x28 71 #define MSA311_TAP_DUR_REG 0x2A 72 #define MSA311_TAP_TH_REG 0x2B 73 #define MSA311_ORIENT_HY_REG 0x2C 74 #define MSA311_Z_BLOCK_REG 0x2D 75 #define MSA311_OFFSET_X_REG 0x38 76 #define MSA311_OFFSET_Y_REG 0x39 77 #define MSA311_OFFSET_Z_REG 0x3A 78 79 enum msa311_fields { 80 /* Soft_Reset */ 81 F_SOFT_RESET_I2C, F_SOFT_RESET_SPI, 82 /* Motion_Interrupt */ 83 F_ORIENT_INT, F_S_TAP_INT, F_D_TAP_INT, F_ACTIVE_INT, F_FREEFALL_INT, 84 /* Data_Interrupt */ 85 F_NEW_DATA_INT, 86 /* Tap_Active_Status */ 87 F_TAP_SIGN, F_TAP_FIRST_X, F_TAP_FIRST_Y, F_TAP_FIRST_Z, F_ACTV_SIGN, 88 F_ACTV_FIRST_X, F_ACTV_FIRST_Y, F_ACTV_FIRST_Z, 89 /* Orientation_Status */ 90 F_ORIENT_Z, F_ORIENT_X_Y, 91 /* Range */ 92 F_FS, 93 /* ODR */ 94 F_X_AXIS_DIS, F_Y_AXIS_DIS, F_Z_AXIS_DIS, F_ODR, 95 /* Power Mode/Bandwidth */ 96 F_PWR_MODE, F_LOW_POWER_BW, 97 /* Swap_Polarity */ 98 F_X_POLARITY, F_Y_POLARITY, F_Z_POLARITY, F_X_Y_SWAP, 99 /* Int_Set_0 */ 100 F_ORIENT_INT_EN, F_S_TAP_INT_EN, F_D_TAP_INT_EN, F_ACTIVE_INT_EN_Z, 101 F_ACTIVE_INT_EN_Y, F_ACTIVE_INT_EN_X, 102 /* Int_Set_1 */ 103 F_NEW_DATA_INT_EN, F_FREEFALL_INT_EN, 104 /* Int_Map_0 */ 105 F_INT1_ORIENT, F_INT1_S_TAP, F_INT1_D_TAP, F_INT1_ACTIVE, 106 F_INT1_FREEFALL, 107 /* Int_Map_1 */ 108 F_INT1_NEW_DATA, 109 /* Int_Config */ 110 F_INT1_OD, F_INT1_LVL, 111 /* Int_Latch */ 112 F_RESET_INT, F_LATCH_INT, 113 /* Freefall_Hy */ 114 F_FREEFALL_MODE, F_FREEFALL_HY, 115 /* Active_Dur */ 116 F_ACTIVE_DUR, 117 /* Tap_Dur */ 118 F_TAP_QUIET, F_TAP_SHOCK, F_TAP_DUR, 119 /* Tap_Th */ 120 F_TAP_TH, 121 /* Orient_Hy */ 122 F_ORIENT_HYST, F_ORIENT_BLOCKING, F_ORIENT_MODE, 123 /* Z_Block */ 124 F_Z_BLOCKING, 125 /* End of register map */ 126 F_MAX_FIELDS, 127 }; 128 129 static const struct reg_field msa311_reg_fields[] = { 130 /* Soft_Reset */ 131 [F_SOFT_RESET_I2C] = REG_FIELD(MSA311_SOFT_RESET_REG, 2, 2), 132 [F_SOFT_RESET_SPI] = REG_FIELD(MSA311_SOFT_RESET_REG, 5, 5), 133 /* Motion_Interrupt */ 134 [F_ORIENT_INT] = REG_FIELD(MSA311_MOTION_INT_REG, 6, 6), 135 [F_S_TAP_INT] = REG_FIELD(MSA311_MOTION_INT_REG, 5, 5), 136 [F_D_TAP_INT] = REG_FIELD(MSA311_MOTION_INT_REG, 4, 4), 137 [F_ACTIVE_INT] = REG_FIELD(MSA311_MOTION_INT_REG, 2, 2), 138 [F_FREEFALL_INT] = REG_FIELD(MSA311_MOTION_INT_REG, 0, 0), 139 /* Data_Interrupt */ 140 [F_NEW_DATA_INT] = REG_FIELD(MSA311_DATA_INT_REG, 0, 0), 141 /* Tap_Active_Status */ 142 [F_TAP_SIGN] = REG_FIELD(MSA311_TAP_ACTIVE_STS_REG, 7, 7), 143 [F_TAP_FIRST_X] = REG_FIELD(MSA311_TAP_ACTIVE_STS_REG, 6, 6), 144 [F_TAP_FIRST_Y] = REG_FIELD(MSA311_TAP_ACTIVE_STS_REG, 5, 5), 145 [F_TAP_FIRST_Z] = REG_FIELD(MSA311_TAP_ACTIVE_STS_REG, 4, 4), 146 [F_ACTV_SIGN] = REG_FIELD(MSA311_TAP_ACTIVE_STS_REG, 3, 3), 147 [F_ACTV_FIRST_X] = REG_FIELD(MSA311_TAP_ACTIVE_STS_REG, 2, 2), 148 [F_ACTV_FIRST_Y] = REG_FIELD(MSA311_TAP_ACTIVE_STS_REG, 1, 1), 149 [F_ACTV_FIRST_Z] = REG_FIELD(MSA311_TAP_ACTIVE_STS_REG, 0, 0), 150 /* Orientation_Status */ 151 [F_ORIENT_Z] = REG_FIELD(MSA311_ORIENT_STS_REG, 6, 6), 152 [F_ORIENT_X_Y] = REG_FIELD(MSA311_ORIENT_STS_REG, 4, 5), 153 /* Range */ 154 [F_FS] = REG_FIELD(MSA311_RANGE_REG, 0, 1), 155 /* ODR */ 156 [F_X_AXIS_DIS] = REG_FIELD(MSA311_ODR_REG, 7, 7), 157 [F_Y_AXIS_DIS] = REG_FIELD(MSA311_ODR_REG, 6, 6), 158 [F_Z_AXIS_DIS] = REG_FIELD(MSA311_ODR_REG, 5, 5), 159 [F_ODR] = REG_FIELD(MSA311_ODR_REG, 0, 3), 160 /* Power Mode/Bandwidth */ 161 [F_PWR_MODE] = REG_FIELD(MSA311_PWR_MODE_REG, 6, 7), 162 [F_LOW_POWER_BW] = REG_FIELD(MSA311_PWR_MODE_REG, 1, 4), 163 /* Swap_Polarity */ 164 [F_X_POLARITY] = REG_FIELD(MSA311_SWAP_POLARITY_REG, 3, 3), 165 [F_Y_POLARITY] = REG_FIELD(MSA311_SWAP_POLARITY_REG, 2, 2), 166 [F_Z_POLARITY] = REG_FIELD(MSA311_SWAP_POLARITY_REG, 1, 1), 167 [F_X_Y_SWAP] = REG_FIELD(MSA311_SWAP_POLARITY_REG, 0, 0), 168 /* Int_Set_0 */ 169 [F_ORIENT_INT_EN] = REG_FIELD(MSA311_INT_SET_0_REG, 6, 6), 170 [F_S_TAP_INT_EN] = REG_FIELD(MSA311_INT_SET_0_REG, 5, 5), 171 [F_D_TAP_INT_EN] = REG_FIELD(MSA311_INT_SET_0_REG, 4, 4), 172 [F_ACTIVE_INT_EN_Z] = REG_FIELD(MSA311_INT_SET_0_REG, 2, 2), 173 [F_ACTIVE_INT_EN_Y] = REG_FIELD(MSA311_INT_SET_0_REG, 1, 1), 174 [F_ACTIVE_INT_EN_X] = REG_FIELD(MSA311_INT_SET_0_REG, 0, 0), 175 /* Int_Set_1 */ 176 [F_NEW_DATA_INT_EN] = REG_FIELD(MSA311_INT_SET_1_REG, 4, 4), 177 [F_FREEFALL_INT_EN] = REG_FIELD(MSA311_INT_SET_1_REG, 3, 3), 178 /* Int_Map_0 */ 179 [F_INT1_ORIENT] = REG_FIELD(MSA311_INT_MAP_0_REG, 6, 6), 180 [F_INT1_S_TAP] = REG_FIELD(MSA311_INT_MAP_0_REG, 5, 5), 181 [F_INT1_D_TAP] = REG_FIELD(MSA311_INT_MAP_0_REG, 4, 4), 182 [F_INT1_ACTIVE] = REG_FIELD(MSA311_INT_MAP_0_REG, 2, 2), 183 [F_INT1_FREEFALL] = REG_FIELD(MSA311_INT_MAP_0_REG, 0, 0), 184 /* Int_Map_1 */ 185 [F_INT1_NEW_DATA] = REG_FIELD(MSA311_INT_MAP_1_REG, 0, 0), 186 /* Int_Config */ 187 [F_INT1_OD] = REG_FIELD(MSA311_INT_CONFIG_REG, 1, 1), 188 [F_INT1_LVL] = REG_FIELD(MSA311_INT_CONFIG_REG, 0, 0), 189 /* Int_Latch */ 190 [F_RESET_INT] = REG_FIELD(MSA311_INT_LATCH_REG, 7, 7), 191 [F_LATCH_INT] = REG_FIELD(MSA311_INT_LATCH_REG, 0, 3), 192 /* Freefall_Hy */ 193 [F_FREEFALL_MODE] = REG_FIELD(MSA311_FREEFALL_HY_REG, 2, 2), 194 [F_FREEFALL_HY] = REG_FIELD(MSA311_FREEFALL_HY_REG, 0, 1), 195 /* Active_Dur */ 196 [F_ACTIVE_DUR] = REG_FIELD(MSA311_ACTIVE_DUR_REG, 0, 1), 197 /* Tap_Dur */ 198 [F_TAP_QUIET] = REG_FIELD(MSA311_TAP_DUR_REG, 7, 7), 199 [F_TAP_SHOCK] = REG_FIELD(MSA311_TAP_DUR_REG, 6, 6), 200 [F_TAP_DUR] = REG_FIELD(MSA311_TAP_DUR_REG, 0, 2), 201 /* Tap_Th */ 202 [F_TAP_TH] = REG_FIELD(MSA311_TAP_TH_REG, 0, 4), 203 /* Orient_Hy */ 204 [F_ORIENT_HYST] = REG_FIELD(MSA311_ORIENT_HY_REG, 4, 6), 205 [F_ORIENT_BLOCKING] = REG_FIELD(MSA311_ORIENT_HY_REG, 2, 3), 206 [F_ORIENT_MODE] = REG_FIELD(MSA311_ORIENT_HY_REG, 0, 1), 207 /* Z_Block */ 208 [F_Z_BLOCKING] = REG_FIELD(MSA311_Z_BLOCK_REG, 0, 3), 209 }; 210 211 #define MSA311_WHO_AM_I 0x13 212 213 /* 214 * Possible Full Scale ranges 215 * 216 * Axis data is 12-bit signed value, so 217 * 218 * fs0 = (2 + 2) * 9.81 / (2^11) = 0.009580 219 * fs1 = (4 + 4) * 9.81 / (2^11) = 0.019160 220 * fs2 = (8 + 8) * 9.81 / (2^11) = 0.038320 221 * fs3 = (16 + 16) * 9.81 / (2^11) = 0.076641 222 */ 223 enum { 224 MSA311_FS_2G, 225 MSA311_FS_4G, 226 MSA311_FS_8G, 227 MSA311_FS_16G, 228 }; 229 230 struct iio_decimal_fract { 231 int integral; 232 int microfract; 233 }; 234 235 static const struct iio_decimal_fract msa311_fs_table[] = { 236 {0, 9580}, {0, 19160}, {0, 38320}, {0, 76641}, 237 }; 238 239 /* Possible Output Data Rate values */ 240 enum { 241 MSA311_ODR_1_HZ, 242 MSA311_ODR_1_95_HZ, 243 MSA311_ODR_3_9_HZ, 244 MSA311_ODR_7_81_HZ, 245 MSA311_ODR_15_63_HZ, 246 MSA311_ODR_31_25_HZ, 247 MSA311_ODR_62_5_HZ, 248 MSA311_ODR_125_HZ, 249 MSA311_ODR_250_HZ, 250 MSA311_ODR_500_HZ, 251 MSA311_ODR_1000_HZ, 252 }; 253 254 static const struct iio_decimal_fract msa311_odr_table[] = { 255 {1, 0}, {1, 950000}, {3, 900000}, {7, 810000}, {15, 630000}, 256 {31, 250000}, {62, 500000}, {125, 0}, {250, 0}, {500, 0}, {1000, 0}, 257 }; 258 259 /* All supported power modes */ 260 #define MSA311_PWR_MODE_NORMAL 0b00 261 #define MSA311_PWR_MODE_LOW 0b01 262 #define MSA311_PWR_MODE_UNKNOWN 0b10 263 #define MSA311_PWR_MODE_SUSPEND 0b11 264 static const char * const msa311_pwr_modes[] = { 265 [MSA311_PWR_MODE_NORMAL] = "normal", 266 [MSA311_PWR_MODE_LOW] = "low", 267 [MSA311_PWR_MODE_UNKNOWN] = "unknown", 268 [MSA311_PWR_MODE_SUSPEND] = "suspend", 269 }; 270 271 /* Autosuspend delay */ 272 #define MSA311_PWR_SLEEP_DELAY_MS 2000 273 274 /* Possible INT1 types and levels */ 275 enum { 276 MSA311_INT1_OD_PUSH_PULL, 277 MSA311_INT1_OD_OPEN_DRAIN, 278 }; 279 280 enum { 281 MSA311_INT1_LVL_LOW, 282 MSA311_INT1_LVL_HIGH, 283 }; 284 285 /* Latch INT modes */ 286 #define MSA311_LATCH_INT_NOT_LATCHED 0b0000 287 #define MSA311_LATCH_INT_250MS 0b0001 288 #define MSA311_LATCH_INT_500MS 0b0010 289 #define MSA311_LATCH_INT_1S 0b0011 290 #define MSA311_LATCH_INT_2S 0b0100 291 #define MSA311_LATCH_INT_4S 0b0101 292 #define MSA311_LATCH_INT_8S 0b0110 293 #define MSA311_LATCH_INT_1MS 0b1010 294 #define MSA311_LATCH_INT_2MS 0b1011 295 #define MSA311_LATCH_INT_25MS 0b1100 296 #define MSA311_LATCH_INT_50MS 0b1101 297 #define MSA311_LATCH_INT_100MS 0b1110 298 #define MSA311_LATCH_INT_LATCHED 0b0111 299 300 static const struct regmap_range msa311_readonly_registers[] = { 301 regmap_reg_range(MSA311_PARTID_REG, MSA311_ORIENT_STS_REG), 302 }; 303 304 static const struct regmap_access_table msa311_writeable_table = { 305 .no_ranges = msa311_readonly_registers, 306 .n_no_ranges = ARRAY_SIZE(msa311_readonly_registers), 307 }; 308 309 static const struct regmap_range msa311_writeonly_registers[] = { 310 regmap_reg_range(MSA311_SOFT_RESET_REG, MSA311_SOFT_RESET_REG), 311 }; 312 313 static const struct regmap_access_table msa311_readable_table = { 314 .no_ranges = msa311_writeonly_registers, 315 .n_no_ranges = ARRAY_SIZE(msa311_writeonly_registers), 316 }; 317 318 static const struct regmap_range msa311_volatile_registers[] = { 319 regmap_reg_range(MSA311_ACC_X_REG, MSA311_ORIENT_STS_REG), 320 }; 321 322 static const struct regmap_access_table msa311_volatile_table = { 323 .yes_ranges = msa311_volatile_registers, 324 .n_yes_ranges = ARRAY_SIZE(msa311_volatile_registers), 325 }; 326 327 static const struct regmap_config msa311_regmap_config = { 328 .name = "msa311", 329 .reg_bits = 8, 330 .val_bits = 8, 331 .max_register = MSA311_OFFSET_Z_REG, 332 .wr_table = &msa311_writeable_table, 333 .rd_table = &msa311_readable_table, 334 .volatile_table = &msa311_volatile_table, 335 .cache_type = REGCACHE_MAPLE, 336 }; 337 338 #define MSA311_GENMASK(field) ({ \ 339 typeof(&(msa311_reg_fields)[0]) _field; \ 340 _field = &msa311_reg_fields[(field)]; \ 341 GENMASK(_field->msb, _field->lsb); \ 342 }) 343 344 /** 345 * struct msa311_priv - MSA311 internal private state 346 * @regs: Underlying I2C bus adapter used to abstract slave 347 * register accesses 348 * @fields: Abstract objects for each registers fields access 349 * @dev: Device handler associated with appropriate bus client 350 * @lock: Protects msa311 device state between setup and data access routines 351 * (power transitions, samp_freq/scale tune, retrieving axes data, etc) 352 * @chip_name: Chip name in the format "msa311-%02x" % partid 353 * @new_data_trig: Optional NEW_DATA interrupt driven trigger used 354 * to notify external consumers a new sample is ready 355 */ 356 struct msa311_priv { 357 struct regmap *regs; 358 struct regmap_field *fields[F_MAX_FIELDS]; 359 360 struct device *dev; 361 struct mutex lock; 362 char *chip_name; 363 364 struct iio_trigger *new_data_trig; 365 }; 366 367 enum msa311_si { 368 MSA311_SI_X, 369 MSA311_SI_Y, 370 MSA311_SI_Z, 371 MSA311_SI_TIMESTAMP, 372 }; 373 374 #define MSA311_ACCEL_CHANNEL(axis) { \ 375 .type = IIO_ACCEL, \ 376 .modified = 1, \ 377 .channel2 = IIO_MOD_##axis, \ 378 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 379 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 380 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 381 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE) | \ 382 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 383 .scan_index = MSA311_SI_##axis, \ 384 .scan_type = { \ 385 .sign = 's', \ 386 .realbits = 12, \ 387 .storagebits = 16, \ 388 .shift = 4, \ 389 .endianness = IIO_LE, \ 390 }, \ 391 .datasheet_name = "ACC_"#axis, \ 392 } 393 394 static const struct iio_chan_spec msa311_channels[] = { 395 MSA311_ACCEL_CHANNEL(X), 396 MSA311_ACCEL_CHANNEL(Y), 397 MSA311_ACCEL_CHANNEL(Z), 398 IIO_CHAN_SOFT_TIMESTAMP(MSA311_SI_TIMESTAMP), 399 }; 400 401 /** 402 * msa311_get_odr() - Read Output Data Rate (ODR) value from MSA311 accel 403 * @msa311: MSA311 internal private state 404 * @odr: output ODR value 405 * 406 * This function should be called under msa311->lock. 407 * 408 * Return: 0 on success, -ERRNO in other failures 409 */ 410 static int msa311_get_odr(struct msa311_priv *msa311, unsigned int *odr) 411 { 412 int err; 413 414 err = regmap_field_read(msa311->fields[F_ODR], odr); 415 if (err) 416 return err; 417 418 /* 419 * Filter the same 1000Hz ODR register values based on datasheet info. 420 * ODR can be equal to 1010-1111 for 1000Hz, but function returns 1010 421 * all the time. 422 */ 423 if (*odr > MSA311_ODR_1000_HZ) 424 *odr = MSA311_ODR_1000_HZ; 425 426 return 0; 427 } 428 429 /** 430 * msa311_set_odr() - Setup Output Data Rate (ODR) value for MSA311 accel 431 * @msa311: MSA311 internal private state 432 * @odr: requested ODR value 433 * 434 * This function should be called under msa311->lock. Possible ODR values: 435 * - 1Hz (not available in normal mode) 436 * - 1.95Hz (not available in normal mode) 437 * - 3.9Hz 438 * - 7.81Hz 439 * - 15.63Hz 440 * - 31.25Hz 441 * - 62.5Hz 442 * - 125Hz 443 * - 250Hz 444 * - 500Hz 445 * - 1000Hz 446 * 447 * Return: 0 on success, -EINVAL for bad ODR value in the certain power mode, 448 * -ERRNO in other failures 449 */ 450 static int msa311_set_odr(struct msa311_priv *msa311, unsigned int odr) 451 { 452 struct device *dev = msa311->dev; 453 unsigned int pwr_mode; 454 bool good_odr; 455 int err; 456 457 err = regmap_field_read(msa311->fields[F_PWR_MODE], &pwr_mode); 458 if (err) 459 return err; 460 461 /* Filter bad ODR values */ 462 if (pwr_mode == MSA311_PWR_MODE_NORMAL) 463 good_odr = (odr > MSA311_ODR_1_95_HZ); 464 else 465 good_odr = false; 466 467 if (!good_odr) { 468 dev_err(dev, 469 "can't set odr %u.%06uHz, not available in %s mode\n", 470 msa311_odr_table[odr].integral, 471 msa311_odr_table[odr].microfract, 472 msa311_pwr_modes[pwr_mode]); 473 return -EINVAL; 474 } 475 476 return regmap_field_write(msa311->fields[F_ODR], odr); 477 } 478 479 /** 480 * msa311_wait_for_next_data() - Wait next accel data available after resume 481 * @msa311: MSA311 internal private state 482 * 483 * Return: 0 on success, -EINTR if msleep() was interrupted, 484 * -ERRNO in other failures 485 */ 486 static int msa311_wait_for_next_data(struct msa311_priv *msa311) 487 { 488 static const unsigned int unintr_thresh_ms = 20; 489 struct device *dev = msa311->dev; 490 unsigned long freq_uhz; 491 unsigned long wait_ms; 492 unsigned int odr; 493 int err; 494 495 err = msa311_get_odr(msa311, &odr); 496 if (err) { 497 dev_err(dev, "can't get actual frequency (%pe)\n", 498 ERR_PTR(err)); 499 return err; 500 } 501 502 /* 503 * After msa311 resuming is done, we need to wait for data 504 * to be refreshed by accel logic. 505 * A certain timeout is calculated based on the current ODR value. 506 * If requested timeout isn't so long (let's assume 20ms), 507 * we can wait for next data in uninterruptible sleep. 508 */ 509 freq_uhz = msa311_odr_table[odr].integral * MICROHZ_PER_HZ + 510 msa311_odr_table[odr].microfract; 511 wait_ms = (MICROHZ_PER_HZ / freq_uhz) * MSEC_PER_SEC; 512 513 if (wait_ms < unintr_thresh_ms) 514 usleep_range(wait_ms * USEC_PER_MSEC, 515 unintr_thresh_ms * USEC_PER_MSEC); 516 else if (msleep_interruptible(wait_ms)) 517 return -EINTR; 518 519 return 0; 520 } 521 522 /** 523 * msa311_set_pwr_mode() - Install certain MSA311 power mode 524 * @msa311: MSA311 internal private state 525 * @mode: Power mode can be equal to NORMAL or SUSPEND 526 * 527 * This function should be called under msa311->lock. 528 * 529 * Return: 0 on success, -ERRNO on failure 530 */ 531 static int msa311_set_pwr_mode(struct msa311_priv *msa311, unsigned int mode) 532 { 533 struct device *dev = msa311->dev; 534 unsigned int prev_mode; 535 int err; 536 537 if (mode >= ARRAY_SIZE(msa311_pwr_modes)) 538 return -EINVAL; 539 540 dev_dbg(dev, "transition to %s mode\n", msa311_pwr_modes[mode]); 541 542 err = regmap_field_read(msa311->fields[F_PWR_MODE], &prev_mode); 543 if (err) 544 return err; 545 546 err = regmap_field_write(msa311->fields[F_PWR_MODE], mode); 547 if (err) 548 return err; 549 550 /* Wait actual data if we wake up */ 551 if (prev_mode == MSA311_PWR_MODE_SUSPEND && 552 mode == MSA311_PWR_MODE_NORMAL) 553 return msa311_wait_for_next_data(msa311); 554 555 return 0; 556 } 557 558 /** 559 * msa311_get_axis() - Read MSA311 accel data for certain IIO channel axis spec 560 * @msa311: MSA311 internal private state 561 * @chan: IIO channel specification 562 * @axis: Output accel axis data for requested IIO channel spec 563 * 564 * This function should be called under msa311->lock. 565 * 566 * Return: 0 on success, -EINVAL for unknown IIO channel specification, 567 * -ERRNO in other failures 568 */ 569 static int msa311_get_axis(struct msa311_priv *msa311, 570 const struct iio_chan_spec * const chan, 571 __le16 *axis) 572 { 573 struct device *dev = msa311->dev; 574 unsigned int axis_reg; 575 576 if (chan->scan_index < MSA311_SI_X || chan->scan_index > MSA311_SI_Z) { 577 dev_err(dev, "invalid scan_index value [%d]\n", 578 chan->scan_index); 579 return -EINVAL; 580 } 581 582 /* Axes data layout has 2 byte gap for each axis starting from X axis */ 583 axis_reg = MSA311_ACC_X_REG + (chan->scan_index << 1); 584 585 return regmap_bulk_read(msa311->regs, axis_reg, axis, sizeof(*axis)); 586 } 587 588 static int msa311_read_raw_data(struct iio_dev *indio_dev, 589 struct iio_chan_spec const *chan, 590 int *val, int *val2) 591 { 592 struct msa311_priv *msa311 = iio_priv(indio_dev); 593 struct device *dev = msa311->dev; 594 __le16 axis; 595 int err; 596 597 if (!iio_device_claim_direct(indio_dev)) 598 return -EBUSY; 599 600 err = pm_runtime_resume_and_get(dev); 601 if (err) { 602 iio_device_release_direct(indio_dev); 603 return err; 604 } 605 606 mutex_lock(&msa311->lock); 607 err = msa311_get_axis(msa311, chan, &axis); 608 mutex_unlock(&msa311->lock); 609 610 pm_runtime_mark_last_busy(dev); 611 pm_runtime_put_autosuspend(dev); 612 613 iio_device_release_direct(indio_dev); 614 615 if (err) { 616 dev_err(dev, "can't get axis %s (%pe)\n", 617 chan->datasheet_name, ERR_PTR(err)); 618 return err; 619 } 620 621 /* 622 * Axis data format is: 623 * ACC_X = (ACC_X_MSB[7:0] << 4) | ACC_X_LSB[7:4] 624 */ 625 *val = sign_extend32(le16_to_cpu(axis) >> chan->scan_type.shift, 626 chan->scan_type.realbits - 1); 627 628 return IIO_VAL_INT; 629 } 630 631 static int msa311_read_scale(struct iio_dev *indio_dev, int *val, int *val2) 632 { 633 struct msa311_priv *msa311 = iio_priv(indio_dev); 634 struct device *dev = msa311->dev; 635 unsigned int fs; 636 int err; 637 638 mutex_lock(&msa311->lock); 639 err = regmap_field_read(msa311->fields[F_FS], &fs); 640 mutex_unlock(&msa311->lock); 641 if (err) { 642 dev_err(dev, "can't get actual scale (%pe)\n", ERR_PTR(err)); 643 return err; 644 } 645 646 *val = msa311_fs_table[fs].integral; 647 *val2 = msa311_fs_table[fs].microfract; 648 649 return IIO_VAL_INT_PLUS_MICRO; 650 } 651 652 static int msa311_read_samp_freq(struct iio_dev *indio_dev, 653 int *val, int *val2) 654 { 655 struct msa311_priv *msa311 = iio_priv(indio_dev); 656 struct device *dev = msa311->dev; 657 unsigned int odr; 658 int err; 659 660 mutex_lock(&msa311->lock); 661 err = msa311_get_odr(msa311, &odr); 662 mutex_unlock(&msa311->lock); 663 if (err) { 664 dev_err(dev, "can't get actual frequency (%pe)\n", 665 ERR_PTR(err)); 666 return err; 667 } 668 669 *val = msa311_odr_table[odr].integral; 670 *val2 = msa311_odr_table[odr].microfract; 671 672 return IIO_VAL_INT_PLUS_MICRO; 673 } 674 675 static int msa311_read_raw(struct iio_dev *indio_dev, 676 struct iio_chan_spec const *chan, 677 int *val, int *val2, long mask) 678 { 679 switch (mask) { 680 case IIO_CHAN_INFO_RAW: 681 return msa311_read_raw_data(indio_dev, chan, val, val2); 682 683 case IIO_CHAN_INFO_SCALE: 684 return msa311_read_scale(indio_dev, val, val2); 685 686 case IIO_CHAN_INFO_SAMP_FREQ: 687 return msa311_read_samp_freq(indio_dev, val, val2); 688 689 default: 690 return -EINVAL; 691 } 692 } 693 694 static int msa311_read_avail(struct iio_dev *indio_dev, 695 struct iio_chan_spec const *chan, 696 const int **vals, int *type, 697 int *length, long mask) 698 { 699 switch (mask) { 700 case IIO_CHAN_INFO_SAMP_FREQ: 701 *vals = (int *)msa311_odr_table; 702 *type = IIO_VAL_INT_PLUS_MICRO; 703 /* ODR value has 2 ints (integer and fractional parts) */ 704 *length = ARRAY_SIZE(msa311_odr_table) * 2; 705 return IIO_AVAIL_LIST; 706 707 case IIO_CHAN_INFO_SCALE: 708 *vals = (int *)msa311_fs_table; 709 *type = IIO_VAL_INT_PLUS_MICRO; 710 /* FS value has 2 ints (integer and fractional parts) */ 711 *length = ARRAY_SIZE(msa311_fs_table) * 2; 712 return IIO_AVAIL_LIST; 713 714 default: 715 return -EINVAL; 716 } 717 } 718 719 static int msa311_write_scale(struct iio_dev *indio_dev, int val, int val2) 720 { 721 struct msa311_priv *msa311 = iio_priv(indio_dev); 722 struct device *dev = msa311->dev; 723 unsigned int fs; 724 int err; 725 726 /* We do not have fs >= 1, so skip such values */ 727 if (val) 728 return 0; 729 730 err = pm_runtime_resume_and_get(dev); 731 if (err) 732 return err; 733 734 err = -EINVAL; 735 for (fs = 0; fs < ARRAY_SIZE(msa311_fs_table); fs++) 736 /* Do not check msa311_fs_table[fs].integral, it's always 0 */ 737 if (val2 == msa311_fs_table[fs].microfract) { 738 mutex_lock(&msa311->lock); 739 err = regmap_field_write(msa311->fields[F_FS], fs); 740 mutex_unlock(&msa311->lock); 741 break; 742 } 743 744 pm_runtime_mark_last_busy(dev); 745 pm_runtime_put_autosuspend(dev); 746 747 if (err) 748 dev_err(dev, "can't update scale (%pe)\n", ERR_PTR(err)); 749 750 return err; 751 } 752 753 static int msa311_write_samp_freq(struct iio_dev *indio_dev, int val, int val2) 754 { 755 struct msa311_priv *msa311 = iio_priv(indio_dev); 756 struct device *dev = msa311->dev; 757 unsigned int odr; 758 int err; 759 760 /* 761 * Sampling frequency changing is prohibited when buffer mode is 762 * enabled, because sometimes MSA311 chip returns outliers during 763 * frequency values growing up in the read operation moment. 764 */ 765 if (!iio_device_claim_direct(indio_dev)) 766 return -EBUSY; 767 768 err = pm_runtime_resume_and_get(dev); 769 if (err) { 770 iio_device_release_direct(indio_dev); 771 return err; 772 } 773 774 err = -EINVAL; 775 for (odr = 0; odr < ARRAY_SIZE(msa311_odr_table); odr++) 776 if (val == msa311_odr_table[odr].integral && 777 val2 == msa311_odr_table[odr].microfract) { 778 mutex_lock(&msa311->lock); 779 err = msa311_set_odr(msa311, odr); 780 mutex_unlock(&msa311->lock); 781 break; 782 } 783 784 pm_runtime_mark_last_busy(dev); 785 pm_runtime_put_autosuspend(dev); 786 787 iio_device_release_direct(indio_dev); 788 789 if (err) 790 dev_err(dev, "can't update frequency (%pe)\n", ERR_PTR(err)); 791 792 return err; 793 } 794 795 static int msa311_write_raw(struct iio_dev *indio_dev, 796 struct iio_chan_spec const *chan, 797 int val, int val2, long mask) 798 { 799 switch (mask) { 800 case IIO_CHAN_INFO_SCALE: 801 return msa311_write_scale(indio_dev, val, val2); 802 803 case IIO_CHAN_INFO_SAMP_FREQ: 804 return msa311_write_samp_freq(indio_dev, val, val2); 805 806 default: 807 return -EINVAL; 808 } 809 } 810 811 static int msa311_debugfs_reg_access(struct iio_dev *indio_dev, 812 unsigned int reg, unsigned int writeval, 813 unsigned int *readval) 814 { 815 struct msa311_priv *msa311 = iio_priv(indio_dev); 816 struct device *dev = msa311->dev; 817 int err; 818 819 if (reg > regmap_get_max_register(msa311->regs)) 820 return -EINVAL; 821 822 err = pm_runtime_resume_and_get(dev); 823 if (err) 824 return err; 825 826 mutex_lock(&msa311->lock); 827 828 if (readval) 829 err = regmap_read(msa311->regs, reg, readval); 830 else 831 err = regmap_write(msa311->regs, reg, writeval); 832 833 mutex_unlock(&msa311->lock); 834 835 pm_runtime_mark_last_busy(dev); 836 pm_runtime_put_autosuspend(dev); 837 838 if (err) 839 dev_err(dev, "can't %s register %u from debugfs (%pe)\n", 840 str_read_write(readval), reg, ERR_PTR(err)); 841 842 return err; 843 } 844 845 static int msa311_buffer_preenable(struct iio_dev *indio_dev) 846 { 847 struct msa311_priv *msa311 = iio_priv(indio_dev); 848 struct device *dev = msa311->dev; 849 850 return pm_runtime_resume_and_get(dev); 851 } 852 853 static int msa311_buffer_postdisable(struct iio_dev *indio_dev) 854 { 855 struct msa311_priv *msa311 = iio_priv(indio_dev); 856 struct device *dev = msa311->dev; 857 858 pm_runtime_mark_last_busy(dev); 859 pm_runtime_put_autosuspend(dev); 860 861 return 0; 862 } 863 864 static int msa311_set_new_data_trig_state(struct iio_trigger *trig, bool state) 865 { 866 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 867 struct msa311_priv *msa311 = iio_priv(indio_dev); 868 struct device *dev = msa311->dev; 869 int err; 870 871 mutex_lock(&msa311->lock); 872 err = regmap_field_write(msa311->fields[F_NEW_DATA_INT_EN], state); 873 mutex_unlock(&msa311->lock); 874 if (err) 875 dev_err(dev, 876 "can't %s buffer due to new_data_int failure (%pe)\n", 877 str_enable_disable(state), ERR_PTR(err)); 878 879 return err; 880 } 881 882 static int msa311_validate_device(struct iio_trigger *trig, 883 struct iio_dev *indio_dev) 884 { 885 return iio_trigger_get_drvdata(trig) == indio_dev ? 0 : -EINVAL; 886 } 887 888 static irqreturn_t msa311_buffer_thread(int irq, void *p) 889 { 890 struct iio_poll_func *pf = p; 891 struct msa311_priv *msa311 = iio_priv(pf->indio_dev); 892 struct iio_dev *indio_dev = pf->indio_dev; 893 const struct iio_chan_spec *chan; 894 struct device *dev = msa311->dev; 895 int bit, err, i = 0; 896 __le16 axis; 897 struct { 898 __le16 channels[MSA311_SI_Z + 1]; 899 aligned_s64 ts; 900 } buf; 901 902 memset(&buf, 0, sizeof(buf)); 903 904 mutex_lock(&msa311->lock); 905 906 iio_for_each_active_channel(indio_dev, bit) { 907 chan = &msa311_channels[bit]; 908 909 err = msa311_get_axis(msa311, chan, &axis); 910 if (err) { 911 mutex_unlock(&msa311->lock); 912 dev_err(dev, "can't get axis %s (%pe)\n", 913 chan->datasheet_name, ERR_PTR(err)); 914 goto notify_done; 915 } 916 917 buf.channels[i++] = axis; 918 } 919 920 mutex_unlock(&msa311->lock); 921 922 iio_push_to_buffers_with_ts(indio_dev, &buf, sizeof(buf), 923 iio_get_time_ns(indio_dev)); 924 925 notify_done: 926 iio_trigger_notify_done(indio_dev->trig); 927 928 return IRQ_HANDLED; 929 } 930 931 static irqreturn_t msa311_irq_thread(int irq, void *p) 932 { 933 struct msa311_priv *msa311 = iio_priv(p); 934 unsigned int new_data_int_enabled; 935 struct device *dev = msa311->dev; 936 int err; 937 938 mutex_lock(&msa311->lock); 939 940 /* 941 * We do not check NEW_DATA int status, because based on the 942 * specification it's cleared automatically after a fixed time. 943 * So just check that is enabled by driver logic. 944 */ 945 err = regmap_field_read(msa311->fields[F_NEW_DATA_INT_EN], 946 &new_data_int_enabled); 947 948 mutex_unlock(&msa311->lock); 949 if (err) { 950 dev_err(dev, "can't read new_data interrupt state (%pe)\n", 951 ERR_PTR(err)); 952 return IRQ_NONE; 953 } 954 955 if (new_data_int_enabled) 956 iio_trigger_poll_nested(msa311->new_data_trig); 957 958 return IRQ_HANDLED; 959 } 960 961 static const struct iio_info msa311_info = { 962 .read_raw = msa311_read_raw, 963 .read_avail = msa311_read_avail, 964 .write_raw = msa311_write_raw, 965 .debugfs_reg_access = msa311_debugfs_reg_access, 966 }; 967 968 static const struct iio_buffer_setup_ops msa311_buffer_setup_ops = { 969 .preenable = msa311_buffer_preenable, 970 .postdisable = msa311_buffer_postdisable, 971 }; 972 973 static const struct iio_trigger_ops msa311_new_data_trig_ops = { 974 .set_trigger_state = msa311_set_new_data_trig_state, 975 .validate_device = msa311_validate_device, 976 }; 977 978 static int msa311_check_partid(struct msa311_priv *msa311) 979 { 980 struct device *dev = msa311->dev; 981 unsigned int partid; 982 int err; 983 984 err = regmap_read(msa311->regs, MSA311_PARTID_REG, &partid); 985 if (err) 986 return dev_err_probe(dev, err, "failed to read partid\n"); 987 988 if (partid != MSA311_WHO_AM_I) 989 dev_warn(dev, "invalid partid (%#x), expected (%#x)\n", 990 partid, MSA311_WHO_AM_I); 991 992 msa311->chip_name = devm_kasprintf(dev, GFP_KERNEL, 993 "msa311-%02x", partid); 994 if (!msa311->chip_name) 995 return dev_err_probe(dev, -ENOMEM, "can't alloc chip name\n"); 996 997 return 0; 998 } 999 1000 static int msa311_soft_reset(struct msa311_priv *msa311) 1001 { 1002 struct device *dev = msa311->dev; 1003 int err; 1004 1005 err = regmap_write(msa311->regs, MSA311_SOFT_RESET_REG, 1006 MSA311_GENMASK(F_SOFT_RESET_I2C) | 1007 MSA311_GENMASK(F_SOFT_RESET_SPI)); 1008 if (err) 1009 return dev_err_probe(dev, err, "can't soft reset all logic\n"); 1010 1011 return 0; 1012 } 1013 1014 static int msa311_chip_init(struct msa311_priv *msa311) 1015 { 1016 struct device *dev = msa311->dev; 1017 const char zero_bulk[2] = { }; 1018 int err; 1019 1020 err = regmap_write(msa311->regs, MSA311_RANGE_REG, MSA311_FS_16G); 1021 if (err) 1022 return dev_err_probe(dev, err, "failed to setup accel range\n"); 1023 1024 /* Disable all interrupts by default */ 1025 err = regmap_bulk_write(msa311->regs, MSA311_INT_SET_0_REG, 1026 zero_bulk, sizeof(zero_bulk)); 1027 if (err) 1028 return dev_err_probe(dev, err, 1029 "can't disable set0/set1 interrupts\n"); 1030 1031 /* Unmap all INT1 interrupts by default */ 1032 err = regmap_bulk_write(msa311->regs, MSA311_INT_MAP_0_REG, 1033 zero_bulk, sizeof(zero_bulk)); 1034 if (err) 1035 return dev_err_probe(dev, err, 1036 "failed to unmap map0/map1 interrupts\n"); 1037 1038 /* Disable all axes by default */ 1039 err = regmap_clear_bits(msa311->regs, MSA311_ODR_REG, 1040 MSA311_GENMASK(F_X_AXIS_DIS) | 1041 MSA311_GENMASK(F_Y_AXIS_DIS) | 1042 MSA311_GENMASK(F_Z_AXIS_DIS)); 1043 if (err) 1044 return dev_err_probe(dev, err, "can't enable all axes\n"); 1045 1046 err = msa311_set_odr(msa311, MSA311_ODR_125_HZ); 1047 if (err) 1048 return dev_err_probe(dev, err, 1049 "failed to set accel frequency\n"); 1050 1051 return 0; 1052 } 1053 1054 static int msa311_setup_interrupts(struct msa311_priv *msa311) 1055 { 1056 struct device *dev = msa311->dev; 1057 struct i2c_client *i2c = to_i2c_client(dev); 1058 struct iio_dev *indio_dev = i2c_get_clientdata(i2c); 1059 struct iio_trigger *trig; 1060 int err; 1061 1062 /* Keep going without interrupts if no initialized I2C IRQ */ 1063 if (i2c->irq <= 0) 1064 return 0; 1065 1066 err = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, 1067 msa311_irq_thread, IRQF_ONESHOT, 1068 msa311->chip_name, indio_dev); 1069 if (err) 1070 return dev_err_probe(dev, err, "failed to request IRQ\n"); 1071 1072 trig = devm_iio_trigger_alloc(dev, "%s-new-data", msa311->chip_name); 1073 if (!trig) 1074 return dev_err_probe(dev, -ENOMEM, 1075 "can't allocate newdata trigger\n"); 1076 1077 msa311->new_data_trig = trig; 1078 msa311->new_data_trig->ops = &msa311_new_data_trig_ops; 1079 iio_trigger_set_drvdata(msa311->new_data_trig, indio_dev); 1080 1081 err = devm_iio_trigger_register(dev, msa311->new_data_trig); 1082 if (err) 1083 return dev_err_probe(dev, err, 1084 "can't register newdata trigger\n"); 1085 1086 err = regmap_field_write(msa311->fields[F_INT1_OD], 1087 MSA311_INT1_OD_PUSH_PULL); 1088 if (err) 1089 return dev_err_probe(dev, err, 1090 "can't enable push-pull interrupt\n"); 1091 1092 err = regmap_field_write(msa311->fields[F_INT1_LVL], 1093 MSA311_INT1_LVL_HIGH); 1094 if (err) 1095 return dev_err_probe(dev, err, 1096 "can't set active interrupt level\n"); 1097 1098 err = regmap_field_write(msa311->fields[F_LATCH_INT], 1099 MSA311_LATCH_INT_LATCHED); 1100 if (err) 1101 return dev_err_probe(dev, err, 1102 "can't latch interrupt\n"); 1103 1104 err = regmap_field_write(msa311->fields[F_RESET_INT], 1); 1105 if (err) 1106 return dev_err_probe(dev, err, 1107 "can't reset interrupt\n"); 1108 1109 err = regmap_field_write(msa311->fields[F_INT1_NEW_DATA], 1); 1110 if (err) 1111 return dev_err_probe(dev, err, 1112 "can't map new data interrupt\n"); 1113 1114 return 0; 1115 } 1116 1117 static int msa311_regmap_init(struct msa311_priv *msa311) 1118 { 1119 struct regmap_field **fields = msa311->fields; 1120 struct device *dev = msa311->dev; 1121 struct i2c_client *i2c = to_i2c_client(dev); 1122 struct regmap *regmap; 1123 int i; 1124 1125 regmap = devm_regmap_init_i2c(i2c, &msa311_regmap_config); 1126 if (IS_ERR(regmap)) 1127 return dev_err_probe(dev, PTR_ERR(regmap), 1128 "failed to register i2c regmap\n"); 1129 1130 msa311->regs = regmap; 1131 1132 for (i = 0; i < F_MAX_FIELDS; i++) { 1133 fields[i] = devm_regmap_field_alloc(dev, 1134 msa311->regs, 1135 msa311_reg_fields[i]); 1136 if (IS_ERR(msa311->fields[i])) 1137 return dev_err_probe(dev, PTR_ERR(msa311->fields[i]), 1138 "can't alloc field[%d]\n", i); 1139 } 1140 1141 return 0; 1142 } 1143 1144 static void msa311_powerdown(void *msa311) 1145 { 1146 msa311_set_pwr_mode(msa311, MSA311_PWR_MODE_SUSPEND); 1147 } 1148 1149 static int msa311_probe(struct i2c_client *i2c) 1150 { 1151 struct device *dev = &i2c->dev; 1152 struct msa311_priv *msa311; 1153 struct iio_dev *indio_dev; 1154 int err; 1155 1156 indio_dev = devm_iio_device_alloc(dev, sizeof(*msa311)); 1157 if (!indio_dev) 1158 return dev_err_probe(dev, -ENOMEM, 1159 "IIO device allocation failed\n"); 1160 1161 msa311 = iio_priv(indio_dev); 1162 msa311->dev = dev; 1163 i2c_set_clientdata(i2c, indio_dev); 1164 1165 err = msa311_regmap_init(msa311); 1166 if (err) 1167 return err; 1168 1169 mutex_init(&msa311->lock); 1170 1171 err = devm_regulator_get_enable(dev, "vdd"); 1172 if (err) 1173 return dev_err_probe(dev, err, "can't get vdd supply\n"); 1174 1175 err = msa311_check_partid(msa311); 1176 if (err) 1177 return err; 1178 1179 err = msa311_soft_reset(msa311); 1180 if (err) 1181 return err; 1182 1183 err = msa311_set_pwr_mode(msa311, MSA311_PWR_MODE_NORMAL); 1184 if (err) 1185 return dev_err_probe(dev, err, "failed to power on device\n"); 1186 1187 /* 1188 * Register powerdown deferred callback which suspends the chip 1189 * after module unloaded. 1190 * 1191 * MSA311 should be in SUSPEND mode in the two cases: 1192 * 1) When driver is loaded, but we do not have any data or 1193 * configuration requests to it (we are solving it using 1194 * autosuspend feature). 1195 * 2) When driver is unloaded and device is not used (devm action is 1196 * used in this case). 1197 */ 1198 err = devm_add_action_or_reset(dev, msa311_powerdown, msa311); 1199 if (err) 1200 return dev_err_probe(dev, err, "can't add powerdown action\n"); 1201 1202 err = pm_runtime_set_active(dev); 1203 if (err) 1204 return err; 1205 1206 err = devm_pm_runtime_enable(dev); 1207 if (err) 1208 return err; 1209 1210 pm_runtime_get_noresume(dev); 1211 pm_runtime_set_autosuspend_delay(dev, MSA311_PWR_SLEEP_DELAY_MS); 1212 pm_runtime_use_autosuspend(dev); 1213 1214 err = msa311_chip_init(msa311); 1215 if (err) 1216 return err; 1217 1218 indio_dev->modes = INDIO_DIRECT_MODE; 1219 indio_dev->channels = msa311_channels; 1220 indio_dev->num_channels = ARRAY_SIZE(msa311_channels); 1221 indio_dev->name = msa311->chip_name; 1222 indio_dev->info = &msa311_info; 1223 1224 err = devm_iio_triggered_buffer_setup(dev, indio_dev, 1225 iio_pollfunc_store_time, 1226 msa311_buffer_thread, 1227 &msa311_buffer_setup_ops); 1228 if (err) 1229 return dev_err_probe(dev, err, 1230 "can't setup IIO trigger buffer\n"); 1231 1232 err = msa311_setup_interrupts(msa311); 1233 if (err) 1234 return err; 1235 1236 pm_runtime_mark_last_busy(dev); 1237 pm_runtime_put_autosuspend(dev); 1238 1239 err = devm_iio_device_register(dev, indio_dev); 1240 if (err) 1241 return dev_err_probe(dev, err, "IIO device register failed\n"); 1242 1243 return 0; 1244 } 1245 1246 static int msa311_runtime_suspend(struct device *dev) 1247 { 1248 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1249 struct msa311_priv *msa311 = iio_priv(indio_dev); 1250 int err; 1251 1252 mutex_lock(&msa311->lock); 1253 err = msa311_set_pwr_mode(msa311, MSA311_PWR_MODE_SUSPEND); 1254 mutex_unlock(&msa311->lock); 1255 if (err) 1256 dev_err(dev, "failed to power off device (%pe)\n", 1257 ERR_PTR(err)); 1258 1259 return err; 1260 } 1261 1262 static int msa311_runtime_resume(struct device *dev) 1263 { 1264 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1265 struct msa311_priv *msa311 = iio_priv(indio_dev); 1266 int err; 1267 1268 mutex_lock(&msa311->lock); 1269 err = msa311_set_pwr_mode(msa311, MSA311_PWR_MODE_NORMAL); 1270 mutex_unlock(&msa311->lock); 1271 if (err) 1272 dev_err(dev, "failed to power on device (%pe)\n", 1273 ERR_PTR(err)); 1274 1275 return err; 1276 } 1277 1278 static DEFINE_RUNTIME_DEV_PM_OPS(msa311_pm_ops, msa311_runtime_suspend, 1279 msa311_runtime_resume, NULL); 1280 1281 static const struct i2c_device_id msa311_i2c_id[] = { 1282 { .name = "msa311" }, 1283 { } 1284 }; 1285 MODULE_DEVICE_TABLE(i2c, msa311_i2c_id); 1286 1287 static const struct of_device_id msa311_of_match[] = { 1288 { .compatible = "memsensing,msa311" }, 1289 { } 1290 }; 1291 MODULE_DEVICE_TABLE(of, msa311_of_match); 1292 1293 static struct i2c_driver msa311_driver = { 1294 .driver = { 1295 .name = "msa311", 1296 .of_match_table = msa311_of_match, 1297 .pm = pm_ptr(&msa311_pm_ops), 1298 }, 1299 .probe = msa311_probe, 1300 .id_table = msa311_i2c_id, 1301 }; 1302 module_i2c_driver(msa311_driver); 1303 1304 MODULE_AUTHOR("Dmitry Rokosov <ddrokosov@sberdevices.ru>"); 1305 MODULE_DESCRIPTION("MEMSensing MSA311 3-axis accelerometer driver"); 1306 MODULE_LICENSE("GPL"); 1307