1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 5 <mdsxyz123@yahoo.com> 6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> 7 Copyright (C) 2010 Intel Corporation, 8 David Woodhouse <dwmw2@infradead.org> 9 10 */ 11 12 /* 13 * Supports the following Intel I/O Controller Hubs (ICH): 14 * 15 * I/O Block I2C 16 * region SMBus Block proc. block 17 * Chip name PCI ID size PEC buffer call read 18 * --------------------------------------------------------------------------- 19 * 82801AA (ICH) 0x2413 16 no no no no 20 * 82801AB (ICH0) 0x2423 16 no no no no 21 * 82801BA (ICH2) 0x2443 16 no no no no 22 * 82801CA (ICH3) 0x2483 32 soft no no no 23 * 82801DB (ICH4) 0x24c3 32 hard yes no no 24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes 25 * 6300ESB 0x25a4 32 hard yes yes yes 26 * 82801F (ICH6) 0x266a 32 hard yes yes yes 27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes 28 * 82801G (ICH7) 0x27da 32 hard yes yes yes 29 * 82801H (ICH8) 0x283e 32 hard yes yes yes 30 * 82801I (ICH9) 0x2930 32 hard yes yes yes 31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes 32 * ICH10 0x3a30 32 hard yes yes yes 33 * ICH10 0x3a60 32 hard yes yes yes 34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes 35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes 36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes 37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes 38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes 39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes 40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes 41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes 42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes 43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes 44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes 45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes 46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes 47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes 50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes 51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes 53 * Braswell (SOC) 0x2292 32 hard yes yes yes 54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes 55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes 56 * DNV (SOC) 0x19df 32 hard yes yes yes 57 * Emmitsburg (PCH) 0x1bc9 32 hard yes yes yes 58 * Broxton (SOC) 0x5ad4 32 hard yes yes yes 59 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes 60 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes 61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes 62 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes 63 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes 64 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes 65 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes 66 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes 67 * Ice Lake-N (PCH) 0x38a3 32 hard yes yes yes 68 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes 69 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes 70 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes 71 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes 72 * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes 73 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes 74 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes 75 * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes 76 * Alder Lake-P (PCH) 0x51a3 32 hard yes yes yes 77 * Alder Lake-M (PCH) 0x54a3 32 hard yes yes yes 78 * Raptor Lake-S (PCH) 0x7a23 32 hard yes yes yes 79 * Meteor Lake-P (SOC) 0x7e22 32 hard yes yes yes 80 * Meteor Lake SoC-S (SOC) 0xae22 32 hard yes yes yes 81 * Meteor Lake PCH-S (PCH) 0x7f23 32 hard yes yes yes 82 * Birch Stream (SOC) 0x5796 32 hard yes yes yes 83 * Arrow Lake-H (SOC) 0x7722 32 hard yes yes yes 84 * Panther Lake-H (SOC) 0xe322 32 hard yes yes yes 85 * Panther Lake-P (SOC) 0xe422 32 hard yes yes yes 86 * 87 * Features supported by this driver: 88 * Software PEC no 89 * Hardware PEC yes 90 * Block buffer yes 91 * Block process call transaction yes 92 * I2C block read transaction yes (doesn't use the block buffer) 93 * Target mode no 94 * SMBus Host Notify yes 95 * Interrupt processing yes 96 * 97 * See the file Documentation/i2c/busses/i2c-i801.rst for details. 98 */ 99 100 #define DRV_NAME "i801_smbus" 101 102 #include <linux/interrupt.h> 103 #include <linux/module.h> 104 #include <linux/pci.h> 105 #include <linux/kernel.h> 106 #include <linux/stddef.h> 107 #include <linux/delay.h> 108 #include <linux/ioport.h> 109 #include <linux/init.h> 110 #include <linux/i2c.h> 111 #include <linux/i2c-mux.h> 112 #include <linux/i2c-smbus.h> 113 #include <linux/acpi.h> 114 #include <linux/io.h> 115 #include <linux/dmi.h> 116 #include <linux/slab.h> 117 #include <linux/string.h> 118 #include <linux/completion.h> 119 #include <linux/err.h> 120 #include <linux/platform_device.h> 121 #include <linux/platform_data/itco_wdt.h> 122 #include <linux/platform_data/x86/p2sb.h> 123 #include <linux/pm_runtime.h> 124 #include <linux/mutex.h> 125 126 #ifdef CONFIG_I2C_I801_MUX 127 #include <linux/gpio/machine.h> 128 #include <linux/platform_data/i2c-mux-gpio.h> 129 #endif 130 131 /* I801 SMBus address offsets */ 132 #define SMBHSTSTS(p) (0 + (p)->smba) 133 #define SMBHSTCNT(p) (2 + (p)->smba) 134 #define SMBHSTCMD(p) (3 + (p)->smba) 135 #define SMBHSTADD(p) (4 + (p)->smba) 136 #define SMBHSTDAT0(p) (5 + (p)->smba) 137 #define SMBHSTDAT1(p) (6 + (p)->smba) 138 #define SMBBLKDAT(p) (7 + (p)->smba) 139 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ 140 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ 141 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ 142 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */ 143 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */ 144 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */ 145 146 /* PCI Address Constants */ 147 #define SMBBAR_MMIO 0 148 #define SMBBAR 4 149 #define SMBHSTCFG 0x040 150 #define TCOBASE 0x050 151 #define TCOCTL 0x054 152 153 #define SBREG_SMBCTRL 0xc6000c 154 #define SBREG_SMBCTRL_DNV 0xcf000c 155 156 /* Host configuration bits for SMBHSTCFG */ 157 #define SMBHSTCFG_HST_EN BIT(0) 158 #define SMBHSTCFG_SMB_SMI_EN BIT(1) 159 #define SMBHSTCFG_I2C_EN BIT(2) 160 #define SMBHSTCFG_SPD_WD BIT(4) 161 162 /* TCO configuration bits for TCOCTL */ 163 #define TCOCTL_EN BIT(8) 164 165 /* Auxiliary status register bits, ICH4+ only */ 166 #define SMBAUXSTS_CRCE BIT(0) 167 #define SMBAUXSTS_STCO BIT(1) 168 169 /* Auxiliary control register bits, ICH4+ only */ 170 #define SMBAUXCTL_CRC BIT(0) 171 #define SMBAUXCTL_E32B BIT(1) 172 173 /* I801 command constants */ 174 #define I801_QUICK 0x00 175 #define I801_BYTE 0x04 176 #define I801_BYTE_DATA 0x08 177 #define I801_WORD_DATA 0x0C 178 #define I801_PROC_CALL 0x10 179 #define I801_BLOCK_DATA 0x14 180 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 181 #define I801_BLOCK_PROC_CALL 0x1C 182 183 /* I801 Host Control register bits */ 184 #define SMBHSTCNT_INTREN BIT(0) 185 #define SMBHSTCNT_KILL BIT(1) 186 #define SMBHSTCNT_LAST_BYTE BIT(5) 187 #define SMBHSTCNT_START BIT(6) 188 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */ 189 190 /* I801 Hosts Status register bits */ 191 #define SMBHSTSTS_BYTE_DONE BIT(7) 192 #define SMBHSTSTS_INUSE_STS BIT(6) 193 #define SMBHSTSTS_SMBALERT_STS BIT(5) 194 #define SMBHSTSTS_FAILED BIT(4) 195 #define SMBHSTSTS_BUS_ERR BIT(3) 196 #define SMBHSTSTS_DEV_ERR BIT(2) 197 #define SMBHSTSTS_INTR BIT(1) 198 #define SMBHSTSTS_HOST_BUSY BIT(0) 199 200 /* Host Notify Status register bits */ 201 #define SMBSLVSTS_HST_NTFY_STS BIT(0) 202 203 /* Host Notify Command register bits */ 204 #define SMBSLVCMD_SMBALERT_DISABLE BIT(2) 205 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0) 206 207 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ 208 SMBHSTSTS_DEV_ERR) 209 210 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ 211 STATUS_ERROR_FLAGS) 212 213 #define SMBUS_LEN_SENTINEL (I2C_SMBUS_BLOCK_MAX + 1) 214 215 /* Older devices have their ID defined in <linux/pci_ids.h> */ 216 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3 217 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3 218 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 219 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df 220 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df 221 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS 0x1bc9 222 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 223 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 224 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ 225 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 226 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 227 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 228 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 229 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c 230 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 231 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 232 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 233 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4 234 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3 235 #define PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS 0x38a3 236 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 237 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3 238 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23 239 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3 240 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS 0x51a3 241 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS 0x54a3 242 #define PCI_DEVICE_ID_INTEL_BIRCH_STREAM_SMBUS 0x5796 243 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 244 #define PCI_DEVICE_ID_INTEL_ARROW_LAKE_H_SMBUS 0x7722 245 #define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_S_SMBUS 0x7a23 246 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3 247 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_P_SMBUS 0x7e22 248 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_PCH_S_SMBUS 0x7f23 249 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 250 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 251 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 252 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d 253 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e 254 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 255 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 256 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 257 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 258 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3 259 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3 260 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 261 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3 262 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223 263 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3 264 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323 265 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3 266 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_SOC_S_SMBUS 0xae22 267 #define PCI_DEVICE_ID_INTEL_PANTHER_LAKE_H_SMBUS 0xe322 268 #define PCI_DEVICE_ID_INTEL_PANTHER_LAKE_P_SMBUS 0xe422 269 270 struct i801_mux_config { 271 char *gpio_chip; 272 unsigned values[3]; 273 int n_values; 274 unsigned gpios[2]; /* Relative to gpio_chip->base */ 275 int n_gpios; 276 }; 277 278 struct i801_priv { 279 struct i2c_adapter adapter; 280 void __iomem *smba; 281 unsigned char original_hstcfg; 282 unsigned char original_hstcnt; 283 unsigned char original_slvcmd; 284 struct pci_dev *pci_dev; 285 unsigned int features; 286 287 /* isr processing */ 288 struct completion done; 289 u8 status; 290 291 /* Command state used by isr for byte-by-byte block transactions */ 292 u8 cmd; 293 bool is_read; 294 int count; 295 int len; 296 u8 *data; 297 298 #ifdef CONFIG_I2C_I801_MUX 299 struct platform_device *mux_pdev; 300 struct gpiod_lookup_table *lookup; 301 struct notifier_block mux_notifier_block; 302 #endif 303 struct platform_device *tco_pdev; 304 305 /* 306 * If set to true the host controller registers are reserved for 307 * ACPI AML use. 308 */ 309 bool acpi_reserved; 310 }; 311 312 #define FEATURE_SMBUS_PEC BIT(0) 313 #define FEATURE_BLOCK_BUFFER BIT(1) 314 #define FEATURE_BLOCK_PROC BIT(2) 315 #define FEATURE_I2C_BLOCK_READ BIT(3) 316 #define FEATURE_IRQ BIT(4) 317 #define FEATURE_HOST_NOTIFY BIT(5) 318 /* Not really a feature, but it's convenient to handle it as such */ 319 #define FEATURE_IDF BIT(15) 320 #define FEATURE_TCO_SPT BIT(16) 321 #define FEATURE_TCO_CNL BIT(17) 322 323 static const char *i801_feature_names[] = { 324 "SMBus PEC", 325 "Block buffer", 326 "Block process call", 327 "I2C block read", 328 "Interrupt", 329 "SMBus Host Notify", 330 }; 331 332 static unsigned int disable_features; 333 module_param(disable_features, uint, S_IRUGO | S_IWUSR); 334 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" 335 "\t\t 0x01 disable SMBus PEC\n" 336 "\t\t 0x02 disable the block buffer\n" 337 "\t\t 0x08 disable the I2C block read functionality\n" 338 "\t\t 0x10 don't use interrupts\n" 339 "\t\t 0x20 disable SMBus Host Notify "); 340 341 /* Wait for BUSY being cleared and either INTR or an error flag being set */ 342 static int i801_wait_intr(struct i801_priv *priv) 343 { 344 unsigned long timeout = jiffies + priv->adapter.timeout; 345 int status, busy; 346 347 do { 348 usleep_range(250, 500); 349 status = ioread8(SMBHSTSTS(priv)); 350 busy = status & SMBHSTSTS_HOST_BUSY; 351 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR; 352 if (!busy && status) 353 return status & STATUS_ERROR_FLAGS; 354 } while (time_is_after_eq_jiffies(timeout)); 355 356 return -ETIMEDOUT; 357 } 358 359 /* Wait for either BYTE_DONE or an error flag being set */ 360 static int i801_wait_byte_done(struct i801_priv *priv) 361 { 362 unsigned long timeout = jiffies + priv->adapter.timeout; 363 int status; 364 365 do { 366 usleep_range(250, 500); 367 status = ioread8(SMBHSTSTS(priv)); 368 if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) 369 return status & STATUS_ERROR_FLAGS; 370 } while (time_is_after_eq_jiffies(timeout)); 371 372 return -ETIMEDOUT; 373 } 374 375 static int i801_get_block_len(struct i801_priv *priv) 376 { 377 u8 len = ioread8(SMBHSTDAT0(priv)); 378 379 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 380 pci_err(priv->pci_dev, "Illegal SMBus block read size %u\n", len); 381 return -EPROTO; 382 } 383 384 return len; 385 } 386 387 static int i801_check_and_clear_pec_error(struct i801_priv *priv) 388 { 389 u8 status; 390 391 if (!(priv->features & FEATURE_SMBUS_PEC)) 392 return 0; 393 394 status = ioread8(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 395 if (status) { 396 iowrite8(status, SMBAUXSTS(priv)); 397 return -EBADMSG; 398 } 399 400 return 0; 401 } 402 403 /* Make sure the SMBus host is ready to start transmitting. 404 Return 0 if it is, -EBUSY if it is not. */ 405 static int i801_check_pre(struct i801_priv *priv) 406 { 407 int status, result; 408 409 status = ioread8(SMBHSTSTS(priv)); 410 if (status & SMBHSTSTS_HOST_BUSY) { 411 pci_err(priv->pci_dev, "SMBus is busy, can't use it!\n"); 412 return -EBUSY; 413 } 414 415 status &= STATUS_FLAGS; 416 if (status) { 417 pci_dbg(priv->pci_dev, "Clearing status flags (%02x)\n", status); 418 iowrite8(status, SMBHSTSTS(priv)); 419 } 420 421 /* 422 * Clear CRC status if needed. 423 * During normal operation, i801_check_post() takes care 424 * of it after every operation. We do it here only in case 425 * the hardware was already in this state when the driver 426 * started. 427 */ 428 result = i801_check_and_clear_pec_error(priv); 429 if (result) 430 pci_dbg(priv->pci_dev, "Clearing aux status flag CRCE\n"); 431 432 return 0; 433 } 434 435 static int i801_check_post(struct i801_priv *priv, int status) 436 { 437 int result = 0; 438 439 /* 440 * If the SMBus is still busy, we give up 441 */ 442 if (unlikely(status < 0)) { 443 /* try to stop the current command */ 444 iowrite8(SMBHSTCNT_KILL, SMBHSTCNT(priv)); 445 status = i801_wait_intr(priv); 446 iowrite8(0, SMBHSTCNT(priv)); 447 448 /* Check if it worked */ 449 if (status < 0 || !(status & SMBHSTSTS_FAILED)) 450 pci_dbg(priv->pci_dev, "Failed terminating the transaction\n"); 451 return -ETIMEDOUT; 452 } 453 454 if (status & SMBHSTSTS_FAILED) { 455 result = -EIO; 456 pci_err(priv->pci_dev, "Transaction failed\n"); 457 } 458 if (status & SMBHSTSTS_DEV_ERR) { 459 /* 460 * This may be a PEC error, check and clear it. 461 * 462 * AUXSTS is handled differently from HSTSTS. 463 * For HSTSTS, i801_isr() or i801_wait_intr() 464 * has already cleared the error bits in hardware, 465 * and we are passed a copy of the original value 466 * in "status". 467 * For AUXSTS, the hardware register is left 468 * for us to handle here. 469 * This is asymmetric, slightly iffy, but safe, 470 * since all this code is serialized and the CRCE 471 * bit is harmless as long as it's cleared before 472 * the next operation. 473 */ 474 result = i801_check_and_clear_pec_error(priv); 475 if (result) { 476 pci_dbg(priv->pci_dev, "PEC error\n"); 477 } else { 478 result = -ENXIO; 479 pci_dbg(priv->pci_dev, "No response\n"); 480 } 481 } 482 if (status & SMBHSTSTS_BUS_ERR) { 483 result = -EAGAIN; 484 pci_dbg(priv->pci_dev, "Lost arbitration\n"); 485 } 486 487 return result; 488 } 489 490 static int i801_transaction(struct i801_priv *priv, int xact) 491 { 492 unsigned long result; 493 const struct i2c_adapter *adap = &priv->adapter; 494 495 if (priv->features & FEATURE_IRQ) { 496 reinit_completion(&priv->done); 497 iowrite8(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 498 SMBHSTCNT(priv)); 499 result = wait_for_completion_timeout(&priv->done, adap->timeout); 500 return result ? priv->status : -ETIMEDOUT; 501 } 502 503 iowrite8(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); 504 505 return i801_wait_intr(priv); 506 } 507 508 static int i801_block_transaction_by_block(struct i801_priv *priv, 509 union i2c_smbus_data *data, 510 char read_write, int command) 511 { 512 int len, status, xact; 513 514 switch (command) { 515 case I2C_SMBUS_BLOCK_PROC_CALL: 516 xact = I801_BLOCK_PROC_CALL; 517 break; 518 case I2C_SMBUS_BLOCK_DATA: 519 xact = I801_BLOCK_DATA; 520 break; 521 default: 522 return -EOPNOTSUPP; 523 } 524 525 /* Set block buffer mode */ 526 iowrite8(ioread8(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); 527 528 if (read_write == I2C_SMBUS_WRITE) { 529 len = data->block[0]; 530 iowrite8(len, SMBHSTDAT0(priv)); 531 ioread8(SMBHSTCNT(priv)); /* reset the data buffer index */ 532 iowrite8_rep(SMBBLKDAT(priv), data->block + 1, len); 533 } 534 535 status = i801_transaction(priv, xact); 536 if (status) 537 goto out; 538 539 if (read_write == I2C_SMBUS_READ || 540 command == I2C_SMBUS_BLOCK_PROC_CALL) { 541 len = i801_get_block_len(priv); 542 if (len < 0) { 543 status = len; 544 goto out; 545 } 546 547 data->block[0] = len; 548 ioread8(SMBHSTCNT(priv)); /* reset the data buffer index */ 549 ioread8_rep(SMBBLKDAT(priv), data->block + 1, len); 550 } 551 out: 552 iowrite8(ioread8(SMBAUXCTL(priv)) & ~SMBAUXCTL_E32B, SMBAUXCTL(priv)); 553 return status; 554 } 555 556 static void i801_isr_byte_done(struct i801_priv *priv) 557 { 558 if (priv->is_read) { 559 /* 560 * At transfer start i801_smbus_block_transaction() marks 561 * the block length as invalid. Check for this sentinel value 562 * and read the block length from SMBHSTDAT0. 563 */ 564 if (priv->len == SMBUS_LEN_SENTINEL) { 565 priv->len = i801_get_block_len(priv); 566 if (priv->len < 0) 567 /* FIXME: Recover */ 568 priv->len = I2C_SMBUS_BLOCK_MAX; 569 570 priv->data[-1] = priv->len; 571 } 572 573 /* Read next byte */ 574 if (priv->count < priv->len) 575 priv->data[priv->count++] = ioread8(SMBBLKDAT(priv)); 576 else 577 pci_dbg(priv->pci_dev, "Discarding extra byte on block read\n"); 578 579 /* Set LAST_BYTE for last byte of read transaction */ 580 if (priv->count == priv->len - 1) 581 iowrite8(priv->cmd | SMBHSTCNT_LAST_BYTE, 582 SMBHSTCNT(priv)); 583 } else if (priv->count < priv->len - 1) { 584 /* Write next byte, except for IRQ after last byte */ 585 iowrite8(priv->data[++priv->count], SMBBLKDAT(priv)); 586 } 587 } 588 589 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv) 590 { 591 unsigned short addr; 592 593 addr = ioread8(SMBNTFDADD(priv)) >> 1; 594 595 /* 596 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba) 597 * always returns 0. Our current implementation doesn't provide 598 * data, so we just ignore it. 599 */ 600 i2c_handle_smbus_host_notify(&priv->adapter, addr); 601 602 /* clear Host Notify bit and return */ 603 iowrite8(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 604 return IRQ_HANDLED; 605 } 606 607 /* 608 * There are three kinds of interrupts: 609 * 610 * 1) i801 signals transaction completion with one of these interrupts: 611 * INTR - Success 612 * DEV_ERR - Invalid command, NAK or communication timeout 613 * BUS_ERR - SMI# transaction collision 614 * FAILED - transaction was canceled due to a KILL request 615 * When any of these occur, update ->status and signal completion. 616 * 617 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt 618 * occurs for each byte of a byte-by-byte to prepare the next byte. 619 * 620 * 3) Host Notify interrupts 621 */ 622 static irqreturn_t i801_isr(int irq, void *dev_id) 623 { 624 struct i801_priv *priv = dev_id; 625 u16 pcists; 626 u8 status; 627 628 /* Confirm this is our interrupt */ 629 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists); 630 if (!(pcists & PCI_STATUS_INTERRUPT)) 631 return IRQ_NONE; 632 633 if (priv->features & FEATURE_HOST_NOTIFY) { 634 status = ioread8(SMBSLVSTS(priv)); 635 if (status & SMBSLVSTS_HST_NTFY_STS) 636 return i801_host_notify_isr(priv); 637 } 638 639 status = ioread8(SMBHSTSTS(priv)); 640 if ((status & (SMBHSTSTS_BYTE_DONE | STATUS_ERROR_FLAGS)) == SMBHSTSTS_BYTE_DONE) 641 i801_isr_byte_done(priv); 642 643 /* 644 * Clear IRQ sources: SMB_ALERT status is set after signal assertion 645 * independently of the interrupt generation being blocked or not 646 * so clear it always when the status is set. 647 */ 648 status &= STATUS_FLAGS | SMBHSTSTS_SMBALERT_STS; 649 iowrite8(status, SMBHSTSTS(priv)); 650 651 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR; 652 if (status) { 653 priv->status = status & STATUS_ERROR_FLAGS; 654 complete(&priv->done); 655 } 656 657 return IRQ_HANDLED; 658 } 659 660 /* 661 * For "byte-by-byte" block transactions: 662 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 663 * I2C read uses cmd=I801_I2C_BLOCK_DATA 664 */ 665 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 666 union i2c_smbus_data *data, 667 char read_write, int command) 668 { 669 int i, len; 670 int smbcmd; 671 int status; 672 unsigned long result; 673 const struct i2c_adapter *adap = &priv->adapter; 674 675 if (command == I2C_SMBUS_BLOCK_PROC_CALL) 676 return -EOPNOTSUPP; 677 678 len = data->block[0]; 679 680 if (read_write == I2C_SMBUS_WRITE) { 681 iowrite8(len, SMBHSTDAT0(priv)); 682 iowrite8(data->block[1], SMBBLKDAT(priv)); 683 } 684 685 if (command == I2C_SMBUS_I2C_BLOCK_DATA && 686 read_write == I2C_SMBUS_READ) 687 smbcmd = I801_I2C_BLOCK_DATA; 688 else 689 smbcmd = I801_BLOCK_DATA; 690 691 if (priv->features & FEATURE_IRQ) { 692 priv->is_read = (read_write == I2C_SMBUS_READ); 693 if (len == 1 && priv->is_read) 694 smbcmd |= SMBHSTCNT_LAST_BYTE; 695 priv->cmd = smbcmd | SMBHSTCNT_INTREN; 696 priv->len = len; 697 priv->count = 0; 698 priv->data = &data->block[1]; 699 700 reinit_completion(&priv->done); 701 iowrite8(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 702 result = wait_for_completion_timeout(&priv->done, adap->timeout); 703 return result ? priv->status : -ETIMEDOUT; 704 } 705 706 if (len == 1 && read_write == I2C_SMBUS_READ) 707 smbcmd |= SMBHSTCNT_LAST_BYTE; 708 iowrite8(smbcmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 709 710 for (i = 1; i <= len; i++) { 711 status = i801_wait_byte_done(priv); 712 if (status) 713 return status; 714 715 /* 716 * At transfer start i801_smbus_block_transaction() marks 717 * the block length as invalid. Check for this sentinel value 718 * and read the block length from SMBHSTDAT0. 719 */ 720 if (len == SMBUS_LEN_SENTINEL) { 721 len = i801_get_block_len(priv); 722 if (len < 0) { 723 /* Recover */ 724 while (ioread8(SMBHSTSTS(priv)) & 725 SMBHSTSTS_HOST_BUSY) 726 iowrite8(SMBHSTSTS_BYTE_DONE, 727 SMBHSTSTS(priv)); 728 iowrite8(SMBHSTSTS_INTR, SMBHSTSTS(priv)); 729 return -EPROTO; 730 } 731 data->block[0] = len; 732 } 733 734 if (read_write == I2C_SMBUS_READ) { 735 data->block[i] = ioread8(SMBBLKDAT(priv)); 736 if (i == len - 1) 737 iowrite8(smbcmd | SMBHSTCNT_LAST_BYTE, SMBHSTCNT(priv)); 738 } 739 740 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 741 iowrite8(data->block[i+1], SMBBLKDAT(priv)); 742 743 /* signals SMBBLKDAT ready */ 744 iowrite8(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 745 } 746 747 return i801_wait_intr(priv); 748 } 749 750 static void i801_set_hstadd(struct i801_priv *priv, u8 addr, char read_write) 751 { 752 iowrite8((addr << 1) | (read_write & 0x01), SMBHSTADD(priv)); 753 } 754 755 /* Single value transaction function */ 756 static int i801_simple_transaction(struct i801_priv *priv, union i2c_smbus_data *data, 757 u8 addr, u8 hstcmd, char read_write, int command) 758 { 759 int xact, ret; 760 761 switch (command) { 762 case I2C_SMBUS_QUICK: 763 i801_set_hstadd(priv, addr, read_write); 764 xact = I801_QUICK; 765 break; 766 case I2C_SMBUS_BYTE: 767 i801_set_hstadd(priv, addr, read_write); 768 if (read_write == I2C_SMBUS_WRITE) 769 iowrite8(hstcmd, SMBHSTCMD(priv)); 770 xact = I801_BYTE; 771 break; 772 case I2C_SMBUS_BYTE_DATA: 773 i801_set_hstadd(priv, addr, read_write); 774 if (read_write == I2C_SMBUS_WRITE) 775 iowrite8(data->byte, SMBHSTDAT0(priv)); 776 iowrite8(hstcmd, SMBHSTCMD(priv)); 777 xact = I801_BYTE_DATA; 778 break; 779 case I2C_SMBUS_WORD_DATA: 780 i801_set_hstadd(priv, addr, read_write); 781 if (read_write == I2C_SMBUS_WRITE) { 782 iowrite8(data->word & 0xff, SMBHSTDAT0(priv)); 783 iowrite8((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 784 } 785 iowrite8(hstcmd, SMBHSTCMD(priv)); 786 xact = I801_WORD_DATA; 787 break; 788 case I2C_SMBUS_PROC_CALL: 789 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE); 790 iowrite8(data->word & 0xff, SMBHSTDAT0(priv)); 791 iowrite8((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 792 iowrite8(hstcmd, SMBHSTCMD(priv)); 793 read_write = I2C_SMBUS_READ; 794 xact = I801_PROC_CALL; 795 break; 796 default: 797 pci_err(priv->pci_dev, "Unsupported transaction %d\n", command); 798 return -EOPNOTSUPP; 799 } 800 801 ret = i801_transaction(priv, xact); 802 if (ret || read_write == I2C_SMBUS_WRITE) 803 return ret; 804 805 switch (command) { 806 case I2C_SMBUS_BYTE: 807 case I2C_SMBUS_BYTE_DATA: 808 data->byte = ioread8(SMBHSTDAT0(priv)); 809 break; 810 case I2C_SMBUS_WORD_DATA: 811 case I2C_SMBUS_PROC_CALL: 812 data->word = ioread8(SMBHSTDAT0(priv)) + 813 (ioread8(SMBHSTDAT1(priv)) << 8); 814 break; 815 } 816 817 return 0; 818 } 819 820 static int i801_smbus_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data, 821 u8 addr, u8 hstcmd, char read_write, int command) 822 { 823 if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA) 824 /* Mark block length as invalid */ 825 data->block[0] = SMBUS_LEN_SENTINEL; 826 else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX) 827 return -EPROTO; 828 829 if (command == I2C_SMBUS_BLOCK_PROC_CALL) 830 /* Needs to be flagged as write transaction */ 831 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE); 832 else 833 i801_set_hstadd(priv, addr, read_write); 834 iowrite8(hstcmd, SMBHSTCMD(priv)); 835 836 if (priv->features & FEATURE_BLOCK_BUFFER) 837 return i801_block_transaction_by_block(priv, data, read_write, command); 838 else 839 return i801_block_transaction_byte_by_byte(priv, data, read_write, command); 840 } 841 842 static int i801_i2c_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data, 843 u8 addr, u8 hstcmd, char read_write, int command) 844 { 845 int result; 846 u8 hostc; 847 848 if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX) 849 return -EPROTO; 850 /* 851 * NB: page 240 of ICH5 datasheet shows that the R/#W bit should be cleared here, 852 * even when reading. However if SPD Write Disable is set (Lynx Point and later), 853 * the read will fail if we don't set the R/#W bit. 854 */ 855 i801_set_hstadd(priv, addr, 856 priv->original_hstcfg & SMBHSTCFG_SPD_WD ? read_write : I2C_SMBUS_WRITE); 857 858 /* NB: page 240 of ICH5 datasheet shows that DATA1 is the cmd field when reading */ 859 if (read_write == I2C_SMBUS_READ) 860 iowrite8(hstcmd, SMBHSTDAT1(priv)); 861 else 862 iowrite8(hstcmd, SMBHSTCMD(priv)); 863 864 if (read_write == I2C_SMBUS_WRITE) { 865 /* set I2C_EN bit in configuration register */ 866 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); 867 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc | SMBHSTCFG_I2C_EN); 868 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { 869 pci_err(priv->pci_dev, "I2C block read is unsupported!\n"); 870 return -EOPNOTSUPP; 871 } 872 873 /* Block buffer isn't supported for I2C block transactions */ 874 result = i801_block_transaction_byte_by_byte(priv, data, read_write, command); 875 876 /* restore saved configuration register value */ 877 if (read_write == I2C_SMBUS_WRITE) 878 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); 879 880 return result; 881 } 882 883 /* Return negative errno on error. */ 884 static s32 i801_access(struct i2c_adapter *adap, u16 addr, 885 unsigned short flags, char read_write, u8 command, 886 int size, union i2c_smbus_data *data) 887 { 888 int hwpec, ret; 889 struct i801_priv *priv = i2c_get_adapdata(adap); 890 891 if (priv->acpi_reserved) 892 return -EBUSY; 893 894 pm_runtime_get_sync(&priv->pci_dev->dev); 895 896 ret = i801_check_pre(priv); 897 if (ret) 898 goto out; 899 900 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) 901 && size != I2C_SMBUS_QUICK 902 && size != I2C_SMBUS_I2C_BLOCK_DATA; 903 904 if (hwpec) /* enable/disable hardware PEC */ 905 iowrite8(ioread8(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); 906 else 907 iowrite8(ioread8(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), 908 SMBAUXCTL(priv)); 909 910 if (size == I2C_SMBUS_BLOCK_DATA || size == I2C_SMBUS_BLOCK_PROC_CALL) 911 ret = i801_smbus_block_transaction(priv, data, addr, command, read_write, size); 912 else if (size == I2C_SMBUS_I2C_BLOCK_DATA) 913 ret = i801_i2c_block_transaction(priv, data, addr, command, read_write, size); 914 else 915 ret = i801_simple_transaction(priv, data, addr, command, read_write, size); 916 917 ret = i801_check_post(priv, ret); 918 919 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 920 * time, so we forcibly disable it after every transaction. 921 */ 922 if (hwpec) 923 iowrite8(ioread8(SMBAUXCTL(priv)) & ~SMBAUXCTL_CRC, SMBAUXCTL(priv)); 924 out: 925 /* 926 * Unlock the SMBus device for use by BIOS/ACPI, 927 * and clear status flags if not done already. 928 */ 929 iowrite8(SMBHSTSTS_INUSE_STS | STATUS_FLAGS, SMBHSTSTS(priv)); 930 931 pm_runtime_mark_last_busy(&priv->pci_dev->dev); 932 pm_runtime_put_autosuspend(&priv->pci_dev->dev); 933 return ret; 934 } 935 936 937 static u32 i801_func(struct i2c_adapter *adapter) 938 { 939 struct i801_priv *priv = i2c_get_adapdata(adapter); 940 941 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 942 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 943 I2C_FUNC_SMBUS_PROC_CALL | 944 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | 945 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | 946 ((priv->features & FEATURE_BLOCK_PROC) ? 947 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) | 948 ((priv->features & FEATURE_I2C_BLOCK_READ) ? 949 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) | 950 ((priv->features & FEATURE_HOST_NOTIFY) ? 951 I2C_FUNC_SMBUS_HOST_NOTIFY : 0); 952 } 953 954 static void i801_enable_host_notify(struct i2c_adapter *adapter) 955 { 956 struct i801_priv *priv = i2c_get_adapdata(adapter); 957 958 if (!(priv->features & FEATURE_HOST_NOTIFY)) 959 return; 960 961 /* 962 * Enable host notify interrupt and block the generation of interrupt 963 * from the SMB_ALERT signal because the driver does not support 964 * SMBus Alert. 965 */ 966 iowrite8(SMBSLVCMD_HST_NTFY_INTREN | SMBSLVCMD_SMBALERT_DISABLE | 967 priv->original_slvcmd, SMBSLVCMD(priv)); 968 969 /* clear Host Notify bit to allow a new notification */ 970 iowrite8(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 971 } 972 973 static void i801_disable_host_notify(struct i801_priv *priv) 974 { 975 if (!(priv->features & FEATURE_HOST_NOTIFY)) 976 return; 977 978 iowrite8(priv->original_slvcmd, SMBSLVCMD(priv)); 979 } 980 981 static const struct i2c_algorithm smbus_algorithm = { 982 .smbus_xfer = i801_access, 983 .functionality = i801_func, 984 }; 985 986 #define FEATURES_ICH4 (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER | \ 987 FEATURE_HOST_NOTIFY) 988 #define FEATURES_ICH5 (FEATURES_ICH4 | FEATURE_BLOCK_PROC | \ 989 FEATURE_I2C_BLOCK_READ | FEATURE_IRQ) 990 991 static const struct pci_device_id i801_ids[] = { 992 { PCI_DEVICE_DATA(INTEL, 82801AA_3, 0) }, 993 { PCI_DEVICE_DATA(INTEL, 82801AB_3, 0) }, 994 { PCI_DEVICE_DATA(INTEL, 82801BA_2, 0) }, 995 { PCI_DEVICE_DATA(INTEL, 82801CA_3, FEATURE_HOST_NOTIFY) }, 996 { PCI_DEVICE_DATA(INTEL, 82801DB_3, FEATURES_ICH4) }, 997 { PCI_DEVICE_DATA(INTEL, 82801EB_3, FEATURES_ICH5) }, 998 { PCI_DEVICE_DATA(INTEL, ESB_4, FEATURES_ICH5) }, 999 { PCI_DEVICE_DATA(INTEL, ICH6_16, FEATURES_ICH5) }, 1000 { PCI_DEVICE_DATA(INTEL, ICH7_17, FEATURES_ICH5) }, 1001 { PCI_DEVICE_DATA(INTEL, ESB2_17, FEATURES_ICH5) }, 1002 { PCI_DEVICE_DATA(INTEL, ICH8_5, FEATURES_ICH5) }, 1003 { PCI_DEVICE_DATA(INTEL, ICH9_6, FEATURES_ICH5) }, 1004 { PCI_DEVICE_DATA(INTEL, EP80579_1, FEATURES_ICH5) }, 1005 { PCI_DEVICE_DATA(INTEL, ICH10_4, FEATURES_ICH5) }, 1006 { PCI_DEVICE_DATA(INTEL, ICH10_5, FEATURES_ICH5) }, 1007 { PCI_DEVICE_DATA(INTEL, 5_3400_SERIES_SMBUS, FEATURES_ICH5) }, 1008 { PCI_DEVICE_DATA(INTEL, COUGARPOINT_SMBUS, FEATURES_ICH5) }, 1009 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS, FEATURES_ICH5) }, 1010 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF0, FEATURES_ICH5 | FEATURE_IDF) }, 1011 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF1, FEATURES_ICH5 | FEATURE_IDF) }, 1012 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF2, FEATURES_ICH5 | FEATURE_IDF) }, 1013 { PCI_DEVICE_DATA(INTEL, DH89XXCC_SMBUS, FEATURES_ICH5) }, 1014 { PCI_DEVICE_DATA(INTEL, PANTHERPOINT_SMBUS, FEATURES_ICH5) }, 1015 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_SMBUS, FEATURES_ICH5) }, 1016 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_LP_SMBUS, FEATURES_ICH5) }, 1017 { PCI_DEVICE_DATA(INTEL, AVOTON_SMBUS, FEATURES_ICH5) }, 1018 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS, FEATURES_ICH5) }, 1019 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS0, FEATURES_ICH5 | FEATURE_IDF) }, 1020 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS1, FEATURES_ICH5 | FEATURE_IDF) }, 1021 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS2, FEATURES_ICH5 | FEATURE_IDF) }, 1022 { PCI_DEVICE_DATA(INTEL, COLETOCREEK_SMBUS, FEATURES_ICH5) }, 1023 { PCI_DEVICE_DATA(INTEL, GEMINILAKE_SMBUS, FEATURES_ICH5) }, 1024 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_SMBUS, FEATURES_ICH5) }, 1025 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_LP_SMBUS, FEATURES_ICH5) }, 1026 { PCI_DEVICE_DATA(INTEL, BAYTRAIL_SMBUS, FEATURES_ICH5) }, 1027 { PCI_DEVICE_DATA(INTEL, BRASWELL_SMBUS, FEATURES_ICH5) }, 1028 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1029 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1030 { PCI_DEVICE_DATA(INTEL, CDF_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1031 { PCI_DEVICE_DATA(INTEL, DNV_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1032 { PCI_DEVICE_DATA(INTEL, EBG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1033 { PCI_DEVICE_DATA(INTEL, BROXTON_SMBUS, FEATURES_ICH5) }, 1034 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1035 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SSKU_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1036 { PCI_DEVICE_DATA(INTEL, KABYLAKE_PCH_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1037 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1038 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1039 { PCI_DEVICE_DATA(INTEL, ICELAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1040 { PCI_DEVICE_DATA(INTEL, ICELAKE_N_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1041 { PCI_DEVICE_DATA(INTEL, COMETLAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1042 { PCI_DEVICE_DATA(INTEL, COMETLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1043 { PCI_DEVICE_DATA(INTEL, COMETLAKE_V_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1044 { PCI_DEVICE_DATA(INTEL, ELKHART_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1045 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1046 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1047 { PCI_DEVICE_DATA(INTEL, JASPER_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1048 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1049 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1050 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1051 { PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1052 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1053 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_SOC_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1054 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_PCH_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1055 { PCI_DEVICE_DATA(INTEL, BIRCH_STREAM_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1056 { PCI_DEVICE_DATA(INTEL, ARROW_LAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1057 { PCI_DEVICE_DATA(INTEL, PANTHER_LAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1058 { PCI_DEVICE_DATA(INTEL, PANTHER_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1059 { 0, } 1060 }; 1061 1062 MODULE_DEVICE_TABLE(pci, i801_ids); 1063 1064 #if defined CONFIG_X86 && defined CONFIG_DMI 1065 static unsigned char apanel_addr __ro_after_init; 1066 1067 /* Scan the system ROM for the signature "FJKEYINF" */ 1068 static __init const void __iomem *bios_signature(const void __iomem *bios) 1069 { 1070 ssize_t offset; 1071 const unsigned char signature[] = "FJKEYINF"; 1072 1073 for (offset = 0; offset < 0x10000; offset += 0x10) { 1074 if (check_signature(bios + offset, signature, 1075 sizeof(signature)-1)) 1076 return bios + offset; 1077 } 1078 return NULL; 1079 } 1080 1081 static void __init input_apanel_init(void) 1082 { 1083 void __iomem *bios; 1084 const void __iomem *p; 1085 1086 bios = ioremap(0xF0000, 0x10000); /* Can't fail */ 1087 p = bios_signature(bios); 1088 if (p) { 1089 /* just use the first address */ 1090 apanel_addr = readb(p + 8 + 3) >> 1; 1091 } 1092 iounmap(bios); 1093 } 1094 1095 struct dmi_onboard_device_info { 1096 const char *name; 1097 u8 type; 1098 unsigned short i2c_addr; 1099 const char *i2c_type; 1100 }; 1101 1102 static const struct dmi_onboard_device_info dmi_devices[] = { 1103 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, 1104 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, 1105 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, 1106 }; 1107 1108 static void dmi_check_onboard_device(u8 type, const char *name, 1109 struct i2c_adapter *adap) 1110 { 1111 int i; 1112 struct i2c_board_info info; 1113 1114 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { 1115 /* & ~0x80, ignore enabled/disabled bit */ 1116 if ((type & ~0x80) != dmi_devices[i].type) 1117 continue; 1118 if (strcasecmp(name, dmi_devices[i].name)) 1119 continue; 1120 1121 memset(&info, 0, sizeof(struct i2c_board_info)); 1122 info.addr = dmi_devices[i].i2c_addr; 1123 strscpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); 1124 i2c_new_client_device(adap, &info); 1125 break; 1126 } 1127 } 1128 1129 /* We use our own function to check for onboard devices instead of 1130 dmi_find_device() as some buggy BIOS's have the devices we are interested 1131 in marked as disabled */ 1132 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) 1133 { 1134 int i, count; 1135 1136 if (dm->type != DMI_ENTRY_ONBOARD_DEVICE) 1137 return; 1138 1139 count = (dm->length - sizeof(struct dmi_header)) / 2; 1140 for (i = 0; i < count; i++) { 1141 const u8 *d = (char *)(dm + 1) + (i * 2); 1142 const char *name = ((char *) dm) + dm->length; 1143 u8 type = d[0]; 1144 u8 s = d[1]; 1145 1146 if (!s) 1147 continue; 1148 s--; 1149 while (s > 0 && name[0]) { 1150 name += strlen(name) + 1; 1151 s--; 1152 } 1153 if (name[0] == 0) /* Bogus string reference */ 1154 continue; 1155 1156 dmi_check_onboard_device(type, name, adap); 1157 } 1158 } 1159 1160 /* Register optional targets */ 1161 static void i801_probe_optional_targets(struct i801_priv *priv) 1162 { 1163 /* Only register targets on main SMBus channel */ 1164 if (priv->features & FEATURE_IDF) 1165 return; 1166 1167 if (apanel_addr) { 1168 struct i2c_board_info info = { 1169 .addr = apanel_addr, 1170 .type = "fujitsu_apanel", 1171 }; 1172 1173 i2c_new_client_device(&priv->adapter, &info); 1174 } 1175 1176 if (dmi_name_in_vendors("FUJITSU")) 1177 dmi_walk(dmi_check_onboard_devices, &priv->adapter); 1178 1179 /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */ 1180 #ifdef CONFIG_I2C_I801_MUX 1181 if (!priv->mux_pdev) 1182 #endif 1183 i2c_register_spd_write_enable(&priv->adapter); 1184 } 1185 #else 1186 static void __init input_apanel_init(void) {} 1187 static void i801_probe_optional_targets(struct i801_priv *priv) {} 1188 #endif /* CONFIG_X86 && CONFIG_DMI */ 1189 1190 #ifdef CONFIG_I2C_I801_MUX 1191 static struct i801_mux_config i801_mux_config_asus_z8_d12 = { 1192 .gpio_chip = "gpio_ich", 1193 .values = { 0x02, 0x03 }, 1194 .n_values = 2, 1195 .gpios = { 52, 53 }, 1196 .n_gpios = 2, 1197 }; 1198 1199 static struct i801_mux_config i801_mux_config_asus_z8_d18 = { 1200 .gpio_chip = "gpio_ich", 1201 .values = { 0x02, 0x03, 0x01 }, 1202 .n_values = 3, 1203 .gpios = { 52, 53 }, 1204 .n_gpios = 2, 1205 }; 1206 1207 static const struct dmi_system_id mux_dmi_table[] = { 1208 { 1209 .matches = { 1210 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1211 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), 1212 }, 1213 .driver_data = &i801_mux_config_asus_z8_d12, 1214 }, 1215 { 1216 .matches = { 1217 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1218 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), 1219 }, 1220 .driver_data = &i801_mux_config_asus_z8_d12, 1221 }, 1222 { 1223 .matches = { 1224 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1225 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), 1226 }, 1227 .driver_data = &i801_mux_config_asus_z8_d12, 1228 }, 1229 { 1230 .matches = { 1231 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1232 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), 1233 }, 1234 .driver_data = &i801_mux_config_asus_z8_d12, 1235 }, 1236 { 1237 .matches = { 1238 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1239 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), 1240 }, 1241 .driver_data = &i801_mux_config_asus_z8_d12, 1242 }, 1243 { 1244 .matches = { 1245 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1246 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), 1247 }, 1248 .driver_data = &i801_mux_config_asus_z8_d12, 1249 }, 1250 { 1251 .matches = { 1252 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1253 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), 1254 }, 1255 .driver_data = &i801_mux_config_asus_z8_d18, 1256 }, 1257 { 1258 .matches = { 1259 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1260 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), 1261 }, 1262 .driver_data = &i801_mux_config_asus_z8_d18, 1263 }, 1264 { 1265 .matches = { 1266 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1267 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), 1268 }, 1269 .driver_data = &i801_mux_config_asus_z8_d12, 1270 }, 1271 { } 1272 }; 1273 1274 static int i801_notifier_call(struct notifier_block *nb, unsigned long action, 1275 void *data) 1276 { 1277 struct i801_priv *priv = container_of(nb, struct i801_priv, mux_notifier_block); 1278 struct device *dev = data; 1279 1280 if (action != BUS_NOTIFY_ADD_DEVICE || 1281 dev->type != &i2c_adapter_type || 1282 i2c_root_adapter(dev) != &priv->adapter) 1283 return NOTIFY_DONE; 1284 1285 /* Call i2c_register_spd for muxed child segments */ 1286 i2c_register_spd_write_enable(to_i2c_adapter(dev)); 1287 1288 return NOTIFY_OK; 1289 } 1290 1291 /* Setup multiplexing if needed */ 1292 static void i801_add_mux(struct i801_priv *priv) 1293 { 1294 struct device *dev = &priv->adapter.dev; 1295 const struct i801_mux_config *mux_config; 1296 struct i2c_mux_gpio_platform_data gpio_data; 1297 struct gpiod_lookup_table *lookup; 1298 const struct dmi_system_id *id; 1299 int i; 1300 1301 id = dmi_first_match(mux_dmi_table); 1302 if (!id) 1303 return; 1304 1305 mux_config = id->driver_data; 1306 1307 /* Prepare the platform data */ 1308 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); 1309 gpio_data.parent = priv->adapter.nr; 1310 gpio_data.values = mux_config->values; 1311 gpio_data.n_values = mux_config->n_values; 1312 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; 1313 1314 /* Register GPIO descriptor lookup table */ 1315 lookup = devm_kzalloc(dev, 1316 struct_size(lookup, table, mux_config->n_gpios + 1), 1317 GFP_KERNEL); 1318 if (!lookup) 1319 return; 1320 lookup->dev_id = "i2c-mux-gpio"; 1321 for (i = 0; i < mux_config->n_gpios; i++) 1322 lookup->table[i] = GPIO_LOOKUP(mux_config->gpio_chip, 1323 mux_config->gpios[i], "mux", 0); 1324 gpiod_add_lookup_table(lookup); 1325 1326 priv->mux_notifier_block.notifier_call = i801_notifier_call; 1327 if (bus_register_notifier(&i2c_bus_type, &priv->mux_notifier_block)) 1328 return; 1329 /* 1330 * Register the mux device, we use PLATFORM_DEVID_NONE here 1331 * because since we are referring to the GPIO chip by name we are 1332 * anyways in deep trouble if there is more than one of these 1333 * devices, and there should likely only be one platform controller 1334 * hub. 1335 */ 1336 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", 1337 PLATFORM_DEVID_NONE, &gpio_data, 1338 sizeof(struct i2c_mux_gpio_platform_data)); 1339 if (IS_ERR(priv->mux_pdev)) { 1340 gpiod_remove_lookup_table(lookup); 1341 devm_kfree(dev, lookup); 1342 dev_err(dev, "Failed to register i2c-mux-gpio device\n"); 1343 } else { 1344 priv->lookup = lookup; 1345 } 1346 } 1347 1348 static void i801_del_mux(struct i801_priv *priv) 1349 { 1350 bus_unregister_notifier(&i2c_bus_type, &priv->mux_notifier_block); 1351 platform_device_unregister(priv->mux_pdev); 1352 gpiod_remove_lookup_table(priv->lookup); 1353 } 1354 #else 1355 static inline void i801_add_mux(struct i801_priv *priv) { } 1356 static inline void i801_del_mux(struct i801_priv *priv) { } 1357 #endif 1358 1359 static struct platform_device * 1360 i801_add_tco_spt(struct pci_dev *pci_dev, struct resource *tco_res) 1361 { 1362 static const struct itco_wdt_platform_data pldata = { 1363 .name = "Intel PCH", 1364 .version = 4, 1365 }; 1366 struct resource *res; 1367 int ret; 1368 1369 /* 1370 * We must access the NO_REBOOT bit over the Primary to Sideband 1371 * (P2SB) bridge. 1372 */ 1373 1374 res = &tco_res[1]; 1375 ret = p2sb_bar(pci_dev->bus, 0, res); 1376 if (ret) 1377 return ERR_PTR(ret); 1378 1379 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS) 1380 res->start += SBREG_SMBCTRL_DNV; 1381 else 1382 res->start += SBREG_SMBCTRL; 1383 1384 res->end = res->start + 3; 1385 1386 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1387 tco_res, 2, &pldata, sizeof(pldata)); 1388 } 1389 1390 static struct platform_device * 1391 i801_add_tco_cnl(struct pci_dev *pci_dev, struct resource *tco_res) 1392 { 1393 static const struct itco_wdt_platform_data pldata = { 1394 .name = "Intel PCH", 1395 .version = 6, 1396 }; 1397 1398 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1399 tco_res, 1, &pldata, sizeof(pldata)); 1400 } 1401 1402 static void i801_add_tco(struct i801_priv *priv) 1403 { 1404 struct pci_dev *pci_dev = priv->pci_dev; 1405 struct resource tco_res[2], *res; 1406 u32 tco_base, tco_ctl; 1407 1408 /* If we have ACPI based watchdog use that instead */ 1409 if (acpi_has_watchdog()) 1410 return; 1411 1412 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL))) 1413 return; 1414 1415 pci_read_config_dword(pci_dev, TCOBASE, &tco_base); 1416 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl); 1417 if (!(tco_ctl & TCOCTL_EN)) 1418 return; 1419 1420 memset(tco_res, 0, sizeof(tco_res)); 1421 /* 1422 * Always populate the main iTCO IO resource here. The second entry 1423 * for NO_REBOOT MMIO is filled by the SPT specific function. 1424 */ 1425 res = &tco_res[0]; 1426 res->start = tco_base & ~1; 1427 res->end = res->start + 32 - 1; 1428 res->flags = IORESOURCE_IO; 1429 1430 if (priv->features & FEATURE_TCO_CNL) 1431 priv->tco_pdev = i801_add_tco_cnl(pci_dev, tco_res); 1432 else 1433 priv->tco_pdev = i801_add_tco_spt(pci_dev, tco_res); 1434 1435 if (IS_ERR(priv->tco_pdev)) 1436 pci_warn(pci_dev, "failed to create iTCO device\n"); 1437 } 1438 1439 #ifdef CONFIG_ACPI 1440 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv, 1441 acpi_physical_address address) 1442 { 1443 return address >= pci_resource_start(priv->pci_dev, SMBBAR) && 1444 address <= pci_resource_end(priv->pci_dev, SMBBAR); 1445 } 1446 1447 static acpi_status 1448 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits, 1449 u64 *value, void *handler_context, void *region_context) 1450 { 1451 struct i801_priv *priv = handler_context; 1452 struct pci_dev *pdev = priv->pci_dev; 1453 acpi_status status; 1454 1455 /* 1456 * Once BIOS AML code touches the OpRegion we warn and inhibit any 1457 * further access from the driver itself. This device is now owned 1458 * by the system firmware. 1459 */ 1460 i2c_lock_bus(&priv->adapter, I2C_LOCK_SEGMENT); 1461 1462 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) { 1463 priv->acpi_reserved = true; 1464 1465 pci_warn(pdev, "BIOS is accessing SMBus registers\n"); 1466 pci_warn(pdev, "Driver SMBus register access inhibited\n"); 1467 1468 /* 1469 * BIOS is accessing the host controller so prevent it from 1470 * suspending automatically from now on. 1471 */ 1472 pm_runtime_get_sync(&pdev->dev); 1473 } 1474 1475 if ((function & ACPI_IO_MASK) == ACPI_READ) 1476 status = acpi_os_read_port(address, (u32 *)value, bits); 1477 else 1478 status = acpi_os_write_port(address, (u32)*value, bits); 1479 1480 i2c_unlock_bus(&priv->adapter, I2C_LOCK_SEGMENT); 1481 1482 return status; 1483 } 1484 1485 static int i801_acpi_probe(struct i801_priv *priv) 1486 { 1487 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev); 1488 acpi_status status; 1489 1490 status = acpi_install_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, 1491 i801_acpi_io_handler, NULL, priv); 1492 if (ACPI_SUCCESS(status)) 1493 return 0; 1494 1495 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]); 1496 } 1497 1498 static void i801_acpi_remove(struct i801_priv *priv) 1499 { 1500 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev); 1501 1502 acpi_remove_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler); 1503 } 1504 #else 1505 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; } 1506 static inline void i801_acpi_remove(struct i801_priv *priv) { } 1507 #endif 1508 1509 static void i801_setup_hstcfg(struct i801_priv *priv) 1510 { 1511 unsigned char hstcfg = priv->original_hstcfg; 1512 1513 hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 1514 hstcfg |= SMBHSTCFG_HST_EN; 1515 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg); 1516 } 1517 1518 static void i801_restore_regs(struct i801_priv *priv) 1519 { 1520 iowrite8(priv->original_hstcnt, SMBHSTCNT(priv)); 1521 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg); 1522 } 1523 1524 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 1525 { 1526 int err, i, bar = SMBBAR; 1527 struct i801_priv *priv; 1528 1529 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); 1530 if (!priv) 1531 return -ENOMEM; 1532 1533 i2c_set_adapdata(&priv->adapter, priv); 1534 priv->adapter.owner = THIS_MODULE; 1535 priv->adapter.class = I2C_CLASS_HWMON; 1536 priv->adapter.algo = &smbus_algorithm; 1537 priv->adapter.dev.parent = &dev->dev; 1538 acpi_use_parent_companion(&priv->adapter.dev); 1539 priv->adapter.retries = 3; 1540 1541 priv->pci_dev = dev; 1542 priv->features = id->driver_data; 1543 1544 /* Disable features on user request */ 1545 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { 1546 if (priv->features & disable_features & (1 << i)) 1547 pci_notice(dev, "%s disabled by user\n", i801_feature_names[i]); 1548 } 1549 priv->features &= ~disable_features; 1550 1551 /* The block process call uses block buffer mode */ 1552 if (!(priv->features & FEATURE_BLOCK_BUFFER)) 1553 priv->features &= ~FEATURE_BLOCK_PROC; 1554 1555 /* 1556 * Do not call pcim_enable_device(), because the device has to remain 1557 * enabled on driver detach. See i801_remove() for the reasoning. 1558 */ 1559 err = pci_enable_device(dev); 1560 if (err) { 1561 pci_err(dev, "Failed to enable SMBus PCI device (%d)\n", err); 1562 return err; 1563 } 1564 1565 /* Determine the address of the SMBus area */ 1566 if (!pci_resource_start(dev, SMBBAR)) { 1567 pci_err(dev, "SMBus base address uninitialized, upgrade BIOS\n"); 1568 return -ENODEV; 1569 } 1570 1571 if (i801_acpi_probe(priv)) 1572 return -ENODEV; 1573 1574 if (pci_resource_flags(dev, SMBBAR_MMIO) & IORESOURCE_MEM) 1575 bar = SMBBAR_MMIO; 1576 1577 priv->smba = pcim_iomap_region(dev, bar, DRV_NAME); 1578 if (IS_ERR(priv->smba)) { 1579 pci_err(dev, "Failed to request SMBus region %pr\n", 1580 pci_resource_n(dev, bar)); 1581 i801_acpi_remove(priv); 1582 return PTR_ERR(priv->smba); 1583 } 1584 1585 pci_read_config_byte(dev, SMBHSTCFG, &priv->original_hstcfg); 1586 i801_setup_hstcfg(priv); 1587 if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN)) 1588 pci_info(dev, "Enabling SMBus device\n"); 1589 1590 if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) { 1591 pci_dbg(dev, "SMBus using interrupt SMI#\n"); 1592 /* Disable SMBus interrupt feature if SMBus using SMI# */ 1593 priv->features &= ~FEATURE_IRQ; 1594 } 1595 if (priv->original_hstcfg & SMBHSTCFG_SPD_WD) 1596 pci_info(dev, "SPD Write Disable is set\n"); 1597 1598 /* Clear special mode bits */ 1599 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) 1600 iowrite8(ioread8(SMBAUXCTL(priv)) & 1601 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 1602 1603 /* Default timeout in interrupt mode: 200 ms */ 1604 priv->adapter.timeout = HZ / 5; 1605 1606 if (dev->irq == IRQ_NOTCONNECTED) 1607 priv->features &= ~FEATURE_IRQ; 1608 1609 if (priv->features & FEATURE_IRQ) { 1610 u16 pcists; 1611 1612 /* Complain if an interrupt is already pending */ 1613 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists); 1614 if (pcists & PCI_STATUS_INTERRUPT) 1615 pci_warn(dev, "An interrupt is pending!\n"); 1616 } 1617 1618 if (priv->features & FEATURE_IRQ) { 1619 init_completion(&priv->done); 1620 1621 err = devm_request_irq(&dev->dev, dev->irq, i801_isr, 1622 IRQF_SHARED, DRV_NAME, priv); 1623 if (err) { 1624 pci_err(dev, "Failed to allocate irq %d: %d\n", dev->irq, err); 1625 priv->features &= ~FEATURE_IRQ; 1626 } 1627 } 1628 pci_info(dev, "SMBus using %s\n", 1629 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); 1630 1631 /* Host notification uses an interrupt */ 1632 if (!(priv->features & FEATURE_IRQ)) 1633 priv->features &= ~FEATURE_HOST_NOTIFY; 1634 1635 /* Remember original Interrupt and Host Notify settings */ 1636 priv->original_hstcnt = ioread8(SMBHSTCNT(priv)) & ~SMBHSTCNT_KILL; 1637 if (priv->features & FEATURE_HOST_NOTIFY) 1638 priv->original_slvcmd = ioread8(SMBSLVCMD(priv)); 1639 1640 i801_add_tco(priv); 1641 1642 /* 1643 * adapter.name is used by platform code to find the main I801 adapter 1644 * to instantiante i2c_clients, do not change. 1645 */ 1646 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 1647 "SMBus %s adapter at %s", 1648 (priv->features & FEATURE_IDF) ? "I801 IDF" : "I801", 1649 pci_name(dev)); 1650 1651 err = i2c_add_adapter(&priv->adapter); 1652 if (err) { 1653 platform_device_unregister(priv->tco_pdev); 1654 i801_acpi_remove(priv); 1655 i801_restore_regs(priv); 1656 return err; 1657 } 1658 1659 i801_enable_host_notify(&priv->adapter); 1660 1661 /* We ignore errors - multiplexing is optional */ 1662 i801_add_mux(priv); 1663 i801_probe_optional_targets(priv); 1664 1665 pci_set_drvdata(dev, priv); 1666 1667 dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 1668 pm_runtime_set_autosuspend_delay(&dev->dev, 1000); 1669 pm_runtime_use_autosuspend(&dev->dev); 1670 pm_runtime_put_autosuspend(&dev->dev); 1671 pm_runtime_allow(&dev->dev); 1672 1673 return 0; 1674 } 1675 1676 static void i801_remove(struct pci_dev *dev) 1677 { 1678 struct i801_priv *priv = pci_get_drvdata(dev); 1679 1680 i801_disable_host_notify(priv); 1681 i801_del_mux(priv); 1682 i2c_del_adapter(&priv->adapter); 1683 i801_acpi_remove(priv); 1684 1685 platform_device_unregister(priv->tco_pdev); 1686 1687 /* if acpi_reserved is set then usage_count is incremented already */ 1688 if (!priv->acpi_reserved) 1689 pm_runtime_get_noresume(&dev->dev); 1690 1691 i801_restore_regs(priv); 1692 1693 /* 1694 * do not call pci_disable_device(dev) since it can cause hard hangs on 1695 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 1696 */ 1697 } 1698 1699 static void i801_shutdown(struct pci_dev *dev) 1700 { 1701 struct i801_priv *priv = pci_get_drvdata(dev); 1702 1703 i801_disable_host_notify(priv); 1704 /* Restore config registers to avoid hard hang on some systems */ 1705 i801_restore_regs(priv); 1706 } 1707 1708 static int i801_suspend(struct device *dev) 1709 { 1710 struct i801_priv *priv = dev_get_drvdata(dev); 1711 1712 i2c_mark_adapter_suspended(&priv->adapter); 1713 i801_restore_regs(priv); 1714 1715 return 0; 1716 } 1717 1718 static int i801_resume(struct device *dev) 1719 { 1720 struct i801_priv *priv = dev_get_drvdata(dev); 1721 1722 i801_setup_hstcfg(priv); 1723 i801_enable_host_notify(&priv->adapter); 1724 i2c_mark_adapter_resumed(&priv->adapter); 1725 1726 return 0; 1727 } 1728 1729 static DEFINE_SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume); 1730 1731 static struct pci_driver i801_driver = { 1732 .name = DRV_NAME, 1733 .id_table = i801_ids, 1734 .probe = i801_probe, 1735 .remove = i801_remove, 1736 .shutdown = i801_shutdown, 1737 .driver = { 1738 .pm = pm_sleep_ptr(&i801_pm_ops), 1739 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1740 }, 1741 }; 1742 1743 static int __init i2c_i801_init(struct pci_driver *drv) 1744 { 1745 if (dmi_name_in_vendors("FUJITSU")) 1746 input_apanel_init(); 1747 return pci_register_driver(drv); 1748 } 1749 1750 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>"); 1751 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>"); 1752 MODULE_DESCRIPTION("I801 SMBus driver"); 1753 MODULE_LICENSE("GPL"); 1754 1755 module_driver(i801_driver, i2c_i801_init, pci_unregister_driver); 1756