1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * APM X-Gene SoC Hardware Monitoring Driver 4 * 5 * Copyright (c) 2016, Applied Micro Circuits Corporation 6 * Author: Loc Ho <lho@apm.com> 7 * Hoan Tran <hotran@apm.com> 8 * 9 * This driver provides the following features: 10 * - Retrieve CPU total power (uW) 11 * - Retrieve IO total power (uW) 12 * - Retrieve SoC temperature (milli-degree C) and alarm 13 */ 14 #include <linux/acpi.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/hwmon.h> 17 #include <linux/hwmon-sysfs.h> 18 #include <linux/io.h> 19 #include <linux/interrupt.h> 20 #include <linux/kfifo.h> 21 #include <linux/mailbox_controller.h> 22 #include <linux/mailbox_client.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/platform_device.h> 26 27 #include <acpi/pcc.h> 28 29 /* SLIMpro message defines */ 30 #define MSG_TYPE_DBG 0 31 #define MSG_TYPE_ERR 7 32 #define MSG_TYPE_PWRMGMT 9 33 34 #define MSG_TYPE(v) (((v) & 0xF0000000) >> 28) 35 #define MSG_TYPE_SET(v) (((v) << 28) & 0xF0000000) 36 #define MSG_SUBTYPE(v) (((v) & 0x0F000000) >> 24) 37 #define MSG_SUBTYPE_SET(v) (((v) << 24) & 0x0F000000) 38 39 #define DBG_SUBTYPE_SENSOR_READ 4 40 #define SENSOR_RD_MSG 0x04FFE902 41 #define SENSOR_RD_EN_ADDR(a) ((a) & 0x000FFFFF) 42 #define PMD_PWR_REG 0x20 43 #define PMD_PWR_MW_REG 0x26 44 #define SOC_PWR_REG 0x21 45 #define SOC_PWR_MW_REG 0x27 46 #define SOC_TEMP_REG 0x10 47 48 #define TEMP_NEGATIVE_BIT 8 49 #define SENSOR_INVALID_DATA BIT(15) 50 51 #define PWRMGMT_SUBTYPE_TPC 1 52 #define TPC_ALARM 2 53 #define TPC_GET_ALARM 3 54 #define TPC_CMD(v) (((v) & 0x00FF0000) >> 16) 55 #define TPC_CMD_SET(v) (((v) << 16) & 0x00FF0000) 56 #define TPC_EN_MSG(hndl, cmd, type) \ 57 (MSG_TYPE_SET(MSG_TYPE_PWRMGMT) | \ 58 MSG_SUBTYPE_SET(hndl) | TPC_CMD_SET(cmd) | type) 59 60 /* 61 * Arbitrary retries in case the remote processor is slow to respond 62 * to PCC commands 63 */ 64 #define PCC_NUM_RETRIES 500 65 66 #define ASYNC_MSG_FIFO_SIZE 16 67 #define MBOX_OP_TIMEOUTMS 1000 68 69 #define WATT_TO_mWATT(x) ((x) * 1000) 70 #define mWATT_TO_uWATT(x) ((x) * 1000) 71 #define CELSIUS_TO_mCELSIUS(x) ((x) * 1000) 72 73 #define to_xgene_hwmon_dev(cl) \ 74 container_of(cl, struct xgene_hwmon_dev, mbox_client) 75 76 enum xgene_hwmon_version { 77 XGENE_HWMON_V1 = 0, 78 XGENE_HWMON_V2 = 1, 79 }; 80 81 struct slimpro_resp_msg { 82 u32 msg; 83 u32 param1; 84 u32 param2; 85 } __packed; 86 87 struct xgene_hwmon_dev { 88 struct device *dev; 89 struct mbox_chan *mbox_chan; 90 struct pcc_mbox_chan *pcc_chan; 91 struct mbox_client mbox_client; 92 int mbox_idx; 93 94 spinlock_t kfifo_lock; 95 struct mutex rd_mutex; 96 struct completion rd_complete; 97 int resp_pending; 98 struct slimpro_resp_msg sync_msg; 99 100 struct work_struct workq; 101 struct kfifo_rec_ptr_1 async_msg_fifo; 102 103 struct device *hwmon_dev; 104 bool temp_critical_alarm; 105 106 unsigned int usecs_lat; 107 }; 108 109 /* 110 * This function tests and clears a bitmask then returns its old value 111 */ 112 static u16 xgene_word_tst_and_clr(u16 *addr, u16 mask) 113 { 114 u16 ret, val; 115 116 val = le16_to_cpu(READ_ONCE(*addr)); 117 ret = val & mask; 118 val &= ~mask; 119 WRITE_ONCE(*addr, cpu_to_le16(val)); 120 121 return ret; 122 } 123 124 static int xgene_hwmon_pcc_rd(struct xgene_hwmon_dev *ctx, u32 *msg) 125 { 126 struct acpi_pcct_shared_memory __iomem *generic_comm_base = 127 ctx->pcc_chan->shmem; 128 u32 *ptr = (void *)(generic_comm_base + 1); 129 int rc, i; 130 u16 val; 131 132 mutex_lock(&ctx->rd_mutex); 133 init_completion(&ctx->rd_complete); 134 ctx->resp_pending = true; 135 136 /* Write signature for subspace */ 137 WRITE_ONCE(generic_comm_base->signature, 138 cpu_to_le32(PCC_SIGNATURE | ctx->mbox_idx)); 139 140 /* Write to the shared command region */ 141 WRITE_ONCE(generic_comm_base->command, 142 cpu_to_le16(MSG_TYPE(msg[0]) | PCC_CMD_GENERATE_DB_INTR)); 143 144 /* Flip CMD COMPLETE bit */ 145 val = le16_to_cpu(READ_ONCE(generic_comm_base->status)); 146 val &= ~PCC_STATUS_CMD_COMPLETE; 147 WRITE_ONCE(generic_comm_base->status, cpu_to_le16(val)); 148 149 /* Copy the message to the PCC comm space */ 150 for (i = 0; i < sizeof(struct slimpro_resp_msg) / 4; i++) 151 WRITE_ONCE(ptr[i], cpu_to_le32(msg[i])); 152 153 /* Ring the doorbell */ 154 rc = mbox_send_message(ctx->mbox_chan, msg); 155 if (rc < 0) { 156 dev_err(ctx->dev, "Mailbox send error %d\n", rc); 157 goto err; 158 } 159 if (!wait_for_completion_timeout(&ctx->rd_complete, 160 usecs_to_jiffies(ctx->usecs_lat))) { 161 dev_err(ctx->dev, "Mailbox operation timed out\n"); 162 rc = -ETIMEDOUT; 163 goto err; 164 } 165 166 /* Check for error message */ 167 if (MSG_TYPE(ctx->sync_msg.msg) == MSG_TYPE_ERR) { 168 rc = -EINVAL; 169 goto err; 170 } 171 172 msg[0] = ctx->sync_msg.msg; 173 msg[1] = ctx->sync_msg.param1; 174 msg[2] = ctx->sync_msg.param2; 175 176 err: 177 mbox_chan_txdone(ctx->mbox_chan, 0); 178 ctx->resp_pending = false; 179 mutex_unlock(&ctx->rd_mutex); 180 return rc; 181 } 182 183 static int xgene_hwmon_rd(struct xgene_hwmon_dev *ctx, u32 *msg) 184 { 185 int rc; 186 187 mutex_lock(&ctx->rd_mutex); 188 init_completion(&ctx->rd_complete); 189 ctx->resp_pending = true; 190 191 rc = mbox_send_message(ctx->mbox_chan, msg); 192 if (rc < 0) { 193 dev_err(ctx->dev, "Mailbox send error %d\n", rc); 194 goto err; 195 } 196 197 if (!wait_for_completion_timeout(&ctx->rd_complete, 198 msecs_to_jiffies(MBOX_OP_TIMEOUTMS))) { 199 dev_err(ctx->dev, "Mailbox operation timed out\n"); 200 rc = -ETIMEDOUT; 201 goto err; 202 } 203 204 /* Check for error message */ 205 if (MSG_TYPE(ctx->sync_msg.msg) == MSG_TYPE_ERR) { 206 rc = -EINVAL; 207 goto err; 208 } 209 210 msg[0] = ctx->sync_msg.msg; 211 msg[1] = ctx->sync_msg.param1; 212 msg[2] = ctx->sync_msg.param2; 213 214 err: 215 ctx->resp_pending = false; 216 mutex_unlock(&ctx->rd_mutex); 217 return rc; 218 } 219 220 static int xgene_hwmon_reg_map_rd(struct xgene_hwmon_dev *ctx, u32 addr, 221 u32 *data) 222 { 223 u32 msg[3]; 224 int rc; 225 226 msg[0] = SENSOR_RD_MSG; 227 msg[1] = SENSOR_RD_EN_ADDR(addr); 228 msg[2] = 0; 229 230 if (acpi_disabled) 231 rc = xgene_hwmon_rd(ctx, msg); 232 else 233 rc = xgene_hwmon_pcc_rd(ctx, msg); 234 235 if (rc < 0) 236 return rc; 237 238 /* 239 * Check if sensor data is valid. 240 */ 241 if (msg[1] & SENSOR_INVALID_DATA) 242 return -ENODATA; 243 244 *data = msg[1]; 245 246 return rc; 247 } 248 249 static int xgene_hwmon_get_notification_msg(struct xgene_hwmon_dev *ctx, 250 u32 *amsg) 251 { 252 u32 msg[3]; 253 int rc; 254 255 msg[0] = TPC_EN_MSG(PWRMGMT_SUBTYPE_TPC, TPC_GET_ALARM, 0); 256 msg[1] = 0; 257 msg[2] = 0; 258 259 rc = xgene_hwmon_pcc_rd(ctx, msg); 260 if (rc < 0) 261 return rc; 262 263 amsg[0] = msg[0]; 264 amsg[1] = msg[1]; 265 amsg[2] = msg[2]; 266 267 return rc; 268 } 269 270 static int xgene_hwmon_get_cpu_pwr(struct xgene_hwmon_dev *ctx, u32 *val) 271 { 272 u32 watt, mwatt; 273 int rc; 274 275 rc = xgene_hwmon_reg_map_rd(ctx, PMD_PWR_REG, &watt); 276 if (rc < 0) 277 return rc; 278 279 rc = xgene_hwmon_reg_map_rd(ctx, PMD_PWR_MW_REG, &mwatt); 280 if (rc < 0) 281 return rc; 282 283 *val = WATT_TO_mWATT(watt) + mwatt; 284 return 0; 285 } 286 287 static int xgene_hwmon_get_io_pwr(struct xgene_hwmon_dev *ctx, u32 *val) 288 { 289 u32 watt, mwatt; 290 int rc; 291 292 rc = xgene_hwmon_reg_map_rd(ctx, SOC_PWR_REG, &watt); 293 if (rc < 0) 294 return rc; 295 296 rc = xgene_hwmon_reg_map_rd(ctx, SOC_PWR_MW_REG, &mwatt); 297 if (rc < 0) 298 return rc; 299 300 *val = WATT_TO_mWATT(watt) + mwatt; 301 return 0; 302 } 303 304 static int xgene_hwmon_get_temp(struct xgene_hwmon_dev *ctx, u32 *val) 305 { 306 return xgene_hwmon_reg_map_rd(ctx, SOC_TEMP_REG, val); 307 } 308 309 /* 310 * Sensor temperature/power functions 311 */ 312 static ssize_t temp1_input_show(struct device *dev, 313 struct device_attribute *attr, 314 char *buf) 315 { 316 struct xgene_hwmon_dev *ctx = dev_get_drvdata(dev); 317 int rc, temp; 318 u32 val; 319 320 rc = xgene_hwmon_get_temp(ctx, &val); 321 if (rc < 0) 322 return rc; 323 324 temp = sign_extend32(val, TEMP_NEGATIVE_BIT); 325 326 return sysfs_emit(buf, "%d\n", CELSIUS_TO_mCELSIUS(temp)); 327 } 328 329 static ssize_t temp1_label_show(struct device *dev, 330 struct device_attribute *attr, 331 char *buf) 332 { 333 return sysfs_emit(buf, "SoC Temperature\n"); 334 } 335 336 static ssize_t temp1_critical_alarm_show(struct device *dev, 337 struct device_attribute *devattr, 338 char *buf) 339 { 340 struct xgene_hwmon_dev *ctx = dev_get_drvdata(dev); 341 342 return sysfs_emit(buf, "%d\n", ctx->temp_critical_alarm); 343 } 344 345 static ssize_t power1_label_show(struct device *dev, 346 struct device_attribute *attr, 347 char *buf) 348 { 349 return sysfs_emit(buf, "CPU power\n"); 350 } 351 352 static ssize_t power2_label_show(struct device *dev, 353 struct device_attribute *attr, 354 char *buf) 355 { 356 return sysfs_emit(buf, "IO power\n"); 357 } 358 359 static ssize_t power1_input_show(struct device *dev, 360 struct device_attribute *attr, 361 char *buf) 362 { 363 struct xgene_hwmon_dev *ctx = dev_get_drvdata(dev); 364 u32 val; 365 int rc; 366 367 rc = xgene_hwmon_get_cpu_pwr(ctx, &val); 368 if (rc < 0) 369 return rc; 370 371 return sysfs_emit(buf, "%u\n", mWATT_TO_uWATT(val)); 372 } 373 374 static ssize_t power2_input_show(struct device *dev, 375 struct device_attribute *attr, 376 char *buf) 377 { 378 struct xgene_hwmon_dev *ctx = dev_get_drvdata(dev); 379 u32 val; 380 int rc; 381 382 rc = xgene_hwmon_get_io_pwr(ctx, &val); 383 if (rc < 0) 384 return rc; 385 386 return sysfs_emit(buf, "%u\n", mWATT_TO_uWATT(val)); 387 } 388 389 static DEVICE_ATTR_RO(temp1_label); 390 static DEVICE_ATTR_RO(temp1_input); 391 static DEVICE_ATTR_RO(temp1_critical_alarm); 392 static DEVICE_ATTR_RO(power1_label); 393 static DEVICE_ATTR_RO(power1_input); 394 static DEVICE_ATTR_RO(power2_label); 395 static DEVICE_ATTR_RO(power2_input); 396 397 static struct attribute *xgene_hwmon_attrs[] = { 398 &dev_attr_temp1_label.attr, 399 &dev_attr_temp1_input.attr, 400 &dev_attr_temp1_critical_alarm.attr, 401 &dev_attr_power1_label.attr, 402 &dev_attr_power1_input.attr, 403 &dev_attr_power2_label.attr, 404 &dev_attr_power2_input.attr, 405 NULL, 406 }; 407 408 ATTRIBUTE_GROUPS(xgene_hwmon); 409 410 static int xgene_hwmon_tpc_alarm(struct xgene_hwmon_dev *ctx, 411 struct slimpro_resp_msg *amsg) 412 { 413 ctx->temp_critical_alarm = !!amsg->param2; 414 sysfs_notify(&ctx->dev->kobj, NULL, "temp1_critical_alarm"); 415 416 return 0; 417 } 418 419 static void xgene_hwmon_process_pwrmsg(struct xgene_hwmon_dev *ctx, 420 struct slimpro_resp_msg *amsg) 421 { 422 if ((MSG_SUBTYPE(amsg->msg) == PWRMGMT_SUBTYPE_TPC) && 423 (TPC_CMD(amsg->msg) == TPC_ALARM)) 424 xgene_hwmon_tpc_alarm(ctx, amsg); 425 } 426 427 /* 428 * This function is called to process async work queue 429 */ 430 static void xgene_hwmon_evt_work(struct work_struct *work) 431 { 432 struct slimpro_resp_msg amsg; 433 struct xgene_hwmon_dev *ctx; 434 int ret; 435 436 ctx = container_of(work, struct xgene_hwmon_dev, workq); 437 while (kfifo_out_spinlocked(&ctx->async_msg_fifo, &amsg, 438 sizeof(struct slimpro_resp_msg), 439 &ctx->kfifo_lock)) { 440 /* 441 * If PCC, send a consumer command to Platform to get info 442 * If Slimpro Mailbox, get message from specific FIFO 443 */ 444 if (!acpi_disabled) { 445 ret = xgene_hwmon_get_notification_msg(ctx, 446 (u32 *)&amsg); 447 if (ret < 0) 448 continue; 449 } 450 451 if (MSG_TYPE(amsg.msg) == MSG_TYPE_PWRMGMT) 452 xgene_hwmon_process_pwrmsg(ctx, &amsg); 453 } 454 } 455 456 static int xgene_hwmon_rx_ready(struct xgene_hwmon_dev *ctx, void *msg) 457 { 458 if (IS_ERR_OR_NULL(ctx->hwmon_dev) && !ctx->resp_pending) { 459 /* Enqueue to the FIFO */ 460 kfifo_in_spinlocked(&ctx->async_msg_fifo, msg, 461 sizeof(struct slimpro_resp_msg), 462 &ctx->kfifo_lock); 463 return -ENODEV; 464 } 465 466 return 0; 467 } 468 469 /* 470 * This function is called when the SLIMpro Mailbox received a message 471 */ 472 static void xgene_hwmon_rx_cb(struct mbox_client *cl, void *msg) 473 { 474 struct xgene_hwmon_dev *ctx = to_xgene_hwmon_dev(cl); 475 476 /* 477 * While the driver registers with the mailbox framework, an interrupt 478 * can be pending before the probe function completes its 479 * initialization. If such condition occurs, just queue up the message 480 * as the driver is not ready for servicing the callback. 481 */ 482 if (xgene_hwmon_rx_ready(ctx, msg) < 0) 483 return; 484 485 /* 486 * Response message format: 487 * msg[0] is the return code of the operation 488 * msg[1] is the first parameter word 489 * msg[2] is the second parameter word 490 * 491 * As message only supports dword size, just assign it. 492 */ 493 494 /* Check for sync query */ 495 if (ctx->resp_pending && 496 ((MSG_TYPE(((u32 *)msg)[0]) == MSG_TYPE_ERR) || 497 (MSG_TYPE(((u32 *)msg)[0]) == MSG_TYPE_DBG && 498 MSG_SUBTYPE(((u32 *)msg)[0]) == DBG_SUBTYPE_SENSOR_READ) || 499 (MSG_TYPE(((u32 *)msg)[0]) == MSG_TYPE_PWRMGMT && 500 MSG_SUBTYPE(((u32 *)msg)[0]) == PWRMGMT_SUBTYPE_TPC && 501 TPC_CMD(((u32 *)msg)[0]) == TPC_ALARM))) { 502 ctx->sync_msg.msg = ((u32 *)msg)[0]; 503 ctx->sync_msg.param1 = ((u32 *)msg)[1]; 504 ctx->sync_msg.param2 = ((u32 *)msg)[2]; 505 506 /* Operation waiting for response */ 507 complete(&ctx->rd_complete); 508 509 return; 510 } 511 512 /* Enqueue to the FIFO */ 513 kfifo_in_spinlocked(&ctx->async_msg_fifo, msg, 514 sizeof(struct slimpro_resp_msg), &ctx->kfifo_lock); 515 /* Schedule the bottom handler */ 516 schedule_work(&ctx->workq); 517 } 518 519 /* 520 * This function is called when the PCC Mailbox received a message 521 */ 522 static void xgene_hwmon_pcc_rx_cb(struct mbox_client *cl, void *msg) 523 { 524 struct xgene_hwmon_dev *ctx = to_xgene_hwmon_dev(cl); 525 struct acpi_pcct_shared_memory __iomem *generic_comm_base = 526 ctx->pcc_chan->shmem; 527 struct slimpro_resp_msg amsg; 528 529 /* 530 * While the driver registers with the mailbox framework, an interrupt 531 * can be pending before the probe function completes its 532 * initialization. If such condition occurs, just queue up the message 533 * as the driver is not ready for servicing the callback. 534 */ 535 if (xgene_hwmon_rx_ready(ctx, &amsg) < 0) 536 return; 537 538 msg = generic_comm_base + 1; 539 /* Check if platform sends interrupt */ 540 if (!xgene_word_tst_and_clr(&generic_comm_base->status, 541 PCC_STATUS_SCI_DOORBELL)) 542 return; 543 544 /* 545 * Response message format: 546 * msg[0] is the return code of the operation 547 * msg[1] is the first parameter word 548 * msg[2] is the second parameter word 549 * 550 * As message only supports dword size, just assign it. 551 */ 552 553 /* Check for sync query */ 554 if (ctx->resp_pending && 555 ((MSG_TYPE(((u32 *)msg)[0]) == MSG_TYPE_ERR) || 556 (MSG_TYPE(((u32 *)msg)[0]) == MSG_TYPE_DBG && 557 MSG_SUBTYPE(((u32 *)msg)[0]) == DBG_SUBTYPE_SENSOR_READ) || 558 (MSG_TYPE(((u32 *)msg)[0]) == MSG_TYPE_PWRMGMT && 559 MSG_SUBTYPE(((u32 *)msg)[0]) == PWRMGMT_SUBTYPE_TPC && 560 TPC_CMD(((u32 *)msg)[0]) == TPC_ALARM))) { 561 /* Check if platform completes command */ 562 if (xgene_word_tst_and_clr(&generic_comm_base->status, 563 PCC_STATUS_CMD_COMPLETE)) { 564 ctx->sync_msg.msg = ((u32 *)msg)[0]; 565 ctx->sync_msg.param1 = ((u32 *)msg)[1]; 566 ctx->sync_msg.param2 = ((u32 *)msg)[2]; 567 568 /* Operation waiting for response */ 569 complete(&ctx->rd_complete); 570 571 return; 572 } 573 } 574 575 /* 576 * Platform notifies interrupt to OSPM. 577 * OPSM schedules a consumer command to get this information 578 * in a workqueue. Platform must wait until OSPM has issued 579 * a consumer command that serves this notification. 580 */ 581 582 /* Enqueue to the FIFO */ 583 kfifo_in_spinlocked(&ctx->async_msg_fifo, &amsg, 584 sizeof(struct slimpro_resp_msg), &ctx->kfifo_lock); 585 /* Schedule the bottom handler */ 586 schedule_work(&ctx->workq); 587 } 588 589 static void xgene_hwmon_tx_done(struct mbox_client *cl, void *msg, int ret) 590 { 591 if (ret) { 592 dev_dbg(cl->dev, "TX did not complete: CMD sent:%x, ret:%d\n", 593 *(u16 *)msg, ret); 594 } else { 595 dev_dbg(cl->dev, "TX completed. CMD sent:%x, ret:%d\n", 596 *(u16 *)msg, ret); 597 } 598 } 599 600 #ifdef CONFIG_ACPI 601 static const struct acpi_device_id xgene_hwmon_acpi_match[] = { 602 {"APMC0D29", XGENE_HWMON_V1}, 603 {"APMC0D8A", XGENE_HWMON_V2}, 604 {}, 605 }; 606 MODULE_DEVICE_TABLE(acpi, xgene_hwmon_acpi_match); 607 #endif 608 609 static int xgene_hwmon_probe(struct platform_device *pdev) 610 { 611 struct xgene_hwmon_dev *ctx; 612 struct mbox_client *cl; 613 int rc; 614 615 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); 616 if (!ctx) 617 return -ENOMEM; 618 619 ctx->dev = &pdev->dev; 620 platform_set_drvdata(pdev, ctx); 621 cl = &ctx->mbox_client; 622 623 spin_lock_init(&ctx->kfifo_lock); 624 mutex_init(&ctx->rd_mutex); 625 626 rc = kfifo_alloc(&ctx->async_msg_fifo, 627 sizeof(struct slimpro_resp_msg) * ASYNC_MSG_FIFO_SIZE, 628 GFP_KERNEL); 629 if (rc) 630 return -ENOMEM; 631 632 INIT_WORK(&ctx->workq, xgene_hwmon_evt_work); 633 634 /* Request mailbox channel */ 635 cl->dev = &pdev->dev; 636 cl->tx_done = xgene_hwmon_tx_done; 637 cl->tx_block = false; 638 cl->tx_tout = MBOX_OP_TIMEOUTMS; 639 cl->knows_txdone = false; 640 if (acpi_disabled) { 641 cl->rx_callback = xgene_hwmon_rx_cb; 642 ctx->mbox_chan = mbox_request_channel(cl, 0); 643 if (IS_ERR(ctx->mbox_chan)) { 644 dev_err(&pdev->dev, 645 "SLIMpro mailbox channel request failed\n"); 646 rc = -ENODEV; 647 goto out_mbox_free; 648 } 649 } else { 650 struct pcc_mbox_chan *pcc_chan; 651 const struct acpi_device_id *acpi_id; 652 653 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table, 654 &pdev->dev); 655 if (!acpi_id) { 656 rc = -EINVAL; 657 goto out_mbox_free; 658 } 659 660 if (device_property_read_u32(&pdev->dev, "pcc-channel", 661 &ctx->mbox_idx)) { 662 dev_err(&pdev->dev, "no pcc-channel property\n"); 663 rc = -ENODEV; 664 goto out_mbox_free; 665 } 666 667 cl->rx_callback = xgene_hwmon_pcc_rx_cb; 668 pcc_chan = pcc_mbox_request_channel(cl, ctx->mbox_idx); 669 if (IS_ERR(pcc_chan)) { 670 dev_err(&pdev->dev, 671 "PPC channel request failed\n"); 672 rc = -ENODEV; 673 goto out_mbox_free; 674 } 675 676 ctx->pcc_chan = pcc_chan; 677 ctx->mbox_chan = pcc_chan->mchan; 678 679 if (!ctx->mbox_chan->mbox->txdone_irq) { 680 dev_err(&pdev->dev, "PCC IRQ not supported\n"); 681 rc = -ENODEV; 682 goto out; 683 } 684 685 /* 686 * pcc_chan->latency is just a Nominal value. In reality 687 * the remote processor could be much slower to reply. 688 * So add an arbitrary amount of wait on top of Nominal. 689 */ 690 ctx->usecs_lat = PCC_NUM_RETRIES * pcc_chan->latency; 691 } 692 693 ctx->hwmon_dev = hwmon_device_register_with_groups(ctx->dev, 694 "apm_xgene", 695 ctx, 696 xgene_hwmon_groups); 697 if (IS_ERR(ctx->hwmon_dev)) { 698 dev_err(&pdev->dev, "Failed to register HW monitor device\n"); 699 rc = PTR_ERR(ctx->hwmon_dev); 700 goto out; 701 } 702 703 /* 704 * Schedule the bottom handler if there is a pending message. 705 */ 706 schedule_work(&ctx->workq); 707 708 dev_info(&pdev->dev, "APM X-Gene SoC HW monitor driver registered\n"); 709 710 return 0; 711 712 out: 713 if (acpi_disabled) 714 mbox_free_channel(ctx->mbox_chan); 715 else 716 pcc_mbox_free_channel(ctx->pcc_chan); 717 out_mbox_free: 718 kfifo_free(&ctx->async_msg_fifo); 719 720 return rc; 721 } 722 723 static void xgene_hwmon_remove(struct platform_device *pdev) 724 { 725 struct xgene_hwmon_dev *ctx = platform_get_drvdata(pdev); 726 727 cancel_work_sync(&ctx->workq); 728 hwmon_device_unregister(ctx->hwmon_dev); 729 kfifo_free(&ctx->async_msg_fifo); 730 if (acpi_disabled) 731 mbox_free_channel(ctx->mbox_chan); 732 else 733 pcc_mbox_free_channel(ctx->pcc_chan); 734 } 735 736 static const struct of_device_id xgene_hwmon_of_match[] = { 737 {.compatible = "apm,xgene-slimpro-hwmon"}, 738 {} 739 }; 740 MODULE_DEVICE_TABLE(of, xgene_hwmon_of_match); 741 742 static struct platform_driver xgene_hwmon_driver = { 743 .probe = xgene_hwmon_probe, 744 .remove = xgene_hwmon_remove, 745 .driver = { 746 .name = "xgene-slimpro-hwmon", 747 .of_match_table = xgene_hwmon_of_match, 748 .acpi_match_table = ACPI_PTR(xgene_hwmon_acpi_match), 749 }, 750 }; 751 module_platform_driver(xgene_hwmon_driver); 752 753 MODULE_DESCRIPTION("APM X-Gene SoC hardware monitor"); 754 MODULE_LICENSE("GPL"); 755