1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Analog Devices LTC4282 I2C High Current Hot Swap Controller over I2C 4 * 5 * Copyright 2023 Analog Devices Inc. 6 */ 7 #include <linux/bitfield.h> 8 #include <linux/cleanup.h> 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/debugfs.h> 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/hwmon.h> 15 #include <linux/hwmon-sysfs.h> 16 #include <linux/i2c.h> 17 #include <linux/math.h> 18 #include <linux/minmax.h> 19 #include <linux/module.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/mutex.h> 22 #include <linux/regmap.h> 23 #include <linux/property.h> 24 #include <linux/string.h> 25 #include <linux/units.h> 26 #include <linux/util_macros.h> 27 28 #define LTC4282_CTRL_LSB 0x00 29 #define LTC4282_CTRL_OV_RETRY_MASK BIT(0) 30 #define LTC4282_CTRL_UV_RETRY_MASK BIT(1) 31 #define LTC4282_CTRL_OC_RETRY_MASK BIT(2) 32 #define LTC4282_CTRL_ON_ACTIVE_LOW_MASK BIT(5) 33 #define LTC4282_CTRL_ON_DELAY_MASK BIT(6) 34 #define LTC4282_CTRL_MSB 0x01 35 #define LTC4282_CTRL_VIN_MODE_MASK GENMASK(1, 0) 36 #define LTC4282_CTRL_OV_MODE_MASK GENMASK(3, 2) 37 #define LTC4282_CTRL_UV_MODE_MASK GENMASK(5, 4) 38 #define LTC4282_FAULT_LOG 0x04 39 #define LTC4282_OV_FAULT_MASK BIT(0) 40 #define LTC4282_UV_FAULT_MASK BIT(1) 41 #define LTC4282_VDD_FAULT_MASK \ 42 (LTC4282_OV_FAULT_MASK | LTC4282_UV_FAULT_MASK) 43 #define LTC4282_OC_FAULT_MASK BIT(2) 44 #define LTC4282_POWER_BAD_FAULT_MASK BIT(3) 45 #define LTC4282_FET_SHORT_FAULT_MASK BIT(5) 46 #define LTC4282_FET_BAD_FAULT_MASK BIT(6) 47 #define LTC4282_FET_FAILURE_FAULT_MASK \ 48 (LTC4282_FET_SHORT_FAULT_MASK | LTC4282_FET_BAD_FAULT_MASK) 49 #define LTC4282_ADC_ALERT_LOG 0x05 50 #define LTC4282_GPIO_ALARM_L_MASK BIT(0) 51 #define LTC4282_GPIO_ALARM_H_MASK BIT(1) 52 #define LTC4282_VSOURCE_ALARM_L_MASK BIT(2) 53 #define LTC4282_VSOURCE_ALARM_H_MASK BIT(3) 54 #define LTC4282_VSENSE_ALARM_L_MASK BIT(4) 55 #define LTC4282_VSENSE_ALARM_H_MASK BIT(5) 56 #define LTC4282_POWER_ALARM_L_MASK BIT(6) 57 #define LTC4282_POWER_ALARM_H_MASK BIT(7) 58 #define LTC4282_FET_BAD_FAULT_TIMEOUT 0x06 59 #define LTC4282_FET_BAD_MAX_TIMEOUT 255 60 #define LTC4282_GPIO_CONFIG 0x07 61 #define LTC4282_GPIO_2_FET_STRESS_MASK BIT(1) 62 #define LTC4282_GPIO_1_CONFIG_MASK GENMASK(5, 4) 63 #define LTC4282_VGPIO_MIN 0x08 64 #define LTC4282_VGPIO_MAX 0x09 65 #define LTC4282_VSOURCE_MIN 0x0a 66 #define LTC4282_VSOURCE_MAX 0x0b 67 #define LTC4282_VSENSE_MIN 0x0c 68 #define LTC4282_VSENSE_MAX 0x0d 69 #define LTC4282_POWER_MIN 0x0e 70 #define LTC4282_POWER_MAX 0x0f 71 #define LTC4282_CLK_DIV 0x10 72 #define LTC4282_CLK_DIV_MASK GENMASK(4, 0) 73 #define LTC4282_CLKOUT_MASK GENMASK(6, 5) 74 #define LTC4282_ILIM_ADJUST 0x11 75 #define LTC4282_GPIO_MODE_MASK BIT(1) 76 #define LTC4282_VDD_MONITOR_MASK BIT(2) 77 #define LTC4282_FOLDBACK_MODE_MASK GENMASK(4, 3) 78 #define LTC4282_ILIM_ADJUST_MASK GENMASK(7, 5) 79 #define LTC4282_ENERGY 0x12 80 #define LTC4282_TIME_COUNTER 0x18 81 #define LTC4282_ALERT_CTRL 0x1c 82 #define LTC4282_ALERT_OUT_MASK BIT(6) 83 #define LTC4282_ADC_CTRL 0x1d 84 #define LTC4282_FAULT_LOG_EN_MASK BIT(2) 85 #define LTC4282_METER_HALT_MASK BIT(5) 86 #define LTC4282_METER_RESET_MASK BIT(6) 87 #define LTC4282_RESET_MASK BIT(7) 88 #define LTC4282_STATUS_LSB 0x1e 89 #define LTC4282_OV_STATUS_MASK BIT(0) 90 #define LTC4282_UV_STATUS_MASK BIT(1) 91 #define LTC4282_VDD_STATUS_MASK \ 92 (LTC4282_OV_STATUS_MASK | LTC4282_UV_STATUS_MASK) 93 #define LTC4282_OC_STATUS_MASK BIT(2) 94 #define LTC4282_POWER_GOOD_MASK BIT(3) 95 #define LTC4282_FET_FAILURE_MASK GENMASK(6, 5) 96 #define LTC4282_STATUS_MSB 0x1f 97 #define LTC4282_RESERVED_1 0x32 98 #define LTC4282_RESERVED_2 0x33 99 #define LTC4282_VGPIO 0x34 100 #define LTC4282_VGPIO_LOWEST 0x36 101 #define LTC4282_VGPIO_HIGHEST 0x38 102 #define LTC4282_VSOURCE 0x3a 103 #define LTC4282_VSOURCE_LOWEST 0x3c 104 #define LTC4282_VSOURCE_HIGHEST 0x3e 105 #define LTC4282_VSENSE 0x40 106 #define LTC4282_VSENSE_LOWEST 0x42 107 #define LTC4282_VSENSE_HIGHEST 0x44 108 #define LTC4282_POWER 0x46 109 #define LTC4282_POWER_LOWEST 0x48 110 #define LTC4282_POWER_HIGHEST 0x4a 111 #define LTC4282_RESERVED_3 0x50 112 113 #define LTC4282_CLKIN_MIN (250 * KILO) 114 #define LTC4282_CLKIN_MAX (15500 * KILO) 115 #define LTC4282_CLKIN_RANGE (LTC4282_CLKIN_MAX - LTC4282_CLKIN_MIN + 1) 116 #define LTC4282_CLKOUT_SYSTEM (250 * KILO) 117 #define LTC4282_CLKOUT_CNV 15 118 119 enum { 120 LTC4282_CHAN_VSOURCE, 121 LTC4282_CHAN_VDD, 122 LTC4282_CHAN_VGPIO, 123 }; 124 125 struct ltc4282_cache { 126 u32 in_max_raw; 127 u32 in_min_raw; 128 long in_highest; 129 long in_lowest; 130 bool en; 131 }; 132 133 struct ltc4282_state { 134 struct regmap *map; 135 /* Protect against multiple accesses to the device registers */ 136 struct mutex lock; 137 struct clk_hw clk_hw; 138 /* 139 * Used to cache values for VDD/VSOURCE depending which will be used 140 * when hwmon is not enabled for that channel. Needed because they share 141 * the same registers. 142 */ 143 struct ltc4282_cache in0_1_cache[LTC4282_CHAN_VGPIO]; 144 u32 vsense_max; 145 long power_max; 146 u32 rsense; 147 u16 vdd; 148 u16 vfs_out; 149 bool energy_en; 150 }; 151 152 enum { 153 LTC4282_CLKOUT_NONE, 154 LTC4282_CLKOUT_INT, 155 LTC4282_CLKOUT_TICK, 156 }; 157 158 static int ltc4282_set_rate(struct clk_hw *hw, 159 unsigned long rate, unsigned long parent_rate) 160 { 161 struct ltc4282_state *st = container_of(hw, struct ltc4282_state, 162 clk_hw); 163 u32 val = LTC4282_CLKOUT_INT; 164 165 if (rate == LTC4282_CLKOUT_CNV) 166 val = LTC4282_CLKOUT_TICK; 167 168 return regmap_update_bits(st->map, LTC4282_CLK_DIV, LTC4282_CLKOUT_MASK, 169 FIELD_PREP(LTC4282_CLKOUT_MASK, val)); 170 } 171 172 /* 173 * Note the 15HZ conversion rate assumes 12bit ADC which is what we are 174 * supporting for now. 175 */ 176 static const unsigned int ltc4282_out_rates[] = { 177 LTC4282_CLKOUT_CNV, LTC4282_CLKOUT_SYSTEM 178 }; 179 180 static int ltc4282_determine_rate(struct clk_hw *hw, 181 struct clk_rate_request *req) 182 { 183 int idx = find_closest(req->rate, ltc4282_out_rates, 184 ARRAY_SIZE(ltc4282_out_rates)); 185 186 req->rate = ltc4282_out_rates[idx]; 187 188 return 0; 189 } 190 191 static unsigned long ltc4282_recalc_rate(struct clk_hw *hw, 192 unsigned long parent) 193 { 194 struct ltc4282_state *st = container_of(hw, struct ltc4282_state, 195 clk_hw); 196 u32 clkdiv; 197 int ret; 198 199 ret = regmap_read(st->map, LTC4282_CLK_DIV, &clkdiv); 200 if (ret) 201 return 0; 202 203 clkdiv = FIELD_GET(LTC4282_CLKOUT_MASK, clkdiv); 204 if (!clkdiv) 205 return 0; 206 if (clkdiv == LTC4282_CLKOUT_INT) 207 return LTC4282_CLKOUT_SYSTEM; 208 209 return LTC4282_CLKOUT_CNV; 210 } 211 212 static void ltc4282_disable(struct clk_hw *clk_hw) 213 { 214 struct ltc4282_state *st = container_of(clk_hw, struct ltc4282_state, 215 clk_hw); 216 217 regmap_clear_bits(st->map, LTC4282_CLK_DIV, LTC4282_CLKOUT_MASK); 218 } 219 220 static int ltc4282_read_voltage_word(const struct ltc4282_state *st, u32 reg, 221 u32 fs, long *val) 222 { 223 __be16 in; 224 int ret; 225 226 ret = regmap_bulk_read(st->map, reg, &in, sizeof(in)); 227 if (ret) 228 return ret; 229 230 /* 231 * This is also used to calculate current in which case fs comes in 232 * 10 * uV. Hence the ULL usage. 233 */ 234 *val = DIV_ROUND_CLOSEST_ULL(be16_to_cpu(in) * (u64)fs, U16_MAX); 235 return 0; 236 } 237 238 static int ltc4282_read_voltage_byte_cached(const struct ltc4282_state *st, 239 u32 reg, u32 fs, long *val, 240 u32 *cached_raw) 241 { 242 int ret; 243 u32 in; 244 245 if (cached_raw) { 246 in = *cached_raw; 247 } else { 248 ret = regmap_read(st->map, reg, &in); 249 if (ret) 250 return ret; 251 } 252 253 *val = DIV_ROUND_CLOSEST(in * fs, U8_MAX); 254 return 0; 255 } 256 257 static int ltc4282_read_voltage_byte(const struct ltc4282_state *st, u32 reg, 258 u32 fs, long *val) 259 { 260 return ltc4282_read_voltage_byte_cached(st, reg, fs, val, NULL); 261 } 262 263 static int __ltc4282_read_alarm(struct ltc4282_state *st, u32 reg, u32 mask, 264 long *val) 265 { 266 u32 alarm; 267 int ret; 268 269 ret = regmap_read(st->map, reg, &alarm); 270 if (ret) 271 return ret; 272 273 *val = !!(alarm & mask); 274 275 /* if not status/fault logs, clear the alarm after reading it */ 276 if (reg != LTC4282_STATUS_LSB && reg != LTC4282_FAULT_LOG) 277 return regmap_clear_bits(st->map, reg, mask); 278 279 return 0; 280 } 281 282 static int ltc4282_read_alarm(struct ltc4282_state *st, u32 reg, u32 mask, 283 long *val) 284 { 285 guard(mutex)(&st->lock); 286 return __ltc4282_read_alarm(st, reg, mask, val); 287 } 288 289 static int ltc4282_vdd_source_read_in(struct ltc4282_state *st, u32 channel, 290 long *val) 291 { 292 guard(mutex)(&st->lock); 293 if (!st->in0_1_cache[channel].en) 294 return -ENODATA; 295 296 return ltc4282_read_voltage_word(st, LTC4282_VSOURCE, st->vfs_out, val); 297 } 298 299 static int ltc4282_vdd_source_read_hist(struct ltc4282_state *st, u32 reg, 300 u32 channel, long *cached, long *val) 301 { 302 int ret; 303 304 guard(mutex)(&st->lock); 305 if (!st->in0_1_cache[channel].en) { 306 *val = *cached; 307 return 0; 308 } 309 310 ret = ltc4282_read_voltage_word(st, reg, st->vfs_out, val); 311 if (ret) 312 return ret; 313 314 *cached = *val; 315 return 0; 316 } 317 318 static int ltc4282_vdd_source_read_lim(struct ltc4282_state *st, u32 reg, 319 u32 channel, u32 *cached, long *val) 320 { 321 guard(mutex)(&st->lock); 322 if (!st->in0_1_cache[channel].en) 323 return ltc4282_read_voltage_byte_cached(st, reg, st->vfs_out, 324 val, cached); 325 326 return ltc4282_read_voltage_byte(st, reg, st->vfs_out, val); 327 } 328 329 static int ltc4282_vdd_source_read_alm(struct ltc4282_state *st, u32 mask, 330 u32 channel, long *val) 331 { 332 guard(mutex)(&st->lock); 333 if (!st->in0_1_cache[channel].en) { 334 /* 335 * Do this otherwise alarms can get confused because we clear 336 * them after reading them. So, if someone mistakenly reads 337 * VSOURCE right before VDD (or the other way around), we might 338 * get no alarm just because it was cleared when reading VSOURCE 339 * and had no time for a new conversion and thus having the 340 * alarm again. 341 */ 342 *val = 0; 343 return 0; 344 } 345 346 return __ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, mask, val); 347 } 348 349 static int ltc4282_read_in(struct ltc4282_state *st, u32 attr, long *val, 350 u32 channel) 351 { 352 switch (attr) { 353 case hwmon_in_input: 354 if (channel == LTC4282_CHAN_VGPIO) 355 return ltc4282_read_voltage_word(st, LTC4282_VGPIO, 356 1280, val); 357 358 return ltc4282_vdd_source_read_in(st, channel, val); 359 case hwmon_in_highest: 360 if (channel == LTC4282_CHAN_VGPIO) 361 return ltc4282_read_voltage_word(st, 362 LTC4282_VGPIO_HIGHEST, 363 1280, val); 364 365 return ltc4282_vdd_source_read_hist(st, LTC4282_VSOURCE_HIGHEST, 366 channel, 367 &st->in0_1_cache[channel].in_highest, val); 368 case hwmon_in_lowest: 369 if (channel == LTC4282_CHAN_VGPIO) 370 return ltc4282_read_voltage_word(st, LTC4282_VGPIO_LOWEST, 371 1280, val); 372 373 return ltc4282_vdd_source_read_hist(st, LTC4282_VSOURCE_LOWEST, 374 channel, 375 &st->in0_1_cache[channel].in_lowest, val); 376 case hwmon_in_max_alarm: 377 if (channel == LTC4282_CHAN_VGPIO) 378 return ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 379 LTC4282_GPIO_ALARM_H_MASK, 380 val); 381 382 return ltc4282_vdd_source_read_alm(st, 383 LTC4282_VSOURCE_ALARM_H_MASK, 384 channel, val); 385 case hwmon_in_min_alarm: 386 if (channel == LTC4282_CHAN_VGPIO) 387 ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 388 LTC4282_GPIO_ALARM_L_MASK, val); 389 390 return ltc4282_vdd_source_read_alm(st, 391 LTC4282_VSOURCE_ALARM_L_MASK, 392 channel, val); 393 case hwmon_in_crit_alarm: 394 return ltc4282_read_alarm(st, LTC4282_STATUS_LSB, 395 LTC4282_OV_STATUS_MASK, val); 396 case hwmon_in_lcrit_alarm: 397 return ltc4282_read_alarm(st, LTC4282_STATUS_LSB, 398 LTC4282_UV_STATUS_MASK, val); 399 case hwmon_in_max: 400 if (channel == LTC4282_CHAN_VGPIO) 401 return ltc4282_read_voltage_byte(st, LTC4282_VGPIO_MAX, 402 1280, val); 403 404 return ltc4282_vdd_source_read_lim(st, LTC4282_VSOURCE_MAX, 405 channel, 406 &st->in0_1_cache[channel].in_max_raw, val); 407 case hwmon_in_min: 408 if (channel == LTC4282_CHAN_VGPIO) 409 return ltc4282_read_voltage_byte(st, LTC4282_VGPIO_MIN, 410 1280, val); 411 412 return ltc4282_vdd_source_read_lim(st, LTC4282_VSOURCE_MIN, 413 channel, 414 &st->in0_1_cache[channel].in_min_raw, val); 415 case hwmon_in_enable: 416 scoped_guard(mutex, &st->lock) { 417 *val = st->in0_1_cache[channel].en; 418 } 419 return 0; 420 case hwmon_in_fault: 421 /* 422 * We report failure if we detect either a fer_bad or a 423 * fet_short in the status register. 424 */ 425 return ltc4282_read_alarm(st, LTC4282_STATUS_LSB, 426 LTC4282_FET_FAILURE_MASK, val); 427 default: 428 return -EOPNOTSUPP; 429 } 430 } 431 432 static int ltc4282_read_current_word(const struct ltc4282_state *st, u32 reg, 433 long *val) 434 { 435 long in; 436 int ret; 437 438 /* 439 * We pass in full scale in 10 * micro (note that 40 is already 440 * millivolt) so we have better approximations to calculate current. 441 */ 442 ret = ltc4282_read_voltage_word(st, reg, DECA * 40 * MILLI, &in); 443 if (ret) 444 return ret; 445 446 *val = DIV_ROUND_CLOSEST(in * MILLI, st->rsense); 447 448 return 0; 449 } 450 451 static int ltc4282_read_current_byte(const struct ltc4282_state *st, u32 reg, 452 long *val) 453 { 454 long in; 455 int ret; 456 457 ret = ltc4282_read_voltage_byte(st, reg, DECA * 40 * MILLI, &in); 458 if (ret) 459 return ret; 460 461 *val = DIV_ROUND_CLOSEST(in * MILLI, st->rsense); 462 463 return 0; 464 } 465 466 static int ltc4282_read_curr(struct ltc4282_state *st, const u32 attr, 467 long *val) 468 { 469 switch (attr) { 470 case hwmon_curr_input: 471 return ltc4282_read_current_word(st, LTC4282_VSENSE, val); 472 case hwmon_curr_highest: 473 return ltc4282_read_current_word(st, LTC4282_VSENSE_HIGHEST, 474 val); 475 case hwmon_curr_lowest: 476 return ltc4282_read_current_word(st, LTC4282_VSENSE_LOWEST, 477 val); 478 case hwmon_curr_max: 479 return ltc4282_read_current_byte(st, LTC4282_VSENSE_MAX, val); 480 case hwmon_curr_min: 481 return ltc4282_read_current_byte(st, LTC4282_VSENSE_MIN, val); 482 case hwmon_curr_max_alarm: 483 return ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 484 LTC4282_VSENSE_ALARM_H_MASK, val); 485 case hwmon_curr_min_alarm: 486 return ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 487 LTC4282_VSENSE_ALARM_L_MASK, val); 488 case hwmon_curr_crit_alarm: 489 return ltc4282_read_alarm(st, LTC4282_STATUS_LSB, 490 LTC4282_OC_STATUS_MASK, val); 491 default: 492 return -EOPNOTSUPP; 493 } 494 } 495 496 static int ltc4282_read_power_word(const struct ltc4282_state *st, u32 reg, 497 long *val) 498 { 499 u64 temp = DECA * 40ULL * st->vfs_out * BIT(16), temp_2; 500 __be16 raw; 501 u16 power; 502 int ret; 503 504 ret = regmap_bulk_read(st->map, reg, &raw, sizeof(raw)); 505 if (ret) 506 return ret; 507 508 power = be16_to_cpu(raw); 509 /* 510 * Power is given by: 511 * P = CODE(16b) * 0.040 * Vfs(out) * 2^16 / ((2^16 - 1)^2 * Rsense) 512 */ 513 if (check_mul_overflow(power * temp, MICRO, &temp_2)) { 514 temp = DIV_ROUND_CLOSEST_ULL(power * temp, U16_MAX); 515 *val = DIV64_U64_ROUND_CLOSEST(temp * MICRO, 516 U16_MAX * (u64)st->rsense); 517 return 0; 518 } 519 520 *val = DIV64_U64_ROUND_CLOSEST(temp_2, 521 st->rsense * int_pow(U16_MAX, 2)); 522 523 return 0; 524 } 525 526 static int ltc4282_read_power_byte(const struct ltc4282_state *st, u32 reg, 527 long *val) 528 { 529 u32 power; 530 u64 temp; 531 int ret; 532 533 ret = regmap_read(st->map, reg, &power); 534 if (ret) 535 return ret; 536 537 temp = power * 40 * DECA * st->vfs_out * BIT_ULL(8); 538 *val = DIV64_U64_ROUND_CLOSEST(temp * MICRO, 539 int_pow(U8_MAX, 2) * st->rsense); 540 541 return 0; 542 } 543 544 static int ltc4282_read_energy(const struct ltc4282_state *st, u64 *val) 545 { 546 u64 temp, energy; 547 __be64 raw; 548 int ret; 549 550 ret = regmap_bulk_read(st->map, LTC4282_ENERGY, &raw, 6); 551 if (ret) 552 return ret; 553 554 energy = be64_to_cpu(raw) >> 16; 555 /* 556 * The formula for energy is given by: 557 * E = CODE(48b) * 0.040 * Vfs(out) * Tconv * 256 / 558 * ((2^16 - 1)^2 * Rsense) 559 * 560 * Since we only support 12bit ADC, Tconv = 0.065535s. Passing Vfs(out) 561 * and 0.040 to mV and Tconv to us, we can simplify the formula to: 562 * E = CODE(48b) * 40 * Vfs(out) * 256 / (U16_MAX * Rsense) 563 * 564 * As Rsense can have tenths of micro-ohm resolution, we need to 565 * multiply by DECA to get microujoule. 566 */ 567 if (check_mul_overflow(DECA * st->vfs_out * 40 * BIT(8), energy, &temp)) { 568 temp = DIV_ROUND_CLOSEST(DECA * st->vfs_out * 40 * BIT(8), U16_MAX); 569 *val = DIV_ROUND_CLOSEST_ULL(temp * energy, st->rsense); 570 return 0; 571 } 572 573 *val = DIV64_U64_ROUND_CLOSEST(temp, U16_MAX * (u64)st->rsense); 574 575 return 0; 576 } 577 578 static int ltc4282_read_power(struct ltc4282_state *st, const u32 attr, 579 long *val) 580 { 581 switch (attr) { 582 case hwmon_power_input: 583 return ltc4282_read_power_word(st, LTC4282_POWER, val); 584 case hwmon_power_input_highest: 585 return ltc4282_read_power_word(st, LTC4282_POWER_HIGHEST, val); 586 case hwmon_power_input_lowest: 587 return ltc4282_read_power_word(st, LTC4282_POWER_LOWEST, val); 588 case hwmon_power_max_alarm: 589 return ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 590 LTC4282_POWER_ALARM_H_MASK, val); 591 case hwmon_power_min_alarm: 592 return ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 593 LTC4282_POWER_ALARM_L_MASK, val); 594 case hwmon_power_max: 595 return ltc4282_read_power_byte(st, LTC4282_POWER_MAX, val); 596 case hwmon_power_min: 597 return ltc4282_read_power_byte(st, LTC4282_POWER_MIN, val); 598 default: 599 return -EOPNOTSUPP; 600 } 601 } 602 603 static int ltc4282_read(struct device *dev, enum hwmon_sensor_types type, 604 u32 attr, int channel, long *val) 605 { 606 struct ltc4282_state *st = dev_get_drvdata(dev); 607 608 switch (type) { 609 case hwmon_in: 610 return ltc4282_read_in(st, attr, val, channel); 611 case hwmon_curr: 612 return ltc4282_read_curr(st, attr, val); 613 case hwmon_power: 614 return ltc4282_read_power(st, attr, val); 615 case hwmon_energy: 616 scoped_guard(mutex, &st->lock) { 617 *val = st->energy_en; 618 } 619 return 0; 620 default: 621 return -EOPNOTSUPP; 622 } 623 } 624 625 static int ltc4282_write_power_byte(const struct ltc4282_state *st, u32 reg, 626 long val) 627 { 628 u32 power; 629 u64 temp; 630 631 if (val > st->power_max) 632 val = st->power_max; 633 634 temp = val * int_pow(U8_MAX, 2) * st->rsense; 635 power = DIV64_U64_ROUND_CLOSEST(temp, 636 MICRO * DECA * 256ULL * st->vfs_out * 40); 637 638 return regmap_write(st->map, reg, power); 639 } 640 641 static int ltc4282_write_power_word(const struct ltc4282_state *st, u32 reg, 642 long val) 643 { 644 u64 temp = int_pow(U16_MAX, 2) * st->rsense, temp_2; 645 __be16 __raw; 646 u16 code; 647 648 if (check_mul_overflow(temp, val, &temp_2)) { 649 temp = DIV_ROUND_CLOSEST_ULL(temp, DECA * MICRO); 650 code = DIV64_U64_ROUND_CLOSEST(temp * val, 651 40ULL * BIT(16) * st->vfs_out); 652 } else { 653 temp = DECA * MICRO * 40ULL * BIT(16) * st->vfs_out; 654 code = DIV64_U64_ROUND_CLOSEST(temp_2, temp); 655 } 656 657 __raw = cpu_to_be16(code); 658 return regmap_bulk_write(st->map, reg, &__raw, sizeof(__raw)); 659 } 660 661 static int __ltc4282_in_write_history(const struct ltc4282_state *st, u32 reg, 662 long lowest, long highest, u32 fs) 663 { 664 __be16 __raw; 665 u16 tmp; 666 int ret; 667 668 tmp = DIV_ROUND_CLOSEST(U16_MAX * lowest, fs); 669 670 __raw = cpu_to_be16(tmp); 671 672 ret = regmap_bulk_write(st->map, reg, &__raw, 2); 673 if (ret) 674 return ret; 675 676 tmp = DIV_ROUND_CLOSEST(U16_MAX * highest, fs); 677 678 __raw = cpu_to_be16(tmp); 679 680 return regmap_bulk_write(st->map, reg + 2, &__raw, 2); 681 } 682 683 static int ltc4282_in_write_history(struct ltc4282_state *st, u32 reg, 684 long lowest, long highest, u32 fs) 685 { 686 guard(mutex)(&st->lock); 687 return __ltc4282_in_write_history(st, reg, lowest, highest, fs); 688 } 689 690 static int ltc4282_power_reset_hist(struct ltc4282_state *st) 691 { 692 int ret; 693 694 guard(mutex)(&st->lock); 695 696 ret = ltc4282_write_power_word(st, LTC4282_POWER_LOWEST, 697 st->power_max); 698 if (ret) 699 return ret; 700 701 ret = ltc4282_write_power_word(st, LTC4282_POWER_HIGHEST, 0); 702 if (ret) 703 return ret; 704 705 /* now, let's also clear possible power_bad fault logs */ 706 return regmap_clear_bits(st->map, LTC4282_FAULT_LOG, 707 LTC4282_POWER_BAD_FAULT_MASK); 708 } 709 710 static int ltc4282_write_power(struct ltc4282_state *st, u32 attr, 711 long val) 712 { 713 switch (attr) { 714 case hwmon_power_max: 715 return ltc4282_write_power_byte(st, LTC4282_POWER_MAX, val); 716 case hwmon_power_min: 717 return ltc4282_write_power_byte(st, LTC4282_POWER_MIN, val); 718 case hwmon_power_reset_history: 719 return ltc4282_power_reset_hist(st); 720 default: 721 return -EOPNOTSUPP; 722 } 723 } 724 725 static int ltc4282_write_voltage_byte_cached(const struct ltc4282_state *st, 726 u32 reg, u32 fs, long val, 727 u32 *cache_raw) 728 { 729 u32 in; 730 731 val = clamp_val(val, 0, fs); 732 in = DIV_ROUND_CLOSEST(val * U8_MAX, fs); 733 734 if (cache_raw) { 735 *cache_raw = in; 736 return 0; 737 } 738 739 return regmap_write(st->map, reg, in); 740 } 741 742 static int ltc4282_write_voltage_byte(const struct ltc4282_state *st, u32 reg, 743 u32 fs, long val) 744 { 745 return ltc4282_write_voltage_byte_cached(st, reg, fs, val, NULL); 746 } 747 748 static int ltc4282_cache_history(struct ltc4282_state *st, u32 channel) 749 { 750 long val; 751 int ret; 752 753 ret = ltc4282_read_voltage_word(st, LTC4282_VSOURCE_LOWEST, st->vfs_out, 754 &val); 755 if (ret) 756 return ret; 757 758 st->in0_1_cache[channel].in_lowest = val; 759 760 ret = ltc4282_read_voltage_word(st, LTC4282_VSOURCE_HIGHEST, 761 st->vfs_out, &val); 762 if (ret) 763 return ret; 764 765 st->in0_1_cache[channel].in_highest = val; 766 767 ret = regmap_read(st->map, LTC4282_VSOURCE_MIN, 768 &st->in0_1_cache[channel].in_min_raw); 769 if (ret) 770 return ret; 771 772 return regmap_read(st->map, LTC4282_VSOURCE_MAX, 773 &st->in0_1_cache[channel].in_max_raw); 774 } 775 776 static int ltc4282_cache_sync(struct ltc4282_state *st, u32 channel) 777 { 778 int ret; 779 780 ret = __ltc4282_in_write_history(st, LTC4282_VSOURCE_LOWEST, 781 st->in0_1_cache[channel].in_lowest, 782 st->in0_1_cache[channel].in_highest, 783 st->vfs_out); 784 if (ret) 785 return ret; 786 787 ret = regmap_write(st->map, LTC4282_VSOURCE_MIN, 788 st->in0_1_cache[channel].in_min_raw); 789 if (ret) 790 return ret; 791 792 return regmap_write(st->map, LTC4282_VSOURCE_MAX, 793 st->in0_1_cache[channel].in_max_raw); 794 } 795 796 static int ltc4282_vdd_source_write_lim(struct ltc4282_state *st, u32 reg, 797 int channel, u32 *cache, long val) 798 { 799 int ret; 800 801 guard(mutex)(&st->lock); 802 if (st->in0_1_cache[channel].en) 803 ret = ltc4282_write_voltage_byte(st, reg, st->vfs_out, val); 804 else 805 ret = ltc4282_write_voltage_byte_cached(st, reg, st->vfs_out, 806 val, cache); 807 808 return ret; 809 } 810 811 static int ltc4282_vdd_source_reset_hist(struct ltc4282_state *st, int channel) 812 { 813 long lowest = st->vfs_out; 814 int ret; 815 816 if (channel == LTC4282_CHAN_VDD) 817 lowest = st->vdd; 818 819 guard(mutex)(&st->lock); 820 if (st->in0_1_cache[channel].en) { 821 ret = __ltc4282_in_write_history(st, LTC4282_VSOURCE_LOWEST, 822 lowest, 0, st->vfs_out); 823 if (ret) 824 return ret; 825 } 826 827 st->in0_1_cache[channel].in_lowest = lowest; 828 st->in0_1_cache[channel].in_highest = 0; 829 830 /* 831 * We are also clearing possible fault logs in reset_history. Clearing 832 * the logs might be important when the auto retry bits are not enabled 833 * as the chip only enables the output again after having these logs 834 * cleared. As some of these logs are related to limits, it makes sense 835 * to clear them in here. For VDD, we need to clear under/over voltage 836 * events. For VSOURCE, fet_short and fet_bad... 837 */ 838 if (channel == LTC4282_CHAN_VSOURCE) 839 return regmap_clear_bits(st->map, LTC4282_FAULT_LOG, 840 LTC4282_FET_FAILURE_FAULT_MASK); 841 842 return regmap_clear_bits(st->map, LTC4282_FAULT_LOG, 843 LTC4282_VDD_FAULT_MASK); 844 } 845 846 /* 847 * We need to mux between VSOURCE and VDD which means they are mutually 848 * exclusive. Moreover, we can't really disable both VDD and VSOURCE as the ADC 849 * is continuously running (we cannot independently halt it without also 850 * stopping VGPIO). Hence, the logic is that disabling or enabling VDD will 851 * automatically have the reverse effect on VSOURCE and vice-versa. 852 */ 853 static int ltc4282_vdd_source_enable(struct ltc4282_state *st, int channel, 854 long val) 855 { 856 int ret, other_chan = ~channel & 0x1; 857 u8 __val = val; 858 859 guard(mutex)(&st->lock); 860 if (st->in0_1_cache[channel].en == !!val) 861 return 0; 862 863 /* clearing the bit makes the ADC to monitor VDD */ 864 if (channel == LTC4282_CHAN_VDD) 865 __val = !__val; 866 867 ret = regmap_update_bits(st->map, LTC4282_ILIM_ADJUST, 868 LTC4282_VDD_MONITOR_MASK, 869 FIELD_PREP(LTC4282_VDD_MONITOR_MASK, !!__val)); 870 if (ret) 871 return ret; 872 873 st->in0_1_cache[channel].en = !!val; 874 st->in0_1_cache[other_chan].en = !val; 875 876 if (st->in0_1_cache[channel].en) { 877 /* 878 * Then, we are disabling @other_chan. Let's save it's current 879 * history. 880 */ 881 ret = ltc4282_cache_history(st, other_chan); 882 if (ret) 883 return ret; 884 885 return ltc4282_cache_sync(st, channel); 886 } 887 /* 888 * Then, we are enabling @other_chan. We need to do the opposite from 889 * above. 890 */ 891 ret = ltc4282_cache_history(st, channel); 892 if (ret) 893 return ret; 894 895 return ltc4282_cache_sync(st, other_chan); 896 } 897 898 static int ltc4282_write_in(struct ltc4282_state *st, u32 attr, long val, 899 int channel) 900 { 901 switch (attr) { 902 case hwmon_in_max: 903 if (channel == LTC4282_CHAN_VGPIO) 904 return ltc4282_write_voltage_byte(st, LTC4282_VGPIO_MAX, 905 1280, val); 906 907 return ltc4282_vdd_source_write_lim(st, LTC4282_VSOURCE_MAX, 908 channel, 909 &st->in0_1_cache[channel].in_max_raw, val); 910 case hwmon_in_min: 911 if (channel == LTC4282_CHAN_VGPIO) 912 return ltc4282_write_voltage_byte(st, LTC4282_VGPIO_MIN, 913 1280, val); 914 915 return ltc4282_vdd_source_write_lim(st, LTC4282_VSOURCE_MIN, 916 channel, 917 &st->in0_1_cache[channel].in_min_raw, val); 918 case hwmon_in_reset_history: 919 if (channel == LTC4282_CHAN_VGPIO) 920 return ltc4282_in_write_history(st, 921 LTC4282_VGPIO_LOWEST, 922 1280, 0, 1280); 923 924 return ltc4282_vdd_source_reset_hist(st, channel); 925 case hwmon_in_enable: 926 return ltc4282_vdd_source_enable(st, channel, val); 927 default: 928 return -EOPNOTSUPP; 929 } 930 } 931 932 static int ltc4282_curr_reset_hist(struct ltc4282_state *st) 933 { 934 int ret; 935 936 guard(mutex)(&st->lock); 937 938 ret = __ltc4282_in_write_history(st, LTC4282_VSENSE_LOWEST, 939 st->vsense_max, 0, 40 * MILLI); 940 if (ret) 941 return ret; 942 943 /* now, let's also clear possible overcurrent fault logs */ 944 return regmap_clear_bits(st->map, LTC4282_FAULT_LOG, 945 LTC4282_OC_FAULT_MASK); 946 } 947 948 static int ltc4282_write_curr(struct ltc4282_state *st, u32 attr, 949 long val) 950 { 951 /* need to pass it in millivolt */ 952 u32 in = DIV_ROUND_CLOSEST_ULL((u64)val * st->rsense, DECA * MICRO); 953 954 switch (attr) { 955 case hwmon_curr_max: 956 return ltc4282_write_voltage_byte(st, LTC4282_VSENSE_MAX, 40, 957 in); 958 case hwmon_curr_min: 959 return ltc4282_write_voltage_byte(st, LTC4282_VSENSE_MIN, 40, 960 in); 961 case hwmon_curr_reset_history: 962 return ltc4282_curr_reset_hist(st); 963 default: 964 return -EOPNOTSUPP; 965 } 966 } 967 968 static int ltc4282_energy_enable_set(struct ltc4282_state *st, long val) 969 { 970 int ret; 971 972 guard(mutex)(&st->lock); 973 /* setting the bit halts the meter */ 974 ret = regmap_update_bits(st->map, LTC4282_ADC_CTRL, 975 LTC4282_METER_HALT_MASK, 976 FIELD_PREP(LTC4282_METER_HALT_MASK, !val)); 977 if (ret) 978 return ret; 979 980 st->energy_en = !!val; 981 982 return 0; 983 } 984 985 static int ltc4282_write(struct device *dev, 986 enum hwmon_sensor_types type, 987 u32 attr, int channel, long val) 988 { 989 struct ltc4282_state *st = dev_get_drvdata(dev); 990 991 switch (type) { 992 case hwmon_power: 993 return ltc4282_write_power(st, attr, val); 994 case hwmon_in: 995 return ltc4282_write_in(st, attr, val, channel); 996 case hwmon_curr: 997 return ltc4282_write_curr(st, attr, val); 998 case hwmon_energy: 999 return ltc4282_energy_enable_set(st, val); 1000 default: 1001 return -EOPNOTSUPP; 1002 } 1003 } 1004 1005 static umode_t ltc4282_in_is_visible(const struct ltc4282_state *st, u32 attr) 1006 { 1007 switch (attr) { 1008 case hwmon_in_input: 1009 case hwmon_in_highest: 1010 case hwmon_in_lowest: 1011 case hwmon_in_max_alarm: 1012 case hwmon_in_min_alarm: 1013 case hwmon_in_label: 1014 case hwmon_in_lcrit_alarm: 1015 case hwmon_in_crit_alarm: 1016 case hwmon_in_fault: 1017 return 0444; 1018 case hwmon_in_max: 1019 case hwmon_in_min: 1020 case hwmon_in_enable: 1021 case hwmon_in_reset_history: 1022 return 0644; 1023 default: 1024 return 0; 1025 } 1026 } 1027 1028 static umode_t ltc4282_curr_is_visible(u32 attr) 1029 { 1030 switch (attr) { 1031 case hwmon_curr_input: 1032 case hwmon_curr_highest: 1033 case hwmon_curr_lowest: 1034 case hwmon_curr_max_alarm: 1035 case hwmon_curr_min_alarm: 1036 case hwmon_curr_crit_alarm: 1037 case hwmon_curr_label: 1038 return 0444; 1039 case hwmon_curr_max: 1040 case hwmon_curr_min: 1041 case hwmon_curr_reset_history: 1042 return 0644; 1043 default: 1044 return 0; 1045 } 1046 } 1047 1048 static umode_t ltc4282_power_is_visible(u32 attr) 1049 { 1050 switch (attr) { 1051 case hwmon_power_input: 1052 case hwmon_power_input_highest: 1053 case hwmon_power_input_lowest: 1054 case hwmon_power_label: 1055 case hwmon_power_max_alarm: 1056 case hwmon_power_min_alarm: 1057 return 0444; 1058 case hwmon_power_max: 1059 case hwmon_power_min: 1060 case hwmon_power_reset_history: 1061 return 0644; 1062 default: 1063 return 0; 1064 } 1065 } 1066 1067 static umode_t ltc4282_is_visible(const void *data, 1068 enum hwmon_sensor_types type, 1069 u32 attr, int channel) 1070 { 1071 switch (type) { 1072 case hwmon_in: 1073 return ltc4282_in_is_visible(data, attr); 1074 case hwmon_curr: 1075 return ltc4282_curr_is_visible(attr); 1076 case hwmon_power: 1077 return ltc4282_power_is_visible(attr); 1078 case hwmon_energy: 1079 /* hwmon_energy_enable */ 1080 return 0644; 1081 default: 1082 return 0; 1083 } 1084 } 1085 1086 static const char * const ltc4282_in_strs[] = { 1087 "VSOURCE", "VDD", "VGPIO" 1088 }; 1089 1090 static int ltc4282_read_labels(struct device *dev, 1091 enum hwmon_sensor_types type, 1092 u32 attr, int channel, const char **str) 1093 { 1094 switch (type) { 1095 case hwmon_in: 1096 *str = ltc4282_in_strs[channel]; 1097 return 0; 1098 case hwmon_curr: 1099 *str = "ISENSE"; 1100 return 0; 1101 case hwmon_power: 1102 *str = "Power"; 1103 return 0; 1104 default: 1105 return -EOPNOTSUPP; 1106 } 1107 } 1108 1109 static ssize_t ltc4282_energy_show(struct device *dev, 1110 struct device_attribute *da, char *buf) 1111 { 1112 struct ltc4282_state *st = dev_get_drvdata(dev); 1113 u64 energy; 1114 int ret; 1115 1116 guard(mutex)(&st->lock); 1117 if (!st->energy_en) 1118 return -ENODATA; 1119 1120 ret = ltc4282_read_energy(st, &energy); 1121 if (ret < 0) 1122 return ret; 1123 1124 return sysfs_emit(buf, "%llu\n", energy); 1125 } 1126 1127 static const struct clk_ops ltc4282_ops = { 1128 .recalc_rate = ltc4282_recalc_rate, 1129 .determine_rate = ltc4282_determine_rate, 1130 .set_rate = ltc4282_set_rate, 1131 .disable = ltc4282_disable, 1132 }; 1133 1134 static int ltc428_clk_provider_setup(struct ltc4282_state *st, 1135 struct device *dev) 1136 { 1137 struct clk_init_data init; 1138 int ret; 1139 1140 if (!IS_ENABLED(CONFIG_COMMON_CLK)) 1141 return 0; 1142 1143 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s-clk", 1144 fwnode_get_name(dev_fwnode(dev))); 1145 if (!init.name) 1146 return -ENOMEM; 1147 1148 init.ops = <c4282_ops; 1149 init.flags = CLK_GET_RATE_NOCACHE; 1150 st->clk_hw.init = &init; 1151 1152 ret = devm_clk_hw_register(dev, &st->clk_hw); 1153 if (ret) 1154 return ret; 1155 1156 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 1157 &st->clk_hw); 1158 } 1159 1160 static int ltc428_clks_setup(struct ltc4282_state *st, struct device *dev) 1161 { 1162 unsigned long rate; 1163 struct clk *clkin; 1164 u32 val; 1165 int ret; 1166 1167 ret = ltc428_clk_provider_setup(st, dev); 1168 if (ret) 1169 return ret; 1170 1171 clkin = devm_clk_get_optional_enabled(dev, NULL); 1172 if (IS_ERR(clkin)) 1173 return dev_err_probe(dev, PTR_ERR(clkin), 1174 "Failed to get clkin"); 1175 if (!clkin) 1176 return 0; 1177 1178 rate = clk_get_rate(clkin); 1179 if (!in_range(rate, LTC4282_CLKIN_MIN, LTC4282_CLKIN_RANGE)) 1180 return dev_err_probe(dev, -EINVAL, 1181 "Invalid clkin range(%lu) [%lu %lu]\n", 1182 rate, LTC4282_CLKIN_MIN, 1183 LTC4282_CLKIN_MAX); 1184 1185 /* 1186 * Clocks faster than 250KHZ should be reduced to 250KHZ. The clock 1187 * frequency is divided by twice the value in the register. 1188 */ 1189 val = rate / (2 * LTC4282_CLKIN_MIN); 1190 1191 return regmap_update_bits(st->map, LTC4282_CLK_DIV, 1192 LTC4282_CLK_DIV_MASK, 1193 FIELD_PREP(LTC4282_CLK_DIV_MASK, val)); 1194 } 1195 1196 static const int ltc4282_curr_lim_uv[] = { 1197 12500, 15625, 18750, 21875, 25000, 28125, 31250, 34375 1198 }; 1199 1200 static int ltc4282_get_defaults(struct ltc4282_state *st, u32 *vin_mode) 1201 { 1202 u32 reg_val, ilm_adjust; 1203 int ret; 1204 1205 ret = regmap_read(st->map, LTC4282_ADC_CTRL, ®_val); 1206 if (ret) 1207 return ret; 1208 1209 st->energy_en = !FIELD_GET(LTC4282_METER_HALT_MASK, reg_val); 1210 1211 ret = regmap_read(st->map, LTC4282_CTRL_MSB, ®_val); 1212 if (ret) 1213 return ret; 1214 1215 *vin_mode = FIELD_GET(LTC4282_CTRL_VIN_MODE_MASK, reg_val); 1216 1217 ret = regmap_read(st->map, LTC4282_ILIM_ADJUST, ®_val); 1218 if (ret) 1219 return ret; 1220 1221 ilm_adjust = FIELD_GET(LTC4282_ILIM_ADJUST_MASK, reg_val); 1222 st->vsense_max = ltc4282_curr_lim_uv[ilm_adjust]; 1223 1224 st->in0_1_cache[LTC4282_CHAN_VSOURCE].en = FIELD_GET(LTC4282_VDD_MONITOR_MASK, 1225 ilm_adjust); 1226 if (!st->in0_1_cache[LTC4282_CHAN_VSOURCE].en) { 1227 st->in0_1_cache[LTC4282_CHAN_VDD].en = true; 1228 return regmap_read(st->map, LTC4282_VSOURCE_MAX, 1229 &st->in0_1_cache[LTC4282_CHAN_VSOURCE].in_max_raw); 1230 } 1231 1232 return regmap_read(st->map, LTC4282_VSOURCE_MAX, 1233 &st->in0_1_cache[LTC4282_CHAN_VDD].in_max_raw); 1234 } 1235 1236 /* 1237 * Set max limits for ISENSE and Power as that depends on the max voltage on 1238 * rsense that is defined in ILIM_ADJUST. This is specially important for power 1239 * because for some rsense and vfsout values, if we allow the default raw 255 1240 * value, that would overflow long in 32bit archs when reading back the max 1241 * power limit. 1242 * 1243 * Also set meaningful historic values for VDD and VSOURCE 1244 * (0 would not mean much). 1245 */ 1246 static int ltc4282_set_max_limits(struct ltc4282_state *st) 1247 { 1248 int ret; 1249 1250 ret = ltc4282_write_voltage_byte(st, LTC4282_VSENSE_MAX, 40 * MILLI, 1251 st->vsense_max); 1252 if (ret) 1253 return ret; 1254 1255 /* Power is given by ISENSE * Vout. */ 1256 st->power_max = DIV_ROUND_CLOSEST(st->vsense_max * DECA * MILLI, st->rsense) * st->vfs_out; 1257 ret = ltc4282_write_power_byte(st, LTC4282_POWER_MAX, st->power_max); 1258 if (ret) 1259 return ret; 1260 1261 if (st->in0_1_cache[LTC4282_CHAN_VDD].en) { 1262 st->in0_1_cache[LTC4282_CHAN_VSOURCE].in_lowest = st->vfs_out; 1263 return __ltc4282_in_write_history(st, LTC4282_VSOURCE_LOWEST, 1264 st->vdd, 0, st->vfs_out); 1265 } 1266 1267 st->in0_1_cache[LTC4282_CHAN_VDD].in_lowest = st->vdd; 1268 return __ltc4282_in_write_history(st, LTC4282_VSOURCE_LOWEST, 1269 st->vfs_out, 0, st->vfs_out); 1270 } 1271 1272 static const char * const ltc4282_gpio1_modes[] = { 1273 "power_bad", "power_good" 1274 }; 1275 1276 static const char * const ltc4282_gpio2_modes[] = { 1277 "adc_input", "stress_fet" 1278 }; 1279 1280 static int ltc4282_gpio_setup(struct ltc4282_state *st, struct device *dev) 1281 { 1282 const char *func = NULL; 1283 int ret; 1284 1285 ret = device_property_read_string(dev, "adi,gpio1-mode", &func); 1286 if (!ret) { 1287 ret = match_string(ltc4282_gpio1_modes, 1288 ARRAY_SIZE(ltc4282_gpio1_modes), func); 1289 if (ret < 0) 1290 return dev_err_probe(dev, ret, 1291 "Invalid func(%s) for gpio1\n", 1292 func); 1293 1294 ret = regmap_update_bits(st->map, LTC4282_GPIO_CONFIG, 1295 LTC4282_GPIO_1_CONFIG_MASK, 1296 FIELD_PREP(LTC4282_GPIO_1_CONFIG_MASK, ret)); 1297 if (ret) 1298 return ret; 1299 } 1300 1301 ret = device_property_read_string(dev, "adi,gpio2-mode", &func); 1302 if (!ret) { 1303 ret = match_string(ltc4282_gpio2_modes, 1304 ARRAY_SIZE(ltc4282_gpio2_modes), func); 1305 if (ret < 0) 1306 return dev_err_probe(dev, ret, 1307 "Invalid func(%s) for gpio2\n", 1308 func); 1309 if (!ret) { 1310 /* setting the bit to 1 so the ADC to monitors GPIO2 */ 1311 ret = regmap_set_bits(st->map, LTC4282_ILIM_ADJUST, 1312 LTC4282_GPIO_MODE_MASK); 1313 } else { 1314 ret = regmap_update_bits(st->map, LTC4282_GPIO_CONFIG, 1315 LTC4282_GPIO_2_FET_STRESS_MASK, 1316 FIELD_PREP(LTC4282_GPIO_2_FET_STRESS_MASK, 1)); 1317 } 1318 1319 if (ret) 1320 return ret; 1321 } 1322 1323 if (!device_property_read_bool(dev, "adi,gpio3-monitor-enable")) 1324 return 0; 1325 1326 if (func && !strcmp(func, "adc_input")) 1327 return dev_err_probe(dev, -EINVAL, 1328 "Cannot have both gpio2 and gpio3 muxed into the ADC"); 1329 1330 return regmap_clear_bits(st->map, LTC4282_ILIM_ADJUST, 1331 LTC4282_GPIO_MODE_MASK); 1332 } 1333 1334 static const char * const ltc4282_dividers[] = { 1335 "external", "vdd_5_percent", "vdd_10_percent", "vdd_15_percent" 1336 }; 1337 1338 /* This maps the Vout full scale for the given Vin mode */ 1339 static const u16 ltc4282_vfs_milli[] = { 5540, 8320, 16640, 33280 }; 1340 1341 static const u16 ltc4282_vdd_milli[] = { 3300, 5000, 12000, 24000 }; 1342 1343 enum { 1344 LTC4282_VIN_3_3V, 1345 LTC4282_VIN_5V, 1346 LTC4282_VIN_12V, 1347 LTC4282_VIN_24V, 1348 }; 1349 1350 static int ltc4282_setup(struct ltc4282_state *st, struct device *dev) 1351 { 1352 const char *divider; 1353 u32 val, vin_mode; 1354 int ret; 1355 1356 /* The part has an eeprom so let's get the needed defaults from it */ 1357 ret = ltc4282_get_defaults(st, &vin_mode); 1358 if (ret) 1359 return ret; 1360 1361 ret = device_property_read_u32(dev, "adi,rsense-nano-ohms", 1362 &st->rsense); 1363 if (ret) 1364 return dev_err_probe(dev, ret, 1365 "Failed to read adi,rsense-nano-ohms\n"); 1366 if (st->rsense < CENTI) 1367 return dev_err_probe(dev, -EINVAL, 1368 "adi,rsense-nano-ohms too small (< %lu)\n", 1369 CENTI); 1370 1371 /* 1372 * The resolution for rsense is tenths of micro (eg: 62.5 uOhm) which 1373 * means we need nano in the bindings. However, to make things easier to 1374 * handle (with respect to overflows) we divide it by 100 as we don't 1375 * really need the last two digits. 1376 */ 1377 st->rsense /= CENTI; 1378 1379 val = vin_mode; 1380 ret = device_property_read_u32(dev, "adi,vin-mode-microvolt", &val); 1381 if (!ret) { 1382 switch (val) { 1383 case 3300000: 1384 val = LTC4282_VIN_3_3V; 1385 break; 1386 case 5000000: 1387 val = LTC4282_VIN_5V; 1388 break; 1389 case 12000000: 1390 val = LTC4282_VIN_12V; 1391 break; 1392 case 24000000: 1393 val = LTC4282_VIN_24V; 1394 break; 1395 default: 1396 return dev_err_probe(dev, -EINVAL, 1397 "Invalid val(%u) for vin-mode-microvolt\n", 1398 val); 1399 } 1400 1401 ret = regmap_update_bits(st->map, LTC4282_CTRL_MSB, 1402 LTC4282_CTRL_VIN_MODE_MASK, 1403 FIELD_PREP(LTC4282_CTRL_VIN_MODE_MASK, val)); 1404 if (ret) 1405 return ret; 1406 1407 /* Foldback mode should also be set to the input voltage */ 1408 ret = regmap_update_bits(st->map, LTC4282_ILIM_ADJUST, 1409 LTC4282_FOLDBACK_MODE_MASK, 1410 FIELD_PREP(LTC4282_FOLDBACK_MODE_MASK, val)); 1411 if (ret) 1412 return ret; 1413 } 1414 1415 st->vfs_out = ltc4282_vfs_milli[val]; 1416 st->vdd = ltc4282_vdd_milli[val]; 1417 1418 ret = device_property_read_u32(dev, "adi,current-limit-sense-microvolt", 1419 &st->vsense_max); 1420 if (!ret) { 1421 int reg_val; 1422 1423 switch (val) { 1424 case 12500: 1425 reg_val = 0; 1426 break; 1427 case 15625: 1428 reg_val = 1; 1429 break; 1430 case 18750: 1431 reg_val = 2; 1432 break; 1433 case 21875: 1434 reg_val = 3; 1435 break; 1436 case 25000: 1437 reg_val = 4; 1438 break; 1439 case 28125: 1440 reg_val = 5; 1441 break; 1442 case 31250: 1443 reg_val = 6; 1444 break; 1445 case 34375: 1446 reg_val = 7; 1447 break; 1448 default: 1449 return dev_err_probe(dev, -EINVAL, 1450 "Invalid val(%u) for adi,current-limit-microvolt\n", 1451 st->vsense_max); 1452 } 1453 1454 ret = regmap_update_bits(st->map, LTC4282_ILIM_ADJUST, 1455 LTC4282_ILIM_ADJUST_MASK, 1456 FIELD_PREP(LTC4282_ILIM_ADJUST_MASK, reg_val)); 1457 if (ret) 1458 return ret; 1459 } 1460 1461 ret = ltc4282_set_max_limits(st); 1462 if (ret) 1463 return ret; 1464 1465 ret = device_property_read_string(dev, "adi,overvoltage-dividers", 1466 ÷r); 1467 if (!ret) { 1468 int div = match_string(ltc4282_dividers, 1469 ARRAY_SIZE(ltc4282_dividers), divider); 1470 if (div < 0) 1471 return dev_err_probe(dev, -EINVAL, 1472 "Invalid val(%s) for adi,overvoltage-divider\n", 1473 divider); 1474 1475 ret = regmap_update_bits(st->map, LTC4282_CTRL_MSB, 1476 LTC4282_CTRL_OV_MODE_MASK, 1477 FIELD_PREP(LTC4282_CTRL_OV_MODE_MASK, div)); 1478 } 1479 1480 ret = device_property_read_string(dev, "adi,undervoltage-dividers", 1481 ÷r); 1482 if (!ret) { 1483 int div = match_string(ltc4282_dividers, 1484 ARRAY_SIZE(ltc4282_dividers), divider); 1485 if (div < 0) 1486 return dev_err_probe(dev, -EINVAL, 1487 "Invalid val(%s) for adi,undervoltage-divider\n", 1488 divider); 1489 1490 ret = regmap_update_bits(st->map, LTC4282_CTRL_MSB, 1491 LTC4282_CTRL_UV_MODE_MASK, 1492 FIELD_PREP(LTC4282_CTRL_UV_MODE_MASK, div)); 1493 } 1494 1495 if (device_property_read_bool(dev, "adi,overcurrent-retry")) { 1496 ret = regmap_set_bits(st->map, LTC4282_CTRL_LSB, 1497 LTC4282_CTRL_OC_RETRY_MASK); 1498 if (ret) 1499 return ret; 1500 } 1501 1502 if (device_property_read_bool(dev, "adi,overvoltage-retry-disable")) { 1503 ret = regmap_clear_bits(st->map, LTC4282_CTRL_LSB, 1504 LTC4282_CTRL_OV_RETRY_MASK); 1505 if (ret) 1506 return ret; 1507 } 1508 1509 if (device_property_read_bool(dev, "adi,undervoltage-retry-disable")) { 1510 ret = regmap_clear_bits(st->map, LTC4282_CTRL_LSB, 1511 LTC4282_CTRL_UV_RETRY_MASK); 1512 if (ret) 1513 return ret; 1514 } 1515 1516 if (device_property_read_bool(dev, "adi,fault-log-enable")) { 1517 ret = regmap_set_bits(st->map, LTC4282_ADC_CTRL, LTC4282_FAULT_LOG_EN_MASK); 1518 if (ret) 1519 return ret; 1520 } 1521 1522 ret = device_property_read_u32(dev, "adi,fet-bad-timeout-ms", &val); 1523 if (!ret) { 1524 if (val > LTC4282_FET_BAD_MAX_TIMEOUT) 1525 return dev_err_probe(dev, -EINVAL, 1526 "Invalid value(%u) for adi,fet-bad-timeout-ms", 1527 val); 1528 1529 ret = regmap_write(st->map, LTC4282_FET_BAD_FAULT_TIMEOUT, val); 1530 if (ret) 1531 return ret; 1532 } 1533 1534 return ltc4282_gpio_setup(st, dev); 1535 } 1536 1537 static bool ltc4282_readable_reg(struct device *dev, unsigned int reg) 1538 { 1539 if (reg == LTC4282_RESERVED_1 || reg == LTC4282_RESERVED_2) 1540 return false; 1541 1542 return true; 1543 } 1544 1545 static bool ltc4282_writable_reg(struct device *dev, unsigned int reg) 1546 { 1547 if (reg == LTC4282_STATUS_LSB || reg == LTC4282_STATUS_MSB) 1548 return false; 1549 if (reg == LTC4282_RESERVED_1 || reg == LTC4282_RESERVED_2) 1550 return false; 1551 1552 return true; 1553 } 1554 1555 static const struct regmap_config ltc4282_regmap_config = { 1556 .reg_bits = 8, 1557 .val_bits = 8, 1558 .max_register = LTC4282_RESERVED_3, 1559 .readable_reg = ltc4282_readable_reg, 1560 .writeable_reg = ltc4282_writable_reg, 1561 }; 1562 1563 static const struct hwmon_channel_info * const ltc4282_info[] = { 1564 HWMON_CHANNEL_INFO(in, 1565 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1566 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1567 HWMON_I_MAX_ALARM | HWMON_I_ENABLE | 1568 HWMON_I_RESET_HISTORY | HWMON_I_FAULT | 1569 HWMON_I_LABEL, 1570 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1571 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1572 HWMON_I_MAX_ALARM | HWMON_I_LCRIT_ALARM | 1573 HWMON_I_CRIT_ALARM | HWMON_I_ENABLE | 1574 HWMON_I_RESET_HISTORY | HWMON_I_LABEL, 1575 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1576 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1577 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1578 HWMON_I_LABEL), 1579 HWMON_CHANNEL_INFO(curr, 1580 HWMON_C_INPUT | HWMON_C_LOWEST | HWMON_C_HIGHEST | 1581 HWMON_C_MAX | HWMON_C_MIN | HWMON_C_MIN_ALARM | 1582 HWMON_C_MAX_ALARM | HWMON_C_CRIT_ALARM | 1583 HWMON_C_RESET_HISTORY | HWMON_C_LABEL), 1584 HWMON_CHANNEL_INFO(power, 1585 HWMON_P_INPUT | HWMON_P_INPUT_LOWEST | 1586 HWMON_P_INPUT_HIGHEST | HWMON_P_MAX | HWMON_P_MIN | 1587 HWMON_P_MAX_ALARM | HWMON_P_MIN_ALARM | 1588 HWMON_P_RESET_HISTORY | HWMON_P_LABEL), 1589 HWMON_CHANNEL_INFO(energy, 1590 HWMON_E_ENABLE), 1591 NULL 1592 }; 1593 1594 static const struct hwmon_ops ltc4282_hwmon_ops = { 1595 .read = ltc4282_read, 1596 .write = ltc4282_write, 1597 .is_visible = ltc4282_is_visible, 1598 .read_string = ltc4282_read_labels, 1599 }; 1600 1601 static const struct hwmon_chip_info ltc4282_chip_info = { 1602 .ops = <c4282_hwmon_ops, 1603 .info = ltc4282_info, 1604 }; 1605 1606 /* energy attributes are 6bytes wide so we need u64 */ 1607 static SENSOR_DEVICE_ATTR_RO(energy1_input, ltc4282_energy, 0); 1608 1609 static struct attribute *ltc4282_attrs[] = { 1610 &sensor_dev_attr_energy1_input.dev_attr.attr, 1611 NULL 1612 }; 1613 ATTRIBUTE_GROUPS(ltc4282); 1614 1615 static int ltc4282_show_fault_log(void *arg, u64 *val, u32 mask) 1616 { 1617 struct ltc4282_state *st = arg; 1618 long alarm; 1619 int ret; 1620 1621 ret = ltc4282_read_alarm(st, LTC4282_FAULT_LOG, mask, &alarm); 1622 if (ret) 1623 return ret; 1624 1625 *val = alarm; 1626 1627 return 0; 1628 } 1629 1630 static int ltc4282_show_curr1_crit_fault_log(void *arg, u64 *val) 1631 { 1632 return ltc4282_show_fault_log(arg, val, LTC4282_OC_FAULT_MASK); 1633 } 1634 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_curr1_crit_fault_log, 1635 ltc4282_show_curr1_crit_fault_log, NULL, "%llu\n"); 1636 1637 static int ltc4282_show_in1_lcrit_fault_log(void *arg, u64 *val) 1638 { 1639 return ltc4282_show_fault_log(arg, val, LTC4282_UV_FAULT_MASK); 1640 } 1641 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_in1_lcrit_fault_log, 1642 ltc4282_show_in1_lcrit_fault_log, NULL, "%llu\n"); 1643 1644 static int ltc4282_show_in1_crit_fault_log(void *arg, u64 *val) 1645 { 1646 return ltc4282_show_fault_log(arg, val, LTC4282_OV_FAULT_MASK); 1647 } 1648 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_in1_crit_fault_log, 1649 ltc4282_show_in1_crit_fault_log, NULL, "%llu\n"); 1650 1651 static int ltc4282_show_fet_bad_fault_log(void *arg, u64 *val) 1652 { 1653 return ltc4282_show_fault_log(arg, val, LTC4282_FET_BAD_FAULT_MASK); 1654 } 1655 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_fet_bad_fault_log, 1656 ltc4282_show_fet_bad_fault_log, NULL, "%llu\n"); 1657 1658 static int ltc4282_show_fet_short_fault_log(void *arg, u64 *val) 1659 { 1660 return ltc4282_show_fault_log(arg, val, LTC4282_FET_SHORT_FAULT_MASK); 1661 } 1662 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_fet_short_fault_log, 1663 ltc4282_show_fet_short_fault_log, NULL, "%llu\n"); 1664 1665 static int ltc4282_show_power1_bad_fault_log(void *arg, u64 *val) 1666 { 1667 return ltc4282_show_fault_log(arg, val, LTC4282_POWER_BAD_FAULT_MASK); 1668 } 1669 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_power1_bad_fault_log, 1670 ltc4282_show_power1_bad_fault_log, NULL, "%llu\n"); 1671 1672 static void ltc4282_debugfs_init(struct ltc4282_state *st, struct i2c_client *i2c) 1673 { 1674 debugfs_create_file_unsafe("power1_bad_fault_log", 0400, i2c->debugfs, st, 1675 <c4282_power1_bad_fault_log); 1676 debugfs_create_file_unsafe("in0_fet_short_fault_log", 0400, i2c->debugfs, st, 1677 <c4282_fet_short_fault_log); 1678 debugfs_create_file_unsafe("in0_fet_bad_fault_log", 0400, i2c->debugfs, st, 1679 <c4282_fet_bad_fault_log); 1680 debugfs_create_file_unsafe("in1_crit_fault_log", 0400, i2c->debugfs, st, 1681 <c4282_in1_crit_fault_log); 1682 debugfs_create_file_unsafe("in1_lcrit_fault_log", 0400, i2c->debugfs, st, 1683 <c4282_in1_lcrit_fault_log); 1684 debugfs_create_file_unsafe("curr1_crit_fault_log", 0400, i2c->debugfs, st, 1685 <c4282_curr1_crit_fault_log); 1686 } 1687 1688 static int ltc4282_probe(struct i2c_client *i2c) 1689 { 1690 struct device *dev = &i2c->dev, *hwmon; 1691 struct ltc4282_state *st; 1692 int ret; 1693 1694 st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL); 1695 if (!st) 1696 return dev_err_probe(dev, -ENOMEM, 1697 "Failed to allocate memory\n"); 1698 1699 st->map = devm_regmap_init_i2c(i2c, <c4282_regmap_config); 1700 if (IS_ERR(st->map)) 1701 return dev_err_probe(dev, PTR_ERR(st->map), 1702 "failed regmap init\n"); 1703 1704 /* Soft reset */ 1705 ret = regmap_set_bits(st->map, LTC4282_ADC_CTRL, LTC4282_RESET_MASK); 1706 if (ret) 1707 return ret; 1708 1709 /* Yes, it's big but it is as specified in the datasheet */ 1710 msleep(3200); 1711 1712 ret = ltc428_clks_setup(st, dev); 1713 if (ret) 1714 return ret; 1715 1716 ret = ltc4282_setup(st, dev); 1717 if (ret) 1718 return ret; 1719 1720 mutex_init(&st->lock); 1721 hwmon = devm_hwmon_device_register_with_info(dev, "ltc4282", st, 1722 <c4282_chip_info, 1723 ltc4282_groups); 1724 if (IS_ERR(hwmon)) 1725 return PTR_ERR(hwmon); 1726 1727 ltc4282_debugfs_init(st, i2c); 1728 1729 return 0; 1730 } 1731 1732 static const struct of_device_id ltc4282_of_match[] = { 1733 { .compatible = "adi,ltc4282" }, 1734 {} 1735 }; 1736 MODULE_DEVICE_TABLE(of, ltc4282_of_match); 1737 1738 static struct i2c_driver ltc4282_driver = { 1739 .driver = { 1740 .name = "ltc4282", 1741 .of_match_table = ltc4282_of_match, 1742 }, 1743 .probe = ltc4282_probe, 1744 }; 1745 module_i2c_driver(ltc4282_driver); 1746 1747 MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>"); 1748 MODULE_DESCRIPTION("LTC4282 I2C High Current Hot Swap Controller"); 1749 MODULE_LICENSE("GPL"); 1750