1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MIPI Display Bus Interface (DBI) LCD controller support 4 * 5 * Copyright 2016 Noralf Trønnes 6 */ 7 8 #include <linux/backlight.h> 9 #include <linux/debugfs.h> 10 #include <linux/delay.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/module.h> 13 #include <linux/regulator/consumer.h> 14 #include <linux/spi/spi.h> 15 16 #include <drm/drm_connector.h> 17 #include <drm/drm_damage_helper.h> 18 #include <drm/drm_drv.h> 19 #include <drm/drm_file.h> 20 #include <drm/drm_format_helper.h> 21 #include <drm/drm_fourcc.h> 22 #include <drm/drm_framebuffer.h> 23 #include <drm/drm_gem.h> 24 #include <drm/drm_gem_atomic_helper.h> 25 #include <drm/drm_gem_framebuffer_helper.h> 26 #include <drm/drm_mipi_dbi.h> 27 #include <drm/drm_modes.h> 28 #include <drm/drm_probe_helper.h> 29 #include <drm/drm_rect.h> 30 #include <video/mipi_display.h> 31 32 #define MIPI_DBI_MAX_SPI_READ_SPEED 2000000 /* 2MHz */ 33 34 #define DCS_POWER_MODE_DISPLAY BIT(2) 35 #define DCS_POWER_MODE_DISPLAY_NORMAL_MODE BIT(3) 36 #define DCS_POWER_MODE_SLEEP_MODE BIT(4) 37 #define DCS_POWER_MODE_PARTIAL_MODE BIT(5) 38 #define DCS_POWER_MODE_IDLE_MODE BIT(6) 39 #define DCS_POWER_MODE_RESERVED_MASK (BIT(0) | BIT(1) | BIT(7)) 40 41 /** 42 * DOC: overview 43 * 44 * This library provides helpers for MIPI Display Bus Interface (DBI) 45 * compatible display controllers. 46 * 47 * Many controllers for tiny lcd displays are MIPI compliant and can use this 48 * library. If a controller uses registers 0x2A and 0x2B to set the area to 49 * update and uses register 0x2C to write to frame memory, it is most likely 50 * MIPI compliant. 51 * 52 * Only MIPI Type 1 displays are supported since a full frame memory is needed. 53 * 54 * There are 3 MIPI DBI implementation types: 55 * 56 * A. Motorola 6800 type parallel bus 57 * 58 * B. Intel 8080 type parallel bus 59 * 60 * C. SPI type with 3 options: 61 * 62 * 1. 9-bit with the Data/Command signal as the ninth bit 63 * 2. Same as above except it's sent as 16 bits 64 * 3. 8-bit with the Data/Command signal as a separate D/CX pin 65 * 66 * Currently mipi_dbi only supports Type C options 1 and 3 with 67 * mipi_dbi_spi_init(). 68 */ 69 70 #define MIPI_DBI_DEBUG_COMMAND(cmd, data, len) \ 71 ({ \ 72 if (!len) \ 73 DRM_DEBUG_DRIVER("cmd=%02x\n", cmd); \ 74 else if (len <= 32) \ 75 DRM_DEBUG_DRIVER("cmd=%02x, par=%*ph\n", cmd, (int)len, data);\ 76 else \ 77 DRM_DEBUG_DRIVER("cmd=%02x, len=%zu\n", cmd, len); \ 78 }) 79 80 static const u8 mipi_dbi_dcs_read_commands[] = { 81 MIPI_DCS_GET_DISPLAY_ID, 82 MIPI_DCS_GET_RED_CHANNEL, 83 MIPI_DCS_GET_GREEN_CHANNEL, 84 MIPI_DCS_GET_BLUE_CHANNEL, 85 MIPI_DCS_GET_DISPLAY_STATUS, 86 MIPI_DCS_GET_POWER_MODE, 87 MIPI_DCS_GET_ADDRESS_MODE, 88 MIPI_DCS_GET_PIXEL_FORMAT, 89 MIPI_DCS_GET_DISPLAY_MODE, 90 MIPI_DCS_GET_SIGNAL_MODE, 91 MIPI_DCS_GET_DIAGNOSTIC_RESULT, 92 MIPI_DCS_READ_MEMORY_START, 93 MIPI_DCS_READ_MEMORY_CONTINUE, 94 MIPI_DCS_GET_SCANLINE, 95 MIPI_DCS_GET_DISPLAY_BRIGHTNESS, 96 MIPI_DCS_GET_CONTROL_DISPLAY, 97 MIPI_DCS_GET_POWER_SAVE, 98 MIPI_DCS_GET_CABC_MIN_BRIGHTNESS, 99 MIPI_DCS_READ_DDB_START, 100 MIPI_DCS_READ_DDB_CONTINUE, 101 0, /* sentinel */ 102 }; 103 104 static bool mipi_dbi_command_is_read(struct mipi_dbi *dbi, u8 cmd) 105 { 106 unsigned int i; 107 108 if (!dbi->read_commands) 109 return false; 110 111 for (i = 0; i < 0xff; i++) { 112 if (!dbi->read_commands[i]) 113 return false; 114 if (cmd == dbi->read_commands[i]) 115 return true; 116 } 117 118 return false; 119 } 120 121 /** 122 * mipi_dbi_command_read - MIPI DCS read command 123 * @dbi: MIPI DBI structure 124 * @cmd: Command 125 * @val: Value read 126 * 127 * Send MIPI DCS read command to the controller. 128 * 129 * Returns: 130 * Zero on success, negative error code on failure. 131 */ 132 int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val) 133 { 134 if (!dbi->read_commands) 135 return -EACCES; 136 137 if (!mipi_dbi_command_is_read(dbi, cmd)) 138 return -EINVAL; 139 140 return mipi_dbi_command_buf(dbi, cmd, val, 1); 141 } 142 EXPORT_SYMBOL(mipi_dbi_command_read); 143 144 /** 145 * mipi_dbi_command_buf - MIPI DCS command with parameter(s) in an array 146 * @dbi: MIPI DBI structure 147 * @cmd: Command 148 * @data: Parameter buffer 149 * @len: Buffer length 150 * 151 * Returns: 152 * Zero on success, negative error code on failure. 153 */ 154 int mipi_dbi_command_buf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len) 155 { 156 u8 *cmdbuf; 157 int ret; 158 159 /* SPI requires dma-safe buffers */ 160 cmdbuf = kmemdup(&cmd, 1, GFP_KERNEL); 161 if (!cmdbuf) 162 return -ENOMEM; 163 164 mutex_lock(&dbi->cmdlock); 165 ret = dbi->command(dbi, cmdbuf, data, len); 166 mutex_unlock(&dbi->cmdlock); 167 168 kfree(cmdbuf); 169 170 return ret; 171 } 172 EXPORT_SYMBOL(mipi_dbi_command_buf); 173 174 /* This should only be used by mipi_dbi_command() */ 175 int mipi_dbi_command_stackbuf(struct mipi_dbi *dbi, u8 cmd, const u8 *data, 176 size_t len) 177 { 178 u8 *buf; 179 int ret; 180 181 buf = kmemdup(data, len, GFP_KERNEL); 182 if (!buf) 183 return -ENOMEM; 184 185 ret = mipi_dbi_command_buf(dbi, cmd, buf, len); 186 187 kfree(buf); 188 189 return ret; 190 } 191 EXPORT_SYMBOL(mipi_dbi_command_stackbuf); 192 193 /** 194 * mipi_dbi_buf_copy - Copy a framebuffer, transforming it if necessary 195 * @dst: The destination buffer 196 * @src: The source buffer 197 * @fb: The source framebuffer 198 * @clip: Clipping rectangle of the area to be copied 199 * @swap: When true, swap MSB/LSB of 16-bit values 200 * @fmtcnv_state: Format-conversion state 201 * 202 * Returns: 203 * Zero on success, negative error code on failure. 204 */ 205 int mipi_dbi_buf_copy(void *dst, struct iosys_map *src, struct drm_framebuffer *fb, 206 struct drm_rect *clip, bool swap, 207 struct drm_format_conv_state *fmtcnv_state) 208 { 209 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev); 210 struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0); 211 struct iosys_map dst_map = IOSYS_MAP_INIT_VADDR(dst); 212 int ret; 213 214 ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE); 215 if (ret) 216 return ret; 217 218 switch (fb->format->format) { 219 case DRM_FORMAT_RGB565: 220 if (swap) 221 drm_fb_swab(&dst_map, NULL, src, fb, clip, !drm_gem_is_imported(gem), 222 fmtcnv_state); 223 else 224 drm_fb_memcpy(&dst_map, NULL, src, fb, clip); 225 break; 226 case DRM_FORMAT_RGB888: 227 drm_fb_memcpy(&dst_map, NULL, src, fb, clip); 228 break; 229 case DRM_FORMAT_XRGB8888: 230 switch (dbidev->pixel_format) { 231 case DRM_FORMAT_RGB565: 232 drm_fb_xrgb8888_to_rgb565(&dst_map, NULL, src, fb, clip, fmtcnv_state, swap); 233 break; 234 case DRM_FORMAT_RGB888: 235 drm_fb_xrgb8888_to_rgb888(&dst_map, NULL, src, fb, clip, fmtcnv_state); 236 break; 237 } 238 break; 239 default: 240 drm_err_once(fb->dev, "Format is not supported: %p4cc\n", 241 &fb->format->format); 242 ret = -EINVAL; 243 } 244 245 drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE); 246 247 return ret; 248 } 249 EXPORT_SYMBOL(mipi_dbi_buf_copy); 250 251 static void mipi_dbi_set_window_address(struct mipi_dbi_dev *dbidev, 252 unsigned int xs, unsigned int xe, 253 unsigned int ys, unsigned int ye) 254 { 255 struct mipi_dbi *dbi = &dbidev->dbi; 256 257 xs += dbidev->left_offset; 258 xe += dbidev->left_offset; 259 ys += dbidev->top_offset; 260 ye += dbidev->top_offset; 261 262 mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, (xs >> 8) & 0xff, 263 xs & 0xff, (xe >> 8) & 0xff, xe & 0xff); 264 mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, (ys >> 8) & 0xff, 265 ys & 0xff, (ye >> 8) & 0xff, ye & 0xff); 266 } 267 268 static void mipi_dbi_fb_dirty(struct iosys_map *src, struct drm_framebuffer *fb, 269 struct drm_rect *rect, struct drm_format_conv_state *fmtcnv_state) 270 { 271 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev); 272 unsigned int height = rect->y2 - rect->y1; 273 unsigned int width = rect->x2 - rect->x1; 274 const struct drm_format_info *dst_format; 275 struct mipi_dbi *dbi = &dbidev->dbi; 276 bool swap = dbi->swap_bytes; 277 int ret = 0; 278 size_t len; 279 bool full; 280 void *tr; 281 282 full = width == fb->width && height == fb->height; 283 284 DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect)); 285 286 if (!dbi->dc || !full || swap || 287 fb->format->format == DRM_FORMAT_XRGB8888) { 288 tr = dbidev->tx_buf; 289 ret = mipi_dbi_buf_copy(tr, src, fb, rect, swap, fmtcnv_state); 290 if (ret) 291 goto err_msg; 292 } else { 293 tr = src->vaddr; /* TODO: Use mapping abstraction properly */ 294 } 295 296 mipi_dbi_set_window_address(dbidev, rect->x1, rect->x2 - 1, rect->y1, 297 rect->y2 - 1); 298 299 if (fb->format->format == DRM_FORMAT_XRGB8888) 300 dst_format = drm_format_info(dbidev->pixel_format); 301 else 302 dst_format = fb->format; 303 len = drm_format_info_min_pitch(dst_format, 0, width) * height; 304 305 ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, tr, len); 306 err_msg: 307 if (ret) 308 drm_err_once(fb->dev, "Failed to update display %d\n", ret); 309 } 310 311 /** 312 * mipi_dbi_pipe_mode_valid - MIPI DBI mode-valid helper 313 * @pipe: Simple display pipe 314 * @mode: The mode to test 315 * 316 * This function validates a given display mode against the MIPI DBI's hardware 317 * display. Drivers can use this as their &drm_simple_display_pipe_funcs->mode_valid 318 * callback. 319 */ 320 enum drm_mode_status mipi_dbi_pipe_mode_valid(struct drm_simple_display_pipe *pipe, 321 const struct drm_display_mode *mode) 322 { 323 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev); 324 325 return drm_crtc_helper_mode_valid_fixed(&pipe->crtc, mode, &dbidev->mode); 326 } 327 EXPORT_SYMBOL(mipi_dbi_pipe_mode_valid); 328 329 /** 330 * mipi_dbi_pipe_update - Display pipe update helper 331 * @pipe: Simple display pipe 332 * @old_state: Old plane state 333 * 334 * This function handles framebuffer flushing and vblank events. Drivers can use 335 * this as their &drm_simple_display_pipe_funcs->update callback. 336 */ 337 void mipi_dbi_pipe_update(struct drm_simple_display_pipe *pipe, 338 struct drm_plane_state *old_state) 339 { 340 struct drm_plane_state *state = pipe->plane.state; 341 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(state); 342 struct drm_framebuffer *fb = state->fb; 343 struct drm_rect rect; 344 int idx; 345 346 if (!pipe->crtc.state->active) 347 return; 348 349 if (WARN_ON(!fb)) 350 return; 351 352 if (!drm_dev_enter(fb->dev, &idx)) 353 return; 354 355 if (drm_atomic_helper_damage_merged(old_state, state, &rect)) 356 mipi_dbi_fb_dirty(&shadow_plane_state->data[0], fb, &rect, 357 &shadow_plane_state->fmtcnv_state); 358 359 drm_dev_exit(idx); 360 } 361 EXPORT_SYMBOL(mipi_dbi_pipe_update); 362 363 /** 364 * mipi_dbi_enable_flush - MIPI DBI enable helper 365 * @dbidev: MIPI DBI device structure 366 * @crtc_state: CRTC state 367 * @plane_state: Plane state 368 * 369 * Flushes the whole framebuffer and enables the backlight. Drivers can use this 370 * in their &drm_simple_display_pipe_funcs->enable callback. 371 * 372 * Note: Drivers which don't use mipi_dbi_pipe_update() because they have custom 373 * framebuffer flushing, can't use this function since they both use the same 374 * flushing code. 375 */ 376 void mipi_dbi_enable_flush(struct mipi_dbi_dev *dbidev, 377 struct drm_crtc_state *crtc_state, 378 struct drm_plane_state *plane_state) 379 { 380 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 381 struct drm_framebuffer *fb = plane_state->fb; 382 struct drm_rect rect = { 383 .x1 = 0, 384 .x2 = fb->width, 385 .y1 = 0, 386 .y2 = fb->height, 387 }; 388 int idx; 389 390 if (!drm_dev_enter(&dbidev->drm, &idx)) 391 return; 392 393 mipi_dbi_fb_dirty(&shadow_plane_state->data[0], fb, &rect, 394 &shadow_plane_state->fmtcnv_state); 395 backlight_enable(dbidev->backlight); 396 397 drm_dev_exit(idx); 398 } 399 EXPORT_SYMBOL(mipi_dbi_enable_flush); 400 401 static void mipi_dbi_blank(struct mipi_dbi_dev *dbidev) 402 { 403 struct drm_device *drm = &dbidev->drm; 404 u16 height = drm->mode_config.min_height; 405 u16 width = drm->mode_config.min_width; 406 struct mipi_dbi *dbi = &dbidev->dbi; 407 const struct drm_format_info *dst_format; 408 size_t len; 409 int idx; 410 411 if (!drm_dev_enter(drm, &idx)) 412 return; 413 414 dst_format = drm_format_info(dbidev->pixel_format); 415 len = drm_format_info_min_pitch(dst_format, 0, width) * height; 416 417 memset(dbidev->tx_buf, 0, len); 418 419 mipi_dbi_set_window_address(dbidev, 0, width - 1, 0, height - 1); 420 mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, 421 (u8 *)dbidev->tx_buf, len); 422 423 drm_dev_exit(idx); 424 } 425 426 /** 427 * mipi_dbi_pipe_disable - MIPI DBI pipe disable helper 428 * @pipe: Display pipe 429 * 430 * This function disables backlight if present, if not the display memory is 431 * blanked. The regulator is disabled if in use. Drivers can use this as their 432 * &drm_simple_display_pipe_funcs->disable callback. 433 */ 434 void mipi_dbi_pipe_disable(struct drm_simple_display_pipe *pipe) 435 { 436 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev); 437 438 DRM_DEBUG_KMS("\n"); 439 440 if (dbidev->backlight) 441 backlight_disable(dbidev->backlight); 442 else 443 mipi_dbi_blank(dbidev); 444 445 if (dbidev->regulator) 446 regulator_disable(dbidev->regulator); 447 if (dbidev->io_regulator) 448 regulator_disable(dbidev->io_regulator); 449 } 450 EXPORT_SYMBOL(mipi_dbi_pipe_disable); 451 452 /** 453 * mipi_dbi_pipe_begin_fb_access - MIPI DBI pipe begin-access helper 454 * @pipe: Display pipe 455 * @plane_state: Plane state 456 * 457 * This function implements struct &drm_simple_display_funcs.begin_fb_access. 458 * 459 * See drm_gem_begin_shadow_fb_access() for details and mipi_dbi_pipe_cleanup_fb() 460 * for cleanup. 461 * 462 * Returns: 463 * 0 on success, or a negative errno code otherwise. 464 */ 465 int mipi_dbi_pipe_begin_fb_access(struct drm_simple_display_pipe *pipe, 466 struct drm_plane_state *plane_state) 467 { 468 return drm_gem_begin_shadow_fb_access(&pipe->plane, plane_state); 469 } 470 EXPORT_SYMBOL(mipi_dbi_pipe_begin_fb_access); 471 472 /** 473 * mipi_dbi_pipe_end_fb_access - MIPI DBI pipe end-access helper 474 * @pipe: Display pipe 475 * @plane_state: Plane state 476 * 477 * This function implements struct &drm_simple_display_funcs.end_fb_access. 478 * 479 * See mipi_dbi_pipe_begin_fb_access(). 480 */ 481 void mipi_dbi_pipe_end_fb_access(struct drm_simple_display_pipe *pipe, 482 struct drm_plane_state *plane_state) 483 { 484 drm_gem_end_shadow_fb_access(&pipe->plane, plane_state); 485 } 486 EXPORT_SYMBOL(mipi_dbi_pipe_end_fb_access); 487 488 /** 489 * mipi_dbi_pipe_reset_plane - MIPI DBI plane-reset helper 490 * @pipe: Display pipe 491 * 492 * This function implements struct &drm_simple_display_funcs.reset_plane 493 * for MIPI DBI planes. 494 */ 495 void mipi_dbi_pipe_reset_plane(struct drm_simple_display_pipe *pipe) 496 { 497 drm_gem_reset_shadow_plane(&pipe->plane); 498 } 499 EXPORT_SYMBOL(mipi_dbi_pipe_reset_plane); 500 501 /** 502 * mipi_dbi_pipe_duplicate_plane_state - duplicates MIPI DBI plane state 503 * @pipe: Display pipe 504 * 505 * This function implements struct &drm_simple_display_funcs.duplicate_plane_state 506 * for MIPI DBI planes. 507 * 508 * See drm_gem_duplicate_shadow_plane_state() for additional details. 509 * 510 * Returns: 511 * A pointer to a new plane state on success, or NULL otherwise. 512 */ 513 struct drm_plane_state *mipi_dbi_pipe_duplicate_plane_state(struct drm_simple_display_pipe *pipe) 514 { 515 return drm_gem_duplicate_shadow_plane_state(&pipe->plane); 516 } 517 EXPORT_SYMBOL(mipi_dbi_pipe_duplicate_plane_state); 518 519 /** 520 * mipi_dbi_pipe_destroy_plane_state - cleans up MIPI DBI plane state 521 * @pipe: Display pipe 522 * @plane_state: Plane state 523 * 524 * This function implements struct drm_simple_display_funcs.destroy_plane_state 525 * for MIPI DBI planes. 526 * 527 * See drm_gem_destroy_shadow_plane_state() for additional details. 528 */ 529 void mipi_dbi_pipe_destroy_plane_state(struct drm_simple_display_pipe *pipe, 530 struct drm_plane_state *plane_state) 531 { 532 drm_gem_destroy_shadow_plane_state(&pipe->plane, plane_state); 533 } 534 EXPORT_SYMBOL(mipi_dbi_pipe_destroy_plane_state); 535 536 static int mipi_dbi_connector_get_modes(struct drm_connector *connector) 537 { 538 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(connector->dev); 539 540 return drm_connector_helper_get_modes_fixed(connector, &dbidev->mode); 541 } 542 543 static const struct drm_connector_helper_funcs mipi_dbi_connector_hfuncs = { 544 .get_modes = mipi_dbi_connector_get_modes, 545 }; 546 547 static const struct drm_connector_funcs mipi_dbi_connector_funcs = { 548 .reset = drm_atomic_helper_connector_reset, 549 .fill_modes = drm_helper_probe_single_connector_modes, 550 .destroy = drm_connector_cleanup, 551 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 552 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 553 }; 554 555 static int mipi_dbi_rotate_mode(struct drm_display_mode *mode, 556 unsigned int rotation) 557 { 558 if (rotation == 0 || rotation == 180) { 559 return 0; 560 } else if (rotation == 90 || rotation == 270) { 561 swap(mode->hdisplay, mode->vdisplay); 562 swap(mode->hsync_start, mode->vsync_start); 563 swap(mode->hsync_end, mode->vsync_end); 564 swap(mode->htotal, mode->vtotal); 565 swap(mode->width_mm, mode->height_mm); 566 return 0; 567 } else { 568 return -EINVAL; 569 } 570 } 571 572 static const struct drm_mode_config_funcs mipi_dbi_mode_config_funcs = { 573 .fb_create = drm_gem_fb_create_with_dirty, 574 .atomic_check = drm_atomic_helper_check, 575 .atomic_commit = drm_atomic_helper_commit, 576 }; 577 578 static const uint32_t mipi_dbi_formats[] = { 579 DRM_FORMAT_RGB565, 580 DRM_FORMAT_XRGB8888, 581 }; 582 583 /** 584 * mipi_dbi_dev_init_with_formats - MIPI DBI device initialization with custom formats 585 * @dbidev: MIPI DBI device structure to initialize 586 * @funcs: Display pipe functions 587 * @formats: Array of supported formats (DRM_FORMAT\_\*). 588 * @format_count: Number of elements in @formats 589 * @mode: Display mode 590 * @rotation: Initial rotation in degrees Counter Clock Wise 591 * @tx_buf_size: Allocate a transmit buffer of this size. 592 * 593 * This function sets up a &drm_simple_display_pipe with a &drm_connector that 594 * has one fixed &drm_display_mode which is rotated according to @rotation. 595 * This mode is used to set the mode config min/max width/height properties. 596 * 597 * Use mipi_dbi_dev_init() if you want native RGB565 and emulated XRGB8888 format. 598 * 599 * Note: 600 * Some of the helper functions expects RGB565 to be the default format and the 601 * transmit buffer sized to fit that. 602 * 603 * Returns: 604 * Zero on success, negative error code on failure. 605 */ 606 int mipi_dbi_dev_init_with_formats(struct mipi_dbi_dev *dbidev, 607 const struct drm_simple_display_pipe_funcs *funcs, 608 const uint32_t *formats, unsigned int format_count, 609 const struct drm_display_mode *mode, 610 unsigned int rotation, size_t tx_buf_size) 611 { 612 static const uint64_t modifiers[] = { 613 DRM_FORMAT_MOD_LINEAR, 614 DRM_FORMAT_MOD_INVALID 615 }; 616 struct drm_device *drm = &dbidev->drm; 617 int ret; 618 619 if (!dbidev->dbi.command) 620 return -EINVAL; 621 622 ret = drmm_mode_config_init(drm); 623 if (ret) 624 return ret; 625 626 dbidev->tx_buf = devm_kmalloc(drm->dev, tx_buf_size, GFP_KERNEL); 627 if (!dbidev->tx_buf) 628 return -ENOMEM; 629 630 drm_mode_copy(&dbidev->mode, mode); 631 ret = mipi_dbi_rotate_mode(&dbidev->mode, rotation); 632 if (ret) { 633 DRM_ERROR("Illegal rotation value %u\n", rotation); 634 return -EINVAL; 635 } 636 637 drm_connector_helper_add(&dbidev->connector, &mipi_dbi_connector_hfuncs); 638 ret = drm_connector_init(drm, &dbidev->connector, &mipi_dbi_connector_funcs, 639 DRM_MODE_CONNECTOR_SPI); 640 if (ret) 641 return ret; 642 643 ret = drm_simple_display_pipe_init(drm, &dbidev->pipe, funcs, formats, format_count, 644 modifiers, &dbidev->connector); 645 if (ret) 646 return ret; 647 648 drm_plane_enable_fb_damage_clips(&dbidev->pipe.plane); 649 650 drm->mode_config.funcs = &mipi_dbi_mode_config_funcs; 651 drm->mode_config.min_width = dbidev->mode.hdisplay; 652 drm->mode_config.max_width = dbidev->mode.hdisplay; 653 drm->mode_config.min_height = dbidev->mode.vdisplay; 654 drm->mode_config.max_height = dbidev->mode.vdisplay; 655 dbidev->rotation = rotation; 656 dbidev->pixel_format = formats[0]; 657 if (formats[0] == DRM_FORMAT_RGB888) 658 dbidev->dbi.write_memory_bpw = 8; 659 660 DRM_DEBUG_KMS("rotation = %u\n", rotation); 661 662 return 0; 663 } 664 EXPORT_SYMBOL(mipi_dbi_dev_init_with_formats); 665 666 /** 667 * mipi_dbi_dev_init - MIPI DBI device initialization 668 * @dbidev: MIPI DBI device structure to initialize 669 * @funcs: Display pipe functions 670 * @mode: Display mode 671 * @rotation: Initial rotation in degrees Counter Clock Wise 672 * 673 * This function sets up a &drm_simple_display_pipe with a &drm_connector that 674 * has one fixed &drm_display_mode which is rotated according to @rotation. 675 * This mode is used to set the mode config min/max width/height properties. 676 * Additionally &mipi_dbi.tx_buf is allocated. 677 * 678 * Supported formats: Native RGB565 and emulated XRGB8888. 679 * 680 * Returns: 681 * Zero on success, negative error code on failure. 682 */ 683 int mipi_dbi_dev_init(struct mipi_dbi_dev *dbidev, 684 const struct drm_simple_display_pipe_funcs *funcs, 685 const struct drm_display_mode *mode, unsigned int rotation) 686 { 687 size_t bufsize = mode->vdisplay * mode->hdisplay * sizeof(u16); 688 689 dbidev->drm.mode_config.preferred_depth = 16; 690 691 return mipi_dbi_dev_init_with_formats(dbidev, funcs, mipi_dbi_formats, 692 ARRAY_SIZE(mipi_dbi_formats), mode, 693 rotation, bufsize); 694 } 695 EXPORT_SYMBOL(mipi_dbi_dev_init); 696 697 /** 698 * mipi_dbi_hw_reset - Hardware reset of controller 699 * @dbi: MIPI DBI structure 700 * 701 * Reset controller if the &mipi_dbi->reset gpio is set. 702 */ 703 void mipi_dbi_hw_reset(struct mipi_dbi *dbi) 704 { 705 if (!dbi->reset) 706 return; 707 708 gpiod_set_value_cansleep(dbi->reset, 0); 709 usleep_range(20, 1000); 710 gpiod_set_value_cansleep(dbi->reset, 1); 711 msleep(120); 712 } 713 EXPORT_SYMBOL(mipi_dbi_hw_reset); 714 715 /** 716 * mipi_dbi_display_is_on - Check if display is on 717 * @dbi: MIPI DBI structure 718 * 719 * This function checks the Power Mode register (if readable) to see if 720 * display output is turned on. This can be used to see if the bootloader 721 * has already turned on the display avoiding flicker when the pipeline is 722 * enabled. 723 * 724 * Returns: 725 * true if the display can be verified to be on, false otherwise. 726 */ 727 bool mipi_dbi_display_is_on(struct mipi_dbi *dbi) 728 { 729 u8 val; 730 731 if (mipi_dbi_command_read(dbi, MIPI_DCS_GET_POWER_MODE, &val)) 732 return false; 733 734 val &= ~DCS_POWER_MODE_RESERVED_MASK; 735 736 /* The poweron/reset value is 08h DCS_POWER_MODE_DISPLAY_NORMAL_MODE */ 737 if (val != (DCS_POWER_MODE_DISPLAY | 738 DCS_POWER_MODE_DISPLAY_NORMAL_MODE | DCS_POWER_MODE_SLEEP_MODE)) 739 return false; 740 741 DRM_DEBUG_DRIVER("Display is ON\n"); 742 743 return true; 744 } 745 EXPORT_SYMBOL(mipi_dbi_display_is_on); 746 747 static int mipi_dbi_poweron_reset_conditional(struct mipi_dbi_dev *dbidev, bool cond) 748 { 749 struct device *dev = dbidev->drm.dev; 750 struct mipi_dbi *dbi = &dbidev->dbi; 751 int ret; 752 753 if (dbidev->regulator) { 754 ret = regulator_enable(dbidev->regulator); 755 if (ret) { 756 DRM_DEV_ERROR(dev, "Failed to enable regulator (%d)\n", ret); 757 return ret; 758 } 759 } 760 761 if (dbidev->io_regulator) { 762 ret = regulator_enable(dbidev->io_regulator); 763 if (ret) { 764 DRM_DEV_ERROR(dev, "Failed to enable I/O regulator (%d)\n", ret); 765 if (dbidev->regulator) 766 regulator_disable(dbidev->regulator); 767 return ret; 768 } 769 } 770 771 if (cond && mipi_dbi_display_is_on(dbi)) 772 return 1; 773 774 mipi_dbi_hw_reset(dbi); 775 ret = mipi_dbi_command(dbi, MIPI_DCS_SOFT_RESET); 776 if (ret) { 777 DRM_DEV_ERROR(dev, "Failed to send reset command (%d)\n", ret); 778 if (dbidev->regulator) 779 regulator_disable(dbidev->regulator); 780 if (dbidev->io_regulator) 781 regulator_disable(dbidev->io_regulator); 782 return ret; 783 } 784 785 /* 786 * If we did a hw reset, we know the controller is in Sleep mode and 787 * per MIPI DSC spec should wait 5ms after soft reset. If we didn't, 788 * we assume worst case and wait 120ms. 789 */ 790 if (dbi->reset) 791 usleep_range(5000, 20000); 792 else 793 msleep(120); 794 795 return 0; 796 } 797 798 /** 799 * mipi_dbi_poweron_reset - MIPI DBI poweron and reset 800 * @dbidev: MIPI DBI device structure 801 * 802 * This function enables the regulator if used and does a hardware and software 803 * reset. 804 * 805 * Returns: 806 * Zero on success, or a negative error code. 807 */ 808 int mipi_dbi_poweron_reset(struct mipi_dbi_dev *dbidev) 809 { 810 return mipi_dbi_poweron_reset_conditional(dbidev, false); 811 } 812 EXPORT_SYMBOL(mipi_dbi_poweron_reset); 813 814 /** 815 * mipi_dbi_poweron_conditional_reset - MIPI DBI poweron and conditional reset 816 * @dbidev: MIPI DBI device structure 817 * 818 * This function enables the regulator if used and if the display is off, it 819 * does a hardware and software reset. If mipi_dbi_display_is_on() determines 820 * that the display is on, no reset is performed. 821 * 822 * Returns: 823 * Zero if the controller was reset, 1 if the display was already on, or a 824 * negative error code. 825 */ 826 int mipi_dbi_poweron_conditional_reset(struct mipi_dbi_dev *dbidev) 827 { 828 return mipi_dbi_poweron_reset_conditional(dbidev, true); 829 } 830 EXPORT_SYMBOL(mipi_dbi_poweron_conditional_reset); 831 832 #if IS_ENABLED(CONFIG_SPI) 833 834 /** 835 * mipi_dbi_spi_cmd_max_speed - get the maximum SPI bus speed 836 * @spi: SPI device 837 * @len: The transfer buffer length. 838 * 839 * Many controllers have a max speed of 10MHz, but can be pushed way beyond 840 * that. Increase reliability by running pixel data at max speed and the rest 841 * at 10MHz, preventing transfer glitches from messing up the init settings. 842 */ 843 u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len) 844 { 845 if (len > 64) 846 return 0; /* use default */ 847 848 return min_t(u32, 10000000, spi->max_speed_hz); 849 } 850 EXPORT_SYMBOL(mipi_dbi_spi_cmd_max_speed); 851 852 /* 853 * MIPI DBI Type C Option 1 854 * 855 * If the SPI controller doesn't have 9 bits per word support, 856 * use blocks of 9 bytes to send 8x 9-bit words using a 8-bit SPI transfer. 857 * Pad partial blocks with MIPI_DCS_NOP (zero). 858 * This is how the D/C bit (x) is added: 859 * x7654321 860 * 0x765432 861 * 10x76543 862 * 210x7654 863 * 3210x765 864 * 43210x76 865 * 543210x7 866 * 6543210x 867 * 76543210 868 */ 869 870 static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi, int dc, 871 const void *buf, size_t len, 872 unsigned int bpw) 873 { 874 bool swap_bytes = (bpw == 16); 875 size_t chunk, max_chunk = dbi->tx_buf9_len; 876 struct spi_device *spi = dbi->spi; 877 struct spi_transfer tr = { 878 .tx_buf = dbi->tx_buf9, 879 .bits_per_word = 8, 880 }; 881 struct spi_message m; 882 const u8 *src = buf; 883 int i, ret; 884 u8 *dst; 885 886 if (drm_debug_enabled(DRM_UT_DRIVER)) 887 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n", 888 __func__, dc, max_chunk); 889 890 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len); 891 spi_message_init_with_transfers(&m, &tr, 1); 892 893 if (!dc) { 894 if (WARN_ON_ONCE(len != 1)) 895 return -EINVAL; 896 897 /* Command: pad no-op's (zeroes) at beginning of block */ 898 dst = dbi->tx_buf9; 899 memset(dst, 0, 9); 900 dst[8] = *src; 901 tr.len = 9; 902 903 return spi_sync(spi, &m); 904 } 905 906 /* max with room for adding one bit per byte */ 907 max_chunk = max_chunk / 9 * 8; 908 /* but no bigger than len */ 909 max_chunk = min(max_chunk, len); 910 /* 8 byte blocks */ 911 max_chunk = max_t(size_t, 8, max_chunk & ~0x7); 912 913 while (len) { 914 size_t added = 0; 915 916 chunk = min(len, max_chunk); 917 len -= chunk; 918 dst = dbi->tx_buf9; 919 920 if (chunk < 8) { 921 u8 val, carry = 0; 922 923 /* Data: pad no-op's (zeroes) at end of block */ 924 memset(dst, 0, 9); 925 926 if (swap_bytes) { 927 for (i = 1; i < (chunk + 1); i++) { 928 val = src[1]; 929 *dst++ = carry | BIT(8 - i) | (val >> i); 930 carry = val << (8 - i); 931 i++; 932 val = src[0]; 933 *dst++ = carry | BIT(8 - i) | (val >> i); 934 carry = val << (8 - i); 935 src += 2; 936 } 937 *dst++ = carry; 938 } else { 939 for (i = 1; i < (chunk + 1); i++) { 940 val = *src++; 941 *dst++ = carry | BIT(8 - i) | (val >> i); 942 carry = val << (8 - i); 943 } 944 *dst++ = carry; 945 } 946 947 chunk = 8; 948 added = 1; 949 } else { 950 for (i = 0; i < chunk; i += 8) { 951 if (swap_bytes) { 952 *dst++ = BIT(7) | (src[1] >> 1); 953 *dst++ = (src[1] << 7) | BIT(6) | (src[0] >> 2); 954 *dst++ = (src[0] << 6) | BIT(5) | (src[3] >> 3); 955 *dst++ = (src[3] << 5) | BIT(4) | (src[2] >> 4); 956 *dst++ = (src[2] << 4) | BIT(3) | (src[5] >> 5); 957 *dst++ = (src[5] << 3) | BIT(2) | (src[4] >> 6); 958 *dst++ = (src[4] << 2) | BIT(1) | (src[7] >> 7); 959 *dst++ = (src[7] << 1) | BIT(0); 960 *dst++ = src[6]; 961 } else { 962 *dst++ = BIT(7) | (src[0] >> 1); 963 *dst++ = (src[0] << 7) | BIT(6) | (src[1] >> 2); 964 *dst++ = (src[1] << 6) | BIT(5) | (src[2] >> 3); 965 *dst++ = (src[2] << 5) | BIT(4) | (src[3] >> 4); 966 *dst++ = (src[3] << 4) | BIT(3) | (src[4] >> 5); 967 *dst++ = (src[4] << 3) | BIT(2) | (src[5] >> 6); 968 *dst++ = (src[5] << 2) | BIT(1) | (src[6] >> 7); 969 *dst++ = (src[6] << 1) | BIT(0); 970 *dst++ = src[7]; 971 } 972 973 src += 8; 974 added++; 975 } 976 } 977 978 tr.len = chunk + added; 979 980 ret = spi_sync(spi, &m); 981 if (ret) 982 return ret; 983 } 984 985 return 0; 986 } 987 988 static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi, int dc, 989 const void *buf, size_t len, 990 unsigned int bpw) 991 { 992 struct spi_device *spi = dbi->spi; 993 struct spi_transfer tr = { 994 .bits_per_word = 9, 995 }; 996 const u16 *src16 = buf; 997 const u8 *src8 = buf; 998 struct spi_message m; 999 size_t max_chunk; 1000 u16 *dst16; 1001 int ret; 1002 1003 if (!spi_is_bpw_supported(spi, 9)) 1004 return mipi_dbi_spi1e_transfer(dbi, dc, buf, len, bpw); 1005 1006 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len); 1007 max_chunk = dbi->tx_buf9_len; 1008 dst16 = dbi->tx_buf9; 1009 1010 if (drm_debug_enabled(DRM_UT_DRIVER)) 1011 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n", 1012 __func__, dc, max_chunk); 1013 1014 max_chunk = min(max_chunk / 2, len); 1015 1016 spi_message_init_with_transfers(&m, &tr, 1); 1017 tr.tx_buf = dst16; 1018 1019 while (len) { 1020 size_t chunk = min(len, max_chunk); 1021 unsigned int i; 1022 1023 if (bpw == 16) { 1024 for (i = 0; i < (chunk * 2); i += 2) { 1025 dst16[i] = *src16 >> 8; 1026 dst16[i + 1] = *src16++ & 0xFF; 1027 if (dc) { 1028 dst16[i] |= 0x0100; 1029 dst16[i + 1] |= 0x0100; 1030 } 1031 } 1032 } else { 1033 for (i = 0; i < chunk; i++) { 1034 dst16[i] = *src8++; 1035 if (dc) 1036 dst16[i] |= 0x0100; 1037 } 1038 } 1039 1040 tr.len = chunk * 2; 1041 len -= chunk; 1042 1043 ret = spi_sync(spi, &m); 1044 if (ret) 1045 return ret; 1046 } 1047 1048 return 0; 1049 } 1050 1051 static int mipi_dbi_typec1_command_read(struct mipi_dbi *dbi, u8 *cmd, 1052 u8 *data, size_t len) 1053 { 1054 struct spi_device *spi = dbi->spi; 1055 u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED, 1056 spi->max_speed_hz / 2); 1057 struct spi_transfer tr[2] = { 1058 { 1059 .speed_hz = speed_hz, 1060 .bits_per_word = 9, 1061 .tx_buf = dbi->tx_buf9, 1062 .len = 2, 1063 }, { 1064 .speed_hz = speed_hz, 1065 .bits_per_word = 8, 1066 .len = len, 1067 .rx_buf = data, 1068 }, 1069 }; 1070 struct spi_message m; 1071 u16 *dst16; 1072 int ret; 1073 1074 if (!len) 1075 return -EINVAL; 1076 1077 if (!spi_is_bpw_supported(spi, 9)) { 1078 /* 1079 * FIXME: implement something like mipi_dbi_spi1e_transfer() but 1080 * for reads using emulation. 1081 */ 1082 dev_err(&spi->dev, 1083 "reading on host not supporting 9 bpw not yet implemented\n"); 1084 return -EOPNOTSUPP; 1085 } 1086 1087 /* 1088 * Turn the 8bit command into a 16bit version of the command in the 1089 * buffer. Only 9 bits of this will be used when executing the actual 1090 * transfer. 1091 */ 1092 dst16 = dbi->tx_buf9; 1093 dst16[0] = *cmd; 1094 1095 spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr)); 1096 ret = spi_sync(spi, &m); 1097 1098 if (!ret) 1099 MIPI_DBI_DEBUG_COMMAND(*cmd, data, len); 1100 1101 return ret; 1102 } 1103 1104 static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd, 1105 u8 *parameters, size_t num) 1106 { 1107 unsigned int bpw = 8; 1108 int ret; 1109 1110 if (mipi_dbi_command_is_read(dbi, *cmd)) 1111 return mipi_dbi_typec1_command_read(dbi, cmd, parameters, num); 1112 1113 MIPI_DBI_DEBUG_COMMAND(*cmd, parameters, num); 1114 1115 ret = mipi_dbi_spi1_transfer(dbi, 0, cmd, 1, 8); 1116 if (ret || !num) 1117 return ret; 1118 1119 if (*cmd == MIPI_DCS_WRITE_MEMORY_START) 1120 bpw = dbi->write_memory_bpw; 1121 1122 return mipi_dbi_spi1_transfer(dbi, 1, parameters, num, bpw); 1123 } 1124 1125 /* MIPI DBI Type C Option 3 */ 1126 1127 static int mipi_dbi_typec3_command_read(struct mipi_dbi *dbi, u8 *cmd, 1128 u8 *data, size_t len) 1129 { 1130 struct spi_device *spi = dbi->spi; 1131 u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED, 1132 spi->max_speed_hz / 2); 1133 struct spi_transfer tr[2] = { 1134 { 1135 .speed_hz = speed_hz, 1136 .tx_buf = cmd, 1137 .len = 1, 1138 }, { 1139 .speed_hz = speed_hz, 1140 .len = len, 1141 }, 1142 }; 1143 struct spi_message m; 1144 u8 *buf; 1145 int ret; 1146 1147 if (!len) 1148 return -EINVAL; 1149 1150 /* 1151 * Support non-standard 24-bit and 32-bit Nokia read commands which 1152 * start with a dummy clock, so we need to read an extra byte. 1153 */ 1154 if (*cmd == MIPI_DCS_GET_DISPLAY_ID || 1155 *cmd == MIPI_DCS_GET_DISPLAY_STATUS) { 1156 if (!(len == 3 || len == 4)) 1157 return -EINVAL; 1158 1159 tr[1].len = len + 1; 1160 } 1161 1162 buf = kmalloc(tr[1].len, GFP_KERNEL); 1163 if (!buf) 1164 return -ENOMEM; 1165 1166 tr[1].rx_buf = buf; 1167 1168 spi_bus_lock(spi->controller); 1169 gpiod_set_value_cansleep(dbi->dc, 0); 1170 1171 spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr)); 1172 ret = spi_sync_locked(spi, &m); 1173 spi_bus_unlock(spi->controller); 1174 if (ret) 1175 goto err_free; 1176 1177 if (tr[1].len == len) { 1178 memcpy(data, buf, len); 1179 } else { 1180 unsigned int i; 1181 1182 for (i = 0; i < len; i++) 1183 data[i] = (buf[i] << 1) | (buf[i + 1] >> 7); 1184 } 1185 1186 MIPI_DBI_DEBUG_COMMAND(*cmd, data, len); 1187 1188 err_free: 1189 kfree(buf); 1190 1191 return ret; 1192 } 1193 1194 static int mipi_dbi_typec3_command(struct mipi_dbi *dbi, u8 *cmd, 1195 u8 *par, size_t num) 1196 { 1197 struct spi_device *spi = dbi->spi; 1198 unsigned int bpw = 8; 1199 u32 speed_hz; 1200 int ret; 1201 1202 if (mipi_dbi_command_is_read(dbi, *cmd)) 1203 return mipi_dbi_typec3_command_read(dbi, cmd, par, num); 1204 1205 MIPI_DBI_DEBUG_COMMAND(*cmd, par, num); 1206 1207 spi_bus_lock(spi->controller); 1208 gpiod_set_value_cansleep(dbi->dc, 0); 1209 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 1); 1210 ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, cmd, 1); 1211 spi_bus_unlock(spi->controller); 1212 if (ret || !num) 1213 return ret; 1214 1215 if (*cmd == MIPI_DCS_WRITE_MEMORY_START) 1216 bpw = dbi->write_memory_bpw; 1217 1218 spi_bus_lock(spi->controller); 1219 gpiod_set_value_cansleep(dbi->dc, 1); 1220 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num); 1221 ret = mipi_dbi_spi_transfer(spi, speed_hz, bpw, par, num); 1222 spi_bus_unlock(spi->controller); 1223 1224 return ret; 1225 } 1226 1227 /** 1228 * mipi_dbi_spi_init - Initialize MIPI DBI SPI interface 1229 * @spi: SPI device 1230 * @dbi: MIPI DBI structure to initialize 1231 * @dc: D/C gpio (optional) 1232 * 1233 * This function sets &mipi_dbi->command, enables &mipi_dbi->read_commands for the 1234 * usual read commands. It should be followed by a call to mipi_dbi_dev_init() or 1235 * a driver-specific init. 1236 * 1237 * If @dc is set, a Type C Option 3 interface is assumed, if not 1238 * Type C Option 1. 1239 * 1240 * If the command is %MIPI_DCS_WRITE_MEMORY_START and the pixel format is RGB565, endianness has 1241 * to be taken into account. The MIPI DBI serial interface is big endian and framebuffers are 1242 * assumed stored in memory as little endian (%DRM_FORMAT_BIG_ENDIAN is not supported). 1243 * 1244 * This is how endianness is handled: 1245 * 1246 * Option 1 (D/C as a bit): The buffer is sent on the wire byte by byte so the 16-bit buffer is 1247 * byteswapped before transfer. 1248 * 1249 * Option 3 (D/C as a gpio): If the SPI controller supports 16 bits per word the buffer can be 1250 * sent as-is. If not the caller is responsible for swapping the bytes 1251 * before calling mipi_dbi_command_buf() and the buffer is sent 8 bpw. 1252 * 1253 * This handling is optimised for %DRM_FORMAT_RGB565 framebuffers. 1254 * 1255 * If the interface is Option 1 and the SPI controller doesn't support 9 bits per word, 1256 * the buffer is sent as 9x 8-bit words, padded with MIPI DCS no-op commands if necessary. 1257 * 1258 * Returns: 1259 * Zero on success, negative error code on failure. 1260 */ 1261 int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi, 1262 struct gpio_desc *dc) 1263 { 1264 struct device *dev = &spi->dev; 1265 int ret; 1266 1267 /* 1268 * Even though it's not the SPI device that does DMA (the master does), 1269 * the dma mask is necessary for the dma_alloc_wc() in the GEM code 1270 * (e.g., drm_gem_dma_create()). The dma_addr returned will be a physical 1271 * address which might be different from the bus address, but this is 1272 * not a problem since the address will not be used. 1273 * The virtual address is used in the transfer and the SPI core 1274 * re-maps it on the SPI master device using the DMA streaming API 1275 * (spi_map_buf()). 1276 */ 1277 if (!dev->coherent_dma_mask) { 1278 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32)); 1279 if (ret) { 1280 dev_warn(dev, "Failed to set dma mask %d\n", ret); 1281 return ret; 1282 } 1283 } 1284 1285 dbi->spi = spi; 1286 dbi->read_commands = mipi_dbi_dcs_read_commands; 1287 dbi->write_memory_bpw = 16; 1288 1289 if (dc) { 1290 dbi->command = mipi_dbi_typec3_command; 1291 dbi->dc = dc; 1292 if (!spi_is_bpw_supported(spi, 16)) { 1293 dbi->write_memory_bpw = 8; 1294 dbi->swap_bytes = true; 1295 } 1296 } else { 1297 dbi->command = mipi_dbi_typec1_command; 1298 dbi->tx_buf9_len = SZ_16K; 1299 dbi->tx_buf9 = devm_kmalloc(dev, dbi->tx_buf9_len, GFP_KERNEL); 1300 if (!dbi->tx_buf9) 1301 return -ENOMEM; 1302 } 1303 1304 mutex_init(&dbi->cmdlock); 1305 1306 DRM_DEBUG_DRIVER("SPI speed: %uMHz\n", spi->max_speed_hz / 1000000); 1307 1308 return 0; 1309 } 1310 EXPORT_SYMBOL(mipi_dbi_spi_init); 1311 1312 /** 1313 * mipi_dbi_spi_transfer - SPI transfer helper 1314 * @spi: SPI device 1315 * @speed_hz: Override speed (optional) 1316 * @bpw: Bits per word 1317 * @buf: Buffer to transfer 1318 * @len: Buffer length 1319 * 1320 * This SPI transfer helper breaks up the transfer of @buf into chunks which 1321 * the SPI controller driver can handle. The SPI bus must be locked when 1322 * calling this. 1323 * 1324 * Returns: 1325 * Zero on success, negative error code on failure. 1326 */ 1327 int mipi_dbi_spi_transfer(struct spi_device *spi, u32 speed_hz, 1328 u8 bpw, const void *buf, size_t len) 1329 { 1330 size_t max_chunk = spi_max_transfer_size(spi); 1331 struct spi_transfer tr = { 1332 .bits_per_word = bpw, 1333 .speed_hz = speed_hz, 1334 }; 1335 struct spi_message m; 1336 size_t chunk; 1337 int ret; 1338 1339 /* In __spi_validate, there's a validation that no partial transfers 1340 * are accepted (xfer->len % w_size must be zero). 1341 * Here we align max_chunk to multiple of 2 (16bits), 1342 * to prevent transfers from being rejected. 1343 */ 1344 max_chunk = ALIGN_DOWN(max_chunk, 2); 1345 1346 spi_message_init_with_transfers(&m, &tr, 1); 1347 1348 while (len) { 1349 chunk = min(len, max_chunk); 1350 1351 tr.tx_buf = buf; 1352 tr.len = chunk; 1353 buf += chunk; 1354 len -= chunk; 1355 1356 ret = spi_sync_locked(spi, &m); 1357 if (ret) 1358 return ret; 1359 } 1360 1361 return 0; 1362 } 1363 EXPORT_SYMBOL(mipi_dbi_spi_transfer); 1364 1365 #endif /* CONFIG_SPI */ 1366 1367 #ifdef CONFIG_DEBUG_FS 1368 1369 static ssize_t mipi_dbi_debugfs_command_write(struct file *file, 1370 const char __user *ubuf, 1371 size_t count, loff_t *ppos) 1372 { 1373 struct seq_file *m = file->private_data; 1374 struct mipi_dbi_dev *dbidev = m->private; 1375 u8 val, cmd = 0, parameters[64]; 1376 char *buf, *pos, *token; 1377 int i, ret, idx; 1378 1379 if (!drm_dev_enter(&dbidev->drm, &idx)) 1380 return -ENODEV; 1381 1382 buf = memdup_user_nul(ubuf, count); 1383 if (IS_ERR(buf)) { 1384 ret = PTR_ERR(buf); 1385 goto err_exit; 1386 } 1387 1388 /* strip trailing whitespace */ 1389 for (i = count - 1; i > 0; i--) 1390 if (isspace(buf[i])) 1391 buf[i] = '\0'; 1392 else 1393 break; 1394 i = 0; 1395 pos = buf; 1396 while (pos) { 1397 token = strsep(&pos, " "); 1398 if (!token) { 1399 ret = -EINVAL; 1400 goto err_free; 1401 } 1402 1403 ret = kstrtou8(token, 16, &val); 1404 if (ret < 0) 1405 goto err_free; 1406 1407 if (token == buf) 1408 cmd = val; 1409 else 1410 parameters[i++] = val; 1411 1412 if (i == 64) { 1413 ret = -E2BIG; 1414 goto err_free; 1415 } 1416 } 1417 1418 ret = mipi_dbi_command_buf(&dbidev->dbi, cmd, parameters, i); 1419 1420 err_free: 1421 kfree(buf); 1422 err_exit: 1423 drm_dev_exit(idx); 1424 1425 return ret < 0 ? ret : count; 1426 } 1427 1428 static int mipi_dbi_debugfs_command_show(struct seq_file *m, void *unused) 1429 { 1430 struct mipi_dbi_dev *dbidev = m->private; 1431 struct mipi_dbi *dbi = &dbidev->dbi; 1432 u8 cmd, val[4]; 1433 int ret, idx; 1434 size_t len; 1435 1436 if (!drm_dev_enter(&dbidev->drm, &idx)) 1437 return -ENODEV; 1438 1439 for (cmd = 0; cmd < 255; cmd++) { 1440 if (!mipi_dbi_command_is_read(dbi, cmd)) 1441 continue; 1442 1443 switch (cmd) { 1444 case MIPI_DCS_READ_MEMORY_START: 1445 case MIPI_DCS_READ_MEMORY_CONTINUE: 1446 len = 2; 1447 break; 1448 case MIPI_DCS_GET_DISPLAY_ID: 1449 len = 3; 1450 break; 1451 case MIPI_DCS_GET_DISPLAY_STATUS: 1452 len = 4; 1453 break; 1454 default: 1455 len = 1; 1456 break; 1457 } 1458 1459 seq_printf(m, "%02x: ", cmd); 1460 ret = mipi_dbi_command_buf(dbi, cmd, val, len); 1461 if (ret) { 1462 seq_puts(m, "XX\n"); 1463 continue; 1464 } 1465 seq_printf(m, "%*phN\n", (int)len, val); 1466 } 1467 1468 drm_dev_exit(idx); 1469 1470 return 0; 1471 } 1472 1473 static int mipi_dbi_debugfs_command_open(struct inode *inode, 1474 struct file *file) 1475 { 1476 return single_open(file, mipi_dbi_debugfs_command_show, 1477 inode->i_private); 1478 } 1479 1480 static const struct file_operations mipi_dbi_debugfs_command_fops = { 1481 .owner = THIS_MODULE, 1482 .open = mipi_dbi_debugfs_command_open, 1483 .read = seq_read, 1484 .llseek = seq_lseek, 1485 .release = single_release, 1486 .write = mipi_dbi_debugfs_command_write, 1487 }; 1488 1489 /** 1490 * mipi_dbi_debugfs_init - Create debugfs entries 1491 * @minor: DRM minor 1492 * 1493 * This function creates a 'command' debugfs file for sending commands to the 1494 * controller or getting the read command values. 1495 * Drivers can use this as their &drm_driver->debugfs_init callback. 1496 * 1497 */ 1498 void mipi_dbi_debugfs_init(struct drm_minor *minor) 1499 { 1500 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(minor->dev); 1501 umode_t mode = S_IFREG | S_IWUSR; 1502 1503 if (dbidev->dbi.read_commands) 1504 mode |= S_IRUGO; 1505 debugfs_create_file("command", mode, minor->debugfs_root, dbidev, 1506 &mipi_dbi_debugfs_command_fops); 1507 } 1508 EXPORT_SYMBOL(mipi_dbi_debugfs_init); 1509 1510 #endif 1511 1512 MODULE_DESCRIPTION("MIPI Display Bus Interface (DBI) LCD controller support"); 1513 MODULE_LICENSE("GPL"); 1514