1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020 Intel Corporation. */ 3 4 #ifndef __CXL_H__ 5 #define __CXL_H__ 6 7 #include <linux/libnvdimm.h> 8 #include <linux/bitfield.h> 9 #include <linux/notifier.h> 10 #include <linux/bitops.h> 11 #include <linux/log2.h> 12 #include <linux/node.h> 13 #include <linux/io.h> 14 15 extern const struct nvdimm_security_ops *cxl_security_ops; 16 17 /** 18 * DOC: cxl objects 19 * 20 * The CXL core objects like ports, decoders, and regions are shared 21 * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers 22 * (port-driver, region-driver, nvdimm object-drivers... etc). 23 */ 24 25 /* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */ 26 #define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K 27 28 /* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/ 29 #define CXL_CM_OFFSET 0x1000 30 #define CXL_CM_CAP_HDR_OFFSET 0x0 31 #define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0) 32 #define CM_CAP_HDR_CAP_ID 1 33 #define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16) 34 #define CM_CAP_HDR_CAP_VERSION 1 35 #define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20) 36 #define CM_CAP_HDR_CACHE_MEM_VERSION 1 37 #define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24) 38 #define CXL_CM_CAP_PTR_MASK GENMASK(31, 20) 39 40 #define CXL_CM_CAP_CAP_ID_RAS 0x2 41 #define CXL_CM_CAP_CAP_ID_HDM 0x5 42 #define CXL_CM_CAP_CAP_HDM_VERSION 1 43 44 /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */ 45 #define CXL_HDM_DECODER_CAP_OFFSET 0x0 46 #define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0) 47 #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4) 48 #define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8) 49 #define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9) 50 #define CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY BIT(11) 51 #define CXL_HDM_DECODER_INTERLEAVE_16_WAY BIT(12) 52 #define CXL_HDM_DECODER_CTRL_OFFSET 0x4 53 #define CXL_HDM_DECODER_ENABLE BIT(1) 54 #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10) 55 #define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14) 56 #define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18) 57 #define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c) 58 #define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20) 59 #define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0) 60 #define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4) 61 #define CXL_HDM_DECODER0_CTRL_LOCK BIT(8) 62 #define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9) 63 #define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10) 64 #define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11) 65 #define CXL_HDM_DECODER0_CTRL_HOSTONLY BIT(12) 66 #define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24) 67 #define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28) 68 #define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i) 69 #define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i) 70 71 /* HDM decoder control register constants CXL 3.0 8.2.5.19.7 */ 72 #define CXL_DECODER_MIN_GRANULARITY 256 73 #define CXL_DECODER_MAX_ENCODED_IG 6 74 75 static inline int cxl_hdm_decoder_count(u32 cap_hdr) 76 { 77 int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr); 78 79 return val ? val * 2 : 1; 80 } 81 82 /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ 83 static inline int eig_to_granularity(u16 eig, unsigned int *granularity) 84 { 85 if (eig > CXL_DECODER_MAX_ENCODED_IG) 86 return -EINVAL; 87 *granularity = CXL_DECODER_MIN_GRANULARITY << eig; 88 return 0; 89 } 90 91 /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */ 92 static inline int eiw_to_ways(u8 eiw, unsigned int *ways) 93 { 94 switch (eiw) { 95 case 0 ... 4: 96 *ways = 1 << eiw; 97 break; 98 case 8 ... 10: 99 *ways = 3 << (eiw - 8); 100 break; 101 default: 102 return -EINVAL; 103 } 104 105 return 0; 106 } 107 108 static inline int granularity_to_eig(int granularity, u16 *eig) 109 { 110 if (granularity > SZ_16K || granularity < CXL_DECODER_MIN_GRANULARITY || 111 !is_power_of_2(granularity)) 112 return -EINVAL; 113 *eig = ilog2(granularity) - 8; 114 return 0; 115 } 116 117 static inline int ways_to_eiw(unsigned int ways, u8 *eiw) 118 { 119 if (ways > 16) 120 return -EINVAL; 121 if (is_power_of_2(ways)) { 122 *eiw = ilog2(ways); 123 return 0; 124 } 125 if (ways % 3) 126 return -EINVAL; 127 ways /= 3; 128 if (!is_power_of_2(ways)) 129 return -EINVAL; 130 *eiw = ilog2(ways) + 8; 131 return 0; 132 } 133 134 /* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */ 135 #define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET 0x0 136 #define CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 137 #define CXL_RAS_UNCORRECTABLE_MASK_OFFSET 0x4 138 #define CXL_RAS_UNCORRECTABLE_MASK_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 139 #define CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK BIT(8) 140 #define CXL_RAS_UNCORRECTABLE_SEVERITY_OFFSET 0x8 141 #define CXL_RAS_UNCORRECTABLE_SEVERITY_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 142 #define CXL_RAS_CORRECTABLE_STATUS_OFFSET 0xC 143 #define CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0) 144 #define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10 145 #define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0) 146 #define CXL_RAS_CAP_CONTROL_OFFSET 0x14 147 #define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0) 148 #define CXL_RAS_HEADER_LOG_OFFSET 0x18 149 #define CXL_RAS_CAPABILITY_LENGTH 0x58 150 #define CXL_HEADERLOG_SIZE SZ_512 151 #define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32) 152 153 /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ 154 #define CXLDEV_CAP_ARRAY_OFFSET 0x0 155 #define CXLDEV_CAP_ARRAY_CAP_ID 0 156 #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0) 157 #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32) 158 /* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */ 159 #define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0) 160 /* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */ 161 #define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1 162 #define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2 163 #define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3 164 #define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000 165 166 /* CXL 3.0 8.2.8.3.1 Event Status Register */ 167 #define CXLDEV_DEV_EVENT_STATUS_OFFSET 0x00 168 #define CXLDEV_EVENT_STATUS_INFO BIT(0) 169 #define CXLDEV_EVENT_STATUS_WARN BIT(1) 170 #define CXLDEV_EVENT_STATUS_FAIL BIT(2) 171 #define CXLDEV_EVENT_STATUS_FATAL BIT(3) 172 173 #define CXLDEV_EVENT_STATUS_ALL (CXLDEV_EVENT_STATUS_INFO | \ 174 CXLDEV_EVENT_STATUS_WARN | \ 175 CXLDEV_EVENT_STATUS_FAIL | \ 176 CXLDEV_EVENT_STATUS_FATAL) 177 178 /* CXL rev 3.0 section 8.2.9.2.4; Table 8-52 */ 179 #define CXLDEV_EVENT_INT_MODE_MASK GENMASK(1, 0) 180 #define CXLDEV_EVENT_INT_MSGNUM_MASK GENMASK(7, 4) 181 182 /* CXL 2.0 8.2.8.4 Mailbox Registers */ 183 #define CXLDEV_MBOX_CAPS_OFFSET 0x00 184 #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0) 185 #define CXLDEV_MBOX_CAP_BG_CMD_IRQ BIT(6) 186 #define CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK GENMASK(10, 7) 187 #define CXLDEV_MBOX_CTRL_OFFSET 0x04 188 #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0) 189 #define CXLDEV_MBOX_CTRL_BG_CMD_IRQ BIT(2) 190 #define CXLDEV_MBOX_CMD_OFFSET 0x08 191 #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 192 #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16) 193 #define CXLDEV_MBOX_STATUS_OFFSET 0x10 194 #define CXLDEV_MBOX_STATUS_BG_CMD BIT(0) 195 #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32) 196 #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18 197 #define CXLDEV_MBOX_BG_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 198 #define CXLDEV_MBOX_BG_CMD_COMMAND_PCT_MASK GENMASK_ULL(22, 16) 199 #define CXLDEV_MBOX_BG_CMD_COMMAND_RC_MASK GENMASK_ULL(47, 32) 200 #define CXLDEV_MBOX_BG_CMD_COMMAND_VENDOR_MASK GENMASK_ULL(63, 48) 201 #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20 202 203 /* 204 * Using struct_group() allows for per register-block-type helper routines, 205 * without requiring block-type agnostic code to include the prefix. 206 */ 207 struct cxl_regs { 208 /* 209 * Common set of CXL Component register block base pointers 210 * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure 211 * @ras: CXL 2.0 8.2.5.9 CXL RAS Capability Structure 212 */ 213 struct_group_tagged(cxl_component_regs, component, 214 void __iomem *hdm_decoder; 215 void __iomem *ras; 216 ); 217 /* 218 * Common set of CXL Device register block base pointers 219 * @status: CXL 2.0 8.2.8.3 Device Status Registers 220 * @mbox: CXL 2.0 8.2.8.4 Mailbox Registers 221 * @memdev: CXL 2.0 8.2.8.5 Memory Device Registers 222 */ 223 struct_group_tagged(cxl_device_regs, device_regs, 224 void __iomem *status, *mbox, *memdev; 225 ); 226 227 struct_group_tagged(cxl_pmu_regs, pmu_regs, 228 void __iomem *pmu; 229 ); 230 231 /* 232 * RCH downstream port specific RAS register 233 * @aer: CXL 3.0 8.2.1.1 RCH Downstream Port RCRB 234 */ 235 struct_group_tagged(cxl_rch_regs, rch_regs, 236 void __iomem *dport_aer; 237 ); 238 239 /* 240 * RCD upstream port specific PCIe cap register 241 * @pcie_cap: CXL 3.0 8.2.1.2 RCD Upstream Port RCRB 242 */ 243 struct_group_tagged(cxl_rcd_regs, rcd_regs, 244 void __iomem *rcd_pcie_cap; 245 ); 246 }; 247 248 struct cxl_reg_map { 249 bool valid; 250 int id; 251 unsigned long offset; 252 unsigned long size; 253 }; 254 255 struct cxl_component_reg_map { 256 struct cxl_reg_map hdm_decoder; 257 struct cxl_reg_map ras; 258 }; 259 260 struct cxl_device_reg_map { 261 struct cxl_reg_map status; 262 struct cxl_reg_map mbox; 263 struct cxl_reg_map memdev; 264 }; 265 266 struct cxl_pmu_reg_map { 267 struct cxl_reg_map pmu; 268 }; 269 270 /** 271 * struct cxl_register_map - DVSEC harvested register block mapping parameters 272 * @host: device for devm operations and logging 273 * @base: virtual base of the register-block-BAR + @block_offset 274 * @resource: physical resource base of the register block 275 * @max_size: maximum mapping size to perform register search 276 * @reg_type: see enum cxl_regloc_type 277 * @component_map: cxl_reg_map for component registers 278 * @device_map: cxl_reg_maps for device registers 279 * @pmu_map: cxl_reg_maps for CXL Performance Monitoring Units 280 */ 281 struct cxl_register_map { 282 struct device *host; 283 void __iomem *base; 284 resource_size_t resource; 285 resource_size_t max_size; 286 u8 reg_type; 287 union { 288 struct cxl_component_reg_map component_map; 289 struct cxl_device_reg_map device_map; 290 struct cxl_pmu_reg_map pmu_map; 291 }; 292 }; 293 294 void cxl_probe_component_regs(struct device *dev, void __iomem *base, 295 struct cxl_component_reg_map *map); 296 void cxl_probe_device_regs(struct device *dev, void __iomem *base, 297 struct cxl_device_reg_map *map); 298 int cxl_map_component_regs(const struct cxl_register_map *map, 299 struct cxl_component_regs *regs, 300 unsigned long map_mask); 301 int cxl_map_device_regs(const struct cxl_register_map *map, 302 struct cxl_device_regs *regs); 303 int cxl_map_pmu_regs(struct cxl_register_map *map, struct cxl_pmu_regs *regs); 304 305 #define CXL_INSTANCES_COUNT -1 306 enum cxl_regloc_type; 307 int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type); 308 int cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type, 309 struct cxl_register_map *map, unsigned int index); 310 int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, 311 struct cxl_register_map *map); 312 int cxl_setup_regs(struct cxl_register_map *map); 313 struct cxl_dport; 314 resource_size_t cxl_rcd_component_reg_phys(struct device *dev, 315 struct cxl_dport *dport); 316 int cxl_dport_map_rcd_linkcap(struct pci_dev *pdev, struct cxl_dport *dport); 317 318 #define CXL_RESOURCE_NONE ((resource_size_t) -1) 319 #define CXL_TARGET_STRLEN 20 320 321 /* 322 * cxl_decoder flags that define the type of memory / devices this 323 * decoder supports as well as configuration lock status See "CXL 2.0 324 * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. 325 * Additionally indicate whether decoder settings were autodetected, 326 * user customized. 327 */ 328 #define CXL_DECODER_F_RAM BIT(0) 329 #define CXL_DECODER_F_PMEM BIT(1) 330 #define CXL_DECODER_F_TYPE2 BIT(2) 331 #define CXL_DECODER_F_TYPE3 BIT(3) 332 #define CXL_DECODER_F_LOCK BIT(4) 333 #define CXL_DECODER_F_ENABLE BIT(5) 334 #define CXL_DECODER_F_MASK GENMASK(5, 0) 335 336 enum cxl_decoder_type { 337 CXL_DECODER_DEVMEM = 2, 338 CXL_DECODER_HOSTONLYMEM = 3, 339 }; 340 341 /* 342 * Current specification goes up to 8, double that seems a reasonable 343 * software max for the foreseeable future 344 */ 345 #define CXL_DECODER_MAX_INTERLEAVE 16 346 347 #define CXL_QOS_CLASS_INVALID -1 348 349 /** 350 * struct cxl_decoder - Common CXL HDM Decoder Attributes 351 * @dev: this decoder's device 352 * @id: kernel device name id 353 * @hpa_range: Host physical address range mapped by this decoder 354 * @interleave_ways: number of cxl_dports in this decode 355 * @interleave_granularity: data stride per dport 356 * @target_type: accelerator vs expander (type2 vs type3) selector 357 * @region: currently assigned region for this decoder 358 * @flags: memory type capabilities and locking 359 * @commit: device/decoder-type specific callback to commit settings to hw 360 * @reset: device/decoder-type specific callback to reset hw settings 361 */ 362 struct cxl_decoder { 363 struct device dev; 364 int id; 365 struct range hpa_range; 366 int interleave_ways; 367 int interleave_granularity; 368 enum cxl_decoder_type target_type; 369 struct cxl_region *region; 370 unsigned long flags; 371 int (*commit)(struct cxl_decoder *cxld); 372 void (*reset)(struct cxl_decoder *cxld); 373 }; 374 375 /* 376 * Track whether this decoder is reserved for region autodiscovery, or 377 * free for userspace provisioning. 378 */ 379 enum cxl_decoder_state { 380 CXL_DECODER_STATE_MANUAL, 381 CXL_DECODER_STATE_AUTO, 382 }; 383 384 /** 385 * struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder 386 * @cxld: base cxl_decoder_object 387 * @dpa_res: actively claimed DPA span of this decoder 388 * @skip: offset into @dpa_res where @cxld.hpa_range maps 389 * @state: autodiscovery state 390 * @part: partition index this decoder maps 391 * @pos: interleave position in @cxld.region 392 */ 393 struct cxl_endpoint_decoder { 394 struct cxl_decoder cxld; 395 struct resource *dpa_res; 396 resource_size_t skip; 397 enum cxl_decoder_state state; 398 int part; 399 int pos; 400 }; 401 402 /** 403 * struct cxl_switch_decoder - Switch specific CXL HDM Decoder 404 * @cxld: base cxl_decoder object 405 * @nr_targets: number of elements in @target 406 * @target: active ordered target list in current decoder configuration 407 * 408 * The 'switch' decoder type represents the decoder instances of cxl_port's that 409 * route from the root of a CXL memory decode topology to the endpoints. They 410 * come in two flavors, root-level decoders, statically defined by platform 411 * firmware, and mid-level decoders, where interleave-granularity, 412 * interleave-width, and the target list are mutable. 413 */ 414 struct cxl_switch_decoder { 415 struct cxl_decoder cxld; 416 int nr_targets; 417 struct cxl_dport *target[]; 418 }; 419 420 struct cxl_root_decoder; 421 typedef u64 (*cxl_hpa_to_spa_fn)(struct cxl_root_decoder *cxlrd, u64 hpa); 422 423 /** 424 * struct cxl_root_decoder - Static platform CXL address decoder 425 * @res: host / parent resource for region allocations 426 * @region_id: region id for next region provisioning event 427 * @hpa_to_spa: translate CXL host-physical-address to Platform system-physical-address 428 * @platform_data: platform specific configuration data 429 * @range_lock: sync region autodiscovery by address range 430 * @qos_class: QoS performance class cookie 431 * @cxlsd: base cxl switch decoder 432 */ 433 struct cxl_root_decoder { 434 struct resource *res; 435 atomic_t region_id; 436 cxl_hpa_to_spa_fn hpa_to_spa; 437 void *platform_data; 438 struct mutex range_lock; 439 int qos_class; 440 struct cxl_switch_decoder cxlsd; 441 }; 442 443 /* 444 * enum cxl_config_state - State machine for region configuration 445 * @CXL_CONFIG_IDLE: Any sysfs attribute can be written freely 446 * @CXL_CONFIG_INTERLEAVE_ACTIVE: region size has been set, no more 447 * changes to interleave_ways or interleave_granularity 448 * @CXL_CONFIG_ACTIVE: All targets have been added the region is now 449 * active 450 * @CXL_CONFIG_RESET_PENDING: see commit_store() 451 * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware 452 */ 453 enum cxl_config_state { 454 CXL_CONFIG_IDLE, 455 CXL_CONFIG_INTERLEAVE_ACTIVE, 456 CXL_CONFIG_ACTIVE, 457 CXL_CONFIG_RESET_PENDING, 458 CXL_CONFIG_COMMIT, 459 }; 460 461 /** 462 * struct cxl_region_params - region settings 463 * @state: allow the driver to lockdown further parameter changes 464 * @uuid: unique id for persistent regions 465 * @interleave_ways: number of endpoints in the region 466 * @interleave_granularity: capacity each endpoint contributes to a stripe 467 * @res: allocated iomem capacity for this region 468 * @targets: active ordered targets in current decoder configuration 469 * @nr_targets: number of targets 470 * @cache_size: extended linear cache size if exists, otherwise zero. 471 * 472 * State transitions are protected by the cxl_region_rwsem 473 */ 474 struct cxl_region_params { 475 enum cxl_config_state state; 476 uuid_t uuid; 477 int interleave_ways; 478 int interleave_granularity; 479 struct resource *res; 480 struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; 481 int nr_targets; 482 resource_size_t cache_size; 483 }; 484 485 enum cxl_partition_mode { 486 CXL_PARTMODE_RAM, 487 CXL_PARTMODE_PMEM, 488 }; 489 490 /* 491 * Indicate whether this region has been assembled by autodetection or 492 * userspace assembly. Prevent endpoint decoders outside of automatic 493 * detection from being added to the region. 494 */ 495 #define CXL_REGION_F_AUTO 0 496 497 /* 498 * Require that a committed region successfully complete a teardown once 499 * any of its associated decoders have been torn down. This maintains 500 * the commit state for the region since there are committed decoders, 501 * but blocks cxl_region_probe(). 502 */ 503 #define CXL_REGION_F_NEEDS_RESET 1 504 505 /** 506 * struct cxl_region - CXL region 507 * @dev: This region's device 508 * @id: This region's id. Id is globally unique across all regions 509 * @mode: Operational mode of the mapped capacity 510 * @type: Endpoint decoder target type 511 * @cxl_nvb: nvdimm bridge for coordinating @cxlr_pmem setup / shutdown 512 * @cxlr_pmem: (for pmem regions) cached copy of the nvdimm bridge 513 * @flags: Region state flags 514 * @params: active + config params for the region 515 * @coord: QoS access coordinates for the region 516 * @memory_notifier: notifier for setting the access coordinates to node 517 * @adist_notifier: notifier for calculating the abstract distance of node 518 */ 519 struct cxl_region { 520 struct device dev; 521 int id; 522 enum cxl_partition_mode mode; 523 enum cxl_decoder_type type; 524 struct cxl_nvdimm_bridge *cxl_nvb; 525 struct cxl_pmem_region *cxlr_pmem; 526 unsigned long flags; 527 struct cxl_region_params params; 528 struct access_coordinate coord[ACCESS_COORDINATE_MAX]; 529 struct notifier_block memory_notifier; 530 struct notifier_block adist_notifier; 531 }; 532 533 struct cxl_nvdimm_bridge { 534 int id; 535 struct device dev; 536 struct cxl_port *port; 537 struct nvdimm_bus *nvdimm_bus; 538 struct nvdimm_bus_descriptor nd_desc; 539 }; 540 541 #define CXL_DEV_ID_LEN 19 542 543 struct cxl_nvdimm { 544 struct device dev; 545 struct cxl_memdev *cxlmd; 546 u8 dev_id[CXL_DEV_ID_LEN]; /* for nvdimm, string of 'serial' */ 547 u64 dirty_shutdowns; 548 }; 549 550 struct cxl_pmem_region_mapping { 551 struct cxl_memdev *cxlmd; 552 struct cxl_nvdimm *cxl_nvd; 553 u64 start; 554 u64 size; 555 int position; 556 }; 557 558 struct cxl_pmem_region { 559 struct device dev; 560 struct cxl_region *cxlr; 561 struct nd_region *nd_region; 562 struct range hpa_range; 563 int nr_mappings; 564 struct cxl_pmem_region_mapping mapping[]; 565 }; 566 567 struct cxl_dax_region { 568 struct device dev; 569 struct cxl_region *cxlr; 570 struct range hpa_range; 571 }; 572 573 /** 574 * struct cxl_port - logical collection of upstream port devices and 575 * downstream port devices to construct a CXL memory 576 * decode hierarchy. 577 * @dev: this port's device 578 * @uport_dev: PCI or platform device implementing the upstream port capability 579 * @host_bridge: Shortcut to the platform attach point for this port 580 * @id: id for port device-name 581 * @dports: cxl_dport instances referenced by decoders 582 * @endpoints: cxl_ep instances, endpoints that are a descendant of this port 583 * @regions: cxl_region_ref instances, regions mapped by this port 584 * @parent_dport: dport that points to this port in the parent 585 * @decoder_ida: allocator for decoder ids 586 * @reg_map: component and ras register mapping parameters 587 * @nr_dports: number of entries in @dports 588 * @hdm_end: track last allocated HDM decoder instance for allocation ordering 589 * @commit_end: cursor to track highest committed decoder for commit ordering 590 * @dead: last ep has been removed, force port re-creation 591 * @depth: How deep this port is relative to the root. depth 0 is the root. 592 * @cdat: Cached CDAT data 593 * @cdat_available: Should a CDAT attribute be available in sysfs 594 * @pci_latency: Upstream latency in picoseconds 595 */ 596 struct cxl_port { 597 struct device dev; 598 struct device *uport_dev; 599 struct device *host_bridge; 600 int id; 601 struct xarray dports; 602 struct xarray endpoints; 603 struct xarray regions; 604 struct cxl_dport *parent_dport; 605 struct ida decoder_ida; 606 struct cxl_register_map reg_map; 607 int nr_dports; 608 int hdm_end; 609 int commit_end; 610 bool dead; 611 unsigned int depth; 612 struct cxl_cdat { 613 void *table; 614 size_t length; 615 } cdat; 616 bool cdat_available; 617 long pci_latency; 618 }; 619 620 /** 621 * struct cxl_root - logical collection of root cxl_port items 622 * 623 * @port: cxl_port member 624 * @ops: cxl root operations 625 */ 626 struct cxl_root { 627 struct cxl_port port; 628 const struct cxl_root_ops *ops; 629 }; 630 631 static inline struct cxl_root * 632 to_cxl_root(const struct cxl_port *port) 633 { 634 return container_of(port, struct cxl_root, port); 635 } 636 637 struct cxl_root_ops { 638 int (*qos_class)(struct cxl_root *cxl_root, 639 struct access_coordinate *coord, int entries, 640 int *qos_class); 641 }; 642 643 static inline struct cxl_dport * 644 cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev) 645 { 646 return xa_load(&port->dports, (unsigned long)dport_dev); 647 } 648 649 struct cxl_rcrb_info { 650 resource_size_t base; 651 u16 aer_cap; 652 }; 653 654 /** 655 * struct cxl_dport - CXL downstream port 656 * @dport_dev: PCI bridge or firmware device representing the downstream link 657 * @reg_map: component and ras register mapping parameters 658 * @port_id: unique hardware identifier for dport in decoder target list 659 * @rcrb: Data about the Root Complex Register Block layout 660 * @rch: Indicate whether this dport was enumerated in RCH or VH mode 661 * @port: reference to cxl_port that contains this downstream port 662 * @regs: Dport parsed register blocks 663 * @coord: access coordinates (bandwidth and latency performance attributes) 664 * @link_latency: calculated PCIe downstream latency 665 * @gpf_dvsec: Cached GPF port DVSEC 666 */ 667 struct cxl_dport { 668 struct device *dport_dev; 669 struct cxl_register_map reg_map; 670 int port_id; 671 struct cxl_rcrb_info rcrb; 672 bool rch; 673 struct cxl_port *port; 674 struct cxl_regs regs; 675 struct access_coordinate coord[ACCESS_COORDINATE_MAX]; 676 long link_latency; 677 int gpf_dvsec; 678 }; 679 680 /** 681 * struct cxl_ep - track an endpoint's interest in a port 682 * @ep: device that hosts a generic CXL endpoint (expander or accelerator) 683 * @dport: which dport routes to this endpoint on @port 684 * @next: cxl switch port across the link attached to @dport NULL if 685 * attached to an endpoint 686 */ 687 struct cxl_ep { 688 struct device *ep; 689 struct cxl_dport *dport; 690 struct cxl_port *next; 691 }; 692 693 /** 694 * struct cxl_region_ref - track a region's interest in a port 695 * @port: point in topology to install this reference 696 * @decoder: decoder assigned for @region in @port 697 * @region: region for this reference 698 * @endpoints: cxl_ep references for region members beneath @port 699 * @nr_targets_set: track how many targets have been programmed during setup 700 * @nr_eps: number of endpoints beneath @port 701 * @nr_targets: number of distinct targets needed to reach @nr_eps 702 */ 703 struct cxl_region_ref { 704 struct cxl_port *port; 705 struct cxl_decoder *decoder; 706 struct cxl_region *region; 707 struct xarray endpoints; 708 int nr_targets_set; 709 int nr_eps; 710 int nr_targets; 711 }; 712 713 /* 714 * The platform firmware device hosting the root is also the top of the 715 * CXL port topology. All other CXL ports have another CXL port as their 716 * parent and their ->uport_dev / host device is out-of-line of the port 717 * ancestry. 718 */ 719 static inline bool is_cxl_root(struct cxl_port *port) 720 { 721 return port->uport_dev == port->dev.parent; 722 } 723 724 int cxl_num_decoders_committed(struct cxl_port *port); 725 bool is_cxl_port(const struct device *dev); 726 struct cxl_port *to_cxl_port(const struct device *dev); 727 struct cxl_port *parent_port_of(struct cxl_port *port); 728 void cxl_port_commit_reap(struct cxl_decoder *cxld); 729 struct pci_bus; 730 int devm_cxl_register_pci_bus(struct device *host, struct device *uport_dev, 731 struct pci_bus *bus); 732 struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port); 733 struct cxl_port *devm_cxl_add_port(struct device *host, 734 struct device *uport_dev, 735 resource_size_t component_reg_phys, 736 struct cxl_dport *parent_dport); 737 struct cxl_root *devm_cxl_add_root(struct device *host, 738 const struct cxl_root_ops *ops); 739 struct cxl_root *find_cxl_root(struct cxl_port *port); 740 741 DEFINE_FREE(put_cxl_root, struct cxl_root *, if (_T) put_device(&_T->port.dev)) 742 DEFINE_FREE(put_cxl_port, struct cxl_port *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->dev)) 743 DEFINE_FREE(put_cxl_root_decoder, struct cxl_root_decoder *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->cxlsd.cxld.dev)) 744 DEFINE_FREE(put_cxl_region, struct cxl_region *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->dev)) 745 746 int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); 747 void cxl_bus_rescan(void); 748 void cxl_bus_drain(void); 749 struct cxl_port *cxl_pci_find_port(struct pci_dev *pdev, 750 struct cxl_dport **dport); 751 struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd, 752 struct cxl_dport **dport); 753 bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd); 754 755 struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, 756 struct device *dport, int port_id, 757 resource_size_t component_reg_phys); 758 struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, 759 struct device *dport_dev, int port_id, 760 resource_size_t rcrb); 761 762 #ifdef CONFIG_PCIEAER_CXL 763 void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport); 764 void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host); 765 #else 766 static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport, 767 struct device *host) { } 768 #endif 769 770 struct cxl_decoder *to_cxl_decoder(struct device *dev); 771 struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev); 772 struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev); 773 struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev); 774 bool is_root_decoder(struct device *dev); 775 bool is_switch_decoder(struct device *dev); 776 bool is_endpoint_decoder(struct device *dev); 777 struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, 778 unsigned int nr_targets); 779 struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port, 780 unsigned int nr_targets); 781 int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map); 782 struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port); 783 int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map); 784 int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld); 785 static inline int cxl_root_decoder_autoremove(struct device *host, 786 struct cxl_root_decoder *cxlrd) 787 { 788 return cxl_decoder_autoremove(host, &cxlrd->cxlsd.cxld); 789 } 790 int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint); 791 792 /** 793 * struct cxl_endpoint_dvsec_info - Cached DVSEC info 794 * @mem_enabled: cached value of mem_enabled in the DVSEC at init time 795 * @ranges: Number of active HDM ranges this device uses. 796 * @port: endpoint port associated with this info instance 797 * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE 798 */ 799 struct cxl_endpoint_dvsec_info { 800 bool mem_enabled; 801 int ranges; 802 struct cxl_port *port; 803 struct range dvsec_range[2]; 804 }; 805 806 struct cxl_hdm; 807 struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port, 808 struct cxl_endpoint_dvsec_info *info); 809 int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm, 810 struct cxl_endpoint_dvsec_info *info); 811 int devm_cxl_add_passthrough_decoder(struct cxl_port *port); 812 struct cxl_dev_state; 813 int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds, 814 struct cxl_endpoint_dvsec_info *info); 815 816 bool is_cxl_region(struct device *dev); 817 818 extern struct bus_type cxl_bus_type; 819 820 struct cxl_driver { 821 const char *name; 822 int (*probe)(struct device *dev); 823 void (*remove)(struct device *dev); 824 struct device_driver drv; 825 int id; 826 }; 827 828 #define to_cxl_drv(__drv) container_of_const(__drv, struct cxl_driver, drv) 829 830 int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner, 831 const char *modname); 832 #define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME) 833 void cxl_driver_unregister(struct cxl_driver *cxl_drv); 834 835 #define module_cxl_driver(__cxl_driver) \ 836 module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister) 837 838 #define CXL_DEVICE_NVDIMM_BRIDGE 1 839 #define CXL_DEVICE_NVDIMM 2 840 #define CXL_DEVICE_PORT 3 841 #define CXL_DEVICE_ROOT 4 842 #define CXL_DEVICE_MEMORY_EXPANDER 5 843 #define CXL_DEVICE_REGION 6 844 #define CXL_DEVICE_PMEM_REGION 7 845 #define CXL_DEVICE_DAX_REGION 8 846 #define CXL_DEVICE_PMU 9 847 848 #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*") 849 #define CXL_MODALIAS_FMT "cxl:t%d" 850 851 struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev); 852 struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host, 853 struct cxl_port *port); 854 struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev); 855 bool is_cxl_nvdimm(struct device *dev); 856 int devm_cxl_add_nvdimm(struct cxl_port *parent_port, struct cxl_memdev *cxlmd); 857 struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_port *port); 858 859 #ifdef CONFIG_CXL_REGION 860 bool is_cxl_pmem_region(struct device *dev); 861 struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev); 862 int cxl_add_to_region(struct cxl_endpoint_decoder *cxled); 863 struct cxl_dax_region *to_cxl_dax_region(struct device *dev); 864 u64 cxl_port_get_spa_cache_alias(struct cxl_port *endpoint, u64 spa); 865 #else 866 static inline bool is_cxl_pmem_region(struct device *dev) 867 { 868 return false; 869 } 870 static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev) 871 { 872 return NULL; 873 } 874 static inline int cxl_add_to_region(struct cxl_endpoint_decoder *cxled) 875 { 876 return 0; 877 } 878 static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev) 879 { 880 return NULL; 881 } 882 static inline u64 cxl_port_get_spa_cache_alias(struct cxl_port *endpoint, 883 u64 spa) 884 { 885 return 0; 886 } 887 #endif 888 889 void cxl_endpoint_parse_cdat(struct cxl_port *port); 890 void cxl_switch_parse_cdat(struct cxl_port *port); 891 892 int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, 893 struct access_coordinate *coord); 894 void cxl_region_perf_data_calculate(struct cxl_region *cxlr, 895 struct cxl_endpoint_decoder *cxled); 896 void cxl_region_shared_upstream_bandwidth_update(struct cxl_region *cxlr); 897 898 void cxl_memdev_update_perf(struct cxl_memdev *cxlmd); 899 900 void cxl_coordinates_combine(struct access_coordinate *out, 901 struct access_coordinate *c1, 902 struct access_coordinate *c2); 903 904 bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port); 905 906 /* 907 * Unit test builds overrides this to __weak, find the 'strong' version 908 * of these symbols in tools/testing/cxl/. 909 */ 910 #ifndef __mock 911 #define __mock static 912 #endif 913 914 u16 cxl_gpf_get_dvsec(struct device *dev); 915 916 static inline struct rw_semaphore *rwsem_read_intr_acquire(struct rw_semaphore *rwsem) 917 { 918 if (down_read_interruptible(rwsem)) 919 return NULL; 920 921 return rwsem; 922 } 923 924 DEFINE_FREE(rwsem_read_release, struct rw_semaphore *, if (_T) up_read(_T)) 925 926 #endif /* __CXL_H__ */ 927