1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Support for OMAP DES and Triple DES HW acceleration. 4 * 5 * Copyright (c) 2013 Texas Instruments Incorporated 6 * Author: Joel Fernandes <joelf@ti.com> 7 */ 8 9 #define pr_fmt(fmt) "%s: " fmt, __func__ 10 11 #ifdef DEBUG 12 #define prn(num) printk(#num "=%d\n", num) 13 #define prx(num) printk(#num "=%x\n", num) 14 #else 15 #define prn(num) do { } while (0) 16 #define prx(num) do { } while (0) 17 #endif 18 19 #include <crypto/engine.h> 20 #include <crypto/internal/des.h> 21 #include <crypto/internal/skcipher.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/dmaengine.h> 24 #include <linux/err.h> 25 #include <linux/init.h> 26 #include <linux/interrupt.h> 27 #include <linux/io.h> 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/of.h> 31 #include <linux/platform_device.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/scatterlist.h> 34 #include <linux/string.h> 35 36 #include "omap-crypto.h" 37 38 #define DST_MAXBURST 2 39 40 #define DES_BLOCK_WORDS (DES_BLOCK_SIZE >> 2) 41 42 #define DES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \ 43 ((x ^ 0x01) * 0x04)) 44 45 #define DES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04)) 46 47 #define DES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs) 48 #define DES_REG_CTRL_CBC BIT(4) 49 #define DES_REG_CTRL_TDES BIT(3) 50 #define DES_REG_CTRL_DIRECTION BIT(2) 51 #define DES_REG_CTRL_INPUT_READY BIT(1) 52 #define DES_REG_CTRL_OUTPUT_READY BIT(0) 53 54 #define DES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04)) 55 56 #define DES_REG_REV(dd) ((dd)->pdata->rev_ofs) 57 58 #define DES_REG_MASK(dd) ((dd)->pdata->mask_ofs) 59 60 #define DES_REG_LENGTH_N(x) (0x24 + ((x) * 0x04)) 61 62 #define DES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs) 63 #define DES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs) 64 #define DES_REG_IRQ_DATA_IN BIT(1) 65 #define DES_REG_IRQ_DATA_OUT BIT(2) 66 67 #define FLAGS_MODE_MASK 0x000f 68 #define FLAGS_ENCRYPT BIT(0) 69 #define FLAGS_CBC BIT(1) 70 #define FLAGS_INIT BIT(4) 71 #define FLAGS_BUSY BIT(6) 72 73 #define DEFAULT_AUTOSUSPEND_DELAY 1000 74 75 #define FLAGS_IN_DATA_ST_SHIFT 8 76 #define FLAGS_OUT_DATA_ST_SHIFT 10 77 78 struct omap_des_ctx { 79 struct omap_des_dev *dd; 80 81 int keylen; 82 __le32 key[(3 * DES_KEY_SIZE) / sizeof(u32)]; 83 unsigned long flags; 84 }; 85 86 struct omap_des_reqctx { 87 unsigned long mode; 88 }; 89 90 #define OMAP_DES_QUEUE_LENGTH 1 91 #define OMAP_DES_CACHE_SIZE 0 92 93 struct omap_des_algs_info { 94 struct skcipher_engine_alg *algs_list; 95 unsigned int size; 96 unsigned int registered; 97 }; 98 99 struct omap_des_pdata { 100 struct omap_des_algs_info *algs_info; 101 unsigned int algs_info_size; 102 103 void (*trigger)(struct omap_des_dev *dd, int length); 104 105 u32 key_ofs; 106 u32 iv_ofs; 107 u32 ctrl_ofs; 108 u32 data_ofs; 109 u32 rev_ofs; 110 u32 mask_ofs; 111 u32 irq_enable_ofs; 112 u32 irq_status_ofs; 113 114 u32 dma_enable_in; 115 u32 dma_enable_out; 116 u32 dma_start; 117 118 u32 major_mask; 119 u32 major_shift; 120 u32 minor_mask; 121 u32 minor_shift; 122 }; 123 124 struct omap_des_dev { 125 struct list_head list; 126 unsigned long phys_base; 127 void __iomem *io_base; 128 struct omap_des_ctx *ctx; 129 struct device *dev; 130 unsigned long flags; 131 int err; 132 133 struct tasklet_struct done_task; 134 135 struct skcipher_request *req; 136 struct crypto_engine *engine; 137 /* 138 * total is used by PIO mode for book keeping so introduce 139 * variable total_save as need it to calc page_order 140 */ 141 size_t total; 142 size_t total_save; 143 144 struct scatterlist *in_sg; 145 struct scatterlist *out_sg; 146 147 /* Buffers for copying for unaligned cases */ 148 struct scatterlist in_sgl; 149 struct scatterlist out_sgl; 150 struct scatterlist *orig_out; 151 152 unsigned int in_sg_offset; 153 unsigned int out_sg_offset; 154 struct dma_chan *dma_lch_in; 155 struct dma_chan *dma_lch_out; 156 int in_sg_len; 157 int out_sg_len; 158 int pio_only; 159 const struct omap_des_pdata *pdata; 160 }; 161 162 /* keep registered devices data here */ 163 static LIST_HEAD(dev_list); 164 static DEFINE_SPINLOCK(list_lock); 165 166 #ifdef DEBUG 167 #define omap_des_read(dd, offset) \ 168 ({ \ 169 int _read_ret; \ 170 _read_ret = __raw_readl(dd->io_base + offset); \ 171 pr_err("omap_des_read(" #offset "=%#x)= %#x\n", \ 172 offset, _read_ret); \ 173 _read_ret; \ 174 }) 175 #else 176 static inline u32 omap_des_read(struct omap_des_dev *dd, u32 offset) 177 { 178 return __raw_readl(dd->io_base + offset); 179 } 180 #endif 181 182 #ifdef DEBUG 183 #define omap_des_write(dd, offset, value) \ 184 do { \ 185 pr_err("omap_des_write(" #offset "=%#x) value=%#x\n", \ 186 offset, value); \ 187 __raw_writel(value, dd->io_base + offset); \ 188 } while (0) 189 #else 190 static inline void omap_des_write(struct omap_des_dev *dd, u32 offset, 191 u32 value) 192 { 193 __raw_writel(value, dd->io_base + offset); 194 } 195 #endif 196 197 static inline void omap_des_write_mask(struct omap_des_dev *dd, u32 offset, 198 u32 value, u32 mask) 199 { 200 u32 val; 201 202 val = omap_des_read(dd, offset); 203 val &= ~mask; 204 val |= value; 205 omap_des_write(dd, offset, val); 206 } 207 208 static void omap_des_write_n(struct omap_des_dev *dd, u32 offset, 209 u32 *value, int count) 210 { 211 for (; count--; value++, offset += 4) 212 omap_des_write(dd, offset, *value); 213 } 214 215 static int omap_des_hw_init(struct omap_des_dev *dd) 216 { 217 int err; 218 219 /* 220 * clocks are enabled when request starts and disabled when finished. 221 * It may be long delays between requests. 222 * Device might go to off mode to save power. 223 */ 224 err = pm_runtime_resume_and_get(dd->dev); 225 if (err < 0) { 226 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err); 227 return err; 228 } 229 230 if (!(dd->flags & FLAGS_INIT)) { 231 dd->flags |= FLAGS_INIT; 232 dd->err = 0; 233 } 234 235 return 0; 236 } 237 238 static int omap_des_write_ctrl(struct omap_des_dev *dd) 239 { 240 unsigned int key32; 241 int i, err; 242 u32 val = 0, mask = 0; 243 244 err = omap_des_hw_init(dd); 245 if (err) 246 return err; 247 248 key32 = dd->ctx->keylen / sizeof(u32); 249 250 /* it seems a key should always be set even if it has not changed */ 251 for (i = 0; i < key32; i++) { 252 omap_des_write(dd, DES_REG_KEY(dd, i), 253 __le32_to_cpu(dd->ctx->key[i])); 254 } 255 256 if ((dd->flags & FLAGS_CBC) && dd->req->iv) 257 omap_des_write_n(dd, DES_REG_IV(dd, 0), (void *)dd->req->iv, 2); 258 259 if (dd->flags & FLAGS_CBC) 260 val |= DES_REG_CTRL_CBC; 261 if (dd->flags & FLAGS_ENCRYPT) 262 val |= DES_REG_CTRL_DIRECTION; 263 if (key32 == 6) 264 val |= DES_REG_CTRL_TDES; 265 266 mask |= DES_REG_CTRL_CBC | DES_REG_CTRL_DIRECTION | DES_REG_CTRL_TDES; 267 268 omap_des_write_mask(dd, DES_REG_CTRL(dd), val, mask); 269 270 return 0; 271 } 272 273 static void omap_des_dma_trigger_omap4(struct omap_des_dev *dd, int length) 274 { 275 u32 mask, val; 276 277 omap_des_write(dd, DES_REG_LENGTH_N(0), length); 278 279 val = dd->pdata->dma_start; 280 281 if (dd->dma_lch_out != NULL) 282 val |= dd->pdata->dma_enable_out; 283 if (dd->dma_lch_in != NULL) 284 val |= dd->pdata->dma_enable_in; 285 286 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 287 dd->pdata->dma_start; 288 289 omap_des_write_mask(dd, DES_REG_MASK(dd), val, mask); 290 } 291 292 static void omap_des_dma_stop(struct omap_des_dev *dd) 293 { 294 u32 mask; 295 296 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 297 dd->pdata->dma_start; 298 299 omap_des_write_mask(dd, DES_REG_MASK(dd), 0, mask); 300 } 301 302 static struct omap_des_dev *omap_des_find_dev(struct omap_des_ctx *ctx) 303 { 304 struct omap_des_dev *dd = NULL, *tmp; 305 306 spin_lock_bh(&list_lock); 307 if (!ctx->dd) { 308 list_for_each_entry(tmp, &dev_list, list) { 309 /* FIXME: take fist available des core */ 310 dd = tmp; 311 break; 312 } 313 ctx->dd = dd; 314 } else { 315 /* already found before */ 316 dd = ctx->dd; 317 } 318 spin_unlock_bh(&list_lock); 319 320 return dd; 321 } 322 323 static void omap_des_dma_out_callback(void *data) 324 { 325 struct omap_des_dev *dd = data; 326 327 /* dma_lch_out - completed */ 328 tasklet_schedule(&dd->done_task); 329 } 330 331 static int omap_des_dma_init(struct omap_des_dev *dd) 332 { 333 int err; 334 335 dd->dma_lch_out = NULL; 336 dd->dma_lch_in = NULL; 337 338 dd->dma_lch_in = dma_request_chan(dd->dev, "rx"); 339 if (IS_ERR(dd->dma_lch_in)) { 340 dev_err(dd->dev, "Unable to request in DMA channel\n"); 341 return PTR_ERR(dd->dma_lch_in); 342 } 343 344 dd->dma_lch_out = dma_request_chan(dd->dev, "tx"); 345 if (IS_ERR(dd->dma_lch_out)) { 346 dev_err(dd->dev, "Unable to request out DMA channel\n"); 347 err = PTR_ERR(dd->dma_lch_out); 348 goto err_dma_out; 349 } 350 351 return 0; 352 353 err_dma_out: 354 dma_release_channel(dd->dma_lch_in); 355 356 return err; 357 } 358 359 static void omap_des_dma_cleanup(struct omap_des_dev *dd) 360 { 361 if (dd->pio_only) 362 return; 363 364 dma_release_channel(dd->dma_lch_out); 365 dma_release_channel(dd->dma_lch_in); 366 } 367 368 static int omap_des_crypt_dma(struct crypto_tfm *tfm, 369 struct scatterlist *in_sg, struct scatterlist *out_sg, 370 int in_sg_len, int out_sg_len) 371 { 372 struct omap_des_ctx *ctx = crypto_tfm_ctx(tfm); 373 struct omap_des_dev *dd = ctx->dd; 374 struct dma_async_tx_descriptor *tx_in, *tx_out; 375 struct dma_slave_config cfg; 376 int ret; 377 378 if (dd->pio_only) { 379 dd->in_sg_offset = 0; 380 dd->out_sg_offset = 0; 381 382 /* Enable DATAIN interrupt and let it take 383 care of the rest */ 384 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2); 385 return 0; 386 } 387 388 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE); 389 390 memset(&cfg, 0, sizeof(cfg)); 391 392 cfg.src_addr = dd->phys_base + DES_REG_DATA_N(dd, 0); 393 cfg.dst_addr = dd->phys_base + DES_REG_DATA_N(dd, 0); 394 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 395 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 396 cfg.src_maxburst = DST_MAXBURST; 397 cfg.dst_maxburst = DST_MAXBURST; 398 399 /* IN */ 400 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg); 401 if (ret) { 402 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n", 403 ret); 404 return ret; 405 } 406 407 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len, 408 DMA_MEM_TO_DEV, 409 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 410 if (!tx_in) { 411 dev_err(dd->dev, "IN prep_slave_sg() failed\n"); 412 return -EINVAL; 413 } 414 415 /* No callback necessary */ 416 tx_in->callback_param = dd; 417 418 /* OUT */ 419 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg); 420 if (ret) { 421 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n", 422 ret); 423 return ret; 424 } 425 426 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len, 427 DMA_DEV_TO_MEM, 428 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 429 if (!tx_out) { 430 dev_err(dd->dev, "OUT prep_slave_sg() failed\n"); 431 return -EINVAL; 432 } 433 434 tx_out->callback = omap_des_dma_out_callback; 435 tx_out->callback_param = dd; 436 437 dmaengine_submit(tx_in); 438 dmaengine_submit(tx_out); 439 440 dma_async_issue_pending(dd->dma_lch_in); 441 dma_async_issue_pending(dd->dma_lch_out); 442 443 /* start DMA */ 444 dd->pdata->trigger(dd, dd->total); 445 446 return 0; 447 } 448 449 static int omap_des_crypt_dma_start(struct omap_des_dev *dd) 450 { 451 struct crypto_tfm *tfm = crypto_skcipher_tfm( 452 crypto_skcipher_reqtfm(dd->req)); 453 int err; 454 455 pr_debug("total: %zd\n", dd->total); 456 457 if (!dd->pio_only) { 458 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len, 459 DMA_TO_DEVICE); 460 if (!err) { 461 dev_err(dd->dev, "dma_map_sg() error\n"); 462 return -EINVAL; 463 } 464 465 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len, 466 DMA_FROM_DEVICE); 467 if (!err) { 468 dev_err(dd->dev, "dma_map_sg() error\n"); 469 return -EINVAL; 470 } 471 } 472 473 err = omap_des_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len, 474 dd->out_sg_len); 475 if (err && !dd->pio_only) { 476 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 477 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, 478 DMA_FROM_DEVICE); 479 } 480 481 return err; 482 } 483 484 static void omap_des_finish_req(struct omap_des_dev *dd, int err) 485 { 486 struct skcipher_request *req = dd->req; 487 488 pr_debug("err: %d\n", err); 489 490 crypto_finalize_skcipher_request(dd->engine, req, err); 491 492 pm_runtime_mark_last_busy(dd->dev); 493 pm_runtime_put_autosuspend(dd->dev); 494 } 495 496 static int omap_des_crypt_dma_stop(struct omap_des_dev *dd) 497 { 498 pr_debug("total: %zd\n", dd->total); 499 500 omap_des_dma_stop(dd); 501 502 dmaengine_terminate_all(dd->dma_lch_in); 503 dmaengine_terminate_all(dd->dma_lch_out); 504 505 return 0; 506 } 507 508 static int omap_des_handle_queue(struct omap_des_dev *dd, 509 struct skcipher_request *req) 510 { 511 if (req) 512 return crypto_transfer_skcipher_request_to_engine(dd->engine, req); 513 514 return 0; 515 } 516 517 static int omap_des_prepare_req(struct skcipher_request *req, 518 struct omap_des_dev *dd) 519 { 520 struct omap_des_ctx *ctx = crypto_skcipher_ctx( 521 crypto_skcipher_reqtfm(req)); 522 struct omap_des_reqctx *rctx; 523 int ret; 524 u16 flags; 525 526 /* assign new request to device */ 527 dd->req = req; 528 dd->total = req->cryptlen; 529 dd->total_save = req->cryptlen; 530 dd->in_sg = req->src; 531 dd->out_sg = req->dst; 532 dd->orig_out = req->dst; 533 534 flags = OMAP_CRYPTO_COPY_DATA; 535 if (req->src == req->dst) 536 flags |= OMAP_CRYPTO_FORCE_COPY; 537 538 ret = omap_crypto_align_sg(&dd->in_sg, dd->total, DES_BLOCK_SIZE, 539 &dd->in_sgl, flags, 540 FLAGS_IN_DATA_ST_SHIFT, &dd->flags); 541 if (ret) 542 return ret; 543 544 ret = omap_crypto_align_sg(&dd->out_sg, dd->total, DES_BLOCK_SIZE, 545 &dd->out_sgl, 0, 546 FLAGS_OUT_DATA_ST_SHIFT, &dd->flags); 547 if (ret) 548 return ret; 549 550 dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total); 551 if (dd->in_sg_len < 0) 552 return dd->in_sg_len; 553 554 dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total); 555 if (dd->out_sg_len < 0) 556 return dd->out_sg_len; 557 558 rctx = skcipher_request_ctx(req); 559 ctx = crypto_skcipher_ctx(crypto_skcipher_reqtfm(req)); 560 rctx->mode &= FLAGS_MODE_MASK; 561 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode; 562 563 dd->ctx = ctx; 564 ctx->dd = dd; 565 566 return omap_des_write_ctrl(dd); 567 } 568 569 static int omap_des_crypt_req(struct crypto_engine *engine, 570 void *areq) 571 { 572 struct skcipher_request *req = container_of(areq, struct skcipher_request, base); 573 struct omap_des_ctx *ctx = crypto_skcipher_ctx( 574 crypto_skcipher_reqtfm(req)); 575 struct omap_des_dev *dd = omap_des_find_dev(ctx); 576 577 if (!dd) 578 return -ENODEV; 579 580 return omap_des_prepare_req(req, dd) ?: 581 omap_des_crypt_dma_start(dd); 582 } 583 584 static void omap_des_done_task(unsigned long data) 585 { 586 struct omap_des_dev *dd = (struct omap_des_dev *)data; 587 int i; 588 589 pr_debug("enter done_task\n"); 590 591 if (!dd->pio_only) { 592 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len, 593 DMA_FROM_DEVICE); 594 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 595 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, 596 DMA_FROM_DEVICE); 597 omap_des_crypt_dma_stop(dd); 598 } 599 600 omap_crypto_cleanup(&dd->in_sgl, NULL, 0, dd->total_save, 601 FLAGS_IN_DATA_ST_SHIFT, dd->flags); 602 603 omap_crypto_cleanup(&dd->out_sgl, dd->orig_out, 0, dd->total_save, 604 FLAGS_OUT_DATA_ST_SHIFT, dd->flags); 605 606 if ((dd->flags & FLAGS_CBC) && dd->req->iv) 607 for (i = 0; i < 2; i++) 608 ((u32 *)dd->req->iv)[i] = 609 omap_des_read(dd, DES_REG_IV(dd, i)); 610 611 omap_des_finish_req(dd, 0); 612 613 pr_debug("exit\n"); 614 } 615 616 static int omap_des_crypt(struct skcipher_request *req, unsigned long mode) 617 { 618 struct omap_des_ctx *ctx = crypto_skcipher_ctx( 619 crypto_skcipher_reqtfm(req)); 620 struct omap_des_reqctx *rctx = skcipher_request_ctx(req); 621 struct omap_des_dev *dd; 622 623 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->cryptlen, 624 !!(mode & FLAGS_ENCRYPT), 625 !!(mode & FLAGS_CBC)); 626 627 if (!req->cryptlen) 628 return 0; 629 630 if (!IS_ALIGNED(req->cryptlen, DES_BLOCK_SIZE)) 631 return -EINVAL; 632 633 dd = omap_des_find_dev(ctx); 634 if (!dd) 635 return -ENODEV; 636 637 rctx->mode = mode; 638 639 return omap_des_handle_queue(dd, req); 640 } 641 642 /* ********************** ALG API ************************************ */ 643 644 static int omap_des_setkey(struct crypto_skcipher *cipher, const u8 *key, 645 unsigned int keylen) 646 { 647 struct omap_des_ctx *ctx = crypto_skcipher_ctx(cipher); 648 int err; 649 650 pr_debug("enter, keylen: %d\n", keylen); 651 652 err = verify_skcipher_des_key(cipher, key); 653 if (err) 654 return err; 655 656 memcpy(ctx->key, key, keylen); 657 ctx->keylen = keylen; 658 659 return 0; 660 } 661 662 static int omap_des3_setkey(struct crypto_skcipher *cipher, const u8 *key, 663 unsigned int keylen) 664 { 665 struct omap_des_ctx *ctx = crypto_skcipher_ctx(cipher); 666 int err; 667 668 pr_debug("enter, keylen: %d\n", keylen); 669 670 err = verify_skcipher_des3_key(cipher, key); 671 if (err) 672 return err; 673 674 memcpy(ctx->key, key, keylen); 675 ctx->keylen = keylen; 676 677 return 0; 678 } 679 680 static int omap_des_ecb_encrypt(struct skcipher_request *req) 681 { 682 return omap_des_crypt(req, FLAGS_ENCRYPT); 683 } 684 685 static int omap_des_ecb_decrypt(struct skcipher_request *req) 686 { 687 return omap_des_crypt(req, 0); 688 } 689 690 static int omap_des_cbc_encrypt(struct skcipher_request *req) 691 { 692 return omap_des_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC); 693 } 694 695 static int omap_des_cbc_decrypt(struct skcipher_request *req) 696 { 697 return omap_des_crypt(req, FLAGS_CBC); 698 } 699 700 static int omap_des_init_tfm(struct crypto_skcipher *tfm) 701 { 702 pr_debug("enter\n"); 703 704 crypto_skcipher_set_reqsize(tfm, sizeof(struct omap_des_reqctx)); 705 706 return 0; 707 } 708 709 /* ********************** ALGS ************************************ */ 710 711 static struct skcipher_engine_alg algs_ecb_cbc[] = { 712 { 713 .base = { 714 .base.cra_name = "ecb(des)", 715 .base.cra_driver_name = "ecb-des-omap", 716 .base.cra_priority = 300, 717 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 718 CRYPTO_ALG_ASYNC, 719 .base.cra_blocksize = DES_BLOCK_SIZE, 720 .base.cra_ctxsize = sizeof(struct omap_des_ctx), 721 .base.cra_module = THIS_MODULE, 722 723 .min_keysize = DES_KEY_SIZE, 724 .max_keysize = DES_KEY_SIZE, 725 .setkey = omap_des_setkey, 726 .encrypt = omap_des_ecb_encrypt, 727 .decrypt = omap_des_ecb_decrypt, 728 .init = omap_des_init_tfm, 729 }, 730 .op.do_one_request = omap_des_crypt_req, 731 }, 732 { 733 .base = { 734 .base.cra_name = "cbc(des)", 735 .base.cra_driver_name = "cbc-des-omap", 736 .base.cra_priority = 300, 737 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 738 CRYPTO_ALG_ASYNC, 739 .base.cra_blocksize = DES_BLOCK_SIZE, 740 .base.cra_ctxsize = sizeof(struct omap_des_ctx), 741 .base.cra_module = THIS_MODULE, 742 743 .min_keysize = DES_KEY_SIZE, 744 .max_keysize = DES_KEY_SIZE, 745 .ivsize = DES_BLOCK_SIZE, 746 .setkey = omap_des_setkey, 747 .encrypt = omap_des_cbc_encrypt, 748 .decrypt = omap_des_cbc_decrypt, 749 .init = omap_des_init_tfm, 750 }, 751 .op.do_one_request = omap_des_crypt_req, 752 }, 753 { 754 .base = { 755 .base.cra_name = "ecb(des3_ede)", 756 .base.cra_driver_name = "ecb-des3-omap", 757 .base.cra_priority = 300, 758 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 759 CRYPTO_ALG_ASYNC, 760 .base.cra_blocksize = DES3_EDE_BLOCK_SIZE, 761 .base.cra_ctxsize = sizeof(struct omap_des_ctx), 762 .base.cra_module = THIS_MODULE, 763 764 .min_keysize = DES3_EDE_KEY_SIZE, 765 .max_keysize = DES3_EDE_KEY_SIZE, 766 .setkey = omap_des3_setkey, 767 .encrypt = omap_des_ecb_encrypt, 768 .decrypt = omap_des_ecb_decrypt, 769 .init = omap_des_init_tfm, 770 }, 771 .op.do_one_request = omap_des_crypt_req, 772 }, 773 { 774 .base = { 775 .base.cra_name = "cbc(des3_ede)", 776 .base.cra_driver_name = "cbc-des3-omap", 777 .base.cra_priority = 300, 778 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 779 CRYPTO_ALG_ASYNC, 780 .base.cra_blocksize = DES3_EDE_BLOCK_SIZE, 781 .base.cra_ctxsize = sizeof(struct omap_des_ctx), 782 .base.cra_module = THIS_MODULE, 783 784 .min_keysize = DES3_EDE_KEY_SIZE, 785 .max_keysize = DES3_EDE_KEY_SIZE, 786 .ivsize = DES3_EDE_BLOCK_SIZE, 787 .setkey = omap_des3_setkey, 788 .encrypt = omap_des_cbc_encrypt, 789 .decrypt = omap_des_cbc_decrypt, 790 .init = omap_des_init_tfm, 791 }, 792 .op.do_one_request = omap_des_crypt_req, 793 } 794 }; 795 796 static struct omap_des_algs_info omap_des_algs_info_ecb_cbc[] = { 797 { 798 .algs_list = algs_ecb_cbc, 799 .size = ARRAY_SIZE(algs_ecb_cbc), 800 }, 801 }; 802 803 #ifdef CONFIG_OF 804 static const struct omap_des_pdata omap_des_pdata_omap4 = { 805 .algs_info = omap_des_algs_info_ecb_cbc, 806 .algs_info_size = ARRAY_SIZE(omap_des_algs_info_ecb_cbc), 807 .trigger = omap_des_dma_trigger_omap4, 808 .key_ofs = 0x14, 809 .iv_ofs = 0x18, 810 .ctrl_ofs = 0x20, 811 .data_ofs = 0x28, 812 .rev_ofs = 0x30, 813 .mask_ofs = 0x34, 814 .irq_status_ofs = 0x3c, 815 .irq_enable_ofs = 0x40, 816 .dma_enable_in = BIT(5), 817 .dma_enable_out = BIT(6), 818 .major_mask = 0x0700, 819 .major_shift = 8, 820 .minor_mask = 0x003f, 821 .minor_shift = 0, 822 }; 823 824 static irqreturn_t omap_des_irq(int irq, void *dev_id) 825 { 826 struct omap_des_dev *dd = dev_id; 827 u32 status, i; 828 u32 *src, *dst; 829 830 status = omap_des_read(dd, DES_REG_IRQ_STATUS(dd)); 831 if (status & DES_REG_IRQ_DATA_IN) { 832 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0); 833 834 BUG_ON(!dd->in_sg); 835 836 BUG_ON(dd->in_sg_offset > dd->in_sg->length); 837 838 src = sg_virt(dd->in_sg) + dd->in_sg_offset; 839 840 for (i = 0; i < DES_BLOCK_WORDS; i++) { 841 omap_des_write(dd, DES_REG_DATA_N(dd, i), *src); 842 dd->in_sg_offset += 4; 843 if (dd->in_sg_offset == dd->in_sg->length) { 844 dd->in_sg = sg_next(dd->in_sg); 845 if (dd->in_sg) { 846 dd->in_sg_offset = 0; 847 src = sg_virt(dd->in_sg); 848 } 849 } else { 850 src++; 851 } 852 } 853 854 /* Clear IRQ status */ 855 status &= ~DES_REG_IRQ_DATA_IN; 856 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status); 857 858 /* Enable DATA_OUT interrupt */ 859 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x4); 860 861 } else if (status & DES_REG_IRQ_DATA_OUT) { 862 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0); 863 864 BUG_ON(!dd->out_sg); 865 866 BUG_ON(dd->out_sg_offset > dd->out_sg->length); 867 868 dst = sg_virt(dd->out_sg) + dd->out_sg_offset; 869 870 for (i = 0; i < DES_BLOCK_WORDS; i++) { 871 *dst = omap_des_read(dd, DES_REG_DATA_N(dd, i)); 872 dd->out_sg_offset += 4; 873 if (dd->out_sg_offset == dd->out_sg->length) { 874 dd->out_sg = sg_next(dd->out_sg); 875 if (dd->out_sg) { 876 dd->out_sg_offset = 0; 877 dst = sg_virt(dd->out_sg); 878 } 879 } else { 880 dst++; 881 } 882 } 883 884 BUG_ON(dd->total < DES_BLOCK_SIZE); 885 886 dd->total -= DES_BLOCK_SIZE; 887 888 /* Clear IRQ status */ 889 status &= ~DES_REG_IRQ_DATA_OUT; 890 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status); 891 892 if (!dd->total) 893 /* All bytes read! */ 894 tasklet_schedule(&dd->done_task); 895 else 896 /* Enable DATA_IN interrupt for next block */ 897 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2); 898 } 899 900 return IRQ_HANDLED; 901 } 902 903 static const struct of_device_id omap_des_of_match[] = { 904 { 905 .compatible = "ti,omap4-des", 906 .data = &omap_des_pdata_omap4, 907 }, 908 {}, 909 }; 910 MODULE_DEVICE_TABLE(of, omap_des_of_match); 911 912 static int omap_des_get_of(struct omap_des_dev *dd, 913 struct platform_device *pdev) 914 { 915 916 dd->pdata = of_device_get_match_data(&pdev->dev); 917 if (!dd->pdata) { 918 dev_err(&pdev->dev, "no compatible OF match\n"); 919 return -EINVAL; 920 } 921 922 return 0; 923 } 924 #else 925 static int omap_des_get_of(struct omap_des_dev *dd, 926 struct device *dev) 927 { 928 return -EINVAL; 929 } 930 #endif 931 932 static int omap_des_get_pdev(struct omap_des_dev *dd, 933 struct platform_device *pdev) 934 { 935 /* non-DT devices get pdata from pdev */ 936 dd->pdata = pdev->dev.platform_data; 937 938 return 0; 939 } 940 941 static int omap_des_probe(struct platform_device *pdev) 942 { 943 struct device *dev = &pdev->dev; 944 struct omap_des_dev *dd; 945 struct skcipher_engine_alg *algp; 946 struct resource *res; 947 int err = -ENOMEM, i, j, irq = -1; 948 u32 reg; 949 950 dd = devm_kzalloc(dev, sizeof(struct omap_des_dev), GFP_KERNEL); 951 if (dd == NULL) { 952 dev_err(dev, "unable to alloc data struct.\n"); 953 goto err_data; 954 } 955 dd->dev = dev; 956 platform_set_drvdata(pdev, dd); 957 958 err = (dev->of_node) ? omap_des_get_of(dd, pdev) : 959 omap_des_get_pdev(dd, pdev); 960 if (err) 961 goto err_res; 962 963 dd->io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 964 if (IS_ERR(dd->io_base)) { 965 err = PTR_ERR(dd->io_base); 966 goto err_res; 967 } 968 dd->phys_base = res->start; 969 970 pm_runtime_use_autosuspend(dev); 971 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY); 972 973 pm_runtime_enable(dev); 974 err = pm_runtime_resume_and_get(dev); 975 if (err < 0) { 976 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err); 977 goto err_get; 978 } 979 980 omap_des_dma_stop(dd); 981 982 reg = omap_des_read(dd, DES_REG_REV(dd)); 983 984 pm_runtime_put_sync(dev); 985 986 dev_info(dev, "OMAP DES hw accel rev: %u.%u\n", 987 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift, 988 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift); 989 990 tasklet_init(&dd->done_task, omap_des_done_task, (unsigned long)dd); 991 992 err = omap_des_dma_init(dd); 993 if (err == -EPROBE_DEFER) { 994 goto err_irq; 995 } else if (err && DES_REG_IRQ_STATUS(dd) && DES_REG_IRQ_ENABLE(dd)) { 996 dd->pio_only = 1; 997 998 irq = platform_get_irq(pdev, 0); 999 if (irq < 0) { 1000 err = irq; 1001 goto err_irq; 1002 } 1003 1004 err = devm_request_irq(dev, irq, omap_des_irq, 0, 1005 dev_name(dev), dd); 1006 if (err) { 1007 dev_err(dev, "Unable to grab omap-des IRQ\n"); 1008 goto err_irq; 1009 } 1010 } 1011 1012 1013 INIT_LIST_HEAD(&dd->list); 1014 spin_lock_bh(&list_lock); 1015 list_add_tail(&dd->list, &dev_list); 1016 spin_unlock_bh(&list_lock); 1017 1018 /* Initialize des crypto engine */ 1019 dd->engine = crypto_engine_alloc_init(dev, 1); 1020 if (!dd->engine) { 1021 err = -ENOMEM; 1022 goto err_engine; 1023 } 1024 1025 err = crypto_engine_start(dd->engine); 1026 if (err) 1027 goto err_engine; 1028 1029 for (i = 0; i < dd->pdata->algs_info_size; i++) { 1030 for (j = 0; j < dd->pdata->algs_info[i].size; j++) { 1031 algp = &dd->pdata->algs_info[i].algs_list[j]; 1032 1033 pr_debug("reg alg: %s\n", algp->base.base.cra_name); 1034 1035 err = crypto_engine_register_skcipher(algp); 1036 if (err) 1037 goto err_algs; 1038 1039 dd->pdata->algs_info[i].registered++; 1040 } 1041 } 1042 1043 return 0; 1044 1045 err_algs: 1046 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1047 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1048 crypto_engine_unregister_skcipher( 1049 &dd->pdata->algs_info[i].algs_list[j]); 1050 1051 err_engine: 1052 if (dd->engine) 1053 crypto_engine_exit(dd->engine); 1054 1055 omap_des_dma_cleanup(dd); 1056 err_irq: 1057 tasklet_kill(&dd->done_task); 1058 err_get: 1059 pm_runtime_disable(dev); 1060 err_res: 1061 dd = NULL; 1062 err_data: 1063 dev_err(dev, "initialization failed.\n"); 1064 return err; 1065 } 1066 1067 static void omap_des_remove(struct platform_device *pdev) 1068 { 1069 struct omap_des_dev *dd = platform_get_drvdata(pdev); 1070 int i, j; 1071 1072 spin_lock_bh(&list_lock); 1073 list_del(&dd->list); 1074 spin_unlock_bh(&list_lock); 1075 1076 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1077 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1078 crypto_engine_unregister_skcipher( 1079 &dd->pdata->algs_info[i].algs_list[j]); 1080 1081 tasklet_kill(&dd->done_task); 1082 omap_des_dma_cleanup(dd); 1083 pm_runtime_disable(dd->dev); 1084 } 1085 1086 #ifdef CONFIG_PM_SLEEP 1087 static int omap_des_suspend(struct device *dev) 1088 { 1089 pm_runtime_put_sync(dev); 1090 return 0; 1091 } 1092 1093 static int omap_des_resume(struct device *dev) 1094 { 1095 int err; 1096 1097 err = pm_runtime_resume_and_get(dev); 1098 if (err < 0) { 1099 dev_err(dev, "%s: failed to get_sync(%d)\n", __func__, err); 1100 return err; 1101 } 1102 return 0; 1103 } 1104 #endif 1105 1106 static SIMPLE_DEV_PM_OPS(omap_des_pm_ops, omap_des_suspend, omap_des_resume); 1107 1108 static struct platform_driver omap_des_driver = { 1109 .probe = omap_des_probe, 1110 .remove = omap_des_remove, 1111 .driver = { 1112 .name = "omap-des", 1113 .pm = &omap_des_pm_ops, 1114 .of_match_table = of_match_ptr(omap_des_of_match), 1115 }, 1116 }; 1117 1118 module_platform_driver(omap_des_driver); 1119 1120 MODULE_DESCRIPTION("OMAP DES hw acceleration support."); 1121 MODULE_LICENSE("GPL v2"); 1122 MODULE_AUTHOR("Joel Fernandes <joelf@ti.com>"); 1123