1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * SHA-256 routines supporting the Power 7+ Nest Accelerators driver 4 * 5 * Copyright (C) 2011-2012 International Business Machines Inc. 6 * 7 * Author: Kent Yoder <yoder1@us.ibm.com> 8 */ 9 10 #include <crypto/internal/hash.h> 11 #include <crypto/sha2.h> 12 #include <linux/errno.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/spinlock.h> 16 #include <linux/string.h> 17 #include <linux/unaligned.h> 18 19 #include "nx_csbcpb.h" 20 #include "nx.h" 21 22 struct sha256_state_be { 23 __be32 state[SHA256_DIGEST_SIZE / 4]; 24 u64 count; 25 }; 26 27 static int nx_crypto_ctx_sha256_init(struct crypto_shash *tfm) 28 { 29 struct nx_crypto_ctx *nx_ctx = crypto_shash_ctx(tfm); 30 int err; 31 32 err = nx_crypto_ctx_sha_init(tfm); 33 if (err) 34 return err; 35 36 nx_ctx_init(nx_ctx, HCOP_FC_SHA); 37 38 nx_ctx->ap = &nx_ctx->props[NX_PROPS_SHA256]; 39 40 NX_CPB_SET_DIGEST_SIZE(nx_ctx->csbcpb, NX_DS_SHA256); 41 42 return 0; 43 } 44 45 static int nx_sha256_init(struct shash_desc *desc) 46 { 47 struct sha256_state_be *sctx = shash_desc_ctx(desc); 48 49 sctx->state[0] = __cpu_to_be32(SHA256_H0); 50 sctx->state[1] = __cpu_to_be32(SHA256_H1); 51 sctx->state[2] = __cpu_to_be32(SHA256_H2); 52 sctx->state[3] = __cpu_to_be32(SHA256_H3); 53 sctx->state[4] = __cpu_to_be32(SHA256_H4); 54 sctx->state[5] = __cpu_to_be32(SHA256_H5); 55 sctx->state[6] = __cpu_to_be32(SHA256_H6); 56 sctx->state[7] = __cpu_to_be32(SHA256_H7); 57 sctx->count = 0; 58 59 return 0; 60 } 61 62 static int nx_sha256_update(struct shash_desc *desc, const u8 *data, 63 unsigned int len) 64 { 65 struct nx_crypto_ctx *nx_ctx = crypto_shash_ctx(desc->tfm); 66 struct sha256_state_be *sctx = shash_desc_ctx(desc); 67 struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb; 68 u64 to_process, leftover, total = len; 69 struct nx_sg *out_sg; 70 unsigned long irq_flags; 71 int rc = 0; 72 int data_len; 73 u32 max_sg_len; 74 75 spin_lock_irqsave(&nx_ctx->lock, irq_flags); 76 77 memcpy(csbcpb->cpb.sha256.message_digest, sctx->state, SHA256_DIGEST_SIZE); 78 NX_CPB_FDM(csbcpb) |= NX_FDM_INTERMEDIATE; 79 NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION; 80 81 max_sg_len = min_t(u64, nx_ctx->ap->sglen, 82 nx_driver.of.max_sg_len/sizeof(struct nx_sg)); 83 max_sg_len = min_t(u64, max_sg_len, 84 nx_ctx->ap->databytelen/NX_PAGE_SIZE); 85 86 data_len = SHA256_DIGEST_SIZE; 87 out_sg = nx_build_sg_list(nx_ctx->out_sg, (u8 *)sctx->state, 88 &data_len, max_sg_len); 89 nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg); 90 91 if (data_len != SHA256_DIGEST_SIZE) { 92 rc = -EINVAL; 93 goto out; 94 } 95 96 do { 97 struct nx_sg *in_sg = nx_ctx->in_sg; 98 99 to_process = total & ~(SHA256_BLOCK_SIZE - 1); 100 101 data_len = to_process; 102 in_sg = nx_build_sg_list(in_sg, (u8 *) data, 103 &data_len, max_sg_len); 104 105 nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg); 106 107 to_process = data_len; 108 leftover = total - to_process; 109 110 /* 111 * we've hit the nx chip previously and we're updating 112 * again, so copy over the partial digest. 113 */ 114 memcpy(csbcpb->cpb.sha256.input_partial_digest, 115 csbcpb->cpb.sha256.message_digest, 116 SHA256_DIGEST_SIZE); 117 118 if (!nx_ctx->op.inlen || !nx_ctx->op.outlen) { 119 rc = -EINVAL; 120 goto out; 121 } 122 123 rc = nx_hcall_sync(nx_ctx, &nx_ctx->op, 0); 124 if (rc) 125 goto out; 126 127 atomic_inc(&(nx_ctx->stats->sha256_ops)); 128 129 total -= to_process; 130 data += to_process; 131 sctx->count += to_process; 132 } while (leftover >= SHA256_BLOCK_SIZE); 133 134 rc = leftover; 135 memcpy(sctx->state, csbcpb->cpb.sha256.message_digest, SHA256_DIGEST_SIZE); 136 out: 137 spin_unlock_irqrestore(&nx_ctx->lock, irq_flags); 138 return rc; 139 } 140 141 static int nx_sha256_finup(struct shash_desc *desc, const u8 *src, 142 unsigned int nbytes, u8 *out) 143 { 144 struct nx_crypto_ctx *nx_ctx = crypto_shash_ctx(desc->tfm); 145 struct sha256_state_be *sctx = shash_desc_ctx(desc); 146 struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb; 147 struct nx_sg *in_sg, *out_sg; 148 unsigned long irq_flags; 149 u32 max_sg_len; 150 int rc = 0; 151 int len; 152 153 spin_lock_irqsave(&nx_ctx->lock, irq_flags); 154 155 max_sg_len = min_t(u64, nx_ctx->ap->sglen, 156 nx_driver.of.max_sg_len/sizeof(struct nx_sg)); 157 max_sg_len = min_t(u64, max_sg_len, 158 nx_ctx->ap->databytelen/NX_PAGE_SIZE); 159 160 /* final is represented by continuing the operation and indicating that 161 * this is not an intermediate operation 162 * copy over the partial digest */ 163 memcpy(csbcpb->cpb.sha256.input_partial_digest, sctx->state, SHA256_DIGEST_SIZE); 164 NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE; 165 NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION; 166 167 sctx->count += nbytes; 168 csbcpb->cpb.sha256.message_bit_length = (u64) (sctx->count * 8); 169 170 len = nbytes; 171 in_sg = nx_build_sg_list(nx_ctx->in_sg, (u8 *)src, &len, max_sg_len); 172 173 if (len != nbytes) { 174 rc = -EINVAL; 175 goto out; 176 } 177 178 len = SHA256_DIGEST_SIZE; 179 out_sg = nx_build_sg_list(nx_ctx->out_sg, out, &len, max_sg_len); 180 181 if (len != SHA256_DIGEST_SIZE) { 182 rc = -EINVAL; 183 goto out; 184 } 185 186 nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg); 187 nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg); 188 if (!nx_ctx->op.outlen) { 189 rc = -EINVAL; 190 goto out; 191 } 192 193 rc = nx_hcall_sync(nx_ctx, &nx_ctx->op, 0); 194 if (rc) 195 goto out; 196 197 atomic_inc(&(nx_ctx->stats->sha256_ops)); 198 199 atomic64_add(sctx->count, &(nx_ctx->stats->sha256_bytes)); 200 memcpy(out, csbcpb->cpb.sha256.message_digest, SHA256_DIGEST_SIZE); 201 out: 202 spin_unlock_irqrestore(&nx_ctx->lock, irq_flags); 203 return rc; 204 } 205 206 static int nx_sha256_export(struct shash_desc *desc, void *out) 207 { 208 struct sha256_state_be *sctx = shash_desc_ctx(desc); 209 union { 210 u8 *u8; 211 u32 *u32; 212 u64 *u64; 213 } p = { .u8 = out }; 214 int i; 215 216 for (i = 0; i < SHA256_DIGEST_SIZE / sizeof(*p.u32); i++) 217 put_unaligned(be32_to_cpu(sctx->state[i]), p.u32++); 218 219 put_unaligned(sctx->count, p.u64++); 220 return 0; 221 } 222 223 static int nx_sha256_import(struct shash_desc *desc, const void *in) 224 { 225 struct sha256_state_be *sctx = shash_desc_ctx(desc); 226 union { 227 const u8 *u8; 228 const u32 *u32; 229 const u64 *u64; 230 } p = { .u8 = in }; 231 int i; 232 233 for (i = 0; i < SHA256_DIGEST_SIZE / sizeof(*p.u32); i++) 234 sctx->state[i] = cpu_to_be32(get_unaligned(p.u32++)); 235 236 sctx->count = get_unaligned(p.u64++); 237 return 0; 238 } 239 240 struct shash_alg nx_shash_sha256_alg = { 241 .digestsize = SHA256_DIGEST_SIZE, 242 .init = nx_sha256_init, 243 .update = nx_sha256_update, 244 .finup = nx_sha256_finup, 245 .export = nx_sha256_export, 246 .import = nx_sha256_import, 247 .init_tfm = nx_crypto_ctx_sha256_init, 248 .exit_tfm = nx_crypto_ctx_shash_exit, 249 .descsize = sizeof(struct sha256_state_be), 250 .statesize = sizeof(struct sha256_state_be), 251 .base = { 252 .cra_name = "sha256", 253 .cra_driver_name = "sha256-nx", 254 .cra_priority = 300, 255 .cra_flags = CRYPTO_AHASH_ALG_BLOCK_ONLY, 256 .cra_blocksize = SHA256_BLOCK_SIZE, 257 .cra_module = THIS_MODULE, 258 .cra_ctxsize = sizeof(struct nx_crypto_ctx), 259 } 260 }; 261