1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ti-sysc.c - Texas Instruments sysc interconnect target driver 4 * 5 * TI SoCs have an interconnect target wrapper IP for many devices. The wrapper 6 * IP manages clock gating, resets, and PM capabilities for the connected devices. 7 * 8 * Copyright (C) 2017-2024 Texas Instruments Incorporated - https://www.ti.com/ 9 * 10 * Many features are based on the earlier omap_hwmod arch code with thanks to all 11 * the people who developed and debugged the code over the years: 12 * 13 * Copyright (C) 2009-2011 Nokia Corporation 14 * Copyright (C) 2011-2021 Texas Instruments Incorporated - https://www.ti.com/ 15 */ 16 17 #include <linux/io.h> 18 #include <linux/clk.h> 19 #include <linux/clkdev.h> 20 #include <linux/cpu_pm.h> 21 #include <linux/delay.h> 22 #include <linux/list.h> 23 #include <linux/module.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_domain.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/reset.h> 28 #include <linux/of_address.h> 29 #include <linux/of_platform.h> 30 #include <linux/slab.h> 31 #include <linux/sys_soc.h> 32 #include <linux/timekeeping.h> 33 #include <linux/iopoll.h> 34 35 #include <linux/platform_data/ti-sysc.h> 36 37 #include <dt-bindings/bus/ti-sysc.h> 38 39 #define DIS_ISP BIT(2) 40 #define DIS_IVA BIT(1) 41 #define DIS_SGX BIT(0) 42 43 #define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), } 44 45 #define MAX_MODULE_SOFTRESET_WAIT 10000 46 47 enum sysc_soc { 48 SOC_UNKNOWN, 49 SOC_2420, 50 SOC_2430, 51 SOC_3430, 52 SOC_AM35, 53 SOC_3630, 54 SOC_4430, 55 SOC_4460, 56 SOC_4470, 57 SOC_5430, 58 SOC_AM3, 59 SOC_AM4, 60 SOC_DRA7, 61 }; 62 63 struct sysc_address { 64 unsigned long base; 65 struct list_head node; 66 }; 67 68 struct sysc_module { 69 struct sysc *ddata; 70 struct list_head node; 71 }; 72 73 struct sysc_soc_info { 74 unsigned long general_purpose:1; 75 enum sysc_soc soc; 76 struct mutex list_lock; /* disabled and restored modules list lock */ 77 struct list_head disabled_modules; 78 struct list_head restored_modules; 79 struct notifier_block nb; 80 }; 81 82 enum sysc_clocks { 83 SYSC_FCK, 84 SYSC_ICK, 85 SYSC_OPTFCK0, 86 SYSC_OPTFCK1, 87 SYSC_OPTFCK2, 88 SYSC_OPTFCK3, 89 SYSC_OPTFCK4, 90 SYSC_OPTFCK5, 91 SYSC_OPTFCK6, 92 SYSC_OPTFCK7, 93 SYSC_MAX_CLOCKS, 94 }; 95 96 static struct sysc_soc_info *sysc_soc; 97 static const char * const reg_names[] = { "rev", "sysc", "syss", }; 98 static const char * const clock_names[SYSC_MAX_CLOCKS] = { 99 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4", 100 "opt5", "opt6", "opt7", 101 }; 102 103 #define SYSC_IDLEMODE_MASK 3 104 #define SYSC_CLOCKACTIVITY_MASK 3 105 106 /** 107 * struct sysc - TI sysc interconnect target module registers and capabilities 108 * @dev: struct device pointer 109 * @module_pa: physical address of the interconnect target module 110 * @module_size: size of the interconnect target module 111 * @module_va: virtual address of the interconnect target module 112 * @offsets: register offsets from module base 113 * @mdata: ti-sysc to hwmod translation data for a module 114 * @clocks: clocks used by the interconnect target module 115 * @clock_roles: clock role names for the found clocks 116 * @nr_clocks: number of clocks used by the interconnect target module 117 * @rsts: resets used by the interconnect target module 118 * @legacy_mode: configured for legacy mode if set 119 * @cap: interconnect target module capabilities 120 * @cfg: interconnect target module configuration 121 * @cookie: data used by legacy platform callbacks 122 * @name: name if available 123 * @revision: interconnect target module revision 124 * @sysconfig: saved sysconfig register value 125 * @reserved: target module is reserved and already in use 126 * @enabled: sysc runtime enabled status 127 * @needs_resume: runtime resume needed on resume from suspend 128 * @child_needs_resume: runtime resume needed for child on resume from suspend 129 * @idle_work: work structure used to perform delayed idle on a module 130 * @pre_reset_quirk: module specific pre-reset quirk 131 * @post_reset_quirk: module specific post-reset quirk 132 * @reset_done_quirk: module specific reset done quirk 133 * @module_enable_quirk: module specific enable quirk 134 * @module_disable_quirk: module specific disable quirk 135 * @module_unlock_quirk: module specific sysconfig unlock quirk 136 * @module_lock_quirk: module specific sysconfig lock quirk 137 */ 138 struct sysc { 139 struct device *dev; 140 u64 module_pa; 141 u32 module_size; 142 void __iomem *module_va; 143 int offsets[SYSC_MAX_REGS]; 144 struct ti_sysc_module_data *mdata; 145 struct clk **clocks; 146 const char **clock_roles; 147 int nr_clocks; 148 struct reset_control *rsts; 149 const char *legacy_mode; 150 const struct sysc_capabilities *cap; 151 struct sysc_config cfg; 152 struct ti_sysc_cookie cookie; 153 const char *name; 154 u32 revision; 155 u32 sysconfig; 156 unsigned int reserved:1; 157 unsigned int enabled:1; 158 unsigned int needs_resume:1; 159 unsigned int child_needs_resume:1; 160 struct delayed_work idle_work; 161 void (*pre_reset_quirk)(struct sysc *sysc); 162 void (*post_reset_quirk)(struct sysc *sysc); 163 void (*reset_done_quirk)(struct sysc *sysc); 164 void (*module_enable_quirk)(struct sysc *sysc); 165 void (*module_disable_quirk)(struct sysc *sysc); 166 void (*module_unlock_quirk)(struct sysc *sysc); 167 void (*module_lock_quirk)(struct sysc *sysc); 168 }; 169 170 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, 171 bool is_child); 172 static int sysc_reset(struct sysc *ddata); 173 174 static void sysc_write(struct sysc *ddata, int offset, u32 value) 175 { 176 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { 177 writew_relaxed(value & 0xffff, ddata->module_va + offset); 178 179 /* Only i2c revision has LO and HI register with stride of 4 */ 180 if (ddata->offsets[SYSC_REVISION] >= 0 && 181 offset == ddata->offsets[SYSC_REVISION]) { 182 u16 hi = value >> 16; 183 184 writew_relaxed(hi, ddata->module_va + offset + 4); 185 } 186 187 return; 188 } 189 190 writel_relaxed(value, ddata->module_va + offset); 191 } 192 193 static u32 sysc_read(struct sysc *ddata, int offset) 194 { 195 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { 196 u32 val; 197 198 val = readw_relaxed(ddata->module_va + offset); 199 200 /* Only i2c revision has LO and HI register with stride of 4 */ 201 if (ddata->offsets[SYSC_REVISION] >= 0 && 202 offset == ddata->offsets[SYSC_REVISION]) { 203 u16 tmp = readw_relaxed(ddata->module_va + offset + 4); 204 205 val |= tmp << 16; 206 } 207 208 return val; 209 } 210 211 return readl_relaxed(ddata->module_va + offset); 212 } 213 214 static bool sysc_opt_clks_needed(struct sysc *ddata) 215 { 216 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED); 217 } 218 219 static u32 sysc_read_revision(struct sysc *ddata) 220 { 221 int offset = ddata->offsets[SYSC_REVISION]; 222 223 if (offset < 0) 224 return 0; 225 226 return sysc_read(ddata, offset); 227 } 228 229 static u32 sysc_read_sysconfig(struct sysc *ddata) 230 { 231 int offset = ddata->offsets[SYSC_SYSCONFIG]; 232 233 if (offset < 0) 234 return 0; 235 236 return sysc_read(ddata, offset); 237 } 238 239 static u32 sysc_read_sysstatus(struct sysc *ddata) 240 { 241 int offset = ddata->offsets[SYSC_SYSSTATUS]; 242 243 if (offset < 0) 244 return 0; 245 246 return sysc_read(ddata, offset); 247 } 248 249 static int sysc_poll_reset_sysstatus(struct sysc *ddata) 250 { 251 int error, retries; 252 u32 syss_done, rstval; 253 254 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED) 255 syss_done = 0; 256 else 257 syss_done = ddata->cfg.syss_mask; 258 259 if (likely(!timekeeping_suspended)) { 260 error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata, 261 rstval, (rstval & ddata->cfg.syss_mask) == 262 syss_done, 100, MAX_MODULE_SOFTRESET_WAIT); 263 } else { 264 retries = MAX_MODULE_SOFTRESET_WAIT; 265 while (retries--) { 266 rstval = sysc_read_sysstatus(ddata); 267 if ((rstval & ddata->cfg.syss_mask) == syss_done) 268 return 0; 269 udelay(2); /* Account for udelay flakeyness */ 270 } 271 error = -ETIMEDOUT; 272 } 273 274 return error; 275 } 276 277 static int sysc_poll_reset_sysconfig(struct sysc *ddata) 278 { 279 int error, retries; 280 u32 sysc_mask, rstval; 281 282 sysc_mask = BIT(ddata->cap->regbits->srst_shift); 283 284 if (likely(!timekeeping_suspended)) { 285 error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata, 286 rstval, !(rstval & sysc_mask), 287 100, MAX_MODULE_SOFTRESET_WAIT); 288 } else { 289 retries = MAX_MODULE_SOFTRESET_WAIT; 290 while (retries--) { 291 rstval = sysc_read_sysconfig(ddata); 292 if (!(rstval & sysc_mask)) 293 return 0; 294 udelay(2); /* Account for udelay flakeyness */ 295 } 296 error = -ETIMEDOUT; 297 } 298 299 return error; 300 } 301 302 /* Poll on reset status */ 303 static int sysc_wait_softreset(struct sysc *ddata) 304 { 305 int syss_offset, error = 0; 306 307 if (ddata->cap->regbits->srst_shift < 0) 308 return 0; 309 310 syss_offset = ddata->offsets[SYSC_SYSSTATUS]; 311 312 if (syss_offset >= 0) 313 error = sysc_poll_reset_sysstatus(ddata); 314 else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) 315 error = sysc_poll_reset_sysconfig(ddata); 316 317 return error; 318 } 319 320 static int sysc_add_named_clock_from_child(struct sysc *ddata, 321 const char *name, 322 const char *optfck_name) 323 { 324 struct device_node *np = ddata->dev->of_node; 325 struct device_node *child; 326 struct clk_lookup *cl; 327 struct clk *clock; 328 const char *n; 329 330 if (name) 331 n = name; 332 else 333 n = optfck_name; 334 335 /* Does the clock alias already exist? */ 336 clock = of_clk_get_by_name(np, n); 337 if (!IS_ERR(clock)) { 338 clk_put(clock); 339 340 return 0; 341 } 342 343 child = of_get_next_available_child(np, NULL); 344 if (!child) 345 return -ENODEV; 346 347 clock = devm_get_clk_from_child(ddata->dev, child, name); 348 if (IS_ERR(clock)) 349 return PTR_ERR(clock); 350 351 /* 352 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID 353 * limit for clk_get(). If cl ever needs to be freed, it should be done 354 * with clkdev_drop(). 355 */ 356 cl = kzalloc(sizeof(*cl), GFP_KERNEL); 357 if (!cl) 358 return -ENOMEM; 359 360 cl->con_id = n; 361 cl->dev_id = dev_name(ddata->dev); 362 cl->clk = clock; 363 clkdev_add(cl); 364 365 clk_put(clock); 366 367 return 0; 368 } 369 370 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name) 371 { 372 const char *optfck_name; 373 int error, index; 374 375 if (ddata->nr_clocks < SYSC_OPTFCK0) 376 index = SYSC_OPTFCK0; 377 else 378 index = ddata->nr_clocks; 379 380 if (name) 381 optfck_name = name; 382 else 383 optfck_name = clock_names[index]; 384 385 error = sysc_add_named_clock_from_child(ddata, name, optfck_name); 386 if (error) 387 return error; 388 389 ddata->clock_roles[index] = optfck_name; 390 ddata->nr_clocks++; 391 392 return 0; 393 } 394 395 static int sysc_get_one_clock(struct sysc *ddata, const char *name) 396 { 397 int error, i, index = -ENODEV; 398 399 if (!strncmp(clock_names[SYSC_FCK], name, 3)) 400 index = SYSC_FCK; 401 else if (!strncmp(clock_names[SYSC_ICK], name, 3)) 402 index = SYSC_ICK; 403 404 if (index < 0) { 405 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 406 if (!ddata->clocks[i]) { 407 index = i; 408 break; 409 } 410 } 411 } 412 413 if (index < 0) { 414 dev_err(ddata->dev, "clock %s not added\n", name); 415 return index; 416 } 417 418 ddata->clocks[index] = devm_clk_get(ddata->dev, name); 419 if (IS_ERR(ddata->clocks[index])) { 420 dev_err(ddata->dev, "clock get error for %s: %li\n", 421 name, PTR_ERR(ddata->clocks[index])); 422 423 return PTR_ERR(ddata->clocks[index]); 424 } 425 426 error = clk_prepare(ddata->clocks[index]); 427 if (error) { 428 dev_err(ddata->dev, "clock prepare error for %s: %i\n", 429 name, error); 430 431 return error; 432 } 433 434 return 0; 435 } 436 437 static int sysc_get_clocks(struct sysc *ddata) 438 { 439 struct device_node *np = ddata->dev->of_node; 440 struct property *prop; 441 const char *name; 442 int nr_fck = 0, nr_ick = 0, i, error = 0; 443 444 ddata->clock_roles = devm_kcalloc(ddata->dev, 445 SYSC_MAX_CLOCKS, 446 sizeof(*ddata->clock_roles), 447 GFP_KERNEL); 448 if (!ddata->clock_roles) 449 return -ENOMEM; 450 451 of_property_for_each_string(np, "clock-names", prop, name) { 452 if (!strncmp(clock_names[SYSC_FCK], name, 3)) 453 nr_fck++; 454 if (!strncmp(clock_names[SYSC_ICK], name, 3)) 455 nr_ick++; 456 ddata->clock_roles[ddata->nr_clocks] = name; 457 ddata->nr_clocks++; 458 } 459 460 if (ddata->nr_clocks < 1) 461 return 0; 462 463 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) { 464 error = sysc_init_ext_opt_clock(ddata, NULL); 465 if (error) 466 return error; 467 } 468 469 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) { 470 dev_err(ddata->dev, "too many clocks for %pOF\n", np); 471 472 return -EINVAL; 473 } 474 475 if (nr_fck > 1 || nr_ick > 1) { 476 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np); 477 478 return -EINVAL; 479 } 480 481 /* Always add a slot for main clocks fck and ick even if unused */ 482 if (!nr_fck) 483 ddata->nr_clocks++; 484 if (!nr_ick) 485 ddata->nr_clocks++; 486 487 ddata->clocks = devm_kcalloc(ddata->dev, 488 ddata->nr_clocks, sizeof(*ddata->clocks), 489 GFP_KERNEL); 490 if (!ddata->clocks) 491 return -ENOMEM; 492 493 for (i = 0; i < SYSC_MAX_CLOCKS; i++) { 494 const char *name = ddata->clock_roles[i]; 495 496 if (!name) 497 continue; 498 499 error = sysc_get_one_clock(ddata, name); 500 if (error) 501 return error; 502 } 503 504 return 0; 505 } 506 507 static int sysc_enable_main_clocks(struct sysc *ddata) 508 { 509 struct clk *clock; 510 int i, error; 511 512 if (!ddata->clocks) 513 return 0; 514 515 for (i = 0; i < SYSC_OPTFCK0; i++) { 516 clock = ddata->clocks[i]; 517 518 /* Main clocks may not have ick */ 519 if (IS_ERR_OR_NULL(clock)) 520 continue; 521 522 error = clk_enable(clock); 523 if (error) 524 goto err_disable; 525 } 526 527 return 0; 528 529 err_disable: 530 for (i--; i >= 0; i--) { 531 clock = ddata->clocks[i]; 532 533 /* Main clocks may not have ick */ 534 if (IS_ERR_OR_NULL(clock)) 535 continue; 536 537 clk_disable(clock); 538 } 539 540 return error; 541 } 542 543 static void sysc_disable_main_clocks(struct sysc *ddata) 544 { 545 struct clk *clock; 546 int i; 547 548 if (!ddata->clocks) 549 return; 550 551 for (i = 0; i < SYSC_OPTFCK0; i++) { 552 clock = ddata->clocks[i]; 553 if (IS_ERR_OR_NULL(clock)) 554 continue; 555 556 clk_disable(clock); 557 } 558 } 559 560 static int sysc_enable_opt_clocks(struct sysc *ddata) 561 { 562 struct clk *clock; 563 int i, error; 564 565 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1) 566 return 0; 567 568 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 569 clock = ddata->clocks[i]; 570 571 /* Assume no holes for opt clocks */ 572 if (IS_ERR_OR_NULL(clock)) 573 return 0; 574 575 error = clk_enable(clock); 576 if (error) 577 goto err_disable; 578 } 579 580 return 0; 581 582 err_disable: 583 for (i--; i >= 0; i--) { 584 clock = ddata->clocks[i]; 585 if (IS_ERR_OR_NULL(clock)) 586 continue; 587 588 clk_disable(clock); 589 } 590 591 return error; 592 } 593 594 static void sysc_disable_opt_clocks(struct sysc *ddata) 595 { 596 struct clk *clock; 597 int i; 598 599 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1) 600 return; 601 602 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 603 clock = ddata->clocks[i]; 604 605 /* Assume no holes for opt clocks */ 606 if (IS_ERR_OR_NULL(clock)) 607 return; 608 609 clk_disable(clock); 610 } 611 } 612 613 static void sysc_clkdm_deny_idle(struct sysc *ddata) 614 { 615 struct ti_sysc_platform_data *pdata; 616 617 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO)) 618 return; 619 620 pdata = dev_get_platdata(ddata->dev); 621 if (pdata && pdata->clkdm_deny_idle) 622 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie); 623 } 624 625 static void sysc_clkdm_allow_idle(struct sysc *ddata) 626 { 627 struct ti_sysc_platform_data *pdata; 628 629 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO)) 630 return; 631 632 pdata = dev_get_platdata(ddata->dev); 633 if (pdata && pdata->clkdm_allow_idle) 634 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie); 635 } 636 637 /** 638 * sysc_init_resets - init rstctrl reset line if configured 639 * @ddata: device driver data 640 * 641 * See sysc_rstctrl_reset_deassert(). 642 */ 643 static int sysc_init_resets(struct sysc *ddata) 644 { 645 ddata->rsts = 646 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl"); 647 648 return PTR_ERR_OR_ZERO(ddata->rsts); 649 } 650 651 /** 652 * sysc_parse_and_check_child_range - parses module IO region from ranges 653 * @ddata: device driver data 654 * 655 * In general we only need rev, syss, and sysc registers and not the whole 656 * module range. But we do want the offsets for these registers from the 657 * module base. This allows us to check them against the legacy hwmod 658 * platform data. Let's also check the ranges are configured properly. 659 */ 660 static int sysc_parse_and_check_child_range(struct sysc *ddata) 661 { 662 struct device_node *np = ddata->dev->of_node; 663 struct of_range_parser parser; 664 struct of_range range; 665 int error; 666 667 error = of_range_parser_init(&parser, np); 668 if (error) 669 return error; 670 671 for_each_of_range(&parser, &range) { 672 ddata->module_pa = range.cpu_addr; 673 ddata->module_size = range.size; 674 break; 675 } 676 677 return 0; 678 } 679 680 static struct device_node *stdout_path; 681 682 static void sysc_init_stdout_path(struct sysc *ddata) 683 { 684 struct device_node *np = NULL; 685 const char *uart; 686 687 if (IS_ERR(stdout_path)) 688 return; 689 690 if (stdout_path) 691 return; 692 693 np = of_find_node_by_path("/chosen"); 694 if (!np) 695 goto err; 696 697 uart = of_get_property(np, "stdout-path", NULL); 698 if (!uart) 699 goto err; 700 701 np = of_find_node_by_path(uart); 702 if (!np) 703 goto err; 704 705 stdout_path = np; 706 707 return; 708 709 err: 710 stdout_path = ERR_PTR(-ENODEV); 711 } 712 713 static void sysc_check_quirk_stdout(struct sysc *ddata, 714 struct device_node *np) 715 { 716 sysc_init_stdout_path(ddata); 717 if (np != stdout_path) 718 return; 719 720 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT | 721 SYSC_QUIRK_NO_RESET_ON_INIT; 722 } 723 724 /** 725 * sysc_check_one_child - check child configuration 726 * @ddata: device driver data 727 * @np: child device node 728 * 729 * Let's avoid messy situations where we have new interconnect target 730 * node but children have "ti,hwmods". These belong to the interconnect 731 * target node and are managed by this driver. 732 */ 733 static void sysc_check_one_child(struct sysc *ddata, 734 struct device_node *np) 735 { 736 const char *name; 737 738 name = of_get_property(np, "ti,hwmods", NULL); 739 if (name && !of_device_is_compatible(np, "ti,sysc")) 740 dev_warn(ddata->dev, "really a child ti,hwmods property?"); 741 742 sysc_check_quirk_stdout(ddata, np); 743 sysc_parse_dts_quirks(ddata, np, true); 744 } 745 746 static void sysc_check_children(struct sysc *ddata) 747 { 748 struct device_node *child; 749 750 for_each_child_of_node(ddata->dev->of_node, child) 751 sysc_check_one_child(ddata, child); 752 } 753 754 /* 755 * So far only I2C uses 16-bit read access with clockactivity with revision 756 * in two registers with stride of 4. We can detect this based on the rev 757 * register size to configure things far enough to be able to properly read 758 * the revision register. 759 */ 760 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res) 761 { 762 if (resource_size(res) == 8) 763 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT; 764 } 765 766 /** 767 * sysc_parse_one - parses the interconnect target module registers 768 * @ddata: device driver data 769 * @reg: register to parse 770 */ 771 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg) 772 { 773 struct resource *res; 774 const char *name; 775 776 switch (reg) { 777 case SYSC_REVISION: 778 case SYSC_SYSCONFIG: 779 case SYSC_SYSSTATUS: 780 name = reg_names[reg]; 781 break; 782 default: 783 return -EINVAL; 784 } 785 786 res = platform_get_resource_byname(to_platform_device(ddata->dev), 787 IORESOURCE_MEM, name); 788 if (!res) { 789 ddata->offsets[reg] = -ENODEV; 790 791 return 0; 792 } 793 794 ddata->offsets[reg] = res->start - ddata->module_pa; 795 if (reg == SYSC_REVISION) 796 sysc_check_quirk_16bit(ddata, res); 797 798 return 0; 799 } 800 801 static int sysc_parse_registers(struct sysc *ddata) 802 { 803 int i, error; 804 805 for (i = 0; i < SYSC_MAX_REGS; i++) { 806 error = sysc_parse_one(ddata, i); 807 if (error) 808 return error; 809 } 810 811 return 0; 812 } 813 814 /** 815 * sysc_check_registers - check for misconfigured register overlaps 816 * @ddata: device driver data 817 */ 818 static int sysc_check_registers(struct sysc *ddata) 819 { 820 int i, j, nr_regs = 0, nr_matches = 0; 821 822 for (i = 0; i < SYSC_MAX_REGS; i++) { 823 if (ddata->offsets[i] < 0) 824 continue; 825 826 if (ddata->offsets[i] > (ddata->module_size - 4)) { 827 dev_err(ddata->dev, "register outside module range"); 828 829 return -EINVAL; 830 } 831 832 for (j = 0; j < SYSC_MAX_REGS; j++) { 833 if (ddata->offsets[j] < 0) 834 continue; 835 836 if (ddata->offsets[i] == ddata->offsets[j]) 837 nr_matches++; 838 } 839 nr_regs++; 840 } 841 842 if (nr_matches > nr_regs) { 843 dev_err(ddata->dev, "overlapping registers: (%i/%i)", 844 nr_regs, nr_matches); 845 846 return -EINVAL; 847 } 848 849 return 0; 850 } 851 852 /** 853 * sysc_ioremap - ioremap register space for the interconnect target module 854 * @ddata: device driver data 855 * 856 * Note that the interconnect target module registers can be anywhere 857 * within the interconnect target module range. For example, SGX has 858 * them at offset 0x1fc00 in the 32MB module address space. And cpsw 859 * has them at offset 0x1200 in the CPSW_WR child. Usually the 860 * interconnect target module registers are at the beginning of 861 * the module range though. 862 */ 863 static int sysc_ioremap(struct sysc *ddata) 864 { 865 int size; 866 867 if (ddata->offsets[SYSC_REVISION] < 0 && 868 ddata->offsets[SYSC_SYSCONFIG] < 0 && 869 ddata->offsets[SYSC_SYSSTATUS] < 0) { 870 size = ddata->module_size; 871 } else { 872 size = max3(ddata->offsets[SYSC_REVISION], 873 ddata->offsets[SYSC_SYSCONFIG], 874 ddata->offsets[SYSC_SYSSTATUS]); 875 876 if (size < SZ_1K) 877 size = SZ_1K; 878 879 if ((size + sizeof(u32)) > ddata->module_size) 880 size = ddata->module_size; 881 } 882 883 ddata->module_va = devm_ioremap(ddata->dev, 884 ddata->module_pa, 885 size + sizeof(u32)); 886 if (!ddata->module_va) 887 return -EIO; 888 889 return 0; 890 } 891 892 /** 893 * sysc_map_and_check_registers - ioremap and check device registers 894 * @ddata: device driver data 895 */ 896 static int sysc_map_and_check_registers(struct sysc *ddata) 897 { 898 struct device_node *np = ddata->dev->of_node; 899 int error; 900 901 error = sysc_parse_and_check_child_range(ddata); 902 if (error) 903 return error; 904 905 sysc_check_children(ddata); 906 907 if (!of_property_present(np, "reg")) 908 return 0; 909 910 error = sysc_parse_registers(ddata); 911 if (error) 912 return error; 913 914 error = sysc_ioremap(ddata); 915 if (error) 916 return error; 917 918 error = sysc_check_registers(ddata); 919 if (error) 920 return error; 921 922 return 0; 923 } 924 925 /** 926 * sysc_show_rev - read and show interconnect target module revision 927 * @bufp: buffer to print the information to 928 * @ddata: device driver data 929 */ 930 static int sysc_show_rev(char *bufp, struct sysc *ddata) 931 { 932 int len; 933 934 if (ddata->offsets[SYSC_REVISION] < 0) 935 return sprintf(bufp, ":NA"); 936 937 len = sprintf(bufp, ":%08x", ddata->revision); 938 939 return len; 940 } 941 942 static int sysc_show_reg(struct sysc *ddata, 943 char *bufp, enum sysc_registers reg) 944 { 945 if (ddata->offsets[reg] < 0) 946 return sprintf(bufp, ":NA"); 947 948 return sprintf(bufp, ":%x", ddata->offsets[reg]); 949 } 950 951 static int sysc_show_name(char *bufp, struct sysc *ddata) 952 { 953 if (!ddata->name) 954 return 0; 955 956 return sprintf(bufp, ":%s", ddata->name); 957 } 958 959 /** 960 * sysc_show_registers - show information about interconnect target module 961 * @ddata: device driver data 962 */ 963 static void sysc_show_registers(struct sysc *ddata) 964 { 965 char buf[128]; 966 char *bufp = buf; 967 int i; 968 969 for (i = 0; i < SYSC_MAX_REGS; i++) 970 bufp += sysc_show_reg(ddata, bufp, i); 971 972 bufp += sysc_show_rev(bufp, ddata); 973 bufp += sysc_show_name(bufp, ddata); 974 975 dev_dbg(ddata->dev, "%llx:%x%s\n", 976 ddata->module_pa, ddata->module_size, 977 buf); 978 } 979 980 /** 981 * sysc_write_sysconfig - handle sysconfig quirks for register write 982 * @ddata: device driver data 983 * @value: register value 984 */ 985 static void sysc_write_sysconfig(struct sysc *ddata, u32 value) 986 { 987 if (ddata->module_unlock_quirk) 988 ddata->module_unlock_quirk(ddata); 989 990 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value); 991 992 if (ddata->module_lock_quirk) 993 ddata->module_lock_quirk(ddata); 994 } 995 996 #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1) 997 #define SYSC_CLOCACT_ICK 2 998 999 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ 1000 static int sysc_enable_module(struct device *dev) 1001 { 1002 struct sysc *ddata; 1003 const struct sysc_regbits *regbits; 1004 u32 reg, idlemodes, best_mode; 1005 int error; 1006 1007 ddata = dev_get_drvdata(dev); 1008 1009 /* 1010 * Some modules like DSS reset automatically on idle. Enable optional 1011 * reset clocks and wait for OCP softreset to complete. 1012 */ 1013 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) { 1014 error = sysc_enable_opt_clocks(ddata); 1015 if (error) { 1016 dev_err(ddata->dev, 1017 "Optional clocks failed for enable: %i\n", 1018 error); 1019 return error; 1020 } 1021 } 1022 /* 1023 * Some modules like i2c and hdq1w have unusable reset status unless 1024 * the module reset quirk is enabled. Skip status check on enable. 1025 */ 1026 if (!(ddata->cfg.quirks & SYSC_MODULE_QUIRK_ENA_RESETDONE)) { 1027 error = sysc_wait_softreset(ddata); 1028 if (error) 1029 dev_warn(ddata->dev, "OCP softreset timed out\n"); 1030 } 1031 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) 1032 sysc_disable_opt_clocks(ddata); 1033 1034 /* 1035 * Some subsystem private interconnects, like DSS top level module, 1036 * need only the automatic OCP softreset handling with no sysconfig 1037 * register bits to configure. 1038 */ 1039 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) 1040 return 0; 1041 1042 regbits = ddata->cap->regbits; 1043 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1044 1045 /* 1046 * Set CLOCKACTIVITY, we only use it for ick. And we only configure it 1047 * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware 1048 * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag. 1049 */ 1050 if (regbits->clkact_shift >= 0 && 1051 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT)) 1052 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift; 1053 1054 /* Set SIDLE mode */ 1055 idlemodes = ddata->cfg.sidlemodes; 1056 if (!idlemodes || regbits->sidle_shift < 0) 1057 goto set_midle; 1058 1059 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE | 1060 SYSC_QUIRK_SWSUP_SIDLE_ACT)) { 1061 best_mode = SYSC_IDLE_NO; 1062 1063 /* Clear WAKEUP */ 1064 if (regbits->enwkup_shift >= 0 && 1065 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift)) 1066 reg &= ~BIT(regbits->enwkup_shift); 1067 } else { 1068 best_mode = fls(ddata->cfg.sidlemodes) - 1; 1069 if (best_mode > SYSC_IDLE_MASK) { 1070 dev_err(dev, "%s: invalid sidlemode\n", __func__); 1071 return -EINVAL; 1072 } 1073 1074 /* Set WAKEUP */ 1075 if (regbits->enwkup_shift >= 0 && 1076 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift)) 1077 reg |= BIT(regbits->enwkup_shift); 1078 } 1079 1080 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); 1081 reg |= best_mode << regbits->sidle_shift; 1082 sysc_write_sysconfig(ddata, reg); 1083 1084 set_midle: 1085 /* Set MIDLE mode */ 1086 idlemodes = ddata->cfg.midlemodes; 1087 if (!idlemodes || regbits->midle_shift < 0) 1088 goto set_autoidle; 1089 1090 best_mode = fls(ddata->cfg.midlemodes) - 1; 1091 if (best_mode > SYSC_IDLE_MASK) { 1092 dev_err(dev, "%s: invalid midlemode\n", __func__); 1093 error = -EINVAL; 1094 goto save_context; 1095 } 1096 1097 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY) 1098 best_mode = SYSC_IDLE_NO; 1099 1100 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); 1101 reg |= best_mode << regbits->midle_shift; 1102 sysc_write_sysconfig(ddata, reg); 1103 1104 set_autoidle: 1105 /* Autoidle bit must enabled separately if available */ 1106 if (regbits->autoidle_shift >= 0 && 1107 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) { 1108 reg |= 1 << regbits->autoidle_shift; 1109 sysc_write_sysconfig(ddata, reg); 1110 } 1111 1112 error = 0; 1113 1114 save_context: 1115 /* Save context and flush posted write */ 1116 ddata->sysconfig = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1117 1118 if (ddata->module_enable_quirk) 1119 ddata->module_enable_quirk(ddata); 1120 1121 return error; 1122 } 1123 1124 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode) 1125 { 1126 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP)) 1127 *best_mode = SYSC_IDLE_SMART_WKUP; 1128 else if (idlemodes & BIT(SYSC_IDLE_SMART)) 1129 *best_mode = SYSC_IDLE_SMART; 1130 else if (idlemodes & BIT(SYSC_IDLE_FORCE)) 1131 *best_mode = SYSC_IDLE_FORCE; 1132 else 1133 return -EINVAL; 1134 1135 return 0; 1136 } 1137 1138 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ 1139 static int sysc_disable_module(struct device *dev) 1140 { 1141 struct sysc *ddata; 1142 const struct sysc_regbits *regbits; 1143 u32 reg, idlemodes, best_mode; 1144 int ret; 1145 1146 ddata = dev_get_drvdata(dev); 1147 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) 1148 return 0; 1149 1150 if (ddata->module_disable_quirk) 1151 ddata->module_disable_quirk(ddata); 1152 1153 regbits = ddata->cap->regbits; 1154 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1155 1156 /* Set MIDLE mode */ 1157 idlemodes = ddata->cfg.midlemodes; 1158 if (!idlemodes || regbits->midle_shift < 0) 1159 goto set_sidle; 1160 1161 ret = sysc_best_idle_mode(idlemodes, &best_mode); 1162 if (ret) { 1163 dev_err(dev, "%s: invalid midlemode\n", __func__); 1164 return ret; 1165 } 1166 1167 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) || 1168 ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY)) 1169 best_mode = SYSC_IDLE_FORCE; 1170 1171 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); 1172 reg |= best_mode << regbits->midle_shift; 1173 sysc_write_sysconfig(ddata, reg); 1174 1175 set_sidle: 1176 /* Set SIDLE mode */ 1177 idlemodes = ddata->cfg.sidlemodes; 1178 if (!idlemodes || regbits->sidle_shift < 0) { 1179 ret = 0; 1180 goto save_context; 1181 } 1182 1183 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) { 1184 best_mode = SYSC_IDLE_FORCE; 1185 } else { 1186 ret = sysc_best_idle_mode(idlemodes, &best_mode); 1187 if (ret) { 1188 dev_err(dev, "%s: invalid sidlemode\n", __func__); 1189 ret = -EINVAL; 1190 goto save_context; 1191 } 1192 } 1193 1194 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE_ACT) { 1195 /* Set WAKEUP */ 1196 if (regbits->enwkup_shift >= 0 && 1197 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift)) 1198 reg |= BIT(regbits->enwkup_shift); 1199 } 1200 1201 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); 1202 reg |= best_mode << regbits->sidle_shift; 1203 if (regbits->autoidle_shift >= 0 && 1204 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) 1205 reg |= 1 << regbits->autoidle_shift; 1206 sysc_write_sysconfig(ddata, reg); 1207 1208 ret = 0; 1209 1210 save_context: 1211 /* Save context and flush posted write */ 1212 ddata->sysconfig = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1213 1214 return ret; 1215 } 1216 1217 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev, 1218 struct sysc *ddata) 1219 { 1220 struct ti_sysc_platform_data *pdata; 1221 int error; 1222 1223 pdata = dev_get_platdata(ddata->dev); 1224 if (!pdata) 1225 return 0; 1226 1227 if (!pdata->idle_module) 1228 return -ENODEV; 1229 1230 error = pdata->idle_module(dev, &ddata->cookie); 1231 if (error) 1232 dev_err(dev, "%s: could not idle: %i\n", 1233 __func__, error); 1234 1235 reset_control_assert(ddata->rsts); 1236 1237 return 0; 1238 } 1239 1240 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev, 1241 struct sysc *ddata) 1242 { 1243 struct ti_sysc_platform_data *pdata; 1244 int error; 1245 1246 pdata = dev_get_platdata(ddata->dev); 1247 if (!pdata) 1248 return 0; 1249 1250 if (!pdata->enable_module) 1251 return -ENODEV; 1252 1253 error = pdata->enable_module(dev, &ddata->cookie); 1254 if (error) 1255 dev_err(dev, "%s: could not enable: %i\n", 1256 __func__, error); 1257 1258 reset_control_deassert(ddata->rsts); 1259 1260 return 0; 1261 } 1262 1263 static int __maybe_unused sysc_runtime_suspend(struct device *dev) 1264 { 1265 struct sysc *ddata; 1266 int error = 0; 1267 1268 ddata = dev_get_drvdata(dev); 1269 1270 if (!ddata->enabled) 1271 return 0; 1272 1273 sysc_clkdm_deny_idle(ddata); 1274 1275 if (ddata->legacy_mode) { 1276 error = sysc_runtime_suspend_legacy(dev, ddata); 1277 if (error) 1278 goto err_allow_idle; 1279 } else { 1280 error = sysc_disable_module(dev); 1281 if (error) 1282 goto err_allow_idle; 1283 } 1284 1285 sysc_disable_main_clocks(ddata); 1286 1287 if (sysc_opt_clks_needed(ddata)) 1288 sysc_disable_opt_clocks(ddata); 1289 1290 ddata->enabled = false; 1291 1292 err_allow_idle: 1293 sysc_clkdm_allow_idle(ddata); 1294 1295 reset_control_assert(ddata->rsts); 1296 1297 return error; 1298 } 1299 1300 static int __maybe_unused sysc_runtime_resume(struct device *dev) 1301 { 1302 struct sysc *ddata; 1303 int error = 0; 1304 1305 ddata = dev_get_drvdata(dev); 1306 1307 if (ddata->enabled) 1308 return 0; 1309 1310 1311 sysc_clkdm_deny_idle(ddata); 1312 1313 if (sysc_opt_clks_needed(ddata)) { 1314 error = sysc_enable_opt_clocks(ddata); 1315 if (error) 1316 goto err_allow_idle; 1317 } 1318 1319 error = sysc_enable_main_clocks(ddata); 1320 if (error) 1321 goto err_opt_clocks; 1322 1323 reset_control_deassert(ddata->rsts); 1324 1325 if (ddata->legacy_mode) { 1326 error = sysc_runtime_resume_legacy(dev, ddata); 1327 if (error) 1328 goto err_main_clocks; 1329 } else { 1330 error = sysc_enable_module(dev); 1331 if (error) 1332 goto err_main_clocks; 1333 } 1334 1335 ddata->enabled = true; 1336 1337 sysc_clkdm_allow_idle(ddata); 1338 1339 return 0; 1340 1341 err_main_clocks: 1342 sysc_disable_main_clocks(ddata); 1343 err_opt_clocks: 1344 if (sysc_opt_clks_needed(ddata)) 1345 sysc_disable_opt_clocks(ddata); 1346 err_allow_idle: 1347 sysc_clkdm_allow_idle(ddata); 1348 1349 return error; 1350 } 1351 1352 /* 1353 * Checks if device context was lost. Assumes the sysconfig register value 1354 * after lost context is different from the configured value. Only works for 1355 * enabled devices. 1356 * 1357 * Eventually we may want to also add support to using the context lost 1358 * registers that some SoCs have. 1359 */ 1360 static int sysc_check_context(struct sysc *ddata) 1361 { 1362 u32 reg; 1363 1364 if (!ddata->enabled) 1365 return -ENODATA; 1366 1367 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1368 if (reg == ddata->sysconfig) 1369 return 0; 1370 1371 return -EACCES; 1372 } 1373 1374 static int sysc_reinit_module(struct sysc *ddata, bool leave_enabled) 1375 { 1376 struct device *dev = ddata->dev; 1377 int error; 1378 1379 if (ddata->enabled) { 1380 /* Nothing to do if enabled and context not lost */ 1381 error = sysc_check_context(ddata); 1382 if (!error) 1383 return 0; 1384 1385 /* Disable target module if it is enabled */ 1386 error = sysc_runtime_suspend(dev); 1387 if (error) 1388 dev_warn(dev, "reinit suspend failed: %i\n", error); 1389 } 1390 1391 /* Enable target module */ 1392 error = sysc_runtime_resume(dev); 1393 if (error) 1394 dev_warn(dev, "reinit resume failed: %i\n", error); 1395 1396 /* Some modules like am335x gpmc need reset and restore of sysconfig */ 1397 if (ddata->cfg.quirks & SYSC_QUIRK_RESET_ON_CTX_LOST) { 1398 error = sysc_reset(ddata); 1399 if (error) 1400 dev_warn(dev, "reinit reset failed: %i\n", error); 1401 1402 sysc_write_sysconfig(ddata, ddata->sysconfig); 1403 } 1404 1405 if (leave_enabled) 1406 return error; 1407 1408 /* Disable target module if no leave_enabled was set */ 1409 error = sysc_runtime_suspend(dev); 1410 if (error) 1411 dev_warn(dev, "reinit suspend failed: %i\n", error); 1412 1413 return error; 1414 } 1415 1416 static int __maybe_unused sysc_noirq_suspend(struct device *dev) 1417 { 1418 struct sysc *ddata; 1419 1420 ddata = dev_get_drvdata(dev); 1421 1422 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE) 1423 return 0; 1424 1425 if (!ddata->enabled) 1426 return 0; 1427 1428 ddata->needs_resume = 1; 1429 1430 return sysc_runtime_suspend(dev); 1431 } 1432 1433 static int __maybe_unused sysc_noirq_resume(struct device *dev) 1434 { 1435 struct sysc *ddata; 1436 int error = 0; 1437 1438 ddata = dev_get_drvdata(dev); 1439 1440 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE) 1441 return 0; 1442 1443 if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_RESUME) { 1444 error = sysc_reinit_module(ddata, ddata->needs_resume); 1445 if (error) 1446 dev_warn(dev, "noirq_resume failed: %i\n", error); 1447 } else if (ddata->needs_resume) { 1448 error = sysc_runtime_resume(dev); 1449 if (error) 1450 dev_warn(dev, "noirq_resume failed: %i\n", error); 1451 } 1452 1453 ddata->needs_resume = 0; 1454 1455 return error; 1456 } 1457 1458 static const struct dev_pm_ops sysc_pm_ops = { 1459 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume) 1460 SET_RUNTIME_PM_OPS(sysc_runtime_suspend, 1461 sysc_runtime_resume, 1462 NULL) 1463 }; 1464 1465 /* Module revision register based quirks */ 1466 struct sysc_revision_quirk { 1467 const char *name; 1468 u32 base; 1469 int rev_offset; 1470 int sysc_offset; 1471 int syss_offset; 1472 u32 revision; 1473 u32 revision_mask; 1474 u32 quirks; 1475 }; 1476 1477 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \ 1478 optrev_val, optrevmask, optquirkmask) \ 1479 { \ 1480 .name = (optname), \ 1481 .base = (optbase), \ 1482 .rev_offset = (optrev), \ 1483 .sysc_offset = (optsysc), \ 1484 .syss_offset = (optsyss), \ 1485 .revision = (optrev_val), \ 1486 .revision_mask = (optrevmask), \ 1487 .quirks = (optquirkmask), \ 1488 } 1489 1490 static const struct sysc_revision_quirk sysc_revision_quirks[] = { 1491 /* Quirks that need to be set based on the module address */ 1492 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff, 1493 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT | 1494 SYSC_QUIRK_SWSUP_SIDLE), 1495 1496 /* Quirks that need to be set based on detected module */ 1497 SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff, 1498 SYSC_MODULE_QUIRK_AESS), 1499 /* Errata i893 handling for dra7 dcan1 and 2 */ 1500 SYSC_QUIRK("dcan", 0x4ae3c000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 1501 SYSC_QUIRK_CLKDM_NOAUTO), 1502 SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 1503 SYSC_QUIRK_CLKDM_NOAUTO), 1504 SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 1505 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), 1506 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff, 1507 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), 1508 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff, 1509 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), 1510 SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 1511 SYSC_QUIRK_CLKDM_NOAUTO), 1512 SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 1513 SYSC_QUIRK_CLKDM_NOAUTO), 1514 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff, 1515 SYSC_QUIRK_OPT_CLKS_IN_RESET), 1516 SYSC_QUIRK("gpmc", 0, 0, 0x10, 0x14, 0x00000060, 0xffffffff, 1517 SYSC_QUIRK_REINIT_ON_CTX_LOST | SYSC_QUIRK_RESET_ON_CTX_LOST | 1518 SYSC_QUIRK_GPMC_DEBUG), 1519 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff, 1520 SYSC_QUIRK_OPT_CLKS_NEEDED), 1521 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, 1522 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1523 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff, 1524 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1525 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff, 1526 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1527 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff, 1528 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1529 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff, 1530 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1531 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0, 1532 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1533 SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0), 1534 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 1535 SYSC_MODULE_QUIRK_SGX), 1536 SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff, 1537 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1538 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff, 1539 SYSC_QUIRK_SWSUP_SIDLE), 1540 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0, 1541 SYSC_MODULE_QUIRK_RTC_UNLOCK), 1542 SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff, 1543 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1544 SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff, 1545 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1546 SYSC_QUIRK("sata", 0, 0xfc, 0x1100, -ENODEV, 0x5e412000, 0xffffffff, 1547 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1548 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff, 1549 SYSC_QUIRK_SWSUP_SIDLE_ACT), 1550 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff, 1551 SYSC_QUIRK_SWSUP_SIDLE_ACT), 1552 /* Uarts on omap4 and later */ 1553 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff, 1554 SYSC_QUIRK_SWSUP_SIDLE_ACT), 1555 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff, 1556 SYSC_QUIRK_SWSUP_SIDLE_ACT), 1557 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47424e03, 0xffffffff, 1558 SYSC_QUIRK_SWSUP_SIDLE_ACT), 1559 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 1560 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1561 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff, 1562 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1563 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000033, 1564 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY | 1565 SYSC_MODULE_QUIRK_OTG), 1566 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000040, 1567 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY | 1568 SYSC_MODULE_QUIRK_OTG), 1569 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050, 1570 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY | 1571 SYSC_MODULE_QUIRK_OTG), 1572 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff, 1573 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY | 1574 SYSC_QUIRK_REINIT_ON_CTX_LOST), 1575 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 1576 SYSC_MODULE_QUIRK_WDT), 1577 /* PRUSS on am3, am4 and am5 */ 1578 SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000, 1579 SYSC_MODULE_QUIRK_PRUSS), 1580 /* Watchdog on am3 and am4 */ 1581 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 1582 SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE), 1583 1584 #ifdef DEBUG 1585 SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0), 1586 SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0), 1587 SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0), 1588 SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0), 1589 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902, 1590 0xffff00f0, 0), 1591 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0), 1592 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0), 1593 SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), 1594 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), 1595 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0), 1596 SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0), 1597 SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), 1598 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), 1599 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), 1600 SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), 1601 SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0), 1602 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1603 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1604 SYSC_QUIRK("elm", 0x48080000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0), 1605 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x40441403, 0xffff0fff, 0), 1606 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x50440500, 0xffffffff, 0), 1607 SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0), 1608 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0), 1609 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0), 1610 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0), 1611 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0), 1612 SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0), 1613 SYSC_QUIRK("keypad", 0x4a31c000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0), 1614 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0), 1615 SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0), 1616 SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0), 1617 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0), 1618 SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0), 1619 SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0), 1620 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0), 1621 SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0), 1622 SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0), 1623 SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0), 1624 SYSC_QUIRK("pcie", 0x51000000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0), 1625 SYSC_QUIRK("pcie", 0x51800000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0), 1626 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0), 1627 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0), 1628 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0), 1629 SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1630 SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1631 SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0), 1632 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0), 1633 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0), 1634 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0), 1635 SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0), 1636 SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0), 1637 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0), 1638 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0), 1639 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, 0), 1640 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0), 1641 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0), 1642 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff, 0), 1643 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff, 0), 1644 SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0), 1645 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0), 1646 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0), 1647 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0), 1648 /* Some timers on omap4 and later */ 1649 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff, 0), 1650 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff, 0), 1651 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000040, 0xffffffff, 0), 1652 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000011, 0xffffffff, 0), 1653 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0), 1654 SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0), 1655 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0), 1656 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0), 1657 SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0), 1658 SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0), 1659 #endif 1660 }; 1661 1662 /* 1663 * Early quirks based on module base and register offsets only that are 1664 * needed before the module revision can be read 1665 */ 1666 static void sysc_init_early_quirks(struct sysc *ddata) 1667 { 1668 const struct sysc_revision_quirk *q; 1669 int i; 1670 1671 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { 1672 q = &sysc_revision_quirks[i]; 1673 1674 if (!q->base) 1675 continue; 1676 1677 if (q->base != ddata->module_pa) 1678 continue; 1679 1680 if (q->rev_offset != ddata->offsets[SYSC_REVISION]) 1681 continue; 1682 1683 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) 1684 continue; 1685 1686 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) 1687 continue; 1688 1689 ddata->name = q->name; 1690 ddata->cfg.quirks |= q->quirks; 1691 } 1692 } 1693 1694 /* Quirks that also consider the revision register value */ 1695 static void sysc_init_revision_quirks(struct sysc *ddata) 1696 { 1697 const struct sysc_revision_quirk *q; 1698 int i; 1699 1700 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { 1701 q = &sysc_revision_quirks[i]; 1702 1703 if (q->base && q->base != ddata->module_pa) 1704 continue; 1705 1706 if (q->rev_offset != ddata->offsets[SYSC_REVISION]) 1707 continue; 1708 1709 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) 1710 continue; 1711 1712 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) 1713 continue; 1714 1715 if (q->revision == ddata->revision || 1716 (q->revision & q->revision_mask) == 1717 (ddata->revision & q->revision_mask)) { 1718 ddata->name = q->name; 1719 ddata->cfg.quirks |= q->quirks; 1720 } 1721 } 1722 } 1723 1724 /* 1725 * DSS needs dispc outputs disabled to reset modules. Returns mask of 1726 * enabled DSS interrupts. Eventually we may be able to do this on 1727 * dispc init rather than top-level DSS init. 1728 */ 1729 static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset, 1730 bool disable) 1731 { 1732 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false; 1733 const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1); 1734 int manager_count; 1735 bool framedonetv_irq = true; 1736 u32 val, irq_mask = 0; 1737 1738 switch (sysc_soc->soc) { 1739 case SOC_2420 ... SOC_3630: 1740 manager_count = 2; 1741 framedonetv_irq = false; 1742 break; 1743 case SOC_4430 ... SOC_4470: 1744 manager_count = 3; 1745 break; 1746 case SOC_5430: 1747 case SOC_DRA7: 1748 manager_count = 4; 1749 break; 1750 case SOC_AM4: 1751 manager_count = 1; 1752 framedonetv_irq = false; 1753 break; 1754 case SOC_UNKNOWN: 1755 default: 1756 return 0; 1757 } 1758 1759 /* Remap the whole module range to be able to reset dispc outputs */ 1760 devm_iounmap(ddata->dev, ddata->module_va); 1761 ddata->module_va = devm_ioremap(ddata->dev, 1762 ddata->module_pa, 1763 ddata->module_size); 1764 if (!ddata->module_va) 1765 return -EIO; 1766 1767 /* DISP_CONTROL, shut down lcd and digit on disable if enabled */ 1768 val = sysc_read(ddata, dispc_offset + 0x40); 1769 lcd_en = val & lcd_en_mask; 1770 digit_en = val & digit_en_mask; 1771 if (lcd_en) 1772 irq_mask |= BIT(0); /* FRAMEDONE */ 1773 if (digit_en) { 1774 if (framedonetv_irq) 1775 irq_mask |= BIT(24); /* FRAMEDONETV */ 1776 else 1777 irq_mask |= BIT(2) | BIT(3); /* EVSYNC bits */ 1778 } 1779 if (disable && (lcd_en || digit_en)) 1780 sysc_write(ddata, dispc_offset + 0x40, 1781 val & ~(lcd_en_mask | digit_en_mask)); 1782 1783 if (manager_count <= 2) 1784 return irq_mask; 1785 1786 /* DISPC_CONTROL2 */ 1787 val = sysc_read(ddata, dispc_offset + 0x238); 1788 lcd2_en = val & lcd_en_mask; 1789 if (lcd2_en) 1790 irq_mask |= BIT(22); /* FRAMEDONE2 */ 1791 if (disable && lcd2_en) 1792 sysc_write(ddata, dispc_offset + 0x238, 1793 val & ~lcd_en_mask); 1794 1795 if (manager_count <= 3) 1796 return irq_mask; 1797 1798 /* DISPC_CONTROL3 */ 1799 val = sysc_read(ddata, dispc_offset + 0x848); 1800 lcd3_en = val & lcd_en_mask; 1801 if (lcd3_en) 1802 irq_mask |= BIT(30); /* FRAMEDONE3 */ 1803 if (disable && lcd3_en) 1804 sysc_write(ddata, dispc_offset + 0x848, 1805 val & ~lcd_en_mask); 1806 1807 return irq_mask; 1808 } 1809 1810 /* DSS needs child outputs disabled and SDI registers cleared for reset */ 1811 static void sysc_pre_reset_quirk_dss(struct sysc *ddata) 1812 { 1813 const int dispc_offset = 0x1000; 1814 int error; 1815 u32 irq_mask, val; 1816 1817 /* Get enabled outputs */ 1818 irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false); 1819 if (!irq_mask) 1820 return; 1821 1822 /* Clear IRQSTATUS */ 1823 sysc_write(ddata, dispc_offset + 0x18, irq_mask); 1824 1825 /* Disable outputs */ 1826 val = sysc_quirk_dispc(ddata, dispc_offset, true); 1827 1828 /* Poll IRQSTATUS */ 1829 error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18, 1830 val, val != irq_mask, 100, 50); 1831 if (error) 1832 dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n", 1833 __func__, val, irq_mask); 1834 1835 if (sysc_soc->soc == SOC_3430 || sysc_soc->soc == SOC_AM35) { 1836 /* Clear DSS_SDI_CONTROL */ 1837 sysc_write(ddata, 0x44, 0); 1838 1839 /* Clear DSS_PLL_CONTROL */ 1840 sysc_write(ddata, 0x48, 0); 1841 } 1842 1843 /* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */ 1844 sysc_write(ddata, 0x40, 0); 1845 } 1846 1847 /* 1-wire needs module's internal clocks enabled for reset */ 1848 static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata) 1849 { 1850 int offset = 0x0c; /* HDQ_CTRL_STATUS */ 1851 u16 val; 1852 1853 val = sysc_read(ddata, offset); 1854 val |= BIT(5); 1855 sysc_write(ddata, offset, val); 1856 } 1857 1858 /* AESS (Audio Engine SubSystem) needs autogating set after enable */ 1859 static void sysc_module_enable_quirk_aess(struct sysc *ddata) 1860 { 1861 int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */ 1862 1863 sysc_write(ddata, offset, 1); 1864 } 1865 1866 /* I2C needs to be disabled for reset */ 1867 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable) 1868 { 1869 int offset; 1870 u16 val; 1871 1872 /* I2C_CON, omap2/3 is different from omap4 and later */ 1873 if ((ddata->revision & 0xffffff00) == 0x001f0000) 1874 offset = 0x24; 1875 else 1876 offset = 0xa4; 1877 1878 /* I2C_EN */ 1879 val = sysc_read(ddata, offset); 1880 if (enable) 1881 val |= BIT(15); 1882 else 1883 val &= ~BIT(15); 1884 sysc_write(ddata, offset, val); 1885 } 1886 1887 static void sysc_pre_reset_quirk_i2c(struct sysc *ddata) 1888 { 1889 sysc_clk_quirk_i2c(ddata, false); 1890 } 1891 1892 static void sysc_post_reset_quirk_i2c(struct sysc *ddata) 1893 { 1894 sysc_clk_quirk_i2c(ddata, true); 1895 } 1896 1897 /* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */ 1898 static void sysc_quirk_rtc(struct sysc *ddata, bool lock) 1899 { 1900 u32 val, kick0_val = 0, kick1_val = 0; 1901 unsigned long flags; 1902 int error; 1903 1904 if (!lock) { 1905 kick0_val = 0x83e70b13; 1906 kick1_val = 0x95a4f1e0; 1907 } 1908 1909 local_irq_save(flags); 1910 /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */ 1911 error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val, 1912 !(val & BIT(0)), 100, 50); 1913 if (error) 1914 dev_warn(ddata->dev, "rtc busy timeout\n"); 1915 /* Now we have ~15 microseconds to read/write various registers */ 1916 sysc_write(ddata, 0x6c, kick0_val); 1917 sysc_write(ddata, 0x70, kick1_val); 1918 local_irq_restore(flags); 1919 } 1920 1921 static void sysc_module_unlock_quirk_rtc(struct sysc *ddata) 1922 { 1923 sysc_quirk_rtc(ddata, false); 1924 } 1925 1926 static void sysc_module_lock_quirk_rtc(struct sysc *ddata) 1927 { 1928 sysc_quirk_rtc(ddata, true); 1929 } 1930 1931 /* OTG omap2430 glue layer up to omap4 needs OTG_FORCESTDBY configured */ 1932 static void sysc_module_enable_quirk_otg(struct sysc *ddata) 1933 { 1934 int offset = 0x414; /* OTG_FORCESTDBY */ 1935 1936 sysc_write(ddata, offset, 0); 1937 } 1938 1939 static void sysc_module_disable_quirk_otg(struct sysc *ddata) 1940 { 1941 int offset = 0x414; /* OTG_FORCESTDBY */ 1942 u32 val = BIT(0); /* ENABLEFORCE */ 1943 1944 sysc_write(ddata, offset, val); 1945 } 1946 1947 /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */ 1948 static void sysc_module_enable_quirk_sgx(struct sysc *ddata) 1949 { 1950 int offset = 0xff08; /* OCP_DEBUG_CONFIG */ 1951 u32 val = BIT(31); /* THALIA_INT_BYPASS */ 1952 1953 sysc_write(ddata, offset, val); 1954 } 1955 1956 /* Watchdog timer needs a disable sequence after reset */ 1957 static void sysc_reset_done_quirk_wdt(struct sysc *ddata) 1958 { 1959 int wps, spr, error; 1960 u32 val; 1961 1962 wps = 0x34; 1963 spr = 0x48; 1964 1965 sysc_write(ddata, spr, 0xaaaa); 1966 error = readl_poll_timeout(ddata->module_va + wps, val, 1967 !(val & 0x10), 100, 1968 MAX_MODULE_SOFTRESET_WAIT); 1969 if (error) 1970 dev_warn(ddata->dev, "wdt disable step1 failed\n"); 1971 1972 sysc_write(ddata, spr, 0x5555); 1973 error = readl_poll_timeout(ddata->module_va + wps, val, 1974 !(val & 0x10), 100, 1975 MAX_MODULE_SOFTRESET_WAIT); 1976 if (error) 1977 dev_warn(ddata->dev, "wdt disable step2 failed\n"); 1978 } 1979 1980 /* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */ 1981 static void sysc_module_disable_quirk_pruss(struct sysc *ddata) 1982 { 1983 u32 reg; 1984 1985 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1986 reg |= SYSC_PRUSS_STANDBY_INIT; 1987 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); 1988 } 1989 1990 static void sysc_module_enable_quirk_pruss(struct sysc *ddata) 1991 { 1992 u32 reg; 1993 1994 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1995 1996 /* 1997 * Clearing the SYSC_PRUSS_STANDBY_INIT bit - Updates OCP master 1998 * port configuration to enable memory access outside of the 1999 * PRU-ICSS subsystem. 2000 */ 2001 reg &= (~SYSC_PRUSS_STANDBY_INIT); 2002 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); 2003 } 2004 2005 static void sysc_init_module_quirks(struct sysc *ddata) 2006 { 2007 if (ddata->legacy_mode || !ddata->name) 2008 return; 2009 2010 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) { 2011 ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w; 2012 2013 return; 2014 } 2015 2016 #ifdef CONFIG_OMAP_GPMC_DEBUG 2017 if (ddata->cfg.quirks & SYSC_QUIRK_GPMC_DEBUG) { 2018 ddata->cfg.quirks |= SYSC_QUIRK_NO_RESET_ON_INIT; 2019 2020 return; 2021 } 2022 #endif 2023 2024 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) { 2025 ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c; 2026 ddata->post_reset_quirk = sysc_post_reset_quirk_i2c; 2027 2028 return; 2029 } 2030 2031 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS) 2032 ddata->module_enable_quirk = sysc_module_enable_quirk_aess; 2033 2034 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET) 2035 ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss; 2036 2037 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) { 2038 ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc; 2039 ddata->module_lock_quirk = sysc_module_lock_quirk_rtc; 2040 2041 return; 2042 } 2043 2044 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_OTG) { 2045 ddata->module_enable_quirk = sysc_module_enable_quirk_otg; 2046 ddata->module_disable_quirk = sysc_module_disable_quirk_otg; 2047 } 2048 2049 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX) 2050 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx; 2051 2052 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) { 2053 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt; 2054 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt; 2055 } 2056 2057 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS) { 2058 ddata->module_enable_quirk = sysc_module_enable_quirk_pruss; 2059 ddata->module_disable_quirk = sysc_module_disable_quirk_pruss; 2060 } 2061 } 2062 2063 static int sysc_clockdomain_init(struct sysc *ddata) 2064 { 2065 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 2066 struct clk *fck = NULL, *ick = NULL; 2067 int error; 2068 2069 if (!pdata || !pdata->init_clockdomain) 2070 return 0; 2071 2072 switch (ddata->nr_clocks) { 2073 case 2: 2074 ick = ddata->clocks[SYSC_ICK]; 2075 fallthrough; 2076 case 1: 2077 fck = ddata->clocks[SYSC_FCK]; 2078 break; 2079 case 0: 2080 return 0; 2081 } 2082 2083 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie); 2084 if (!error || error == -ENODEV) 2085 return 0; 2086 2087 return error; 2088 } 2089 2090 /* 2091 * Note that pdata->init_module() typically does a reset first. After 2092 * pdata->init_module() is done, PM runtime can be used for the interconnect 2093 * target module. 2094 */ 2095 static int sysc_legacy_init(struct sysc *ddata) 2096 { 2097 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 2098 int error; 2099 2100 if (!pdata || !pdata->init_module) 2101 return 0; 2102 2103 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie); 2104 if (error == -EEXIST) 2105 error = 0; 2106 2107 return error; 2108 } 2109 2110 /* 2111 * Note that the caller must ensure the interconnect target module is enabled 2112 * before calling reset. Otherwise reset will not complete. 2113 */ 2114 static int sysc_reset(struct sysc *ddata) 2115 { 2116 int sysc_offset, sysc_val, error; 2117 u32 sysc_mask; 2118 2119 sysc_offset = ddata->offsets[SYSC_SYSCONFIG]; 2120 2121 if (ddata->legacy_mode || 2122 ddata->cap->regbits->srst_shift < 0) 2123 return 0; 2124 2125 sysc_mask = BIT(ddata->cap->regbits->srst_shift); 2126 2127 if (ddata->pre_reset_quirk) 2128 ddata->pre_reset_quirk(ddata); 2129 2130 if (sysc_offset >= 0) { 2131 sysc_val = sysc_read_sysconfig(ddata); 2132 sysc_val |= sysc_mask; 2133 sysc_write(ddata, sysc_offset, sysc_val); 2134 2135 /* 2136 * Some devices need a delay before reading registers 2137 * after reset. Presumably a srst_udelay is not needed 2138 * for devices that use a rstctrl register reset. 2139 */ 2140 if (ddata->cfg.srst_udelay) 2141 fsleep(ddata->cfg.srst_udelay); 2142 2143 /* 2144 * Flush posted write. For devices needing srst_udelay 2145 * this should trigger an interconnect error if the 2146 * srst_udelay value is needed but not configured. 2147 */ 2148 sysc_val = sysc_read_sysconfig(ddata); 2149 } 2150 2151 if (ddata->post_reset_quirk) 2152 ddata->post_reset_quirk(ddata); 2153 2154 error = sysc_wait_softreset(ddata); 2155 if (error) 2156 dev_warn(ddata->dev, "OCP softreset timed out\n"); 2157 2158 if (ddata->reset_done_quirk) 2159 ddata->reset_done_quirk(ddata); 2160 2161 return error; 2162 } 2163 2164 /* 2165 * At this point the module is configured enough to read the revision but 2166 * module may not be completely configured yet to use PM runtime. Enable 2167 * all clocks directly during init to configure the quirks needed for PM 2168 * runtime based on the revision register. 2169 */ 2170 static int sysc_init_module(struct sysc *ddata) 2171 { 2172 bool rstctrl_deasserted = false; 2173 int error = 0; 2174 2175 error = sysc_clockdomain_init(ddata); 2176 if (error) 2177 return error; 2178 2179 sysc_clkdm_deny_idle(ddata); 2180 2181 /* 2182 * Always enable clocks. The bootloader may or may not have enabled 2183 * the related clocks. 2184 */ 2185 error = sysc_enable_opt_clocks(ddata); 2186 if (error) 2187 return error; 2188 2189 error = sysc_enable_main_clocks(ddata); 2190 if (error) 2191 goto err_opt_clocks; 2192 2193 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) { 2194 error = reset_control_deassert(ddata->rsts); 2195 if (error) 2196 goto err_main_clocks; 2197 rstctrl_deasserted = true; 2198 } 2199 2200 ddata->revision = sysc_read_revision(ddata); 2201 sysc_init_revision_quirks(ddata); 2202 sysc_init_module_quirks(ddata); 2203 2204 if (ddata->legacy_mode) { 2205 error = sysc_legacy_init(ddata); 2206 if (error) 2207 goto err_main_clocks; 2208 } 2209 2210 if (!ddata->legacy_mode) { 2211 error = sysc_enable_module(ddata->dev); 2212 if (error) 2213 goto err_main_clocks; 2214 } 2215 2216 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) { 2217 error = sysc_reset(ddata); 2218 if (error) 2219 dev_err(ddata->dev, "Reset failed with %d\n", error); 2220 2221 if (error && !ddata->legacy_mode) 2222 sysc_disable_module(ddata->dev); 2223 } 2224 2225 err_main_clocks: 2226 if (error) 2227 sysc_disable_main_clocks(ddata); 2228 err_opt_clocks: 2229 /* No re-enable of clockdomain autoidle to prevent module autoidle */ 2230 if (error) { 2231 sysc_disable_opt_clocks(ddata); 2232 sysc_clkdm_allow_idle(ddata); 2233 } 2234 2235 if (error && rstctrl_deasserted && 2236 !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) 2237 reset_control_assert(ddata->rsts); 2238 2239 return error; 2240 } 2241 2242 static int sysc_init_sysc_mask(struct sysc *ddata) 2243 { 2244 struct device_node *np = ddata->dev->of_node; 2245 int error; 2246 u32 val; 2247 2248 error = of_property_read_u32(np, "ti,sysc-mask", &val); 2249 if (error) 2250 return 0; 2251 2252 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask; 2253 2254 return 0; 2255 } 2256 2257 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes, 2258 const char *name) 2259 { 2260 struct device_node *np = ddata->dev->of_node; 2261 u32 val; 2262 2263 of_property_for_each_u32(np, name, val) { 2264 if (val >= SYSC_NR_IDLEMODES) { 2265 dev_err(ddata->dev, "invalid idlemode: %i\n", val); 2266 return -EINVAL; 2267 } 2268 *idlemodes |= (1 << val); 2269 } 2270 2271 return 0; 2272 } 2273 2274 static int sysc_init_idlemodes(struct sysc *ddata) 2275 { 2276 int error; 2277 2278 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes, 2279 "ti,sysc-midle"); 2280 if (error) 2281 return error; 2282 2283 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes, 2284 "ti,sysc-sidle"); 2285 if (error) 2286 return error; 2287 2288 return 0; 2289 } 2290 2291 /* 2292 * Only some devices on omap4 and later have SYSCONFIG reset done 2293 * bit. We can detect this if there is no SYSSTATUS at all, or the 2294 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers 2295 * have multiple bits for the child devices like OHCI and EHCI. 2296 * Depends on SYSC being parsed first. 2297 */ 2298 static int sysc_init_syss_mask(struct sysc *ddata) 2299 { 2300 struct device_node *np = ddata->dev->of_node; 2301 int error; 2302 u32 val; 2303 2304 error = of_property_read_u32(np, "ti,syss-mask", &val); 2305 if (error) { 2306 if ((ddata->cap->type == TI_SYSC_OMAP4 || 2307 ddata->cap->type == TI_SYSC_OMAP4_TIMER) && 2308 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) 2309 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; 2310 2311 return 0; 2312 } 2313 2314 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) 2315 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; 2316 2317 ddata->cfg.syss_mask = val; 2318 2319 return 0; 2320 } 2321 2322 /* 2323 * Many child device drivers need to have fck and opt clocks available 2324 * to get the clock rate for device internal configuration etc. 2325 */ 2326 static int sysc_child_add_named_clock(struct sysc *ddata, 2327 struct device *child, 2328 const char *name) 2329 { 2330 struct clk *clk; 2331 struct clk_lookup *l; 2332 int error = 0; 2333 2334 if (!name) 2335 return 0; 2336 2337 clk = clk_get(child, name); 2338 if (!IS_ERR(clk)) { 2339 error = -EEXIST; 2340 goto put_clk; 2341 } 2342 2343 clk = clk_get(ddata->dev, name); 2344 if (IS_ERR(clk)) 2345 return -ENODEV; 2346 2347 l = clkdev_create(clk, name, dev_name(child)); 2348 if (!l) 2349 error = -ENOMEM; 2350 put_clk: 2351 clk_put(clk); 2352 2353 return error; 2354 } 2355 2356 static int sysc_child_add_clocks(struct sysc *ddata, 2357 struct device *child) 2358 { 2359 int i, error; 2360 2361 for (i = 0; i < ddata->nr_clocks; i++) { 2362 error = sysc_child_add_named_clock(ddata, 2363 child, 2364 ddata->clock_roles[i]); 2365 if (error && error != -EEXIST) { 2366 dev_err(ddata->dev, "could not add child clock %s: %i\n", 2367 ddata->clock_roles[i], error); 2368 2369 return error; 2370 } 2371 } 2372 2373 return 0; 2374 } 2375 2376 static const struct device_type sysc_device_type = { 2377 }; 2378 2379 static struct sysc *sysc_child_to_parent(struct device *dev) 2380 { 2381 struct device *parent = dev->parent; 2382 2383 if (!parent || parent->type != &sysc_device_type) 2384 return NULL; 2385 2386 return dev_get_drvdata(parent); 2387 } 2388 2389 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev) 2390 { 2391 struct sysc *ddata; 2392 int error; 2393 2394 ddata = sysc_child_to_parent(dev); 2395 2396 error = pm_generic_runtime_suspend(dev); 2397 if (error) 2398 return error; 2399 2400 if (!ddata->enabled) 2401 return 0; 2402 2403 return sysc_runtime_suspend(ddata->dev); 2404 } 2405 2406 static int __maybe_unused sysc_child_runtime_resume(struct device *dev) 2407 { 2408 struct sysc *ddata; 2409 int error; 2410 2411 ddata = sysc_child_to_parent(dev); 2412 2413 if (!ddata->enabled) { 2414 error = sysc_runtime_resume(ddata->dev); 2415 if (error < 0) 2416 dev_err(ddata->dev, 2417 "%s error: %i\n", __func__, error); 2418 } 2419 2420 return pm_generic_runtime_resume(dev); 2421 } 2422 2423 /* Caller needs to take list_lock if ever used outside of cpu_pm */ 2424 static void sysc_reinit_modules(struct sysc_soc_info *soc) 2425 { 2426 struct sysc_module *module; 2427 struct sysc *ddata; 2428 2429 list_for_each_entry(module, &sysc_soc->restored_modules, node) { 2430 ddata = module->ddata; 2431 sysc_reinit_module(ddata, ddata->enabled); 2432 } 2433 } 2434 2435 /** 2436 * sysc_context_notifier - optionally reset and restore module after idle 2437 * @nb: notifier block 2438 * @cmd: unused 2439 * @v: unused 2440 * 2441 * Some interconnect target modules need to be restored, or reset and restored 2442 * on CPU_PM CPU_PM_CLUSTER_EXIT notifier. This is needed at least for am335x 2443 * OTG and GPMC target modules even if the modules are unused. 2444 */ 2445 static int sysc_context_notifier(struct notifier_block *nb, unsigned long cmd, 2446 void *v) 2447 { 2448 struct sysc_soc_info *soc; 2449 2450 soc = container_of(nb, struct sysc_soc_info, nb); 2451 2452 switch (cmd) { 2453 case CPU_CLUSTER_PM_ENTER: 2454 break; 2455 case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */ 2456 break; 2457 case CPU_CLUSTER_PM_EXIT: 2458 sysc_reinit_modules(soc); 2459 break; 2460 } 2461 2462 return NOTIFY_OK; 2463 } 2464 2465 /** 2466 * sysc_add_restored - optionally add reset and restore quirk hanlling 2467 * @ddata: device data 2468 */ 2469 static void sysc_add_restored(struct sysc *ddata) 2470 { 2471 struct sysc_module *restored_module; 2472 2473 restored_module = kzalloc(sizeof(*restored_module), GFP_KERNEL); 2474 if (!restored_module) 2475 return; 2476 2477 restored_module->ddata = ddata; 2478 2479 mutex_lock(&sysc_soc->list_lock); 2480 2481 list_add(&restored_module->node, &sysc_soc->restored_modules); 2482 2483 if (sysc_soc->nb.notifier_call) 2484 goto out_unlock; 2485 2486 sysc_soc->nb.notifier_call = sysc_context_notifier; 2487 cpu_pm_register_notifier(&sysc_soc->nb); 2488 2489 out_unlock: 2490 mutex_unlock(&sysc_soc->list_lock); 2491 } 2492 2493 static int sysc_notifier_call(struct notifier_block *nb, 2494 unsigned long event, void *device) 2495 { 2496 struct device *dev = device; 2497 struct sysc *ddata; 2498 int error; 2499 2500 ddata = sysc_child_to_parent(dev); 2501 if (!ddata) 2502 return NOTIFY_DONE; 2503 2504 switch (event) { 2505 case BUS_NOTIFY_ADD_DEVICE: 2506 error = sysc_child_add_clocks(ddata, dev); 2507 if (error) 2508 return error; 2509 break; 2510 default: 2511 break; 2512 } 2513 2514 return NOTIFY_DONE; 2515 } 2516 2517 static struct notifier_block sysc_nb = { 2518 .notifier_call = sysc_notifier_call, 2519 }; 2520 2521 /* Device tree configured quirks */ 2522 struct sysc_dts_quirk { 2523 const char *name; 2524 u32 mask; 2525 }; 2526 2527 static const struct sysc_dts_quirk sysc_dts_quirks[] = { 2528 { .name = "ti,no-idle-on-init", 2529 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, }, 2530 { .name = "ti,no-reset-on-init", 2531 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, }, 2532 { .name = "ti,no-idle", 2533 .mask = SYSC_QUIRK_NO_IDLE, }, 2534 }; 2535 2536 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, 2537 bool is_child) 2538 { 2539 int i; 2540 2541 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) { 2542 const char *name = sysc_dts_quirks[i].name; 2543 2544 if (!of_property_present(np, name)) 2545 continue; 2546 2547 ddata->cfg.quirks |= sysc_dts_quirks[i].mask; 2548 if (is_child) { 2549 dev_warn(ddata->dev, 2550 "dts flag should be at module level for %s\n", 2551 name); 2552 } 2553 } 2554 } 2555 2556 static int sysc_init_dts_quirks(struct sysc *ddata) 2557 { 2558 struct device_node *np = ddata->dev->of_node; 2559 int error; 2560 u32 val; 2561 2562 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL); 2563 2564 sysc_parse_dts_quirks(ddata, np, false); 2565 error = of_property_read_u32(np, "ti,sysc-delay-us", &val); 2566 if (!error) { 2567 if (val > 255) { 2568 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n", 2569 val); 2570 } 2571 2572 ddata->cfg.srst_udelay = (u8)val; 2573 } 2574 2575 return 0; 2576 } 2577 2578 static void sysc_unprepare(struct sysc *ddata) 2579 { 2580 int i; 2581 2582 if (!ddata->clocks) 2583 return; 2584 2585 for (i = 0; i < SYSC_MAX_CLOCKS; i++) { 2586 if (!IS_ERR_OR_NULL(ddata->clocks[i])) 2587 clk_unprepare(ddata->clocks[i]); 2588 } 2589 } 2590 2591 /* 2592 * Common sysc register bits found on omap2, also known as type1 2593 */ 2594 static const struct sysc_regbits sysc_regbits_omap2 = { 2595 .dmadisable_shift = -ENODEV, 2596 .midle_shift = 12, 2597 .sidle_shift = 3, 2598 .clkact_shift = 8, 2599 .emufree_shift = 5, 2600 .enwkup_shift = 2, 2601 .srst_shift = 1, 2602 .autoidle_shift = 0, 2603 }; 2604 2605 static const struct sysc_capabilities sysc_omap2 = { 2606 .type = TI_SYSC_OMAP2, 2607 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | 2608 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | 2609 SYSC_OMAP2_AUTOIDLE, 2610 .regbits = &sysc_regbits_omap2, 2611 }; 2612 2613 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */ 2614 static const struct sysc_capabilities sysc_omap2_timer = { 2615 .type = TI_SYSC_OMAP2_TIMER, 2616 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | 2617 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | 2618 SYSC_OMAP2_AUTOIDLE, 2619 .regbits = &sysc_regbits_omap2, 2620 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT, 2621 }; 2622 2623 /* 2624 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2 2625 * with different sidle position 2626 */ 2627 static const struct sysc_regbits sysc_regbits_omap3_sham = { 2628 .dmadisable_shift = -ENODEV, 2629 .midle_shift = -ENODEV, 2630 .sidle_shift = 4, 2631 .clkact_shift = -ENODEV, 2632 .enwkup_shift = -ENODEV, 2633 .srst_shift = 1, 2634 .autoidle_shift = 0, 2635 .emufree_shift = -ENODEV, 2636 }; 2637 2638 static const struct sysc_capabilities sysc_omap3_sham = { 2639 .type = TI_SYSC_OMAP3_SHAM, 2640 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, 2641 .regbits = &sysc_regbits_omap3_sham, 2642 }; 2643 2644 /* 2645 * AES register bits found on omap3 and later, a variant of 2646 * sysc_regbits_omap2 with different sidle position 2647 */ 2648 static const struct sysc_regbits sysc_regbits_omap3_aes = { 2649 .dmadisable_shift = -ENODEV, 2650 .midle_shift = -ENODEV, 2651 .sidle_shift = 6, 2652 .clkact_shift = -ENODEV, 2653 .enwkup_shift = -ENODEV, 2654 .srst_shift = 1, 2655 .autoidle_shift = 0, 2656 .emufree_shift = -ENODEV, 2657 }; 2658 2659 static const struct sysc_capabilities sysc_omap3_aes = { 2660 .type = TI_SYSC_OMAP3_AES, 2661 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, 2662 .regbits = &sysc_regbits_omap3_aes, 2663 }; 2664 2665 /* 2666 * Common sysc register bits found on omap4, also known as type2 2667 */ 2668 static const struct sysc_regbits sysc_regbits_omap4 = { 2669 .dmadisable_shift = 16, 2670 .midle_shift = 4, 2671 .sidle_shift = 2, 2672 .clkact_shift = -ENODEV, 2673 .enwkup_shift = -ENODEV, 2674 .emufree_shift = 1, 2675 .srst_shift = 0, 2676 .autoidle_shift = -ENODEV, 2677 }; 2678 2679 static const struct sysc_capabilities sysc_omap4 = { 2680 .type = TI_SYSC_OMAP4, 2681 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | 2682 SYSC_OMAP4_SOFTRESET, 2683 .regbits = &sysc_regbits_omap4, 2684 }; 2685 2686 static const struct sysc_capabilities sysc_omap4_timer = { 2687 .type = TI_SYSC_OMAP4_TIMER, 2688 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | 2689 SYSC_OMAP4_SOFTRESET, 2690 .regbits = &sysc_regbits_omap4, 2691 }; 2692 2693 /* 2694 * Common sysc register bits found on omap4, also known as type3 2695 */ 2696 static const struct sysc_regbits sysc_regbits_omap4_simple = { 2697 .dmadisable_shift = -ENODEV, 2698 .midle_shift = 2, 2699 .sidle_shift = 0, 2700 .clkact_shift = -ENODEV, 2701 .enwkup_shift = -ENODEV, 2702 .srst_shift = -ENODEV, 2703 .emufree_shift = -ENODEV, 2704 .autoidle_shift = -ENODEV, 2705 }; 2706 2707 static const struct sysc_capabilities sysc_omap4_simple = { 2708 .type = TI_SYSC_OMAP4_SIMPLE, 2709 .regbits = &sysc_regbits_omap4_simple, 2710 }; 2711 2712 /* 2713 * SmartReflex sysc found on omap34xx 2714 */ 2715 static const struct sysc_regbits sysc_regbits_omap34xx_sr = { 2716 .dmadisable_shift = -ENODEV, 2717 .midle_shift = -ENODEV, 2718 .sidle_shift = -ENODEV, 2719 .clkact_shift = 20, 2720 .enwkup_shift = -ENODEV, 2721 .srst_shift = -ENODEV, 2722 .emufree_shift = -ENODEV, 2723 .autoidle_shift = -ENODEV, 2724 }; 2725 2726 static const struct sysc_capabilities sysc_34xx_sr = { 2727 .type = TI_SYSC_OMAP34XX_SR, 2728 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY, 2729 .regbits = &sysc_regbits_omap34xx_sr, 2730 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED, 2731 }; 2732 2733 /* 2734 * SmartReflex sysc found on omap36xx and later 2735 */ 2736 static const struct sysc_regbits sysc_regbits_omap36xx_sr = { 2737 .dmadisable_shift = -ENODEV, 2738 .midle_shift = -ENODEV, 2739 .sidle_shift = 24, 2740 .clkact_shift = -ENODEV, 2741 .enwkup_shift = 26, 2742 .srst_shift = -ENODEV, 2743 .emufree_shift = -ENODEV, 2744 .autoidle_shift = -ENODEV, 2745 }; 2746 2747 static const struct sysc_capabilities sysc_36xx_sr = { 2748 .type = TI_SYSC_OMAP36XX_SR, 2749 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP, 2750 .regbits = &sysc_regbits_omap36xx_sr, 2751 .mod_quirks = SYSC_QUIRK_UNCACHED, 2752 }; 2753 2754 static const struct sysc_capabilities sysc_omap4_sr = { 2755 .type = TI_SYSC_OMAP4_SR, 2756 .regbits = &sysc_regbits_omap36xx_sr, 2757 }; 2758 2759 /* 2760 * McASP register bits found on omap4 and later 2761 */ 2762 static const struct sysc_regbits sysc_regbits_omap4_mcasp = { 2763 .dmadisable_shift = -ENODEV, 2764 .midle_shift = -ENODEV, 2765 .sidle_shift = 0, 2766 .clkact_shift = -ENODEV, 2767 .enwkup_shift = -ENODEV, 2768 .srst_shift = -ENODEV, 2769 .emufree_shift = -ENODEV, 2770 .autoidle_shift = -ENODEV, 2771 }; 2772 2773 static const struct sysc_capabilities sysc_omap4_mcasp = { 2774 .type = TI_SYSC_OMAP4_MCASP, 2775 .regbits = &sysc_regbits_omap4_mcasp, 2776 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, 2777 }; 2778 2779 /* 2780 * McASP found on dra7 and later 2781 */ 2782 static const struct sysc_capabilities sysc_dra7_mcasp = { 2783 .type = TI_SYSC_OMAP4_SIMPLE, 2784 .regbits = &sysc_regbits_omap4_simple, 2785 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, 2786 }; 2787 2788 /* 2789 * FS USB host found on omap4 and later 2790 */ 2791 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = { 2792 .dmadisable_shift = -ENODEV, 2793 .midle_shift = -ENODEV, 2794 .sidle_shift = 24, 2795 .clkact_shift = -ENODEV, 2796 .enwkup_shift = 26, 2797 .srst_shift = -ENODEV, 2798 .emufree_shift = -ENODEV, 2799 .autoidle_shift = -ENODEV, 2800 }; 2801 2802 static const struct sysc_capabilities sysc_omap4_usb_host_fs = { 2803 .type = TI_SYSC_OMAP4_USB_HOST_FS, 2804 .sysc_mask = SYSC_OMAP2_ENAWAKEUP, 2805 .regbits = &sysc_regbits_omap4_usb_host_fs, 2806 }; 2807 2808 static const struct sysc_regbits sysc_regbits_dra7_mcan = { 2809 .dmadisable_shift = -ENODEV, 2810 .midle_shift = -ENODEV, 2811 .sidle_shift = -ENODEV, 2812 .clkact_shift = -ENODEV, 2813 .enwkup_shift = 4, 2814 .srst_shift = 0, 2815 .emufree_shift = -ENODEV, 2816 .autoidle_shift = -ENODEV, 2817 }; 2818 2819 static const struct sysc_capabilities sysc_dra7_mcan = { 2820 .type = TI_SYSC_DRA7_MCAN, 2821 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET, 2822 .regbits = &sysc_regbits_dra7_mcan, 2823 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED, 2824 }; 2825 2826 /* 2827 * PRUSS found on some AM33xx, AM437x and AM57xx SoCs 2828 */ 2829 static const struct sysc_capabilities sysc_pruss = { 2830 .type = TI_SYSC_PRUSS, 2831 .sysc_mask = SYSC_PRUSS_STANDBY_INIT | SYSC_PRUSS_SUB_MWAIT, 2832 .regbits = &sysc_regbits_omap4_simple, 2833 .mod_quirks = SYSC_MODULE_QUIRK_PRUSS, 2834 }; 2835 2836 static int sysc_init_pdata(struct sysc *ddata) 2837 { 2838 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 2839 struct ti_sysc_module_data *mdata; 2840 2841 if (!pdata) 2842 return 0; 2843 2844 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL); 2845 if (!mdata) 2846 return -ENOMEM; 2847 2848 if (ddata->legacy_mode) { 2849 mdata->name = ddata->legacy_mode; 2850 mdata->module_pa = ddata->module_pa; 2851 mdata->module_size = ddata->module_size; 2852 mdata->offsets = ddata->offsets; 2853 mdata->nr_offsets = SYSC_MAX_REGS; 2854 mdata->cap = ddata->cap; 2855 mdata->cfg = &ddata->cfg; 2856 } 2857 2858 ddata->mdata = mdata; 2859 2860 return 0; 2861 } 2862 2863 static int sysc_init_match(struct sysc *ddata) 2864 { 2865 const struct sysc_capabilities *cap; 2866 2867 cap = of_device_get_match_data(ddata->dev); 2868 if (!cap) 2869 return -EINVAL; 2870 2871 ddata->cap = cap; 2872 if (ddata->cap) 2873 ddata->cfg.quirks |= ddata->cap->mod_quirks; 2874 2875 return 0; 2876 } 2877 2878 static void ti_sysc_idle(struct work_struct *work) 2879 { 2880 struct sysc *ddata; 2881 2882 ddata = container_of(work, struct sysc, idle_work.work); 2883 2884 /* 2885 * One time decrement of clock usage counts if left on from init. 2886 * Note that we disable opt clocks unconditionally in this case 2887 * as they are enabled unconditionally during init without 2888 * considering sysc_opt_clks_needed() at that point. 2889 */ 2890 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | 2891 SYSC_QUIRK_NO_IDLE_ON_INIT)) { 2892 sysc_disable_main_clocks(ddata); 2893 sysc_disable_opt_clocks(ddata); 2894 sysc_clkdm_allow_idle(ddata); 2895 } 2896 2897 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */ 2898 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE) 2899 return; 2900 2901 /* 2902 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT 2903 * and SYSC_QUIRK_NO_RESET_ON_INIT 2904 */ 2905 if (pm_runtime_active(ddata->dev)) 2906 pm_runtime_put_sync(ddata->dev); 2907 } 2908 2909 /* 2910 * SoC model and features detection. Only needed for SoCs that need 2911 * special handling for quirks, no need to list others. 2912 */ 2913 static const struct soc_device_attribute sysc_soc_match[] = { 2914 SOC_FLAG("OMAP242*", SOC_2420), 2915 SOC_FLAG("OMAP243*", SOC_2430), 2916 SOC_FLAG("AM35*", SOC_AM35), 2917 SOC_FLAG("OMAP3[45]*", SOC_3430), 2918 SOC_FLAG("OMAP3[67]*", SOC_3630), 2919 SOC_FLAG("OMAP443*", SOC_4430), 2920 SOC_FLAG("OMAP446*", SOC_4460), 2921 SOC_FLAG("OMAP447*", SOC_4470), 2922 SOC_FLAG("OMAP54*", SOC_5430), 2923 SOC_FLAG("AM433", SOC_AM3), 2924 SOC_FLAG("AM43*", SOC_AM4), 2925 SOC_FLAG("DRA7*", SOC_DRA7), 2926 2927 { /* sentinel */ } 2928 }; 2929 2930 /* 2931 * List of SoCs variants with disabled features. By default we assume all 2932 * devices in the device tree are available so no need to list those SoCs. 2933 */ 2934 static const struct soc_device_attribute sysc_soc_feat_match[] = { 2935 /* OMAP3430/3530 and AM3517 variants with some accelerators disabled */ 2936 SOC_FLAG("AM3505", DIS_SGX), 2937 SOC_FLAG("OMAP3525", DIS_SGX), 2938 SOC_FLAG("OMAP3515", DIS_IVA | DIS_SGX), 2939 SOC_FLAG("OMAP3503", DIS_ISP | DIS_IVA | DIS_SGX), 2940 2941 /* OMAP3630/DM3730 variants with some accelerators disabled */ 2942 SOC_FLAG("AM3703", DIS_IVA | DIS_SGX), 2943 SOC_FLAG("DM3725", DIS_SGX), 2944 SOC_FLAG("OMAP3611", DIS_ISP | DIS_IVA | DIS_SGX), 2945 SOC_FLAG("OMAP3615/AM3715", DIS_IVA), 2946 SOC_FLAG("OMAP3621", DIS_ISP), 2947 2948 { /* sentinel */ } 2949 }; 2950 2951 static int sysc_add_disabled(unsigned long base) 2952 { 2953 struct sysc_address *disabled_module; 2954 2955 disabled_module = kzalloc(sizeof(*disabled_module), GFP_KERNEL); 2956 if (!disabled_module) 2957 return -ENOMEM; 2958 2959 disabled_module->base = base; 2960 2961 mutex_lock(&sysc_soc->list_lock); 2962 list_add(&disabled_module->node, &sysc_soc->disabled_modules); 2963 mutex_unlock(&sysc_soc->list_lock); 2964 2965 return 0; 2966 } 2967 2968 /* 2969 * One time init to detect the booted SoC, disable unavailable features 2970 * and initialize list for optional cpu_pm notifier. 2971 * 2972 * Note that we initialize static data shared across all ti-sysc instances 2973 * so ddata is only used for SoC type. This can be called from module_init 2974 * once we no longer need to rely on platform data. 2975 */ 2976 static int sysc_init_static_data(struct sysc *ddata) 2977 { 2978 const struct soc_device_attribute *match; 2979 struct ti_sysc_platform_data *pdata; 2980 unsigned long features = 0; 2981 struct device_node *np; 2982 2983 if (sysc_soc) 2984 return 0; 2985 2986 sysc_soc = kzalloc(sizeof(*sysc_soc), GFP_KERNEL); 2987 if (!sysc_soc) 2988 return -ENOMEM; 2989 2990 mutex_init(&sysc_soc->list_lock); 2991 INIT_LIST_HEAD(&sysc_soc->disabled_modules); 2992 INIT_LIST_HEAD(&sysc_soc->restored_modules); 2993 sysc_soc->general_purpose = true; 2994 2995 pdata = dev_get_platdata(ddata->dev); 2996 if (pdata && pdata->soc_type_gp) 2997 sysc_soc->general_purpose = pdata->soc_type_gp(); 2998 2999 match = soc_device_match(sysc_soc_match); 3000 if (match && match->data) 3001 sysc_soc->soc = (enum sysc_soc)(uintptr_t)match->data; 3002 3003 /* 3004 * Check and warn about possible old incomplete dtb. We now want to see 3005 * simple-pm-bus instead of simple-bus in the dtb for genpd using SoCs. 3006 */ 3007 switch (sysc_soc->soc) { 3008 case SOC_AM3: 3009 case SOC_AM4: 3010 case SOC_4430 ... SOC_4470: 3011 case SOC_5430: 3012 case SOC_DRA7: 3013 np = of_find_node_by_path("/ocp"); 3014 WARN_ONCE(np && of_device_is_compatible(np, "simple-bus"), 3015 "ti-sysc: Incomplete old dtb, please update\n"); 3016 break; 3017 default: 3018 break; 3019 } 3020 3021 /* Ignore devices that are not available on HS and EMU SoCs */ 3022 if (!sysc_soc->general_purpose) { 3023 switch (sysc_soc->soc) { 3024 case SOC_3430 ... SOC_3630: 3025 sysc_add_disabled(0x48304000); /* timer12 */ 3026 break; 3027 case SOC_AM3: 3028 sysc_add_disabled(0x48310000); /* rng */ 3029 break; 3030 default: 3031 break; 3032 } 3033 } 3034 3035 match = soc_device_match(sysc_soc_feat_match); 3036 if (!match) 3037 return 0; 3038 3039 if (match->data) 3040 features = (unsigned long)match->data; 3041 3042 /* 3043 * Add disabled devices to the list based on the module base. 3044 * Note that this must be done before we attempt to access the 3045 * device and have module revision checks working. 3046 */ 3047 if (features & DIS_ISP) 3048 sysc_add_disabled(0x480bd400); 3049 if (features & DIS_IVA) 3050 sysc_add_disabled(0x5d000000); 3051 if (features & DIS_SGX) 3052 sysc_add_disabled(0x50000000); 3053 3054 return 0; 3055 } 3056 3057 static void sysc_cleanup_static_data(void) 3058 { 3059 struct sysc_module *restored_module; 3060 struct sysc_address *disabled_module; 3061 struct list_head *pos, *tmp; 3062 3063 if (!sysc_soc) 3064 return; 3065 3066 if (sysc_soc->nb.notifier_call) 3067 cpu_pm_unregister_notifier(&sysc_soc->nb); 3068 3069 mutex_lock(&sysc_soc->list_lock); 3070 list_for_each_safe(pos, tmp, &sysc_soc->restored_modules) { 3071 restored_module = list_entry(pos, struct sysc_module, node); 3072 list_del(pos); 3073 kfree(restored_module); 3074 } 3075 list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) { 3076 disabled_module = list_entry(pos, struct sysc_address, node); 3077 list_del(pos); 3078 kfree(disabled_module); 3079 } 3080 mutex_unlock(&sysc_soc->list_lock); 3081 } 3082 3083 static int sysc_check_disabled_devices(struct sysc *ddata) 3084 { 3085 struct sysc_address *disabled_module; 3086 int error = 0; 3087 3088 mutex_lock(&sysc_soc->list_lock); 3089 list_for_each_entry(disabled_module, &sysc_soc->disabled_modules, node) { 3090 if (ddata->module_pa == disabled_module->base) { 3091 dev_dbg(ddata->dev, "module disabled for this SoC\n"); 3092 error = -ENODEV; 3093 break; 3094 } 3095 } 3096 mutex_unlock(&sysc_soc->list_lock); 3097 3098 return error; 3099 } 3100 3101 /* 3102 * Ignore timers tagged with no-reset and no-idle. These are likely in use, 3103 * for example by drivers/clocksource/timer-ti-dm-systimer.c. If more checks 3104 * are needed, we could also look at the timer register configuration. 3105 */ 3106 static int sysc_check_active_timer(struct sysc *ddata) 3107 { 3108 int error; 3109 3110 if (ddata->cap->type != TI_SYSC_OMAP2_TIMER && 3111 ddata->cap->type != TI_SYSC_OMAP4_TIMER) 3112 return 0; 3113 3114 /* 3115 * Quirk for omap3 beagleboard revision A to B4 to use gpt12. 3116 * Revision C and later are fixed with commit 23885389dbbb ("ARM: 3117 * dts: Fix timer regression for beagleboard revision c"). This all 3118 * can be dropped if we stop supporting old beagleboard revisions 3119 * A to B4 at some point. 3120 */ 3121 if (sysc_soc->soc == SOC_3430 || sysc_soc->soc == SOC_AM35) 3122 error = -ENXIO; 3123 else 3124 error = -EBUSY; 3125 3126 if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) && 3127 (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)) 3128 return error; 3129 3130 return 0; 3131 } 3132 3133 static const struct of_device_id sysc_match_table[] = { 3134 { .compatible = "simple-bus", }, 3135 { /* sentinel */ }, 3136 }; 3137 3138 static int sysc_probe(struct platform_device *pdev) 3139 { 3140 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev); 3141 struct sysc *ddata; 3142 int error; 3143 3144 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); 3145 if (!ddata) 3146 return -ENOMEM; 3147 3148 ddata->offsets[SYSC_REVISION] = -ENODEV; 3149 ddata->offsets[SYSC_SYSCONFIG] = -ENODEV; 3150 ddata->offsets[SYSC_SYSSTATUS] = -ENODEV; 3151 ddata->dev = &pdev->dev; 3152 platform_set_drvdata(pdev, ddata); 3153 3154 error = sysc_init_static_data(ddata); 3155 if (error) 3156 return error; 3157 3158 error = sysc_init_match(ddata); 3159 if (error) 3160 return error; 3161 3162 error = sysc_init_dts_quirks(ddata); 3163 if (error) 3164 return error; 3165 3166 error = sysc_map_and_check_registers(ddata); 3167 if (error) 3168 return error; 3169 3170 error = sysc_init_sysc_mask(ddata); 3171 if (error) 3172 return error; 3173 3174 error = sysc_init_idlemodes(ddata); 3175 if (error) 3176 return error; 3177 3178 error = sysc_init_syss_mask(ddata); 3179 if (error) 3180 return error; 3181 3182 error = sysc_init_pdata(ddata); 3183 if (error) 3184 return error; 3185 3186 sysc_init_early_quirks(ddata); 3187 3188 error = sysc_check_disabled_devices(ddata); 3189 if (error) 3190 return error; 3191 3192 error = sysc_check_active_timer(ddata); 3193 if (error == -ENXIO) 3194 ddata->reserved = true; 3195 else if (error) 3196 return error; 3197 3198 error = sysc_get_clocks(ddata); 3199 if (error) 3200 return error; 3201 3202 error = sysc_init_resets(ddata); 3203 if (error) 3204 goto unprepare; 3205 3206 error = sysc_init_module(ddata); 3207 if (error) 3208 goto unprepare; 3209 3210 pm_runtime_enable(ddata->dev); 3211 error = pm_runtime_resume_and_get(ddata->dev); 3212 if (error < 0) { 3213 pm_runtime_disable(ddata->dev); 3214 goto unprepare; 3215 } 3216 3217 /* Balance use counts as PM runtime should have enabled these all */ 3218 if (!(ddata->cfg.quirks & 3219 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) { 3220 sysc_disable_main_clocks(ddata); 3221 sysc_disable_opt_clocks(ddata); 3222 sysc_clkdm_allow_idle(ddata); 3223 } 3224 3225 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) 3226 reset_control_assert(ddata->rsts); 3227 3228 sysc_show_registers(ddata); 3229 3230 ddata->dev->type = &sysc_device_type; 3231 3232 if (!ddata->reserved) { 3233 error = of_platform_populate(ddata->dev->of_node, 3234 sysc_match_table, 3235 pdata ? pdata->auxdata : NULL, 3236 ddata->dev); 3237 if (error) 3238 goto err; 3239 } 3240 3241 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle); 3242 3243 /* At least earlycon won't survive without deferred idle */ 3244 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | 3245 SYSC_QUIRK_NO_IDLE_ON_INIT | 3246 SYSC_QUIRK_NO_RESET_ON_INIT)) { 3247 schedule_delayed_work(&ddata->idle_work, 3000); 3248 } else { 3249 pm_runtime_put(&pdev->dev); 3250 } 3251 3252 if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_CTX_LOST) 3253 sysc_add_restored(ddata); 3254 3255 return 0; 3256 3257 err: 3258 pm_runtime_put_sync(&pdev->dev); 3259 pm_runtime_disable(&pdev->dev); 3260 unprepare: 3261 sysc_unprepare(ddata); 3262 3263 return error; 3264 } 3265 3266 static void sysc_remove(struct platform_device *pdev) 3267 { 3268 struct sysc *ddata = platform_get_drvdata(pdev); 3269 int error; 3270 3271 /* Device can still be enabled, see deferred idle quirk in probe */ 3272 if (cancel_delayed_work_sync(&ddata->idle_work)) 3273 ti_sysc_idle(&ddata->idle_work.work); 3274 3275 error = pm_runtime_resume_and_get(ddata->dev); 3276 if (error < 0) { 3277 pm_runtime_disable(ddata->dev); 3278 goto unprepare; 3279 } 3280 3281 of_platform_depopulate(&pdev->dev); 3282 3283 pm_runtime_put_sync(&pdev->dev); 3284 pm_runtime_disable(&pdev->dev); 3285 3286 if (!reset_control_status(ddata->rsts)) 3287 reset_control_assert(ddata->rsts); 3288 3289 unprepare: 3290 sysc_unprepare(ddata); 3291 } 3292 3293 static const struct of_device_id sysc_match[] = { 3294 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, }, 3295 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, }, 3296 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, }, 3297 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, }, 3298 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, }, 3299 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, }, 3300 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, }, 3301 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, }, 3302 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, }, 3303 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, }, 3304 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, }, 3305 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, }, 3306 { .compatible = "ti,sysc-usb-host-fs", 3307 .data = &sysc_omap4_usb_host_fs, }, 3308 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, }, 3309 { .compatible = "ti,sysc-pruss", .data = &sysc_pruss, }, 3310 { }, 3311 }; 3312 MODULE_DEVICE_TABLE(of, sysc_match); 3313 3314 static struct platform_driver sysc_driver = { 3315 .probe = sysc_probe, 3316 .remove = sysc_remove, 3317 .driver = { 3318 .name = "ti-sysc", 3319 .of_match_table = sysc_match, 3320 .pm = &sysc_pm_ops, 3321 }, 3322 }; 3323 3324 static int __init sysc_init(void) 3325 { 3326 bus_register_notifier(&platform_bus_type, &sysc_nb); 3327 3328 return platform_driver_register(&sysc_driver); 3329 } 3330 module_init(sysc_init); 3331 3332 static void __exit sysc_exit(void) 3333 { 3334 bus_unregister_notifier(&platform_bus_type, &sysc_nb); 3335 platform_driver_unregister(&sysc_driver); 3336 sysc_cleanup_static_data(); 3337 } 3338 module_exit(sysc_exit); 3339 3340 MODULE_DESCRIPTION("TI sysc interconnect target driver"); 3341 MODULE_LICENSE("GPL v2"); 3342