1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com> 4 */ 5 6#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/pinctrl/pinctrl-cv1812h.h> 10#include "cv180x-cpus.dtsi" 11#include "cv180x.dtsi" 12#include "cv181x.dtsi" 13 14/ { 15 compatible = "sophgo,cv1812h"; 16 17 memory@80000000 { 18 device_type = "memory"; 19 reg = <0x80000000 0x10000000>; 20 }; 21 22 soc { 23 interrupt-parent = <&plic>; 24 dma-noncoherent; 25 26 pinctrl: pinctrl@3001000 { 27 compatible = "sophgo,cv1812h-pinctrl"; 28 reg = <0x03001000 0x1000>, 29 <0x05027000 0x1000>; 30 reg-names = "sys", "rtc"; 31 }; 32 33 clk: clock-controller@3002000 { 34 compatible = "sophgo,cv1812h-clk"; 35 reg = <0x03002000 0x1000>; 36 clocks = <&osc>; 37 #clock-cells = <1>; 38 }; 39 40 plic: interrupt-controller@70000000 { 41 compatible = "sophgo,cv1812h-plic", "thead,c900-plic"; 42 reg = <0x70000000 0x4000000>; 43 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; 44 interrupt-controller; 45 #address-cells = <0>; 46 #interrupt-cells = <2>; 47 riscv,ndev = <101>; 48 }; 49 50 clint: timer@74000000 { 51 compatible = "sophgo,cv1812h-clint", "thead,c900-clint"; 52 reg = <0x74000000 0x10000>; 53 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; 54 }; 55 }; 56}; 57