1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Kernel execution entry point code. 4 * 5 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> 6 * Initial PowerPC version. 7 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> 8 * Rewritten for PReP 9 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> 10 * Low-level exception handers, MMU support, and rewrite. 11 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> 12 * PowerPC 8xx modifications. 13 * Copyright (c) 1998-1999 TiVo, Inc. 14 * PowerPC 403GCX modifications. 15 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> 16 * PowerPC 403GCX/405GP modifications. 17 * Copyright 2000 MontaVista Software Inc. 18 * PPC405 modifications 19 * PowerPC 403GCX/405GP modifications. 20 * Author: MontaVista Software, Inc. 21 * frank_rowand@mvista.com or source@mvista.com 22 * debbie_chu@mvista.com 23 * Copyright 2002-2004 MontaVista Software, Inc. 24 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org> 25 * Copyright 2004 Freescale Semiconductor, Inc 26 * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org> 27 */ 28 29#include <linux/init.h> 30#include <linux/threads.h> 31#include <linux/pgtable.h> 32#include <linux/linkage.h> 33 34#include <asm/processor.h> 35#include <asm/page.h> 36#include <asm/mmu.h> 37#include <asm/cputable.h> 38#include <asm/thread_info.h> 39#include <asm/ppc_asm.h> 40#include <asm/asm-offsets.h> 41#include <asm/cache.h> 42#include <asm/ptrace.h> 43#include <asm/feature-fixups.h> 44#include "head_booke.h" 45 46/* As with the other PowerPC ports, it is expected that when code 47 * execution begins here, the following registers contain valid, yet 48 * optional, information: 49 * 50 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) 51 * r4 - Starting address of the init RAM disk 52 * r5 - Ending address of the init RAM disk 53 * r6 - Start of kernel command line string (e.g. "mem=128") 54 * r7 - End of kernel command line string 55 * 56 */ 57 __HEAD 58_GLOBAL(_stext); 59_GLOBAL(_start); 60 /* 61 * Reserve a word at a fixed location to store the address 62 * of abatron_pteptrs 63 */ 64 nop 65 66 /* Translate device tree address to physical, save in r30/r31 */ 67 bl get_phys_addr 68 mr r30,r3 69 mr r31,r4 70 71 li r25,0 /* phys kernel start (low) */ 72 li r24,0 /* CPU number */ 73 li r23,0 /* phys kernel start (high) */ 74 75#ifdef CONFIG_RELOCATABLE 76 LOAD_REG_ADDR_PIC(r3, _stext) /* Get our current runtime base */ 77 78 /* Translate _stext address to physical, save in r23/r25 */ 79 bl get_phys_addr 80 mr r23,r3 81 mr r25,r4 82 83 bcl 20,31,$+4 840: mflr r8 85 addis r3,r8,(is_second_reloc - 0b)@ha 86 lwz r19,(is_second_reloc - 0b)@l(r3) 87 88 /* Check if this is the second relocation. */ 89 cmpwi r19,1 90 bne 1f 91 92 /* 93 * For the second relocation, we already get the real memstart_addr 94 * from device tree. So we will map PAGE_OFFSET to memstart_addr, 95 * then the virtual address of start kernel should be: 96 * PAGE_OFFSET + (kernstart_addr - memstart_addr) 97 * Since the offset between kernstart_addr and memstart_addr should 98 * never be beyond 1G, so we can just use the lower 32bit of them 99 * for the calculation. 100 */ 101 lis r3,PAGE_OFFSET@h 102 103 addis r4,r8,(kernstart_addr - 0b)@ha 104 addi r4,r4,(kernstart_addr - 0b)@l 105 lwz r5,4(r4) 106 107 addis r6,r8,(memstart_addr - 0b)@ha 108 addi r6,r6,(memstart_addr - 0b)@l 109 lwz r7,4(r6) 110 111 subf r5,r7,r5 112 add r3,r3,r5 113 b 2f 114 1151: 116 /* 117 * We have the runtime (virtual) address of our base. 118 * We calculate our shift of offset from a 64M page. 119 * We could map the 64M page we belong to at PAGE_OFFSET and 120 * get going from there. 121 */ 122 lis r4,KERNELBASE@h 123 ori r4,r4,KERNELBASE@l 124 rlwinm r6,r25,0,0x3ffffff /* r6 = PHYS_START % 64M */ 125 rlwinm r5,r4,0,0x3ffffff /* r5 = KERNELBASE % 64M */ 126 subf r3,r5,r6 /* r3 = r6 - r5 */ 127 add r3,r4,r3 /* Required Virtual Address */ 128 1292: bl relocate 130 131 /* 132 * For the second relocation, we already set the right tlb entries 133 * for the kernel space, so skip the code in 85xx_entry_mapping.S 134 */ 135 cmpwi r19,1 136 beq set_ivor 137#endif 138 139/* We try to not make any assumptions about how the boot loader 140 * setup or used the TLBs. We invalidate all mappings from the 141 * boot loader and load a single entry in TLB1[0] to map the 142 * first 64M of kernel memory. Any boot info passed from the 143 * bootloader needs to live in this first 64M. 144 * 145 * Requirement on bootloader: 146 * - The page we're executing in needs to reside in TLB1 and 147 * have IPROT=1. If not an invalidate broadcast could 148 * evict the entry we're currently executing in. 149 * 150 * r3 = Index of TLB1 were executing in 151 * r4 = Current MSR[IS] 152 * r5 = Index of TLB1 temp mapping 153 * 154 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0] 155 * if needed 156 */ 157 158_GLOBAL(__early_start) 159 LOAD_REG_ADDR_PIC(r20, kernstart_virt_addr) 160 lwz r20,0(r20) 161 162#define ENTRY_MAPPING_BOOT_SETUP 163#include "85xx_entry_mapping.S" 164#undef ENTRY_MAPPING_BOOT_SETUP 165 166set_ivor: 167 /* Establish the interrupt vector offsets */ 168 SET_IVOR(0, CriticalInput); 169 SET_IVOR(1, MachineCheck); 170 SET_IVOR(2, DataStorage); 171 SET_IVOR(3, InstructionStorage); 172 SET_IVOR(4, ExternalInput); 173 SET_IVOR(5, Alignment); 174 SET_IVOR(6, Program); 175 SET_IVOR(7, FloatingPointUnavailable); 176 SET_IVOR(8, SystemCall); 177 SET_IVOR(9, AuxillaryProcessorUnavailable); 178 SET_IVOR(10, Decrementer); 179 SET_IVOR(11, FixedIntervalTimer); 180 SET_IVOR(12, WatchdogTimer); 181 SET_IVOR(13, DataTLBError); 182 SET_IVOR(14, InstructionTLBError); 183 SET_IVOR(15, DebugCrit); 184 185 /* Establish the interrupt vector base */ 186 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ 187 mtspr SPRN_IVPR,r4 188 189 /* Setup the defaults for TLB entries */ 190 li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l 191 mtspr SPRN_MAS4, r2 192 193#if !defined(CONFIG_BDI_SWITCH) 194 /* 195 * The Abatron BDI JTAG debugger does not tolerate others 196 * mucking with the debug registers. 197 */ 198 lis r2,DBCR0_IDM@h 199 mtspr SPRN_DBCR0,r2 200 isync 201 /* clear any residual debug events */ 202 li r2,-1 203 mtspr SPRN_DBSR,r2 204#endif 205 206#ifdef CONFIG_SMP 207 /* Check to see if we're the second processor, and jump 208 * to the secondary_start code if so 209 */ 210 LOAD_REG_ADDR_PIC(r24, boot_cpuid) 211 lwz r24, 0(r24) 212 cmpwi r24, -1 213 mfspr r24,SPRN_PIR 214 bne __secondary_start 215#endif 216 217 /* 218 * This is where the main kernel code starts. 219 */ 220 221 /* ptr to current */ 222 lis r2,init_task@h 223 ori r2,r2,init_task@l 224 225 /* ptr to current thread */ 226 addi r4,r2,THREAD /* init task's THREAD */ 227 mtspr SPRN_SPRG_THREAD,r4 228 229 /* stack */ 230 lis r1,init_thread_union@h 231 ori r1,r1,init_thread_union@l 232 li r0,0 233 stwu r0,THREAD_SIZE-STACK_FRAME_MIN_SIZE(r1) 234 235#ifdef CONFIG_SMP 236 stw r24, TASK_CPU(r2) 237#endif 238 239 bl early_init 240 241#ifdef CONFIG_KASAN 242 bl kasan_early_init 243#endif 244#ifdef CONFIG_RELOCATABLE 245 mr r3,r30 246 mr r4,r31 247#ifdef CONFIG_PHYS_64BIT 248 mr r5,r23 249 mr r6,r25 250#else 251 mr r5,r25 252#endif 253 bl relocate_init 254#endif 255 256#ifdef CONFIG_DYNAMIC_MEMSTART 257 lis r3,kernstart_addr@ha 258 la r3,kernstart_addr@l(r3) 259#ifdef CONFIG_PHYS_64BIT 260 stw r23,0(r3) 261 stw r25,4(r3) 262#else 263 stw r25,0(r3) 264#endif 265#endif 266 267/* 268 * Decide what sort of machine this is and initialize the MMU. 269 */ 270 mr r3,r30 271 mr r4,r31 272 bl machine_init 273 bl MMU_init 274 275 /* Setup PTE pointers for the Abatron bdiGDB */ 276 lis r6, swapper_pg_dir@h 277 ori r6, r6, swapper_pg_dir@l 278 lis r5, abatron_pteptrs@h 279 ori r5, r5, abatron_pteptrs@l 280 lis r3, kernstart_virt_addr@ha 281 lwz r4, kernstart_virt_addr@l(r3) 282 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */ 283 stw r6, 0(r5) 284 285 /* Let's move on */ 286 lis r4,start_kernel@h 287 ori r4,r4,start_kernel@l 288 lis r3,MSR_KERNEL@h 289 ori r3,r3,MSR_KERNEL@l 290 mtspr SPRN_SRR0,r4 291 mtspr SPRN_SRR1,r3 292 rfi /* change context and jump to start_kernel */ 293 294/* Macros to hide the PTE size differences 295 * 296 * FIND_PTE -- walks the page tables given EA & pgdir pointer 297 * r10 -- free 298 * r11 -- PGDIR pointer 299 * r12 -- free 300 * r13 -- EA of fault 301 * label 2: is the bailout case 302 * 303 * if we find the pte (fall through): 304 * r11 is low pte word 305 * r12 is pointer to the pte 306 * r10 is the pshift from the PGD, if we're a hugepage 307 */ 308#ifdef CONFIG_HUGETLB_PAGE 309#define FIND_PTE \ 310 rlwinm r12, r13, 14, 18, 28; /* Compute pgdir/pmd offset */ \ 311 add r12, r11, r12; \ 312 lwz r11, 4(r12); /* Get pgd/pmd entry */ \ 313 rlwinm. r10, r11, 32 - _PAGE_PSIZE_SHIFT, 0x1e; /* get tsize*/ \ 314 bne 1000f; /* Huge page (leaf entry) */ \ 315 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \ 316 beq 2f; /* Bail if no table */ \ 317 rlwimi r12, r13, 23, 20, 28; /* Compute pte address */ \ 318 li r10, 0; /* clear r10 */ \ 319 lwz r11, 4(r12); /* Get pte entry */ \ 3201000: 321#else 322#define FIND_PTE \ 323 rlwinm r12, r13, 14, 18, 28; /* Compute pgdir/pmd offset */ \ 324 add r12, r11, r12; \ 325 lwz r11, 4(r12); /* Get pgd/pmd entry */ \ 326 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \ 327 beq 2f; /* Bail if no table */ \ 328 rlwimi r12, r13, 23, 20, 28; /* Compute pte address */ \ 329 lwz r11, 4(r12); /* Get pte entry */ 330#endif /* HUGEPAGE */ 331 332/* 333 * Interrupt vector entry code 334 * 335 * The Book E MMUs are always on so we don't need to handle 336 * interrupts in real mode as with previous PPC processors. In 337 * this case we handle interrupts in the kernel virtual address 338 * space. 339 * 340 * Interrupt vectors are dynamically placed relative to the 341 * interrupt prefix as determined by the address of interrupt_base. 342 * The interrupt vectors offsets are programmed using the labels 343 * for each interrupt vector entry. 344 * 345 * Interrupt vectors must be aligned on a 16 byte boundary. 346 * We align on a 32 byte cache line boundary for good measure. 347 */ 348 349interrupt_base: 350 /* Critical Input Interrupt */ 351 CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception) 352 353 /* Machine Check Interrupt */ 354 MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception) 355 356 /* Data Storage Interrupt */ 357 START_EXCEPTION(DataStorage) 358 NORMAL_EXCEPTION_PROLOG(0x300, DATA_STORAGE) 359 mfspr r5,SPRN_ESR /* Grab the ESR, save it */ 360 stw r5,_ESR(r11) 361 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it */ 362 stw r4, _DEAR(r11) 363 andis. r10,r5,(ESR_ILK|ESR_DLK)@h 364 bne 1f 365 prepare_transfer_to_handler 366 bl do_page_fault 367 b interrupt_return 3681: 369 prepare_transfer_to_handler 370 bl CacheLockingException 371 b interrupt_return 372 373 /* Instruction Storage Interrupt */ 374 INSTRUCTION_STORAGE_EXCEPTION 375 376 /* External Input Interrupt */ 377 EXCEPTION(0x0500, EXTERNAL, ExternalInput, do_IRQ) 378 379 /* Alignment Interrupt */ 380 ALIGNMENT_EXCEPTION 381 382 /* Program Interrupt */ 383 PROGRAM_EXCEPTION 384 385 /* Floating Point Unavailable Interrupt */ 386#ifdef CONFIG_PPC_FPU 387 FP_UNAVAILABLE_EXCEPTION 388#else 389 EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, emulation_assist_interrupt) 390#endif 391 392 /* System Call Interrupt */ 393 START_EXCEPTION(SystemCall) 394 SYSCALL_ENTRY 0xc00 BOOKE_INTERRUPT_SYSCALL SPRN_SRR1 395 396 /* Auxiliary Processor Unavailable Interrupt */ 397 EXCEPTION(0x2900, AP_UNAVAIL, AuxillaryProcessorUnavailable, unknown_exception) 398 399 /* Decrementer Interrupt */ 400 DECREMENTER_EXCEPTION 401 402 /* Fixed Internal Timer Interrupt */ 403 /* TODO: Add FIT support */ 404 EXCEPTION(0x3100, FIT, FixedIntervalTimer, unknown_exception) 405 406 /* Watchdog Timer Interrupt */ 407#ifdef CONFIG_BOOKE_WDT 408 CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, WatchdogException) 409#else 410 CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, unknown_exception) 411#endif 412 413 /* Data TLB Error Interrupt */ 414 START_EXCEPTION(DataTLBError) 415 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */ 416 mfspr r10, SPRN_SPRG_THREAD 417 stw r11, THREAD_NORMSAVE(0)(r10) 418#ifdef CONFIG_KVM_BOOKE_HV 419BEGIN_FTR_SECTION 420 mfspr r11, SPRN_SRR1 421END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) 422#endif 423 stw r12, THREAD_NORMSAVE(1)(r10) 424 stw r13, THREAD_NORMSAVE(2)(r10) 425 mfcr r13 426 stw r13, THREAD_NORMSAVE(3)(r10) 427 DO_KVM BOOKE_INTERRUPT_DTLB_MISS SPRN_SRR1 428START_BTB_FLUSH_SECTION 429 mfspr r11, SPRN_SRR1 430 andi. r10,r11,MSR_PR 431 beq 1f 432 BTB_FLUSH(r10) 4331: 434END_BTB_FLUSH_SECTION 435 mfspr r13, SPRN_DEAR /* Get faulting address */ 436 437 /* If we are faulting a kernel address, we have to use the 438 * kernel page tables. 439 */ 440 lis r11, PAGE_OFFSET@h 441 cmplw 5, r13, r11 442 blt 5, 3f 443 lis r11, swapper_pg_dir@h 444 ori r11, r11, swapper_pg_dir@l 445 446 mfspr r12,SPRN_MAS1 /* Set TID to 0 */ 447 rlwinm r12,r12,0,16,1 448 mtspr SPRN_MAS1,r12 449 450 b 4f 451 452 /* Get the PGD for the current thread */ 4533: 454 mfspr r11,SPRN_SPRG_THREAD 455 lwz r11,PGDIR(r11) 456 457#ifdef CONFIG_PPC_KUAP 458 mfspr r12, SPRN_MAS1 459 rlwinm. r12,r12,0,0x3fff0000 460 beq 2f /* KUAP fault */ 461#endif 462 4634: 464 FIND_PTE 465 466 li r13,_PAGE_PRESENT|_PAGE_BAP_SR 467 oris r13,r13,_PAGE_ACCESSED@h 468 andc. r13,r13,r11 /* Check permission */ 469 470#ifdef CONFIG_SMP 471 subf r13,r11,r12 /* create false data dep */ 472 lwzx r13,r11,r13 /* Get upper pte bits */ 473#else 474 lwz r13,0(r12) /* Get upper pte bits */ 475#endif 476 477 bne 2f /* Bail if permission/valid mismatch */ 478 479 /* Jump to common tlb load */ 480 b finish_tlb_load 4812: 482 /* The bailout. Restore registers to pre-exception conditions 483 * and call the heavyweights to help us out. 484 */ 485 mfspr r10, SPRN_SPRG_THREAD 486 lwz r11, THREAD_NORMSAVE(3)(r10) 487 mtcr r11 488 lwz r13, THREAD_NORMSAVE(2)(r10) 489 lwz r12, THREAD_NORMSAVE(1)(r10) 490 lwz r11, THREAD_NORMSAVE(0)(r10) 491 mfspr r10, SPRN_SPRG_RSCRATCH0 492 b DataStorage 493 494 /* Instruction TLB Error Interrupt */ 495 /* 496 * Nearly the same as above, except we get our 497 * information from different registers and bailout 498 * to a different point. 499 */ 500 START_EXCEPTION(InstructionTLBError) 501 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */ 502 mfspr r10, SPRN_SPRG_THREAD 503 stw r11, THREAD_NORMSAVE(0)(r10) 504#ifdef CONFIG_KVM_BOOKE_HV 505BEGIN_FTR_SECTION 506 mfspr r11, SPRN_SRR1 507END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) 508#endif 509 stw r12, THREAD_NORMSAVE(1)(r10) 510 stw r13, THREAD_NORMSAVE(2)(r10) 511 mfcr r13 512 stw r13, THREAD_NORMSAVE(3)(r10) 513 DO_KVM BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR1 514START_BTB_FLUSH_SECTION 515 mfspr r11, SPRN_SRR1 516 andi. r10,r11,MSR_PR 517 beq 1f 518 BTB_FLUSH(r10) 5191: 520END_BTB_FLUSH_SECTION 521 522 mfspr r13, SPRN_SRR0 /* Get faulting address */ 523 524 /* If we are faulting a kernel address, we have to use the 525 * kernel page tables. 526 */ 527 lis r11, PAGE_OFFSET@h 528 cmplw 5, r13, r11 529 blt 5, 3f 530 lis r11, swapper_pg_dir@h 531 ori r11, r11, swapper_pg_dir@l 532 533 mfspr r12,SPRN_MAS1 /* Set TID to 0 */ 534 rlwinm r12,r12,0,16,1 535 mtspr SPRN_MAS1,r12 536 537 FIND_PTE 538 /* Make up the required permissions for kernel code */ 539 li r13,_PAGE_PRESENT | _PAGE_BAP_SX 540 oris r13,r13,_PAGE_ACCESSED@h 541 b 4f 542 543 /* Get the PGD for the current thread */ 5443: 545 mfspr r11,SPRN_SPRG_THREAD 546 lwz r11,PGDIR(r11) 547 548#ifdef CONFIG_PPC_KUAP 549 mfspr r12, SPRN_MAS1 550 rlwinm. r12,r12,0,0x3fff0000 551 beq 2f /* KUAP fault */ 552#endif 553 554 FIND_PTE 555 /* Make up the required permissions for user code */ 556 li r13,_PAGE_PRESENT | _PAGE_BAP_UX 557 oris r13,r13,_PAGE_ACCESSED@h 558 5594: 560 andc. r13,r13,r11 /* Check permission */ 561 562#ifdef CONFIG_SMP 563 subf r13,r11,r12 /* create false data dep */ 564 lwzx r13,r11,r13 /* Get upper pte bits */ 565#else 566 lwz r13,0(r12) /* Get upper pte bits */ 567#endif 568 569 bne 2f /* Bail if permission mismatch */ 570 571 /* Jump to common TLB load point */ 572 b finish_tlb_load 573 5742: 575 /* The bailout. Restore registers to pre-exception conditions 576 * and call the heavyweights to help us out. 577 */ 578 mfspr r10, SPRN_SPRG_THREAD 579 lwz r11, THREAD_NORMSAVE(3)(r10) 580 mtcr r11 581 lwz r13, THREAD_NORMSAVE(2)(r10) 582 lwz r12, THREAD_NORMSAVE(1)(r10) 583 lwz r11, THREAD_NORMSAVE(0)(r10) 584 mfspr r10, SPRN_SPRG_RSCRATCH0 585 b InstructionStorage 586 587/* Define SPE handlers for e500v2 */ 588#ifdef CONFIG_SPE 589 /* SPE Unavailable */ 590 START_EXCEPTION(SPEUnavailable) 591 NORMAL_EXCEPTION_PROLOG(0x2010, SPE_UNAVAIL) 592 beq 1f 593 bl load_up_spe 594 b fast_exception_return 5951: prepare_transfer_to_handler 596 bl KernelSPE 597 b interrupt_return 598#elif defined(CONFIG_SPE_POSSIBLE) 599 EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, unknown_exception) 600#endif /* CONFIG_SPE_POSSIBLE */ 601 602 /* SPE Floating Point Data */ 603#ifdef CONFIG_SPE 604 START_EXCEPTION(SPEFloatingPointData) 605 NORMAL_EXCEPTION_PROLOG(0x2030, SPE_FP_DATA) 606 prepare_transfer_to_handler 607 bl SPEFloatingPointException 608 REST_NVGPRS(r1) 609 b interrupt_return 610 611 /* SPE Floating Point Round */ 612 START_EXCEPTION(SPEFloatingPointRound) 613 NORMAL_EXCEPTION_PROLOG(0x2050, SPE_FP_ROUND) 614 prepare_transfer_to_handler 615 bl SPEFloatingPointRoundException 616 REST_NVGPRS(r1) 617 b interrupt_return 618#elif defined(CONFIG_SPE_POSSIBLE) 619 EXCEPTION(0x2040, SPE_FP_DATA, SPEFloatingPointData, unknown_exception) 620 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, unknown_exception) 621#endif /* CONFIG_SPE_POSSIBLE */ 622 623 624 /* Performance Monitor */ 625 EXCEPTION(0x2060, PERFORMANCE_MONITOR, PerformanceMonitor, \ 626 performance_monitor_exception) 627 628 EXCEPTION(0x2070, DOORBELL, Doorbell, doorbell_exception) 629 630 CRITICAL_EXCEPTION(0x2080, DOORBELL_CRITICAL, \ 631 CriticalDoorbell, unknown_exception) 632 633 /* Debug Interrupt */ 634 DEBUG_DEBUG_EXCEPTION 635 DEBUG_CRIT_EXCEPTION 636 637 GUEST_DOORBELL_EXCEPTION 638 639 CRITICAL_EXCEPTION(0, GUEST_DBELL_CRIT, CriticalGuestDoorbell, \ 640 unknown_exception) 641 642 /* Hypercall */ 643 EXCEPTION(0, HV_SYSCALL, Hypercall, unknown_exception) 644 645 /* Embedded Hypervisor Privilege */ 646 EXCEPTION(0, HV_PRIV, Ehvpriv, unknown_exception) 647 648interrupt_end: 649 650/* 651 * Local functions 652 */ 653 654/* 655 * Both the instruction and data TLB miss get to this 656 * point to load the TLB. 657 * r10 - tsize encoding (if HUGETLB_PAGE) or available to use 658 * r11 - TLB (info from Linux PTE) 659 * r12 - available to use 660 * r13 - upper bits of PTE 661 * CR5 - results of addr >= PAGE_OFFSET 662 * MAS0, MAS1 - loaded with proper value when we get here 663 * MAS2, MAS3 - will need additional info from Linux PTE 664 * Upon exit, we reload everything and RFI. 665 */ 666finish_tlb_load: 667#ifdef CONFIG_HUGETLB_PAGE 668 cmpwi 6, r10, 0 /* check for huge page */ 669 beq 6, finish_tlb_load_cont /* !huge */ 670 671 /* Alas, we need more scratch registers for hugepages */ 672 mfspr r12, SPRN_SPRG_THREAD 673 stw r14, THREAD_NORMSAVE(4)(r12) 674 stw r15, THREAD_NORMSAVE(5)(r12) 675 stw r16, THREAD_NORMSAVE(6)(r12) 676 stw r17, THREAD_NORMSAVE(7)(r12) 677 678 /* Get the next_tlbcam_idx percpu var */ 679#ifdef CONFIG_SMP 680 lwz r15, TASK_CPU-THREAD(r12) 681 lis r14, __per_cpu_offset@h 682 ori r14, r14, __per_cpu_offset@l 683 rlwinm r15, r15, 2, 0, 29 684 lwzx r16, r14, r15 685#else 686 li r16, 0 687#endif 688 lis r17, next_tlbcam_idx@h 689 ori r17, r17, next_tlbcam_idx@l 690 add r17, r17, r16 /* r17 = *next_tlbcam_idx */ 691 lwz r15, 0(r17) /* r15 = next_tlbcam_idx */ 692 693 lis r14, MAS0_TLBSEL(1)@h /* select TLB1 (TLBCAM) */ 694 rlwimi r14, r15, 16, 4, 15 /* next_tlbcam_idx entry */ 695 mtspr SPRN_MAS0, r14 696 697 /* Extract TLB1CFG(NENTRY) */ 698 mfspr r16, SPRN_TLB1CFG 699 andi. r16, r16, 0xfff 700 701 /* Update next_tlbcam_idx, wrapping when necessary */ 702 addi r15, r15, 1 703 cmpw r15, r16 704 blt 100f 705 lis r14, tlbcam_index@h 706 ori r14, r14, tlbcam_index@l 707 lwz r15, 0(r14) 708100: stw r15, 0(r17) 709 710 mfspr r16, SPRN_MAS1 711 rlwimi r16, r10, MAS1_TSIZE_SHIFT, MAS1_TSIZE_MASK 712 mtspr SPRN_MAS1, r16 713 714 /* copy the pshift for use later */ 715 addi r14, r10, _PAGE_PSIZE_SHIFT_OFFSET 716 717 /* fall through */ 718 719#endif /* CONFIG_HUGETLB_PAGE */ 720 721 /* 722 * We set execute, because we don't have the granularity to 723 * properly set this at the page level (Linux problem). 724 * Many of these bits are software only. Bits we don't set 725 * here we (properly should) assume have the appropriate value. 726 */ 727finish_tlb_load_cont: 728 rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */ 729 andi. r10, r11, _PAGE_DIRTY 730 bne 1f 731 li r10, MAS3_SW | MAS3_UW 732 andc r12, r12, r10 7331: rlwimi r12, r13, 20, 0, 11 /* grab RPN[32:43] */ 734 rlwimi r12, r11, 20, 12, 19 /* grab RPN[44:51] */ 7352: mtspr SPRN_MAS3, r12 736BEGIN_MMU_FTR_SECTION 737 srwi r10, r13, 12 /* grab RPN[12:31] */ 738 mtspr SPRN_MAS7, r10 739END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS) 740 741 mfspr r12, SPRN_MAS2 742 rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */ 743#ifdef CONFIG_HUGETLB_PAGE 744 beq 6, 3f /* don't mask if page isn't huge */ 745 li r13, 1 746 slw r13, r13, r14 747 subi r13, r13, 1 748 rlwinm r13, r13, 0, 0, 19 /* bottom bits used for WIMGE/etc */ 749 andc r12, r12, r13 /* mask off ea bits within the page */ 750#endif 7513: mtspr SPRN_MAS2, r12 752 753tlb_write_entry: 754 tlbwe 755 756 /* Done...restore registers and get out of here. */ 757 mfspr r10, SPRN_SPRG_THREAD 758#ifdef CONFIG_HUGETLB_PAGE 759 beq 6, 8f /* skip restore for 4k page faults */ 760 lwz r14, THREAD_NORMSAVE(4)(r10) 761 lwz r15, THREAD_NORMSAVE(5)(r10) 762 lwz r16, THREAD_NORMSAVE(6)(r10) 763 lwz r17, THREAD_NORMSAVE(7)(r10) 764#endif 7658: lwz r11, THREAD_NORMSAVE(3)(r10) 766 mtcr r11 767 lwz r13, THREAD_NORMSAVE(2)(r10) 768 lwz r12, THREAD_NORMSAVE(1)(r10) 769 lwz r11, THREAD_NORMSAVE(0)(r10) 770 mfspr r10, SPRN_SPRG_RSCRATCH0 771 rfi /* Force context change */ 772 773#ifdef CONFIG_SPE 774/* Note that the SPE support is closely modeled after the AltiVec 775 * support. Changes to one are likely to be applicable to the 776 * other! */ 777_GLOBAL(load_up_spe) 778/* 779 * Disable SPE for the task which had SPE previously, 780 * and save its SPE registers in its thread_struct. 781 * Enables SPE for use in the kernel on return. 782 * On SMP we know the SPE units are free, since we give it up every 783 * switch. -- Kumar 784 */ 785 mfmsr r5 786 oris r5,r5,MSR_SPE@h 787 mtmsr r5 /* enable use of SPE now */ 788 isync 789 /* enable use of SPE after return */ 790 oris r9,r9,MSR_SPE@h 791 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ 792 li r4,1 793 li r10,THREAD_ACC 794 stw r4,THREAD_USED_SPE(r5) 795 evlddx evr4,r10,r5 796 evmra evr4,evr4 797 REST_32EVRS(0,r10,r5,THREAD_EVR0) 798 blr 799 800/* 801 * SPE unavailable trap from kernel - print a message, but let 802 * the task use SPE in the kernel until it returns to user mode. 803 */ 804SYM_FUNC_START_LOCAL(KernelSPE) 805 lwz r3,_MSR(r1) 806 oris r3,r3,MSR_SPE@h 807 stw r3,_MSR(r1) /* enable use of SPE after return */ 808#ifdef CONFIG_PRINTK 809 lis r3,87f@h 810 ori r3,r3,87f@l 811 mr r4,r2 /* current */ 812 lwz r5,_NIP(r1) 813 bl _printk 814#endif 815 b interrupt_return 816#ifdef CONFIG_PRINTK 81787: .string "SPE used in kernel (task=%p, pc=%x) \n" 818#endif 819 .align 4,0 820 821SYM_FUNC_END(KernelSPE) 822#endif /* CONFIG_SPE */ 823 824/* 825 * Translate the effec addr in r3 to phys addr. The phys addr will be put 826 * into r3(higher 32bit) and r4(lower 32bit) 827 */ 828SYM_FUNC_START_LOCAL(get_phys_addr) 829 mfmsr r8 830 mfspr r9,SPRN_PID 831 rlwinm r9,r9,16,0x3fff0000 /* turn PID into MAS6[SPID] */ 832 rlwimi r9,r8,28,0x00000001 /* turn MSR[DS] into MAS6[SAS] */ 833 mtspr SPRN_MAS6,r9 834 835 tlbsx 0,r3 /* must succeed */ 836 837 mfspr r8,SPRN_MAS1 838 mfspr r12,SPRN_MAS3 839 rlwinm r9,r8,25,0x1f /* r9 = log2(page size) */ 840 li r10,1024 841 slw r10,r10,r9 /* r10 = page size */ 842 addi r10,r10,-1 843 and r11,r3,r10 /* r11 = page offset */ 844 andc r4,r12,r10 /* r4 = page base */ 845 or r4,r4,r11 /* r4 = devtree phys addr */ 846#ifdef CONFIG_PHYS_64BIT 847 mfspr r3,SPRN_MAS7 848#endif 849 blr 850SYM_FUNC_END(get_phys_addr) 851 852/* 853 * Global functions 854 */ 855 856#ifdef CONFIG_PPC_E500 857#ifndef CONFIG_PPC_E500MC 858/* Adjust or setup IVORs for e500v1/v2 */ 859_GLOBAL(__setup_e500_ivors) 860 li r3,DebugCrit@l 861 mtspr SPRN_IVOR15,r3 862 li r3,SPEUnavailable@l 863 mtspr SPRN_IVOR32,r3 864 li r3,SPEFloatingPointData@l 865 mtspr SPRN_IVOR33,r3 866 li r3,SPEFloatingPointRound@l 867 mtspr SPRN_IVOR34,r3 868 li r3,PerformanceMonitor@l 869 mtspr SPRN_IVOR35,r3 870 sync 871 blr 872#else 873/* Adjust or setup IVORs for e500mc */ 874_GLOBAL(__setup_e500mc_ivors) 875 li r3,DebugDebug@l 876 mtspr SPRN_IVOR15,r3 877 li r3,PerformanceMonitor@l 878 mtspr SPRN_IVOR35,r3 879 li r3,Doorbell@l 880 mtspr SPRN_IVOR36,r3 881 li r3,CriticalDoorbell@l 882 mtspr SPRN_IVOR37,r3 883 sync 884 blr 885 886/* setup ehv ivors for */ 887_GLOBAL(__setup_ehv_ivors) 888 li r3,GuestDoorbell@l 889 mtspr SPRN_IVOR38,r3 890 li r3,CriticalGuestDoorbell@l 891 mtspr SPRN_IVOR39,r3 892 li r3,Hypercall@l 893 mtspr SPRN_IVOR40,r3 894 li r3,Ehvpriv@l 895 mtspr SPRN_IVOR41,r3 896 sync 897 blr 898#endif /* CONFIG_PPC_E500MC */ 899#endif /* CONFIG_PPC_E500 */ 900 901#ifdef CONFIG_SPE 902/* 903 * extern void __giveup_spe(struct task_struct *prev) 904 * 905 */ 906_GLOBAL(__giveup_spe) 907 addi r3,r3,THREAD /* want THREAD of task */ 908 lwz r5,PT_REGS(r3) 909 cmpi 0,r5,0 910 SAVE_32EVRS(0, r4, r3, THREAD_EVR0) 911 evxor evr6, evr6, evr6 /* clear out evr6 */ 912 evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */ 913 li r4,THREAD_ACC 914 evstddx evr6, r4, r3 /* save off accumulator */ 915 beq 1f 916 lwz r4,_MSR-STACK_INT_FRAME_REGS(r5) 917 lis r3,MSR_SPE@h 918 andc r4,r4,r3 /* disable SPE for previous task */ 919 stw r4,_MSR-STACK_INT_FRAME_REGS(r5) 9201: 921 blr 922#endif /* CONFIG_SPE */ 923 924/* 925 * extern void abort(void) 926 * 927 * At present, this routine just applies a system reset. 928 */ 929_GLOBAL(abort) 930 li r13,0 931 mtspr SPRN_DBCR0,r13 /* disable all debug events */ 932 isync 933 mfmsr r13 934 ori r13,r13,MSR_DE@l /* Enable Debug Events */ 935 mtmsr r13 936 isync 937 mfspr r13,SPRN_DBCR0 938 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h 939 mtspr SPRN_DBCR0,r13 940 isync 941 942#ifdef CONFIG_SMP 943/* When we get here, r24 needs to hold the CPU # */ 944 .globl __secondary_start 945__secondary_start: 946 LOAD_REG_ADDR_PIC(r3, tlbcam_index) 947 lwz r3,0(r3) 948 mtctr r3 949 li r26,0 /* r26 safe? */ 950 951 bl switch_to_as1 952 mr r27,r3 /* tlb entry */ 953 /* Load each CAM entry */ 9541: mr r3,r26 955 bl loadcam_entry 956 addi r26,r26,1 957 bdnz 1b 958 mr r3,r27 /* tlb entry */ 959 LOAD_REG_ADDR_PIC(r4, memstart_addr) 960 lwz r4,0(r4) 961 mr r5,r25 /* phys kernel start */ 962 rlwinm r5,r5,0,~0x3ffffff /* aligned 64M */ 963 subf r4,r5,r4 /* memstart_addr - phys kernel start */ 964 lis r7,KERNELBASE@h 965 ori r7,r7,KERNELBASE@l 966 cmpw r20,r7 /* if kernstart_virt_addr != KERNELBASE, randomized */ 967 beq 2f 968 li r4,0 9692: li r5,0 /* no device tree */ 970 li r6,0 /* not boot cpu */ 971 bl restore_to_as0 972 973 974 lis r3,__secondary_hold_acknowledge@h 975 ori r3,r3,__secondary_hold_acknowledge@l 976 stw r24,0(r3) 977 978 li r3,0 979 mr r4,r24 /* Why? */ 980 bl call_setup_cpu 981 982 /* get current's stack and current */ 983 lis r2,secondary_current@ha 984 lwz r2,secondary_current@l(r2) 985 lwz r1,TASK_STACK(r2) 986 987 /* stack */ 988 addi r1,r1,THREAD_SIZE-STACK_FRAME_MIN_SIZE 989 li r0,0 990 stw r0,0(r1) 991 992 /* ptr to current thread */ 993 addi r4,r2,THREAD /* address of our thread_struct */ 994 mtspr SPRN_SPRG_THREAD,r4 995 996 /* Setup the defaults for TLB entries */ 997 li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l 998 mtspr SPRN_MAS4,r4 999 1000 /* Jump to start_secondary */ 1001 lis r4,MSR_KERNEL@h 1002 ori r4,r4,MSR_KERNEL@l 1003 lis r3,start_secondary@h 1004 ori r3,r3,start_secondary@l 1005 mtspr SPRN_SRR0,r3 1006 mtspr SPRN_SRR1,r4 1007 sync 1008 rfi 1009 sync 1010 1011 .globl __secondary_hold_acknowledge 1012__secondary_hold_acknowledge: 1013 .long -1 1014#endif 1015 1016/* 1017 * Create a 64M tlb by address and entry 1018 * r3 - entry 1019 * r4 - virtual address 1020 * r5/r6 - physical address 1021 */ 1022_GLOBAL(create_kaslr_tlb_entry) 1023 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ 1024 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */ 1025 mtspr SPRN_MAS0,r7 /* Write MAS0 */ 1026 1027 lis r3,(MAS1_VALID|MAS1_IPROT)@h 1028 ori r3,r3,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l 1029 mtspr SPRN_MAS1,r3 /* Write MAS1 */ 1030 1031 lis r3,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@h 1032 ori r3,r3,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@l 1033 and r3,r3,r4 1034 ori r3,r3,MAS2_M_IF_NEEDED@l 1035 mtspr SPRN_MAS2,r3 /* Write MAS2(EPN) */ 1036 1037#ifdef CONFIG_PHYS_64BIT 1038 ori r8,r6,(MAS3_SW|MAS3_SR|MAS3_SX) 1039 mtspr SPRN_MAS3,r8 /* Write MAS3(RPN) */ 1040 mtspr SPRN_MAS7,r5 1041#else 1042 ori r8,r5,(MAS3_SW|MAS3_SR|MAS3_SX) 1043 mtspr SPRN_MAS3,r8 /* Write MAS3(RPN) */ 1044#endif 1045 1046 tlbwe /* Write TLB */ 1047 isync 1048 sync 1049 blr 1050 1051/* 1052 * Return to the start of the relocated kernel and run again 1053 * r3 - virtual address of fdt 1054 * r4 - entry of the kernel 1055 */ 1056_GLOBAL(reloc_kernel_entry) 1057 mfmsr r7 1058 rlwinm r7, r7, 0, ~(MSR_IS | MSR_DS) 1059 1060 mtspr SPRN_SRR0,r4 1061 mtspr SPRN_SRR1,r7 1062 rfi 1063 1064/* 1065 * Create a tlb entry with the same effective and physical address as 1066 * the tlb entry used by the current running code. But set the TS to 1. 1067 * Then switch to the address space 1. It will return with the r3 set to 1068 * the ESEL of the new created tlb. 1069 */ 1070_GLOBAL(switch_to_as1) 1071 mflr r5 1072 1073 /* Find a entry not used */ 1074 mfspr r3,SPRN_TLB1CFG 1075 andi. r3,r3,0xfff 1076 mfspr r4,SPRN_PID 1077 rlwinm r4,r4,16,0x3fff0000 /* turn PID into MAS6[SPID] */ 1078 mtspr SPRN_MAS6,r4 10791: lis r4,0x1000 /* Set MAS0(TLBSEL) = 1 */ 1080 addi r3,r3,-1 1081 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ 1082 mtspr SPRN_MAS0,r4 1083 tlbre 1084 mfspr r4,SPRN_MAS1 1085 andis. r4,r4,MAS1_VALID@h 1086 bne 1b 1087 1088 /* Get the tlb entry used by the current running code */ 1089 bcl 20,31,$+4 10900: mflr r4 1091 tlbsx 0,r4 1092 1093 mfspr r4,SPRN_MAS1 1094 ori r4,r4,MAS1_TS /* Set the TS = 1 */ 1095 mtspr SPRN_MAS1,r4 1096 1097 mfspr r4,SPRN_MAS0 1098 rlwinm r4,r4,0,~MAS0_ESEL_MASK 1099 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ 1100 mtspr SPRN_MAS0,r4 1101 tlbwe 1102 isync 1103 sync 1104 1105 mfmsr r4 1106 ori r4,r4,MSR_IS | MSR_DS 1107 mtspr SPRN_SRR0,r5 1108 mtspr SPRN_SRR1,r4 1109 sync 1110 rfi 1111 1112/* 1113 * Restore to the address space 0 and also invalidate the tlb entry created 1114 * by switch_to_as1. 1115 * r3 - the tlb entry which should be invalidated 1116 * r4 - __pa(PAGE_OFFSET in AS1) - __pa(PAGE_OFFSET in AS0) 1117 * r5 - device tree virtual address. If r4 is 0, r5 is ignored. 1118 * r6 - boot cpu 1119*/ 1120_GLOBAL(restore_to_as0) 1121 mflr r0 1122 1123 bcl 20,31,$+4 11240: mflr r9 1125 addi r9,r9,1f - 0b 1126 1127 /* 1128 * We may map the PAGE_OFFSET in AS0 to a different physical address, 1129 * so we need calculate the right jump and device tree address based 1130 * on the offset passed by r4. 1131 */ 1132 add r9,r9,r4 1133 add r5,r5,r4 1134 add r0,r0,r4 1135 11362: mfmsr r7 1137 li r8,(MSR_IS | MSR_DS) 1138 andc r7,r7,r8 1139 1140 mtspr SPRN_SRR0,r9 1141 mtspr SPRN_SRR1,r7 1142 sync 1143 rfi 1144 1145 /* Invalidate the temporary tlb entry for AS1 */ 11461: lis r9,0x1000 /* Set MAS0(TLBSEL) = 1 */ 1147 rlwimi r9,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ 1148 mtspr SPRN_MAS0,r9 1149 tlbre 1150 mfspr r9,SPRN_MAS1 1151 rlwinm r9,r9,0,2,31 /* Clear MAS1 Valid and IPPROT */ 1152 mtspr SPRN_MAS1,r9 1153 tlbwe 1154 isync 1155 1156 cmpwi r4,0 1157 cmpwi cr1,r6,0 1158 cror eq,4*cr1+eq,eq 1159 bne 3f /* offset != 0 && is_boot_cpu */ 1160 mtlr r0 1161 blr 1162 1163 /* 1164 * The PAGE_OFFSET will map to a different physical address, 1165 * jump to _start to do another relocation again. 1166 */ 11673: mr r3,r5 1168 bl _start 1169