1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/handle_exit.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #include <linux/kvm.h> 12 #include <linux/kvm_host.h> 13 #include <linux/ubsan.h> 14 15 #include <asm/esr.h> 16 #include <asm/exception.h> 17 #include <asm/kvm_asm.h> 18 #include <asm/kvm_emulate.h> 19 #include <asm/kvm_mmu.h> 20 #include <asm/kvm_nested.h> 21 #include <asm/debug-monitors.h> 22 #include <asm/stacktrace/nvhe.h> 23 #include <asm/traps.h> 24 25 #include <kvm/arm_hypercalls.h> 26 27 #define CREATE_TRACE_POINTS 28 #include "trace_handle_exit.h" 29 30 typedef int (*exit_handle_fn)(struct kvm_vcpu *); 31 32 static void kvm_handle_guest_serror(struct kvm_vcpu *vcpu, u64 esr) 33 { 34 if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(NULL, esr)) 35 kvm_inject_vabt(vcpu); 36 } 37 38 static int handle_hvc(struct kvm_vcpu *vcpu) 39 { 40 trace_kvm_hvc_arm64(*vcpu_pc(vcpu), vcpu_get_reg(vcpu, 0), 41 kvm_vcpu_hvc_get_imm(vcpu)); 42 vcpu->stat.hvc_exit_stat++; 43 44 /* Forward hvc instructions to the virtual EL2 if the guest has EL2. */ 45 if (vcpu_has_nv(vcpu)) { 46 if (vcpu_read_sys_reg(vcpu, HCR_EL2) & HCR_HCD) 47 kvm_inject_undefined(vcpu); 48 else 49 kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu)); 50 51 return 1; 52 } 53 54 return kvm_smccc_call_handler(vcpu); 55 } 56 57 static int handle_smc(struct kvm_vcpu *vcpu) 58 { 59 /* 60 * Forward this trapped smc instruction to the virtual EL2 if 61 * the guest has asked for it. 62 */ 63 if (forward_smc_trap(vcpu)) 64 return 1; 65 66 /* 67 * "If an SMC instruction executed at Non-secure EL1 is 68 * trapped to EL2 because HCR_EL2.TSC is 1, the exception is a 69 * Trap exception, not a Secure Monitor Call exception [...]" 70 * 71 * We need to advance the PC after the trap, as it would 72 * otherwise return to the same address. Furthermore, pre-incrementing 73 * the PC before potentially exiting to userspace maintains the same 74 * abstraction for both SMCs and HVCs. 75 */ 76 kvm_incr_pc(vcpu); 77 78 /* 79 * SMCs with a nonzero immediate are reserved according to DEN0028E 2.9 80 * "SMC and HVC immediate value". 81 */ 82 if (kvm_vcpu_hvc_get_imm(vcpu)) { 83 vcpu_set_reg(vcpu, 0, ~0UL); 84 return 1; 85 } 86 87 /* 88 * If imm is zero then it is likely an SMCCC call. 89 * 90 * Note that on ARMv8.3, even if EL3 is not implemented, SMC executed 91 * at Non-secure EL1 is trapped to EL2 if HCR_EL2.TSC==1, rather than 92 * being treated as UNDEFINED. 93 */ 94 return kvm_smccc_call_handler(vcpu); 95 } 96 97 /* 98 * This handles the cases where the system does not support FP/ASIMD or when 99 * we are running nested virtualization and the guest hypervisor is trapping 100 * FP/ASIMD accesses by its guest guest. 101 * 102 * All other handling of guest vs. host FP/ASIMD register state is handled in 103 * fixup_guest_exit(). 104 */ 105 static int kvm_handle_fpasimd(struct kvm_vcpu *vcpu) 106 { 107 if (guest_hyp_fpsimd_traps_enabled(vcpu)) 108 return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu)); 109 110 /* This is the case when the system doesn't support FP/ASIMD. */ 111 kvm_inject_undefined(vcpu); 112 return 1; 113 } 114 115 /** 116 * kvm_handle_wfx - handle a wait-for-interrupts or wait-for-event 117 * instruction executed by a guest 118 * 119 * @vcpu: the vcpu pointer 120 * 121 * WFE[T]: Yield the CPU and come back to this vcpu when the scheduler 122 * decides to. 123 * WFI: Simply call kvm_vcpu_halt(), which will halt execution of 124 * world-switches and schedule other host processes until there is an 125 * incoming IRQ or FIQ to the VM. 126 * WFIT: Same as WFI, with a timed wakeup implemented as a background timer 127 * 128 * WF{I,E}T can immediately return if the deadline has already expired. 129 */ 130 static int kvm_handle_wfx(struct kvm_vcpu *vcpu) 131 { 132 u64 esr = kvm_vcpu_get_esr(vcpu); 133 bool is_wfe = !!(esr & ESR_ELx_WFx_ISS_WFE); 134 135 if (guest_hyp_wfx_traps_enabled(vcpu)) 136 return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu)); 137 138 if (is_wfe) { 139 trace_kvm_wfx_arm64(*vcpu_pc(vcpu), true); 140 vcpu->stat.wfe_exit_stat++; 141 } else { 142 trace_kvm_wfx_arm64(*vcpu_pc(vcpu), false); 143 vcpu->stat.wfi_exit_stat++; 144 } 145 146 if (esr & ESR_ELx_WFx_ISS_WFxT) { 147 if (esr & ESR_ELx_WFx_ISS_RV) { 148 u64 val, now; 149 150 now = kvm_arm_timer_get_reg(vcpu, KVM_REG_ARM_TIMER_CNT); 151 val = vcpu_get_reg(vcpu, kvm_vcpu_sys_get_rt(vcpu)); 152 153 if (now >= val) 154 goto out; 155 } else { 156 /* Treat WFxT as WFx if RN is invalid */ 157 esr &= ~ESR_ELx_WFx_ISS_WFxT; 158 } 159 } 160 161 if (esr & ESR_ELx_WFx_ISS_WFE) { 162 kvm_vcpu_on_spin(vcpu, vcpu_mode_priv(vcpu)); 163 } else { 164 if (esr & ESR_ELx_WFx_ISS_WFxT) 165 vcpu_set_flag(vcpu, IN_WFIT); 166 167 kvm_vcpu_wfi(vcpu); 168 } 169 out: 170 kvm_incr_pc(vcpu); 171 172 return 1; 173 } 174 175 /** 176 * kvm_handle_guest_debug - handle a debug exception instruction 177 * 178 * @vcpu: the vcpu pointer 179 * 180 * We route all debug exceptions through the same handler. If both the 181 * guest and host are using the same debug facilities it will be up to 182 * userspace to re-inject the correct exception for guest delivery. 183 * 184 * @return: 0 (while setting vcpu->run->exit_reason) 185 */ 186 static int kvm_handle_guest_debug(struct kvm_vcpu *vcpu) 187 { 188 struct kvm_run *run = vcpu->run; 189 u64 esr = kvm_vcpu_get_esr(vcpu); 190 191 if (!vcpu->guest_debug && forward_debug_exception(vcpu)) 192 return 1; 193 194 run->exit_reason = KVM_EXIT_DEBUG; 195 run->debug.arch.hsr = lower_32_bits(esr); 196 run->debug.arch.hsr_high = upper_32_bits(esr); 197 run->flags = KVM_DEBUG_ARCH_HSR_HIGH_VALID; 198 199 switch (ESR_ELx_EC(esr)) { 200 case ESR_ELx_EC_WATCHPT_LOW: 201 run->debug.arch.far = vcpu->arch.fault.far_el2; 202 break; 203 case ESR_ELx_EC_SOFTSTP_LOW: 204 *vcpu_cpsr(vcpu) |= DBG_SPSR_SS; 205 break; 206 } 207 208 return 0; 209 } 210 211 static int kvm_handle_unknown_ec(struct kvm_vcpu *vcpu) 212 { 213 u64 esr = kvm_vcpu_get_esr(vcpu); 214 215 kvm_pr_unimpl("Unknown exception class: esr: %#016llx -- %s\n", 216 esr, esr_get_class_string(esr)); 217 218 kvm_inject_undefined(vcpu); 219 return 1; 220 } 221 222 /* 223 * Guest access to SVE registers should be routed to this handler only 224 * when the system doesn't support SVE. 225 */ 226 static int handle_sve(struct kvm_vcpu *vcpu) 227 { 228 if (guest_hyp_sve_traps_enabled(vcpu)) 229 return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu)); 230 231 kvm_inject_undefined(vcpu); 232 return 1; 233 } 234 235 /* 236 * Two possibilities to handle a trapping ptrauth instruction: 237 * 238 * - Guest usage of a ptrauth instruction (which the guest EL1 did not 239 * turn into a NOP). If we get here, it is because we didn't enable 240 * ptrauth for the guest. This results in an UNDEF, as it isn't 241 * supposed to use ptrauth without being told it could. 242 * 243 * - Running an L2 NV guest while L1 has left HCR_EL2.API==0, and for 244 * which we reinject the exception into L1. 245 * 246 * Anything else is an emulation bug (hence the WARN_ON + UNDEF). 247 */ 248 static int kvm_handle_ptrauth(struct kvm_vcpu *vcpu) 249 { 250 if (!vcpu_has_ptrauth(vcpu)) { 251 kvm_inject_undefined(vcpu); 252 return 1; 253 } 254 255 if (vcpu_has_nv(vcpu) && !is_hyp_ctxt(vcpu)) { 256 kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu)); 257 return 1; 258 } 259 260 /* Really shouldn't be here! */ 261 WARN_ON_ONCE(1); 262 kvm_inject_undefined(vcpu); 263 return 1; 264 } 265 266 static int kvm_handle_eret(struct kvm_vcpu *vcpu) 267 { 268 if (esr_iss_is_eretax(kvm_vcpu_get_esr(vcpu)) && 269 !vcpu_has_ptrauth(vcpu)) 270 return kvm_handle_ptrauth(vcpu); 271 272 /* 273 * If we got here, two possibilities: 274 * 275 * - the guest is in EL2, and we need to fully emulate ERET 276 * 277 * - the guest is in EL1, and we need to reinject the 278 * exception into the L1 hypervisor. 279 * 280 * If KVM ever traps ERET for its own use, we'll have to 281 * revisit this. 282 */ 283 if (is_hyp_ctxt(vcpu)) 284 kvm_emulate_nested_eret(vcpu); 285 else 286 kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu)); 287 288 return 1; 289 } 290 291 static int handle_svc(struct kvm_vcpu *vcpu) 292 { 293 /* 294 * So far, SVC traps only for NV via HFGITR_EL2. A SVC from a 295 * 32bit guest would be caught by vpcu_mode_is_bad_32bit(), so 296 * we should only have to deal with a 64 bit exception. 297 */ 298 kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu)); 299 return 1; 300 } 301 302 static int kvm_handle_gcs(struct kvm_vcpu *vcpu) 303 { 304 /* We don't expect GCS, so treat it with contempt */ 305 if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, GCS, IMP)) 306 WARN_ON_ONCE(1); 307 308 kvm_inject_undefined(vcpu); 309 return 1; 310 } 311 312 static int handle_other(struct kvm_vcpu *vcpu) 313 { 314 bool is_l2 = vcpu_has_nv(vcpu) && !is_hyp_ctxt(vcpu); 315 u64 hcrx = __vcpu_sys_reg(vcpu, HCRX_EL2); 316 u64 esr = kvm_vcpu_get_esr(vcpu); 317 u64 iss = ESR_ELx_ISS(esr); 318 struct kvm *kvm = vcpu->kvm; 319 bool allowed, fwd = false; 320 321 /* 322 * We only trap for two reasons: 323 * 324 * - the feature is disabled, and the only outcome is to 325 * generate an UNDEF. 326 * 327 * - the feature is enabled, but a NV guest wants to trap the 328 * feature used by its L2 guest. We forward the exception in 329 * this case. 330 * 331 * What we don't expect is to end-up here if the guest is 332 * expected be be able to directly use the feature, hence the 333 * WARN_ON below. 334 */ 335 switch (iss) { 336 case ESR_ELx_ISS_OTHER_ST64BV: 337 allowed = kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64_V); 338 if (is_l2) 339 fwd = !(hcrx & HCRX_EL2_EnASR); 340 break; 341 case ESR_ELx_ISS_OTHER_ST64BV0: 342 allowed = kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64_ACCDATA); 343 if (is_l2) 344 fwd = !(hcrx & HCRX_EL2_EnAS0); 345 break; 346 case ESR_ELx_ISS_OTHER_LDST64B: 347 allowed = kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64); 348 if (is_l2) 349 fwd = !(hcrx & HCRX_EL2_EnALS); 350 break; 351 case ESR_ELx_ISS_OTHER_TSBCSYNC: 352 allowed = kvm_has_feat(kvm, ID_AA64DFR0_EL1, TraceBuffer, TRBE_V1P1); 353 if (is_l2) 354 fwd = (__vcpu_sys_reg(vcpu, HFGITR2_EL2) & HFGITR2_EL2_TSBCSYNC); 355 break; 356 case ESR_ELx_ISS_OTHER_PSBCSYNC: 357 allowed = kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMSVer, V1P5); 358 if (is_l2) 359 fwd = (__vcpu_sys_reg(vcpu, HFGITR_EL2) & HFGITR_EL2_PSBCSYNC); 360 break; 361 default: 362 /* Clearly, we're missing something. */ 363 WARN_ON_ONCE(1); 364 allowed = false; 365 } 366 367 WARN_ON_ONCE(allowed && !fwd); 368 369 if (allowed && fwd) 370 kvm_inject_nested_sync(vcpu, esr); 371 else 372 kvm_inject_undefined(vcpu); 373 374 return 1; 375 } 376 377 static exit_handle_fn arm_exit_handlers[] = { 378 [0 ... ESR_ELx_EC_MAX] = kvm_handle_unknown_ec, 379 [ESR_ELx_EC_WFx] = kvm_handle_wfx, 380 [ESR_ELx_EC_CP15_32] = kvm_handle_cp15_32, 381 [ESR_ELx_EC_CP15_64] = kvm_handle_cp15_64, 382 [ESR_ELx_EC_CP14_MR] = kvm_handle_cp14_32, 383 [ESR_ELx_EC_CP14_LS] = kvm_handle_cp14_load_store, 384 [ESR_ELx_EC_CP10_ID] = kvm_handle_cp10_id, 385 [ESR_ELx_EC_CP14_64] = kvm_handle_cp14_64, 386 [ESR_ELx_EC_OTHER] = handle_other, 387 [ESR_ELx_EC_HVC32] = handle_hvc, 388 [ESR_ELx_EC_SMC32] = handle_smc, 389 [ESR_ELx_EC_HVC64] = handle_hvc, 390 [ESR_ELx_EC_SMC64] = handle_smc, 391 [ESR_ELx_EC_SVC64] = handle_svc, 392 [ESR_ELx_EC_SYS64] = kvm_handle_sys_reg, 393 [ESR_ELx_EC_SVE] = handle_sve, 394 [ESR_ELx_EC_ERET] = kvm_handle_eret, 395 [ESR_ELx_EC_IABT_LOW] = kvm_handle_guest_abort, 396 [ESR_ELx_EC_DABT_LOW] = kvm_handle_guest_abort, 397 [ESR_ELx_EC_DABT_CUR] = kvm_handle_vncr_abort, 398 [ESR_ELx_EC_SOFTSTP_LOW]= kvm_handle_guest_debug, 399 [ESR_ELx_EC_WATCHPT_LOW]= kvm_handle_guest_debug, 400 [ESR_ELx_EC_BREAKPT_LOW]= kvm_handle_guest_debug, 401 [ESR_ELx_EC_BKPT32] = kvm_handle_guest_debug, 402 [ESR_ELx_EC_BRK64] = kvm_handle_guest_debug, 403 [ESR_ELx_EC_FP_ASIMD] = kvm_handle_fpasimd, 404 [ESR_ELx_EC_PAC] = kvm_handle_ptrauth, 405 [ESR_ELx_EC_GCS] = kvm_handle_gcs, 406 }; 407 408 static exit_handle_fn kvm_get_exit_handler(struct kvm_vcpu *vcpu) 409 { 410 u64 esr = kvm_vcpu_get_esr(vcpu); 411 u8 esr_ec = ESR_ELx_EC(esr); 412 413 return arm_exit_handlers[esr_ec]; 414 } 415 416 /* 417 * We may be single-stepping an emulated instruction. If the emulation 418 * has been completed in the kernel, we can return to userspace with a 419 * KVM_EXIT_DEBUG, otherwise userspace needs to complete its 420 * emulation first. 421 */ 422 static int handle_trap_exceptions(struct kvm_vcpu *vcpu) 423 { 424 int handled; 425 426 /* 427 * See ARM ARM B1.14.1: "Hyp traps on instructions 428 * that fail their condition code check" 429 */ 430 if (!kvm_condition_valid(vcpu)) { 431 kvm_incr_pc(vcpu); 432 handled = 1; 433 } else { 434 exit_handle_fn exit_handler; 435 436 exit_handler = kvm_get_exit_handler(vcpu); 437 handled = exit_handler(vcpu); 438 } 439 440 return handled; 441 } 442 443 /* 444 * Return > 0 to return to guest, < 0 on error, 0 (and set exit_reason) on 445 * proper exit to userspace. 446 */ 447 int handle_exit(struct kvm_vcpu *vcpu, int exception_index) 448 { 449 struct kvm_run *run = vcpu->run; 450 451 if (ARM_SERROR_PENDING(exception_index)) { 452 /* 453 * The SError is handled by handle_exit_early(). If the guest 454 * survives it will re-execute the original instruction. 455 */ 456 return 1; 457 } 458 459 exception_index = ARM_EXCEPTION_CODE(exception_index); 460 461 switch (exception_index) { 462 case ARM_EXCEPTION_IRQ: 463 return 1; 464 case ARM_EXCEPTION_EL1_SERROR: 465 return 1; 466 case ARM_EXCEPTION_TRAP: 467 return handle_trap_exceptions(vcpu); 468 case ARM_EXCEPTION_HYP_GONE: 469 /* 470 * EL2 has been reset to the hyp-stub. This happens when a guest 471 * is pre-emptied by kvm_reboot()'s shutdown call. 472 */ 473 run->exit_reason = KVM_EXIT_FAIL_ENTRY; 474 return 0; 475 case ARM_EXCEPTION_IL: 476 /* 477 * We attempted an illegal exception return. Guest state must 478 * have been corrupted somehow. Give up. 479 */ 480 run->exit_reason = KVM_EXIT_FAIL_ENTRY; 481 return -EINVAL; 482 default: 483 kvm_pr_unimpl("Unsupported exception type: %d", 484 exception_index); 485 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 486 return 0; 487 } 488 } 489 490 /* For exit types that need handling before we can be preempted */ 491 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index) 492 { 493 if (ARM_SERROR_PENDING(exception_index)) { 494 if (this_cpu_has_cap(ARM64_HAS_RAS_EXTN)) { 495 u64 disr = kvm_vcpu_get_disr(vcpu); 496 497 kvm_handle_guest_serror(vcpu, disr_to_esr(disr)); 498 } else { 499 kvm_inject_vabt(vcpu); 500 } 501 502 return; 503 } 504 505 exception_index = ARM_EXCEPTION_CODE(exception_index); 506 507 if (exception_index == ARM_EXCEPTION_EL1_SERROR) 508 kvm_handle_guest_serror(vcpu, kvm_vcpu_get_esr(vcpu)); 509 } 510 511 static void print_nvhe_hyp_panic(const char *name, u64 panic_addr) 512 { 513 kvm_err("nVHE hyp %s at: [<%016llx>] %pB!\n", name, panic_addr, 514 (void *)(panic_addr + kaslr_offset())); 515 } 516 517 static void kvm_nvhe_report_cfi_failure(u64 panic_addr) 518 { 519 print_nvhe_hyp_panic("CFI failure", panic_addr); 520 521 if (IS_ENABLED(CONFIG_CFI_PERMISSIVE)) 522 kvm_err(" (CONFIG_CFI_PERMISSIVE ignored for hyp failures)\n"); 523 } 524 525 void __noreturn __cold nvhe_hyp_panic_handler(u64 esr, u64 spsr, 526 u64 elr_virt, u64 elr_phys, 527 u64 par, uintptr_t vcpu, 528 u64 far, u64 hpfar) { 529 u64 elr_in_kimg = __phys_to_kimg(elr_phys); 530 u64 hyp_offset = elr_in_kimg - kaslr_offset() - elr_virt; 531 u64 mode = spsr & PSR_MODE_MASK; 532 u64 panic_addr = elr_virt + hyp_offset; 533 534 if (mode != PSR_MODE_EL2t && mode != PSR_MODE_EL2h) { 535 kvm_err("Invalid host exception to nVHE hyp!\n"); 536 } else if (ESR_ELx_EC(esr) == ESR_ELx_EC_BRK64 && 537 esr_brk_comment(esr) == BUG_BRK_IMM) { 538 const char *file = NULL; 539 unsigned int line = 0; 540 541 /* All hyp bugs, including warnings, are treated as fatal. */ 542 if (!is_protected_kvm_enabled() || 543 IS_ENABLED(CONFIG_NVHE_EL2_DEBUG)) { 544 struct bug_entry *bug = find_bug(elr_in_kimg); 545 546 if (bug) 547 bug_get_file_line(bug, &file, &line); 548 } 549 550 if (file) 551 kvm_err("nVHE hyp BUG at: %s:%u!\n", file, line); 552 else 553 print_nvhe_hyp_panic("BUG", panic_addr); 554 } else if (IS_ENABLED(CONFIG_CFI_CLANG) && esr_is_cfi_brk(esr)) { 555 kvm_nvhe_report_cfi_failure(panic_addr); 556 } else if (IS_ENABLED(CONFIG_UBSAN_KVM_EL2) && 557 ESR_ELx_EC(esr) == ESR_ELx_EC_BRK64 && 558 esr_is_ubsan_brk(esr)) { 559 print_nvhe_hyp_panic(report_ubsan_failure(esr & UBSAN_BRK_MASK), 560 panic_addr); 561 } else { 562 print_nvhe_hyp_panic("panic", panic_addr); 563 } 564 565 /* Dump the nVHE hypervisor backtrace */ 566 kvm_nvhe_dump_backtrace(hyp_offset); 567 568 /* 569 * Hyp has panicked and we're going to handle that by panicking the 570 * kernel. The kernel offset will be revealed in the panic so we're 571 * also safe to reveal the hyp offset as a debugging aid for translating 572 * hyp VAs to vmlinux addresses. 573 */ 574 kvm_err("Hyp Offset: 0x%llx\n", hyp_offset); 575 576 panic("HYP panic:\nPS:%08llx PC:%016llx ESR:%016llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%016lx\n", 577 spsr, elr_virt, esr, far, hpfar, par, vcpu); 578 } 579