1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2025 Google LLC 4 * Author: Marc Zyngier <maz@kernel.org> 5 */ 6 7 #include <linux/kvm_host.h> 8 #include <asm/sysreg.h> 9 10 struct reg_bits_to_feat_map { 11 u64 bits; 12 13 #define NEVER_FGU BIT(0) /* Can trap, but never UNDEF */ 14 #define CALL_FUNC BIT(1) /* Needs to evaluate tons of crap */ 15 #define FIXED_VALUE BIT(2) /* RAZ/WI or RAO/WI in KVM */ 16 unsigned long flags; 17 18 union { 19 struct { 20 u8 regidx; 21 u8 shift; 22 u8 width; 23 bool sign; 24 s8 lo_lim; 25 }; 26 bool (*match)(struct kvm *); 27 bool (*fval)(struct kvm *, u64 *); 28 }; 29 }; 30 31 #define __NEEDS_FEAT_3(m, f, id, fld, lim) \ 32 { \ 33 .bits = (m), \ 34 .flags = (f), \ 35 .regidx = IDREG_IDX(SYS_ ## id), \ 36 .shift = id ##_## fld ## _SHIFT, \ 37 .width = id ##_## fld ## _WIDTH, \ 38 .sign = id ##_## fld ## _SIGNED, \ 39 .lo_lim = id ##_## fld ##_## lim \ 40 } 41 42 #define __NEEDS_FEAT_2(m, f, fun, dummy) \ 43 { \ 44 .bits = (m), \ 45 .flags = (f) | CALL_FUNC, \ 46 .fval = (fun), \ 47 } 48 49 #define __NEEDS_FEAT_1(m, f, fun) \ 50 { \ 51 .bits = (m), \ 52 .flags = (f) | CALL_FUNC, \ 53 .match = (fun), \ 54 } 55 56 #define NEEDS_FEAT_FLAG(m, f, ...) \ 57 CONCATENATE(__NEEDS_FEAT_, COUNT_ARGS(__VA_ARGS__))(m, f, __VA_ARGS__) 58 59 #define NEEDS_FEAT_FIXED(m, ...) \ 60 NEEDS_FEAT_FLAG(m, FIXED_VALUE, __VA_ARGS__, 0) 61 62 #define NEEDS_FEAT(m, ...) NEEDS_FEAT_FLAG(m, 0, __VA_ARGS__) 63 64 #define FEAT_SPE ID_AA64DFR0_EL1, PMSVer, IMP 65 #define FEAT_SPE_FnE ID_AA64DFR0_EL1, PMSVer, V1P2 66 #define FEAT_BRBE ID_AA64DFR0_EL1, BRBE, IMP 67 #define FEAT_TRC_SR ID_AA64DFR0_EL1, TraceVer, IMP 68 #define FEAT_PMUv3 ID_AA64DFR0_EL1, PMUVer, IMP 69 #define FEAT_PMUv3p9 ID_AA64DFR0_EL1, PMUVer, V3P9 70 #define FEAT_TRBE ID_AA64DFR0_EL1, TraceBuffer, IMP 71 #define FEAT_TRBEv1p1 ID_AA64DFR0_EL1, TraceBuffer, TRBE_V1P1 72 #define FEAT_DoubleLock ID_AA64DFR0_EL1, DoubleLock, IMP 73 #define FEAT_TRF ID_AA64DFR0_EL1, TraceFilt, IMP 74 #define FEAT_AA32EL0 ID_AA64PFR0_EL1, EL0, AARCH32 75 #define FEAT_AA32EL1 ID_AA64PFR0_EL1, EL1, AARCH32 76 #define FEAT_AA64EL1 ID_AA64PFR0_EL1, EL1, IMP 77 #define FEAT_AA64EL3 ID_AA64PFR0_EL1, EL3, IMP 78 #define FEAT_AIE ID_AA64MMFR3_EL1, AIE, IMP 79 #define FEAT_S2POE ID_AA64MMFR3_EL1, S2POE, IMP 80 #define FEAT_S1POE ID_AA64MMFR3_EL1, S1POE, IMP 81 #define FEAT_S1PIE ID_AA64MMFR3_EL1, S1PIE, IMP 82 #define FEAT_THE ID_AA64PFR1_EL1, THE, IMP 83 #define FEAT_SME ID_AA64PFR1_EL1, SME, IMP 84 #define FEAT_GCS ID_AA64PFR1_EL1, GCS, IMP 85 #define FEAT_LS64 ID_AA64ISAR1_EL1, LS64, LS64 86 #define FEAT_LS64_V ID_AA64ISAR1_EL1, LS64, LS64_V 87 #define FEAT_LS64_ACCDATA ID_AA64ISAR1_EL1, LS64, LS64_ACCDATA 88 #define FEAT_RAS ID_AA64PFR0_EL1, RAS, IMP 89 #define FEAT_RASv2 ID_AA64PFR0_EL1, RAS, V2 90 #define FEAT_GICv3 ID_AA64PFR0_EL1, GIC, IMP 91 #define FEAT_LOR ID_AA64MMFR1_EL1, LO, IMP 92 #define FEAT_SPEv1p4 ID_AA64DFR0_EL1, PMSVer, V1P4 93 #define FEAT_SPEv1p5 ID_AA64DFR0_EL1, PMSVer, V1P5 94 #define FEAT_ATS1A ID_AA64ISAR2_EL1, ATS1A, IMP 95 #define FEAT_SPECRES2 ID_AA64ISAR1_EL1, SPECRES, COSP_RCTX 96 #define FEAT_SPECRES ID_AA64ISAR1_EL1, SPECRES, IMP 97 #define FEAT_TLBIRANGE ID_AA64ISAR0_EL1, TLB, RANGE 98 #define FEAT_TLBIOS ID_AA64ISAR0_EL1, TLB, OS 99 #define FEAT_PAN2 ID_AA64MMFR1_EL1, PAN, PAN2 100 #define FEAT_DPB2 ID_AA64ISAR1_EL1, DPB, DPB2 101 #define FEAT_AMUv1 ID_AA64PFR0_EL1, AMU, IMP 102 #define FEAT_AMUv1p1 ID_AA64PFR0_EL1, AMU, V1P1 103 #define FEAT_CMOW ID_AA64MMFR1_EL1, CMOW, IMP 104 #define FEAT_D128 ID_AA64MMFR3_EL1, D128, IMP 105 #define FEAT_DoubleFault2 ID_AA64PFR1_EL1, DF2, IMP 106 #define FEAT_FPMR ID_AA64PFR2_EL1, FPMR, IMP 107 #define FEAT_MOPS ID_AA64ISAR2_EL1, MOPS, IMP 108 #define FEAT_NMI ID_AA64PFR1_EL1, NMI, IMP 109 #define FEAT_SCTLR2 ID_AA64MMFR3_EL1, SCTLRX, IMP 110 #define FEAT_SYSREG128 ID_AA64ISAR2_EL1, SYSREG_128, IMP 111 #define FEAT_TCR2 ID_AA64MMFR3_EL1, TCRX, IMP 112 #define FEAT_XS ID_AA64ISAR1_EL1, XS, IMP 113 #define FEAT_EVT ID_AA64MMFR2_EL1, EVT, IMP 114 #define FEAT_EVT_TTLBxS ID_AA64MMFR2_EL1, EVT, TTLBxS 115 #define FEAT_MTE2 ID_AA64PFR1_EL1, MTE, MTE2 116 #define FEAT_RME ID_AA64PFR0_EL1, RME, IMP 117 #define FEAT_MPAM ID_AA64PFR0_EL1, MPAM, 1 118 #define FEAT_S2FWB ID_AA64MMFR2_EL1, FWB, IMP 119 #define FEAT_TME ID_AA64ISAR0_EL1, TME, IMP 120 #define FEAT_TWED ID_AA64MMFR1_EL1, TWED, IMP 121 #define FEAT_E2H0 ID_AA64MMFR4_EL1, E2H0, IMP 122 #define FEAT_SRMASK ID_AA64MMFR4_EL1, SRMASK, IMP 123 #define FEAT_PoPS ID_AA64MMFR4_EL1, PoPS, IMP 124 #define FEAT_PFAR ID_AA64PFR1_EL1, PFAR, IMP 125 #define FEAT_Debugv8p9 ID_AA64DFR0_EL1, PMUVer, V3P9 126 #define FEAT_PMUv3_SS ID_AA64DFR0_EL1, PMSS, IMP 127 #define FEAT_SEBEP ID_AA64DFR0_EL1, SEBEP, IMP 128 #define FEAT_EBEP ID_AA64DFR1_EL1, EBEP, IMP 129 #define FEAT_ITE ID_AA64DFR1_EL1, ITE, IMP 130 #define FEAT_PMUv3_ICNTR ID_AA64DFR1_EL1, PMICNTR, IMP 131 #define FEAT_SPMU ID_AA64DFR1_EL1, SPMU, IMP 132 #define FEAT_SPE_nVM ID_AA64DFR2_EL1, SPE_nVM, IMP 133 #define FEAT_STEP2 ID_AA64DFR2_EL1, STEP, IMP 134 135 static bool not_feat_aa64el3(struct kvm *kvm) 136 { 137 return !kvm_has_feat(kvm, FEAT_AA64EL3); 138 } 139 140 static bool feat_nv2(struct kvm *kvm) 141 { 142 return ((kvm_has_feat(kvm, ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY) && 143 kvm_has_feat_enum(kvm, ID_AA64MMFR2_EL1, NV, NI)) || 144 kvm_has_feat(kvm, ID_AA64MMFR2_EL1, NV, NV2)); 145 } 146 147 static bool feat_nv2_e2h0_ni(struct kvm *kvm) 148 { 149 return feat_nv2(kvm) && !kvm_has_feat(kvm, FEAT_E2H0); 150 } 151 152 static bool feat_rasv1p1(struct kvm *kvm) 153 { 154 return (kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, V1P1) || 155 (kvm_has_feat_enum(kvm, ID_AA64PFR0_EL1, RAS, IMP) && 156 kvm_has_feat(kvm, ID_AA64PFR1_EL1, RAS_frac, RASv1p1))); 157 } 158 159 static bool feat_csv2_2_csv2_1p2(struct kvm *kvm) 160 { 161 return (kvm_has_feat(kvm, ID_AA64PFR0_EL1, CSV2, CSV2_2) || 162 (kvm_has_feat(kvm, ID_AA64PFR1_EL1, CSV2_frac, CSV2_1p2) && 163 kvm_has_feat_enum(kvm, ID_AA64PFR0_EL1, CSV2, IMP))); 164 } 165 166 static bool feat_pauth(struct kvm *kvm) 167 { 168 return kvm_has_pauth(kvm, PAuth); 169 } 170 171 static bool feat_pauth_lr(struct kvm *kvm) 172 { 173 return kvm_has_pauth(kvm, PAuth_LR); 174 } 175 176 static bool feat_aderr(struct kvm *kvm) 177 { 178 return (kvm_has_feat(kvm, ID_AA64MMFR3_EL1, ADERR, FEAT_ADERR) && 179 kvm_has_feat(kvm, ID_AA64MMFR3_EL1, SDERR, FEAT_ADERR)); 180 } 181 182 static bool feat_anerr(struct kvm *kvm) 183 { 184 return (kvm_has_feat(kvm, ID_AA64MMFR3_EL1, ANERR, FEAT_ANERR) && 185 kvm_has_feat(kvm, ID_AA64MMFR3_EL1, SNERR, FEAT_ANERR)); 186 } 187 188 static bool feat_sme_smps(struct kvm *kvm) 189 { 190 /* 191 * Revists this if KVM ever supports SME -- this really should 192 * look at the guest's view of SMIDR_EL1. Funnily enough, this 193 * is not captured in the JSON file, but only as a note in the 194 * ARM ARM. 195 */ 196 return (kvm_has_feat(kvm, FEAT_SME) && 197 (read_sysreg_s(SYS_SMIDR_EL1) & SMIDR_EL1_SMPS)); 198 } 199 200 static bool feat_spe_fds(struct kvm *kvm) 201 { 202 /* 203 * Revists this if KVM ever supports SPE -- this really should 204 * look at the guest's view of PMSIDR_EL1. 205 */ 206 return (kvm_has_feat(kvm, FEAT_SPEv1p4) && 207 (read_sysreg_s(SYS_PMSIDR_EL1) & PMSIDR_EL1_FDS)); 208 } 209 210 static bool feat_trbe_mpam(struct kvm *kvm) 211 { 212 /* 213 * Revists this if KVM ever supports both MPAM and TRBE -- 214 * this really should look at the guest's view of TRBIDR_EL1. 215 */ 216 return (kvm_has_feat(kvm, FEAT_TRBE) && 217 kvm_has_feat(kvm, FEAT_MPAM) && 218 (read_sysreg_s(SYS_TRBIDR_EL1) & TRBIDR_EL1_MPAM)); 219 } 220 221 static bool feat_ebep_pmuv3_ss(struct kvm *kvm) 222 { 223 return kvm_has_feat(kvm, FEAT_EBEP) || kvm_has_feat(kvm, FEAT_PMUv3_SS); 224 } 225 226 static bool compute_hcr_rw(struct kvm *kvm, u64 *bits) 227 { 228 /* This is purely academic: AArch32 and NV are mutually exclusive */ 229 if (bits) { 230 if (kvm_has_feat(kvm, FEAT_AA32EL1)) 231 *bits &= ~HCR_EL2_RW; 232 else 233 *bits |= HCR_EL2_RW; 234 } 235 236 return true; 237 } 238 239 static bool compute_hcr_e2h(struct kvm *kvm, u64 *bits) 240 { 241 if (bits) { 242 if (kvm_has_feat(kvm, FEAT_E2H0)) 243 *bits &= ~HCR_EL2_E2H; 244 else 245 *bits |= HCR_EL2_E2H; 246 } 247 248 return true; 249 } 250 251 static const struct reg_bits_to_feat_map hfgrtr_feat_map[] = { 252 NEEDS_FEAT(HFGRTR_EL2_nAMAIR2_EL1 | 253 HFGRTR_EL2_nMAIR2_EL1, 254 FEAT_AIE), 255 NEEDS_FEAT(HFGRTR_EL2_nS2POR_EL1, FEAT_S2POE), 256 NEEDS_FEAT(HFGRTR_EL2_nPOR_EL1 | 257 HFGRTR_EL2_nPOR_EL0, 258 FEAT_S1POE), 259 NEEDS_FEAT(HFGRTR_EL2_nPIR_EL1 | 260 HFGRTR_EL2_nPIRE0_EL1, 261 FEAT_S1PIE), 262 NEEDS_FEAT(HFGRTR_EL2_nRCWMASK_EL1, FEAT_THE), 263 NEEDS_FEAT(HFGRTR_EL2_nTPIDR2_EL0 | 264 HFGRTR_EL2_nSMPRI_EL1, 265 FEAT_SME), 266 NEEDS_FEAT(HFGRTR_EL2_nGCS_EL1 | 267 HFGRTR_EL2_nGCS_EL0, 268 FEAT_GCS), 269 NEEDS_FEAT(HFGRTR_EL2_nACCDATA_EL1, FEAT_LS64_ACCDATA), 270 NEEDS_FEAT(HFGRTR_EL2_ERXADDR_EL1 | 271 HFGRTR_EL2_ERXMISCn_EL1 | 272 HFGRTR_EL2_ERXSTATUS_EL1 | 273 HFGRTR_EL2_ERXCTLR_EL1 | 274 HFGRTR_EL2_ERXFR_EL1 | 275 HFGRTR_EL2_ERRSELR_EL1 | 276 HFGRTR_EL2_ERRIDR_EL1, 277 FEAT_RAS), 278 NEEDS_FEAT(HFGRTR_EL2_ERXPFGCDN_EL1 | 279 HFGRTR_EL2_ERXPFGCTL_EL1 | 280 HFGRTR_EL2_ERXPFGF_EL1, 281 feat_rasv1p1), 282 NEEDS_FEAT(HFGRTR_EL2_ICC_IGRPENn_EL1, FEAT_GICv3), 283 NEEDS_FEAT(HFGRTR_EL2_SCXTNUM_EL0 | 284 HFGRTR_EL2_SCXTNUM_EL1, 285 feat_csv2_2_csv2_1p2), 286 NEEDS_FEAT(HFGRTR_EL2_LORSA_EL1 | 287 HFGRTR_EL2_LORN_EL1 | 288 HFGRTR_EL2_LORID_EL1 | 289 HFGRTR_EL2_LOREA_EL1 | 290 HFGRTR_EL2_LORC_EL1, 291 FEAT_LOR), 292 NEEDS_FEAT(HFGRTR_EL2_APIBKey | 293 HFGRTR_EL2_APIAKey | 294 HFGRTR_EL2_APGAKey | 295 HFGRTR_EL2_APDBKey | 296 HFGRTR_EL2_APDAKey, 297 feat_pauth), 298 NEEDS_FEAT_FLAG(HFGRTR_EL2_VBAR_EL1 | 299 HFGRTR_EL2_TTBR1_EL1 | 300 HFGRTR_EL2_TTBR0_EL1 | 301 HFGRTR_EL2_TPIDR_EL0 | 302 HFGRTR_EL2_TPIDRRO_EL0 | 303 HFGRTR_EL2_TPIDR_EL1 | 304 HFGRTR_EL2_TCR_EL1 | 305 HFGRTR_EL2_SCTLR_EL1 | 306 HFGRTR_EL2_REVIDR_EL1 | 307 HFGRTR_EL2_PAR_EL1 | 308 HFGRTR_EL2_MPIDR_EL1 | 309 HFGRTR_EL2_MIDR_EL1 | 310 HFGRTR_EL2_MAIR_EL1 | 311 HFGRTR_EL2_ISR_EL1 | 312 HFGRTR_EL2_FAR_EL1 | 313 HFGRTR_EL2_ESR_EL1 | 314 HFGRTR_EL2_DCZID_EL0 | 315 HFGRTR_EL2_CTR_EL0 | 316 HFGRTR_EL2_CSSELR_EL1 | 317 HFGRTR_EL2_CPACR_EL1 | 318 HFGRTR_EL2_CONTEXTIDR_EL1| 319 HFGRTR_EL2_CLIDR_EL1 | 320 HFGRTR_EL2_CCSIDR_EL1 | 321 HFGRTR_EL2_AMAIR_EL1 | 322 HFGRTR_EL2_AIDR_EL1 | 323 HFGRTR_EL2_AFSR1_EL1 | 324 HFGRTR_EL2_AFSR0_EL1, 325 NEVER_FGU, FEAT_AA64EL1), 326 }; 327 328 static const struct reg_bits_to_feat_map hfgwtr_feat_map[] = { 329 NEEDS_FEAT(HFGWTR_EL2_nAMAIR2_EL1 | 330 HFGWTR_EL2_nMAIR2_EL1, 331 FEAT_AIE), 332 NEEDS_FEAT(HFGWTR_EL2_nS2POR_EL1, FEAT_S2POE), 333 NEEDS_FEAT(HFGWTR_EL2_nPOR_EL1 | 334 HFGWTR_EL2_nPOR_EL0, 335 FEAT_S1POE), 336 NEEDS_FEAT(HFGWTR_EL2_nPIR_EL1 | 337 HFGWTR_EL2_nPIRE0_EL1, 338 FEAT_S1PIE), 339 NEEDS_FEAT(HFGWTR_EL2_nRCWMASK_EL1, FEAT_THE), 340 NEEDS_FEAT(HFGWTR_EL2_nTPIDR2_EL0 | 341 HFGWTR_EL2_nSMPRI_EL1, 342 FEAT_SME), 343 NEEDS_FEAT(HFGWTR_EL2_nGCS_EL1 | 344 HFGWTR_EL2_nGCS_EL0, 345 FEAT_GCS), 346 NEEDS_FEAT(HFGWTR_EL2_nACCDATA_EL1, FEAT_LS64_ACCDATA), 347 NEEDS_FEAT(HFGWTR_EL2_ERXADDR_EL1 | 348 HFGWTR_EL2_ERXMISCn_EL1 | 349 HFGWTR_EL2_ERXSTATUS_EL1 | 350 HFGWTR_EL2_ERXCTLR_EL1 | 351 HFGWTR_EL2_ERRSELR_EL1, 352 FEAT_RAS), 353 NEEDS_FEAT(HFGWTR_EL2_ERXPFGCDN_EL1 | 354 HFGWTR_EL2_ERXPFGCTL_EL1, 355 feat_rasv1p1), 356 NEEDS_FEAT(HFGWTR_EL2_ICC_IGRPENn_EL1, FEAT_GICv3), 357 NEEDS_FEAT(HFGWTR_EL2_SCXTNUM_EL0 | 358 HFGWTR_EL2_SCXTNUM_EL1, 359 feat_csv2_2_csv2_1p2), 360 NEEDS_FEAT(HFGWTR_EL2_LORSA_EL1 | 361 HFGWTR_EL2_LORN_EL1 | 362 HFGWTR_EL2_LOREA_EL1 | 363 HFGWTR_EL2_LORC_EL1, 364 FEAT_LOR), 365 NEEDS_FEAT(HFGWTR_EL2_APIBKey | 366 HFGWTR_EL2_APIAKey | 367 HFGWTR_EL2_APGAKey | 368 HFGWTR_EL2_APDBKey | 369 HFGWTR_EL2_APDAKey, 370 feat_pauth), 371 NEEDS_FEAT_FLAG(HFGWTR_EL2_VBAR_EL1 | 372 HFGWTR_EL2_TTBR1_EL1 | 373 HFGWTR_EL2_TTBR0_EL1 | 374 HFGWTR_EL2_TPIDR_EL0 | 375 HFGWTR_EL2_TPIDRRO_EL0 | 376 HFGWTR_EL2_TPIDR_EL1 | 377 HFGWTR_EL2_TCR_EL1 | 378 HFGWTR_EL2_SCTLR_EL1 | 379 HFGWTR_EL2_PAR_EL1 | 380 HFGWTR_EL2_MAIR_EL1 | 381 HFGWTR_EL2_FAR_EL1 | 382 HFGWTR_EL2_ESR_EL1 | 383 HFGWTR_EL2_CSSELR_EL1 | 384 HFGWTR_EL2_CPACR_EL1 | 385 HFGWTR_EL2_CONTEXTIDR_EL1| 386 HFGWTR_EL2_AMAIR_EL1 | 387 HFGWTR_EL2_AFSR1_EL1 | 388 HFGWTR_EL2_AFSR0_EL1, 389 NEVER_FGU, FEAT_AA64EL1), 390 }; 391 392 static const struct reg_bits_to_feat_map hdfgrtr_feat_map[] = { 393 NEEDS_FEAT(HDFGRTR_EL2_PMBIDR_EL1 | 394 HDFGRTR_EL2_PMSLATFR_EL1 | 395 HDFGRTR_EL2_PMSIRR_EL1 | 396 HDFGRTR_EL2_PMSIDR_EL1 | 397 HDFGRTR_EL2_PMSICR_EL1 | 398 HDFGRTR_EL2_PMSFCR_EL1 | 399 HDFGRTR_EL2_PMSEVFR_EL1 | 400 HDFGRTR_EL2_PMSCR_EL1 | 401 HDFGRTR_EL2_PMBSR_EL1 | 402 HDFGRTR_EL2_PMBPTR_EL1 | 403 HDFGRTR_EL2_PMBLIMITR_EL1, 404 FEAT_SPE), 405 NEEDS_FEAT(HDFGRTR_EL2_nPMSNEVFR_EL1, FEAT_SPE_FnE), 406 NEEDS_FEAT(HDFGRTR_EL2_nBRBDATA | 407 HDFGRTR_EL2_nBRBCTL | 408 HDFGRTR_EL2_nBRBIDR, 409 FEAT_BRBE), 410 NEEDS_FEAT(HDFGRTR_EL2_TRCVICTLR | 411 HDFGRTR_EL2_TRCSTATR | 412 HDFGRTR_EL2_TRCSSCSRn | 413 HDFGRTR_EL2_TRCSEQSTR | 414 HDFGRTR_EL2_TRCPRGCTLR | 415 HDFGRTR_EL2_TRCOSLSR | 416 HDFGRTR_EL2_TRCIMSPECn | 417 HDFGRTR_EL2_TRCID | 418 HDFGRTR_EL2_TRCCNTVRn | 419 HDFGRTR_EL2_TRCCLAIM | 420 HDFGRTR_EL2_TRCAUXCTLR | 421 HDFGRTR_EL2_TRCAUTHSTATUS | 422 HDFGRTR_EL2_TRC, 423 FEAT_TRC_SR), 424 NEEDS_FEAT(HDFGRTR_EL2_PMCEIDn_EL0 | 425 HDFGRTR_EL2_PMUSERENR_EL0 | 426 HDFGRTR_EL2_PMMIR_EL1 | 427 HDFGRTR_EL2_PMSELR_EL0 | 428 HDFGRTR_EL2_PMOVS | 429 HDFGRTR_EL2_PMINTEN | 430 HDFGRTR_EL2_PMCNTEN | 431 HDFGRTR_EL2_PMCCNTR_EL0 | 432 HDFGRTR_EL2_PMCCFILTR_EL0 | 433 HDFGRTR_EL2_PMEVTYPERn_EL0 | 434 HDFGRTR_EL2_PMEVCNTRn_EL0, 435 FEAT_PMUv3), 436 NEEDS_FEAT(HDFGRTR_EL2_TRBTRG_EL1 | 437 HDFGRTR_EL2_TRBSR_EL1 | 438 HDFGRTR_EL2_TRBPTR_EL1 | 439 HDFGRTR_EL2_TRBMAR_EL1 | 440 HDFGRTR_EL2_TRBLIMITR_EL1 | 441 HDFGRTR_EL2_TRBIDR_EL1 | 442 HDFGRTR_EL2_TRBBASER_EL1, 443 FEAT_TRBE), 444 NEEDS_FEAT_FLAG(HDFGRTR_EL2_OSDLR_EL1, NEVER_FGU, 445 FEAT_DoubleLock), 446 NEEDS_FEAT_FLAG(HDFGRTR_EL2_OSECCR_EL1 | 447 HDFGRTR_EL2_OSLSR_EL1 | 448 HDFGRTR_EL2_DBGPRCR_EL1 | 449 HDFGRTR_EL2_DBGAUTHSTATUS_EL1| 450 HDFGRTR_EL2_DBGCLAIM | 451 HDFGRTR_EL2_MDSCR_EL1 | 452 HDFGRTR_EL2_DBGWVRn_EL1 | 453 HDFGRTR_EL2_DBGWCRn_EL1 | 454 HDFGRTR_EL2_DBGBVRn_EL1 | 455 HDFGRTR_EL2_DBGBCRn_EL1, 456 NEVER_FGU, FEAT_AA64EL1) 457 }; 458 459 static const struct reg_bits_to_feat_map hdfgwtr_feat_map[] = { 460 NEEDS_FEAT(HDFGWTR_EL2_PMSLATFR_EL1 | 461 HDFGWTR_EL2_PMSIRR_EL1 | 462 HDFGWTR_EL2_PMSICR_EL1 | 463 HDFGWTR_EL2_PMSFCR_EL1 | 464 HDFGWTR_EL2_PMSEVFR_EL1 | 465 HDFGWTR_EL2_PMSCR_EL1 | 466 HDFGWTR_EL2_PMBSR_EL1 | 467 HDFGWTR_EL2_PMBPTR_EL1 | 468 HDFGWTR_EL2_PMBLIMITR_EL1, 469 FEAT_SPE), 470 NEEDS_FEAT(HDFGWTR_EL2_nPMSNEVFR_EL1, FEAT_SPE_FnE), 471 NEEDS_FEAT(HDFGWTR_EL2_nBRBDATA | 472 HDFGWTR_EL2_nBRBCTL, 473 FEAT_BRBE), 474 NEEDS_FEAT(HDFGWTR_EL2_TRCVICTLR | 475 HDFGWTR_EL2_TRCSSCSRn | 476 HDFGWTR_EL2_TRCSEQSTR | 477 HDFGWTR_EL2_TRCPRGCTLR | 478 HDFGWTR_EL2_TRCOSLAR | 479 HDFGWTR_EL2_TRCIMSPECn | 480 HDFGWTR_EL2_TRCCNTVRn | 481 HDFGWTR_EL2_TRCCLAIM | 482 HDFGWTR_EL2_TRCAUXCTLR | 483 HDFGWTR_EL2_TRC, 484 FEAT_TRC_SR), 485 NEEDS_FEAT(HDFGWTR_EL2_PMUSERENR_EL0 | 486 HDFGWTR_EL2_PMCR_EL0 | 487 HDFGWTR_EL2_PMSWINC_EL0 | 488 HDFGWTR_EL2_PMSELR_EL0 | 489 HDFGWTR_EL2_PMOVS | 490 HDFGWTR_EL2_PMINTEN | 491 HDFGWTR_EL2_PMCNTEN | 492 HDFGWTR_EL2_PMCCNTR_EL0 | 493 HDFGWTR_EL2_PMCCFILTR_EL0 | 494 HDFGWTR_EL2_PMEVTYPERn_EL0 | 495 HDFGWTR_EL2_PMEVCNTRn_EL0, 496 FEAT_PMUv3), 497 NEEDS_FEAT(HDFGWTR_EL2_TRBTRG_EL1 | 498 HDFGWTR_EL2_TRBSR_EL1 | 499 HDFGWTR_EL2_TRBPTR_EL1 | 500 HDFGWTR_EL2_TRBMAR_EL1 | 501 HDFGWTR_EL2_TRBLIMITR_EL1 | 502 HDFGWTR_EL2_TRBBASER_EL1, 503 FEAT_TRBE), 504 NEEDS_FEAT_FLAG(HDFGWTR_EL2_OSDLR_EL1, 505 NEVER_FGU, FEAT_DoubleLock), 506 NEEDS_FEAT_FLAG(HDFGWTR_EL2_OSECCR_EL1 | 507 HDFGWTR_EL2_OSLAR_EL1 | 508 HDFGWTR_EL2_DBGPRCR_EL1 | 509 HDFGWTR_EL2_DBGCLAIM | 510 HDFGWTR_EL2_MDSCR_EL1 | 511 HDFGWTR_EL2_DBGWVRn_EL1 | 512 HDFGWTR_EL2_DBGWCRn_EL1 | 513 HDFGWTR_EL2_DBGBVRn_EL1 | 514 HDFGWTR_EL2_DBGBCRn_EL1, 515 NEVER_FGU, FEAT_AA64EL1), 516 NEEDS_FEAT(HDFGWTR_EL2_TRFCR_EL1, FEAT_TRF), 517 }; 518 519 520 static const struct reg_bits_to_feat_map hfgitr_feat_map[] = { 521 NEEDS_FEAT(HFGITR_EL2_PSBCSYNC, FEAT_SPEv1p5), 522 NEEDS_FEAT(HFGITR_EL2_ATS1E1A, FEAT_ATS1A), 523 NEEDS_FEAT(HFGITR_EL2_COSPRCTX, FEAT_SPECRES2), 524 NEEDS_FEAT(HFGITR_EL2_nGCSEPP | 525 HFGITR_EL2_nGCSSTR_EL1 | 526 HFGITR_EL2_nGCSPUSHM_EL1, 527 FEAT_GCS), 528 NEEDS_FEAT(HFGITR_EL2_nBRBIALL | 529 HFGITR_EL2_nBRBINJ, 530 FEAT_BRBE), 531 NEEDS_FEAT(HFGITR_EL2_CPPRCTX | 532 HFGITR_EL2_DVPRCTX | 533 HFGITR_EL2_CFPRCTX, 534 FEAT_SPECRES), 535 NEEDS_FEAT(HFGITR_EL2_TLBIRVAALE1 | 536 HFGITR_EL2_TLBIRVALE1 | 537 HFGITR_EL2_TLBIRVAAE1 | 538 HFGITR_EL2_TLBIRVAE1 | 539 HFGITR_EL2_TLBIRVAALE1IS | 540 HFGITR_EL2_TLBIRVALE1IS | 541 HFGITR_EL2_TLBIRVAAE1IS | 542 HFGITR_EL2_TLBIRVAE1IS | 543 HFGITR_EL2_TLBIRVAALE1OS | 544 HFGITR_EL2_TLBIRVALE1OS | 545 HFGITR_EL2_TLBIRVAAE1OS | 546 HFGITR_EL2_TLBIRVAE1OS, 547 FEAT_TLBIRANGE), 548 NEEDS_FEAT(HFGITR_EL2_TLBIVAALE1OS | 549 HFGITR_EL2_TLBIVALE1OS | 550 HFGITR_EL2_TLBIVAAE1OS | 551 HFGITR_EL2_TLBIASIDE1OS | 552 HFGITR_EL2_TLBIVAE1OS | 553 HFGITR_EL2_TLBIVMALLE1OS, 554 FEAT_TLBIOS), 555 NEEDS_FEAT(HFGITR_EL2_ATS1E1WP | 556 HFGITR_EL2_ATS1E1RP, 557 FEAT_PAN2), 558 NEEDS_FEAT(HFGITR_EL2_DCCVADP, FEAT_DPB2), 559 NEEDS_FEAT_FLAG(HFGITR_EL2_DCCVAC | 560 HFGITR_EL2_SVC_EL1 | 561 HFGITR_EL2_SVC_EL0 | 562 HFGITR_EL2_ERET | 563 HFGITR_EL2_TLBIVAALE1 | 564 HFGITR_EL2_TLBIVALE1 | 565 HFGITR_EL2_TLBIVAAE1 | 566 HFGITR_EL2_TLBIASIDE1 | 567 HFGITR_EL2_TLBIVAE1 | 568 HFGITR_EL2_TLBIVMALLE1 | 569 HFGITR_EL2_TLBIVAALE1IS | 570 HFGITR_EL2_TLBIVALE1IS | 571 HFGITR_EL2_TLBIVAAE1IS | 572 HFGITR_EL2_TLBIASIDE1IS | 573 HFGITR_EL2_TLBIVAE1IS | 574 HFGITR_EL2_TLBIVMALLE1IS| 575 HFGITR_EL2_ATS1E0W | 576 HFGITR_EL2_ATS1E0R | 577 HFGITR_EL2_ATS1E1W | 578 HFGITR_EL2_ATS1E1R | 579 HFGITR_EL2_DCZVA | 580 HFGITR_EL2_DCCIVAC | 581 HFGITR_EL2_DCCVAP | 582 HFGITR_EL2_DCCVAU | 583 HFGITR_EL2_DCCISW | 584 HFGITR_EL2_DCCSW | 585 HFGITR_EL2_DCISW | 586 HFGITR_EL2_DCIVAC | 587 HFGITR_EL2_ICIVAU | 588 HFGITR_EL2_ICIALLU | 589 HFGITR_EL2_ICIALLUIS, 590 NEVER_FGU, FEAT_AA64EL1), 591 }; 592 593 static const struct reg_bits_to_feat_map hafgrtr_feat_map[] = { 594 NEEDS_FEAT(HAFGRTR_EL2_AMEVTYPER115_EL0 | 595 HAFGRTR_EL2_AMEVTYPER114_EL0 | 596 HAFGRTR_EL2_AMEVTYPER113_EL0 | 597 HAFGRTR_EL2_AMEVTYPER112_EL0 | 598 HAFGRTR_EL2_AMEVTYPER111_EL0 | 599 HAFGRTR_EL2_AMEVTYPER110_EL0 | 600 HAFGRTR_EL2_AMEVTYPER19_EL0 | 601 HAFGRTR_EL2_AMEVTYPER18_EL0 | 602 HAFGRTR_EL2_AMEVTYPER17_EL0 | 603 HAFGRTR_EL2_AMEVTYPER16_EL0 | 604 HAFGRTR_EL2_AMEVTYPER15_EL0 | 605 HAFGRTR_EL2_AMEVTYPER14_EL0 | 606 HAFGRTR_EL2_AMEVTYPER13_EL0 | 607 HAFGRTR_EL2_AMEVTYPER12_EL0 | 608 HAFGRTR_EL2_AMEVTYPER11_EL0 | 609 HAFGRTR_EL2_AMEVTYPER10_EL0 | 610 HAFGRTR_EL2_AMEVCNTR115_EL0 | 611 HAFGRTR_EL2_AMEVCNTR114_EL0 | 612 HAFGRTR_EL2_AMEVCNTR113_EL0 | 613 HAFGRTR_EL2_AMEVCNTR112_EL0 | 614 HAFGRTR_EL2_AMEVCNTR111_EL0 | 615 HAFGRTR_EL2_AMEVCNTR110_EL0 | 616 HAFGRTR_EL2_AMEVCNTR19_EL0 | 617 HAFGRTR_EL2_AMEVCNTR18_EL0 | 618 HAFGRTR_EL2_AMEVCNTR17_EL0 | 619 HAFGRTR_EL2_AMEVCNTR16_EL0 | 620 HAFGRTR_EL2_AMEVCNTR15_EL0 | 621 HAFGRTR_EL2_AMEVCNTR14_EL0 | 622 HAFGRTR_EL2_AMEVCNTR13_EL0 | 623 HAFGRTR_EL2_AMEVCNTR12_EL0 | 624 HAFGRTR_EL2_AMEVCNTR11_EL0 | 625 HAFGRTR_EL2_AMEVCNTR10_EL0 | 626 HAFGRTR_EL2_AMCNTEN1 | 627 HAFGRTR_EL2_AMCNTEN0 | 628 HAFGRTR_EL2_AMEVCNTR03_EL0 | 629 HAFGRTR_EL2_AMEVCNTR02_EL0 | 630 HAFGRTR_EL2_AMEVCNTR01_EL0 | 631 HAFGRTR_EL2_AMEVCNTR00_EL0, 632 FEAT_AMUv1), 633 }; 634 635 static const struct reg_bits_to_feat_map hfgitr2_feat_map[] = { 636 NEEDS_FEAT(HFGITR2_EL2_nDCCIVAPS, FEAT_PoPS), 637 NEEDS_FEAT(HFGITR2_EL2_TSBCSYNC, FEAT_TRBEv1p1) 638 }; 639 640 static const struct reg_bits_to_feat_map hfgrtr2_feat_map[] = { 641 NEEDS_FEAT(HFGRTR2_EL2_nPFAR_EL1, FEAT_PFAR), 642 NEEDS_FEAT(HFGRTR2_EL2_nERXGSR_EL1, FEAT_RASv2), 643 NEEDS_FEAT(HFGRTR2_EL2_nACTLRALIAS_EL1 | 644 HFGRTR2_EL2_nACTLRMASK_EL1 | 645 HFGRTR2_EL2_nCPACRALIAS_EL1 | 646 HFGRTR2_EL2_nCPACRMASK_EL1 | 647 HFGRTR2_EL2_nSCTLR2MASK_EL1 | 648 HFGRTR2_EL2_nSCTLRALIAS2_EL1 | 649 HFGRTR2_EL2_nSCTLRALIAS_EL1 | 650 HFGRTR2_EL2_nSCTLRMASK_EL1 | 651 HFGRTR2_EL2_nTCR2ALIAS_EL1 | 652 HFGRTR2_EL2_nTCR2MASK_EL1 | 653 HFGRTR2_EL2_nTCRALIAS_EL1 | 654 HFGRTR2_EL2_nTCRMASK_EL1, 655 FEAT_SRMASK), 656 NEEDS_FEAT(HFGRTR2_EL2_nRCWSMASK_EL1, FEAT_THE), 657 }; 658 659 static const struct reg_bits_to_feat_map hfgwtr2_feat_map[] = { 660 NEEDS_FEAT(HFGWTR2_EL2_nPFAR_EL1, FEAT_PFAR), 661 NEEDS_FEAT(HFGWTR2_EL2_nACTLRALIAS_EL1 | 662 HFGWTR2_EL2_nACTLRMASK_EL1 | 663 HFGWTR2_EL2_nCPACRALIAS_EL1 | 664 HFGWTR2_EL2_nCPACRMASK_EL1 | 665 HFGWTR2_EL2_nSCTLR2MASK_EL1 | 666 HFGWTR2_EL2_nSCTLRALIAS2_EL1 | 667 HFGWTR2_EL2_nSCTLRALIAS_EL1 | 668 HFGWTR2_EL2_nSCTLRMASK_EL1 | 669 HFGWTR2_EL2_nTCR2ALIAS_EL1 | 670 HFGWTR2_EL2_nTCR2MASK_EL1 | 671 HFGWTR2_EL2_nTCRALIAS_EL1 | 672 HFGWTR2_EL2_nTCRMASK_EL1, 673 FEAT_SRMASK), 674 NEEDS_FEAT(HFGWTR2_EL2_nRCWSMASK_EL1, FEAT_THE), 675 }; 676 677 static const struct reg_bits_to_feat_map hdfgrtr2_feat_map[] = { 678 NEEDS_FEAT(HDFGRTR2_EL2_nMDSELR_EL1, FEAT_Debugv8p9), 679 NEEDS_FEAT(HDFGRTR2_EL2_nPMECR_EL1, feat_ebep_pmuv3_ss), 680 NEEDS_FEAT(HDFGRTR2_EL2_nTRCITECR_EL1, FEAT_ITE), 681 NEEDS_FEAT(HDFGRTR2_EL2_nPMICFILTR_EL0 | 682 HDFGRTR2_EL2_nPMICNTR_EL0, 683 FEAT_PMUv3_ICNTR), 684 NEEDS_FEAT(HDFGRTR2_EL2_nPMUACR_EL1, FEAT_PMUv3p9), 685 NEEDS_FEAT(HDFGRTR2_EL2_nPMSSCR_EL1 | 686 HDFGRTR2_EL2_nPMSSDATA, 687 FEAT_PMUv3_SS), 688 NEEDS_FEAT(HDFGRTR2_EL2_nPMIAR_EL1, FEAT_SEBEP), 689 NEEDS_FEAT(HDFGRTR2_EL2_nPMSDSFR_EL1, feat_spe_fds), 690 NEEDS_FEAT(HDFGRTR2_EL2_nPMBMAR_EL1, FEAT_SPE_nVM), 691 NEEDS_FEAT(HDFGRTR2_EL2_nSPMACCESSR_EL1 | 692 HDFGRTR2_EL2_nSPMCNTEN | 693 HDFGRTR2_EL2_nSPMCR_EL0 | 694 HDFGRTR2_EL2_nSPMDEVAFF_EL1 | 695 HDFGRTR2_EL2_nSPMEVCNTRn_EL0 | 696 HDFGRTR2_EL2_nSPMEVTYPERn_EL0| 697 HDFGRTR2_EL2_nSPMID | 698 HDFGRTR2_EL2_nSPMINTEN | 699 HDFGRTR2_EL2_nSPMOVS | 700 HDFGRTR2_EL2_nSPMSCR_EL1 | 701 HDFGRTR2_EL2_nSPMSELR_EL0, 702 FEAT_SPMU), 703 NEEDS_FEAT(HDFGRTR2_EL2_nMDSTEPOP_EL1, FEAT_STEP2), 704 NEEDS_FEAT(HDFGRTR2_EL2_nTRBMPAM_EL1, feat_trbe_mpam), 705 }; 706 707 static const struct reg_bits_to_feat_map hdfgwtr2_feat_map[] = { 708 NEEDS_FEAT(HDFGWTR2_EL2_nMDSELR_EL1, FEAT_Debugv8p9), 709 NEEDS_FEAT(HDFGWTR2_EL2_nPMECR_EL1, feat_ebep_pmuv3_ss), 710 NEEDS_FEAT(HDFGWTR2_EL2_nTRCITECR_EL1, FEAT_ITE), 711 NEEDS_FEAT(HDFGWTR2_EL2_nPMICFILTR_EL0 | 712 HDFGWTR2_EL2_nPMICNTR_EL0, 713 FEAT_PMUv3_ICNTR), 714 NEEDS_FEAT(HDFGWTR2_EL2_nPMUACR_EL1 | 715 HDFGWTR2_EL2_nPMZR_EL0, 716 FEAT_PMUv3p9), 717 NEEDS_FEAT(HDFGWTR2_EL2_nPMSSCR_EL1, FEAT_PMUv3_SS), 718 NEEDS_FEAT(HDFGWTR2_EL2_nPMIAR_EL1, FEAT_SEBEP), 719 NEEDS_FEAT(HDFGWTR2_EL2_nPMSDSFR_EL1, feat_spe_fds), 720 NEEDS_FEAT(HDFGWTR2_EL2_nPMBMAR_EL1, FEAT_SPE_nVM), 721 NEEDS_FEAT(HDFGWTR2_EL2_nSPMACCESSR_EL1 | 722 HDFGWTR2_EL2_nSPMCNTEN | 723 HDFGWTR2_EL2_nSPMCR_EL0 | 724 HDFGWTR2_EL2_nSPMEVCNTRn_EL0 | 725 HDFGWTR2_EL2_nSPMEVTYPERn_EL0| 726 HDFGWTR2_EL2_nSPMINTEN | 727 HDFGWTR2_EL2_nSPMOVS | 728 HDFGWTR2_EL2_nSPMSCR_EL1 | 729 HDFGWTR2_EL2_nSPMSELR_EL0, 730 FEAT_SPMU), 731 NEEDS_FEAT(HDFGWTR2_EL2_nMDSTEPOP_EL1, FEAT_STEP2), 732 NEEDS_FEAT(HDFGWTR2_EL2_nTRBMPAM_EL1, feat_trbe_mpam), 733 }; 734 735 static const struct reg_bits_to_feat_map hcrx_feat_map[] = { 736 NEEDS_FEAT(HCRX_EL2_PACMEn, feat_pauth_lr), 737 NEEDS_FEAT(HCRX_EL2_EnFPM, FEAT_FPMR), 738 NEEDS_FEAT(HCRX_EL2_GCSEn, FEAT_GCS), 739 NEEDS_FEAT(HCRX_EL2_EnIDCP128, FEAT_SYSREG128), 740 NEEDS_FEAT(HCRX_EL2_EnSDERR, feat_aderr), 741 NEEDS_FEAT(HCRX_EL2_TMEA, FEAT_DoubleFault2), 742 NEEDS_FEAT(HCRX_EL2_EnSNERR, feat_anerr), 743 NEEDS_FEAT(HCRX_EL2_D128En, FEAT_D128), 744 NEEDS_FEAT(HCRX_EL2_PTTWI, FEAT_THE), 745 NEEDS_FEAT(HCRX_EL2_SCTLR2En, FEAT_SCTLR2), 746 NEEDS_FEAT(HCRX_EL2_TCR2En, FEAT_TCR2), 747 NEEDS_FEAT(HCRX_EL2_MSCEn | 748 HCRX_EL2_MCE2, 749 FEAT_MOPS), 750 NEEDS_FEAT(HCRX_EL2_CMOW, FEAT_CMOW), 751 NEEDS_FEAT(HCRX_EL2_VFNMI | 752 HCRX_EL2_VINMI | 753 HCRX_EL2_TALLINT, 754 FEAT_NMI), 755 NEEDS_FEAT(HCRX_EL2_SMPME, feat_sme_smps), 756 NEEDS_FEAT(HCRX_EL2_FGTnXS | 757 HCRX_EL2_FnXS, 758 FEAT_XS), 759 NEEDS_FEAT(HCRX_EL2_EnASR, FEAT_LS64_V), 760 NEEDS_FEAT(HCRX_EL2_EnALS, FEAT_LS64), 761 NEEDS_FEAT(HCRX_EL2_EnAS0, FEAT_LS64_ACCDATA), 762 }; 763 764 static const struct reg_bits_to_feat_map hcr_feat_map[] = { 765 NEEDS_FEAT(HCR_EL2_TID0, FEAT_AA32EL0), 766 NEEDS_FEAT_FIXED(HCR_EL2_RW, compute_hcr_rw), 767 NEEDS_FEAT(HCR_EL2_HCD, not_feat_aa64el3), 768 NEEDS_FEAT(HCR_EL2_AMO | 769 HCR_EL2_BSU | 770 HCR_EL2_CD | 771 HCR_EL2_DC | 772 HCR_EL2_FB | 773 HCR_EL2_FMO | 774 HCR_EL2_ID | 775 HCR_EL2_IMO | 776 HCR_EL2_MIOCNCE | 777 HCR_EL2_PTW | 778 HCR_EL2_SWIO | 779 HCR_EL2_TACR | 780 HCR_EL2_TDZ | 781 HCR_EL2_TGE | 782 HCR_EL2_TID1 | 783 HCR_EL2_TID2 | 784 HCR_EL2_TID3 | 785 HCR_EL2_TIDCP | 786 HCR_EL2_TPCP | 787 HCR_EL2_TPU | 788 HCR_EL2_TRVM | 789 HCR_EL2_TSC | 790 HCR_EL2_TSW | 791 HCR_EL2_TTLB | 792 HCR_EL2_TVM | 793 HCR_EL2_TWE | 794 HCR_EL2_TWI | 795 HCR_EL2_VF | 796 HCR_EL2_VI | 797 HCR_EL2_VM | 798 HCR_EL2_VSE, 799 FEAT_AA64EL1), 800 NEEDS_FEAT(HCR_EL2_AMVOFFEN, FEAT_AMUv1p1), 801 NEEDS_FEAT(HCR_EL2_EnSCXT, feat_csv2_2_csv2_1p2), 802 NEEDS_FEAT(HCR_EL2_TICAB | 803 HCR_EL2_TID4 | 804 HCR_EL2_TOCU, 805 FEAT_EVT), 806 NEEDS_FEAT(HCR_EL2_TTLBIS | 807 HCR_EL2_TTLBOS, 808 FEAT_EVT_TTLBxS), 809 NEEDS_FEAT(HCR_EL2_TLOR, FEAT_LOR), 810 NEEDS_FEAT(HCR_EL2_ATA | 811 HCR_EL2_DCT | 812 HCR_EL2_TID5, 813 FEAT_MTE2), 814 NEEDS_FEAT(HCR_EL2_AT | /* Ignore the original FEAT_NV */ 815 HCR_EL2_NV2 | 816 HCR_EL2_NV, 817 feat_nv2), 818 NEEDS_FEAT(HCR_EL2_NV1, feat_nv2_e2h0_ni), /* Missing from JSON */ 819 NEEDS_FEAT(HCR_EL2_API | 820 HCR_EL2_APK, 821 feat_pauth), 822 NEEDS_FEAT(HCR_EL2_TEA | 823 HCR_EL2_TERR, 824 FEAT_RAS), 825 NEEDS_FEAT(HCR_EL2_FIEN, feat_rasv1p1), 826 NEEDS_FEAT(HCR_EL2_GPF, FEAT_RME), 827 NEEDS_FEAT(HCR_EL2_FWB, FEAT_S2FWB), 828 NEEDS_FEAT(HCR_EL2_TME, FEAT_TME), 829 NEEDS_FEAT(HCR_EL2_TWEDEL | 830 HCR_EL2_TWEDEn, 831 FEAT_TWED), 832 NEEDS_FEAT_FIXED(HCR_EL2_E2H, compute_hcr_e2h), 833 }; 834 835 static void __init check_feat_map(const struct reg_bits_to_feat_map *map, 836 int map_size, u64 res0, const char *str) 837 { 838 u64 mask = 0; 839 840 for (int i = 0; i < map_size; i++) 841 mask |= map[i].bits; 842 843 if (mask != ~res0) 844 kvm_err("Undefined %s behaviour, bits %016llx\n", 845 str, mask ^ ~res0); 846 } 847 848 void __init check_feature_map(void) 849 { 850 check_feat_map(hfgrtr_feat_map, ARRAY_SIZE(hfgrtr_feat_map), 851 hfgrtr_masks.res0, hfgrtr_masks.str); 852 check_feat_map(hfgwtr_feat_map, ARRAY_SIZE(hfgwtr_feat_map), 853 hfgwtr_masks.res0, hfgwtr_masks.str); 854 check_feat_map(hfgitr_feat_map, ARRAY_SIZE(hfgitr_feat_map), 855 hfgitr_masks.res0, hfgitr_masks.str); 856 check_feat_map(hdfgrtr_feat_map, ARRAY_SIZE(hdfgrtr_feat_map), 857 hdfgrtr_masks.res0, hdfgrtr_masks.str); 858 check_feat_map(hdfgwtr_feat_map, ARRAY_SIZE(hdfgwtr_feat_map), 859 hdfgwtr_masks.res0, hdfgwtr_masks.str); 860 check_feat_map(hafgrtr_feat_map, ARRAY_SIZE(hafgrtr_feat_map), 861 hafgrtr_masks.res0, hafgrtr_masks.str); 862 check_feat_map(hcrx_feat_map, ARRAY_SIZE(hcrx_feat_map), 863 __HCRX_EL2_RES0, "HCRX_EL2"); 864 check_feat_map(hcr_feat_map, ARRAY_SIZE(hcr_feat_map), 865 HCR_EL2_RES0, "HCR_EL2"); 866 } 867 868 static bool idreg_feat_match(struct kvm *kvm, const struct reg_bits_to_feat_map *map) 869 { 870 u64 regval = kvm->arch.id_regs[map->regidx]; 871 u64 regfld = (regval >> map->shift) & GENMASK(map->width - 1, 0); 872 873 if (map->sign) { 874 s64 sfld = sign_extend64(regfld, map->width - 1); 875 s64 slim = sign_extend64(map->lo_lim, map->width - 1); 876 return sfld >= slim; 877 } else { 878 return regfld >= map->lo_lim; 879 } 880 } 881 882 static u64 __compute_fixed_bits(struct kvm *kvm, 883 const struct reg_bits_to_feat_map *map, 884 int map_size, 885 u64 *fixed_bits, 886 unsigned long require, 887 unsigned long exclude) 888 { 889 u64 val = 0; 890 891 for (int i = 0; i < map_size; i++) { 892 bool match; 893 894 if ((map[i].flags & require) != require) 895 continue; 896 897 if (map[i].flags & exclude) 898 continue; 899 900 if (map[i].flags & CALL_FUNC) 901 match = (map[i].flags & FIXED_VALUE) ? 902 map[i].fval(kvm, fixed_bits) : 903 map[i].match(kvm); 904 else 905 match = idreg_feat_match(kvm, &map[i]); 906 907 if (!match || (map[i].flags & FIXED_VALUE)) 908 val |= map[i].bits; 909 } 910 911 return val; 912 } 913 914 static u64 compute_res0_bits(struct kvm *kvm, 915 const struct reg_bits_to_feat_map *map, 916 int map_size, 917 unsigned long require, 918 unsigned long exclude) 919 { 920 return __compute_fixed_bits(kvm, map, map_size, NULL, 921 require, exclude | FIXED_VALUE); 922 } 923 924 static u64 compute_fixed_bits(struct kvm *kvm, 925 const struct reg_bits_to_feat_map *map, 926 int map_size, 927 u64 *fixed_bits, 928 unsigned long require, 929 unsigned long exclude) 930 { 931 return __compute_fixed_bits(kvm, map, map_size, fixed_bits, 932 require | FIXED_VALUE, exclude); 933 } 934 935 void compute_fgu(struct kvm *kvm, enum fgt_group_id fgt) 936 { 937 u64 val = 0; 938 939 switch (fgt) { 940 case HFGRTR_GROUP: 941 val |= compute_res0_bits(kvm, hfgrtr_feat_map, 942 ARRAY_SIZE(hfgrtr_feat_map), 943 0, NEVER_FGU); 944 val |= compute_res0_bits(kvm, hfgwtr_feat_map, 945 ARRAY_SIZE(hfgwtr_feat_map), 946 0, NEVER_FGU); 947 break; 948 case HFGITR_GROUP: 949 val |= compute_res0_bits(kvm, hfgitr_feat_map, 950 ARRAY_SIZE(hfgitr_feat_map), 951 0, NEVER_FGU); 952 break; 953 case HDFGRTR_GROUP: 954 val |= compute_res0_bits(kvm, hdfgrtr_feat_map, 955 ARRAY_SIZE(hdfgrtr_feat_map), 956 0, NEVER_FGU); 957 val |= compute_res0_bits(kvm, hdfgwtr_feat_map, 958 ARRAY_SIZE(hdfgwtr_feat_map), 959 0, NEVER_FGU); 960 break; 961 case HAFGRTR_GROUP: 962 val |= compute_res0_bits(kvm, hafgrtr_feat_map, 963 ARRAY_SIZE(hafgrtr_feat_map), 964 0, NEVER_FGU); 965 break; 966 case HFGRTR2_GROUP: 967 val |= compute_res0_bits(kvm, hfgrtr2_feat_map, 968 ARRAY_SIZE(hfgrtr2_feat_map), 969 0, NEVER_FGU); 970 val |= compute_res0_bits(kvm, hfgwtr2_feat_map, 971 ARRAY_SIZE(hfgwtr2_feat_map), 972 0, NEVER_FGU); 973 break; 974 case HFGITR2_GROUP: 975 val |= compute_res0_bits(kvm, hfgitr2_feat_map, 976 ARRAY_SIZE(hfgitr2_feat_map), 977 0, NEVER_FGU); 978 break; 979 case HDFGRTR2_GROUP: 980 val |= compute_res0_bits(kvm, hdfgrtr2_feat_map, 981 ARRAY_SIZE(hdfgrtr2_feat_map), 982 0, NEVER_FGU); 983 val |= compute_res0_bits(kvm, hdfgwtr2_feat_map, 984 ARRAY_SIZE(hdfgwtr2_feat_map), 985 0, NEVER_FGU); 986 break; 987 default: 988 BUG(); 989 } 990 991 kvm->arch.fgu[fgt] = val; 992 } 993 994 void get_reg_fixed_bits(struct kvm *kvm, enum vcpu_sysreg reg, u64 *res0, u64 *res1) 995 { 996 u64 fixed = 0, mask; 997 998 switch (reg) { 999 case HFGRTR_EL2: 1000 *res0 = compute_res0_bits(kvm, hfgrtr_feat_map, 1001 ARRAY_SIZE(hfgrtr_feat_map), 0, 0); 1002 *res0 |= hfgrtr_masks.res0; 1003 *res1 = HFGRTR_EL2_RES1; 1004 break; 1005 case HFGWTR_EL2: 1006 *res0 = compute_res0_bits(kvm, hfgwtr_feat_map, 1007 ARRAY_SIZE(hfgwtr_feat_map), 0, 0); 1008 *res0 |= hfgwtr_masks.res0; 1009 *res1 = HFGWTR_EL2_RES1; 1010 break; 1011 case HFGITR_EL2: 1012 *res0 = compute_res0_bits(kvm, hfgitr_feat_map, 1013 ARRAY_SIZE(hfgitr_feat_map), 0, 0); 1014 *res0 |= hfgitr_masks.res0; 1015 *res1 = HFGITR_EL2_RES1; 1016 break; 1017 case HDFGRTR_EL2: 1018 *res0 = compute_res0_bits(kvm, hdfgrtr_feat_map, 1019 ARRAY_SIZE(hdfgrtr_feat_map), 0, 0); 1020 *res0 |= hdfgrtr_masks.res0; 1021 *res1 = HDFGRTR_EL2_RES1; 1022 break; 1023 case HDFGWTR_EL2: 1024 *res0 = compute_res0_bits(kvm, hdfgwtr_feat_map, 1025 ARRAY_SIZE(hdfgwtr_feat_map), 0, 0); 1026 *res0 |= hdfgwtr_masks.res0; 1027 *res1 = HDFGWTR_EL2_RES1; 1028 break; 1029 case HAFGRTR_EL2: 1030 *res0 = compute_res0_bits(kvm, hafgrtr_feat_map, 1031 ARRAY_SIZE(hafgrtr_feat_map), 0, 0); 1032 *res0 |= hafgrtr_masks.res0; 1033 *res1 = HAFGRTR_EL2_RES1; 1034 break; 1035 case HFGRTR2_EL2: 1036 *res0 = compute_res0_bits(kvm, hfgrtr2_feat_map, 1037 ARRAY_SIZE(hfgrtr2_feat_map), 0, 0); 1038 *res0 |= hfgrtr2_masks.res0; 1039 *res1 = HFGRTR2_EL2_RES1; 1040 break; 1041 case HFGWTR2_EL2: 1042 *res0 = compute_res0_bits(kvm, hfgwtr2_feat_map, 1043 ARRAY_SIZE(hfgwtr2_feat_map), 0, 0); 1044 *res0 |= hfgwtr2_masks.res0; 1045 *res1 = HFGWTR2_EL2_RES1; 1046 break; 1047 case HFGITR2_EL2: 1048 *res0 = compute_res0_bits(kvm, hfgitr2_feat_map, 1049 ARRAY_SIZE(hfgitr2_feat_map), 0, 0); 1050 *res0 |= hfgitr2_masks.res0; 1051 *res1 = HFGITR2_EL2_RES1; 1052 break; 1053 case HDFGRTR2_EL2: 1054 *res0 = compute_res0_bits(kvm, hdfgrtr2_feat_map, 1055 ARRAY_SIZE(hdfgrtr2_feat_map), 0, 0); 1056 *res0 |= hdfgrtr2_masks.res0; 1057 *res1 = HDFGRTR2_EL2_RES1; 1058 break; 1059 case HDFGWTR2_EL2: 1060 *res0 = compute_res0_bits(kvm, hdfgwtr2_feat_map, 1061 ARRAY_SIZE(hdfgwtr2_feat_map), 0, 0); 1062 *res0 |= hdfgwtr2_masks.res0; 1063 *res1 = HDFGWTR2_EL2_RES1; 1064 break; 1065 case HCRX_EL2: 1066 *res0 = compute_res0_bits(kvm, hcrx_feat_map, 1067 ARRAY_SIZE(hcrx_feat_map), 0, 0); 1068 *res0 |= __HCRX_EL2_RES0; 1069 *res1 = __HCRX_EL2_RES1; 1070 break; 1071 case HCR_EL2: 1072 mask = compute_fixed_bits(kvm, hcr_feat_map, 1073 ARRAY_SIZE(hcr_feat_map), &fixed, 1074 0, 0); 1075 *res0 = compute_res0_bits(kvm, hcr_feat_map, 1076 ARRAY_SIZE(hcr_feat_map), 0, 0); 1077 *res0 |= HCR_EL2_RES0 | (mask & ~fixed); 1078 *res1 = HCR_EL2_RES1 | (mask & fixed); 1079 break; 1080 default: 1081 WARN_ON_ONCE(1); 1082 *res0 = *res1 = 0; 1083 break; 1084 } 1085 } 1086