1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #ifndef __ARM_KVM_INIT_H__ 8 #define __ARM_KVM_INIT_H__ 9 10 #ifndef __ASSEMBLY__ 11 #error Assembly-only header 12 #endif 13 14 #include <asm/kvm_arm.h> 15 #include <asm/ptrace.h> 16 #include <asm/sysreg.h> 17 #include <linux/irqchip/arm-gic-v3.h> 18 19 .macro init_el2_hcr val 20 mov_q x0, \val 21 22 /* 23 * Compliant CPUs advertise their VHE-onlyness with 24 * ID_AA64MMFR4_EL1.E2H0 < 0. On such CPUs HCR_EL2.E2H is RES1, but it 25 * can reset into an UNKNOWN state and might not read as 1 until it has 26 * been initialized explicitly. 27 * 28 * Fruity CPUs seem to have HCR_EL2.E2H set to RAO/WI, but 29 * don't advertise it (they predate this relaxation). 30 * 31 * Initalize HCR_EL2.E2H so that later code can rely upon HCR_EL2.E2H 32 * indicating whether the CPU is running in E2H mode. 33 */ 34 mrs_s x1, SYS_ID_AA64MMFR4_EL1 35 sbfx x1, x1, #ID_AA64MMFR4_EL1_E2H0_SHIFT, #ID_AA64MMFR4_EL1_E2H0_WIDTH 36 cmp x1, #0 37 b.ge .LnVHE_\@ 38 39 orr x0, x0, #HCR_E2H 40 .LnVHE_\@: 41 msr_hcr_el2 x0 42 isb 43 .endm 44 45 .macro __init_el2_sctlr 46 mov_q x0, INIT_SCTLR_EL2_MMU_OFF 47 msr sctlr_el2, x0 48 isb 49 .endm 50 51 .macro __init_el2_hcrx 52 mrs x0, id_aa64mmfr1_el1 53 ubfx x0, x0, #ID_AA64MMFR1_EL1_HCX_SHIFT, #4 54 cbz x0, .Lskip_hcrx_\@ 55 mov_q x0, (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En | HCRX_EL2_EnFPM) 56 57 /* Enable GCS if supported */ 58 mrs_s x1, SYS_ID_AA64PFR1_EL1 59 ubfx x1, x1, #ID_AA64PFR1_EL1_GCS_SHIFT, #4 60 cbz x1, .Lset_hcrx_\@ 61 orr x0, x0, #HCRX_EL2_GCSEn 62 63 .Lset_hcrx_\@: 64 msr_s SYS_HCRX_EL2, x0 65 .Lskip_hcrx_\@: 66 .endm 67 68 /* Check if running in host at EL2 mode, i.e., (h)VHE. Jump to fail if not. */ 69 .macro __check_hvhe fail, tmp 70 mrs \tmp, hcr_el2 71 and \tmp, \tmp, #HCR_E2H 72 cbz \tmp, \fail 73 .endm 74 75 /* 76 * Allow Non-secure EL1 and EL0 to access physical timer and counter. 77 * This is not necessary for VHE, since the host kernel runs in EL2, 78 * and EL0 accesses are configured in the later stage of boot process. 79 * Note that when HCR_EL2.E2H == 1, CNTHCTL_EL2 has the same bit layout 80 * as CNTKCTL_EL1, and CNTKCTL_EL1 accessing instructions are redefined 81 * to access CNTHCTL_EL2. This allows the kernel designed to run at EL1 82 * to transparently mess with the EL0 bits via CNTKCTL_EL1 access in 83 * EL2. 84 */ 85 .macro __init_el2_timers 86 mov x0, #3 // Enable EL1 physical timers 87 __check_hvhe .LnVHE_\@, x1 88 lsl x0, x0, #10 89 .LnVHE_\@: 90 msr cnthctl_el2, x0 91 msr cntvoff_el2, xzr // Clear virtual offset 92 .endm 93 94 .macro __init_el2_debug 95 mrs x1, id_aa64dfr0_el1 96 ubfx x0, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4 97 cmp x0, #ID_AA64DFR0_EL1_PMUVer_NI 98 ccmp x0, #ID_AA64DFR0_EL1_PMUVer_IMP_DEF, #4, ne 99 b.eq .Lskip_pmu_\@ // Skip if no PMU present or IMP_DEF 100 mrs x0, pmcr_el0 // Disable debug access traps 101 ubfx x0, x0, #11, #5 // to EL2 and allow access to 102 .Lskip_pmu_\@: 103 csel x2, xzr, x0, eq // all PMU counters from EL1 104 105 /* Statistical profiling */ 106 ubfx x0, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4 107 cbz x0, .Lskip_spe_\@ // Skip if SPE not present 108 109 mrs_s x0, SYS_PMBIDR_EL1 // If SPE available at EL2, 110 and x0, x0, #(1 << PMBIDR_EL1_P_SHIFT) 111 cbnz x0, .Lskip_spe_el2_\@ // then permit sampling of physical 112 mov x0, #(1 << PMSCR_EL2_PCT_SHIFT | \ 113 1 << PMSCR_EL2_PA_SHIFT) 114 msr_s SYS_PMSCR_EL2, x0 // addresses and physical counter 115 .Lskip_spe_el2_\@: 116 mov x0, #MDCR_EL2_E2PB_MASK 117 orr x2, x2, x0 // If we don't have VHE, then 118 // use EL1&0 translation. 119 120 .Lskip_spe_\@: 121 /* Trace buffer */ 122 ubfx x0, x1, #ID_AA64DFR0_EL1_TraceBuffer_SHIFT, #4 123 cbz x0, .Lskip_trace_\@ // Skip if TraceBuffer is not present 124 125 mrs_s x0, SYS_TRBIDR_EL1 126 and x0, x0, TRBIDR_EL1_P 127 cbnz x0, .Lskip_trace_\@ // If TRBE is available at EL2 128 129 mov x0, #MDCR_EL2_E2TB_MASK 130 orr x2, x2, x0 // allow the EL1&0 translation 131 // to own it. 132 133 .Lskip_trace_\@: 134 msr mdcr_el2, x2 // Configure debug traps 135 .endm 136 137 /* LORegions */ 138 .macro __init_el2_lor 139 mrs x1, id_aa64mmfr1_el1 140 ubfx x0, x1, #ID_AA64MMFR1_EL1_LO_SHIFT, 4 141 cbz x0, .Lskip_lor_\@ 142 msr_s SYS_LORC_EL1, xzr 143 .Lskip_lor_\@: 144 .endm 145 146 /* Stage-2 translation */ 147 .macro __init_el2_stage2 148 msr vttbr_el2, xzr 149 .endm 150 151 /* GICv3 system register access */ 152 .macro __init_el2_gicv3 153 mrs x0, id_aa64pfr0_el1 154 ubfx x0, x0, #ID_AA64PFR0_EL1_GIC_SHIFT, #4 155 cbz x0, .Lskip_gicv3_\@ 156 157 mrs_s x0, SYS_ICC_SRE_EL2 158 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 159 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 160 msr_s SYS_ICC_SRE_EL2, x0 161 isb // Make sure SRE is now set 162 mrs_s x0, SYS_ICC_SRE_EL2 // Read SRE back, 163 tbz x0, #0, .Lskip_gicv3_\@ // and check that it sticks 164 msr_s SYS_ICH_HCR_EL2, xzr // Reset ICH_HCR_EL2 to defaults 165 .Lskip_gicv3_\@: 166 .endm 167 168 .macro __init_el2_hstr 169 msr hstr_el2, xzr // Disable CP15 traps to EL2 170 .endm 171 172 /* Virtual CPU ID registers */ 173 .macro __init_el2_nvhe_idregs 174 mrs x0, midr_el1 175 mrs x1, mpidr_el1 176 msr vpidr_el2, x0 177 msr vmpidr_el2, x1 178 .endm 179 180 /* Coprocessor traps */ 181 .macro __init_el2_cptr 182 __check_hvhe .LnVHE_\@, x1 183 mov x0, #CPACR_EL1_FPEN 184 msr cpacr_el1, x0 185 b .Lskip_set_cptr_\@ 186 .LnVHE_\@: 187 mov x0, #0x33ff 188 msr cptr_el2, x0 // Disable copro. traps to EL2 189 .Lskip_set_cptr_\@: 190 .endm 191 192 /* Disable any fine grained traps */ 193 .macro __init_el2_fgt 194 mrs x1, id_aa64mmfr0_el1 195 ubfx x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4 196 cbz x1, .Lskip_fgt_\@ 197 198 mov x0, xzr 199 mrs x1, id_aa64dfr0_el1 200 ubfx x1, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4 201 cmp x1, #3 202 b.lt .Lskip_spe_fgt_\@ 203 /* Disable PMSNEVFR_EL1 read and write traps */ 204 orr x0, x0, #(1 << 62) 205 206 .Lskip_spe_fgt_\@: 207 208 .Lset_debug_fgt_\@: 209 msr_s SYS_HDFGRTR_EL2, x0 210 msr_s SYS_HDFGWTR_EL2, x0 211 212 mov x0, xzr 213 mrs x1, id_aa64pfr1_el1 214 ubfx x1, x1, #ID_AA64PFR1_EL1_SME_SHIFT, #4 215 cbz x1, .Lskip_sme_fgt_\@ 216 217 /* Disable nVHE traps of TPIDR2 and SMPRI */ 218 orr x0, x0, #HFGRTR_EL2_nSMPRI_EL1_MASK 219 orr x0, x0, #HFGRTR_EL2_nTPIDR2_EL0_MASK 220 221 .Lskip_sme_fgt_\@: 222 mrs_s x1, SYS_ID_AA64MMFR3_EL1 223 ubfx x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4 224 cbz x1, .Lskip_pie_fgt_\@ 225 226 /* Disable trapping of PIR_EL1 / PIRE0_EL1 */ 227 orr x0, x0, #HFGRTR_EL2_nPIR_EL1 228 orr x0, x0, #HFGRTR_EL2_nPIRE0_EL1 229 230 .Lskip_pie_fgt_\@: 231 mrs_s x1, SYS_ID_AA64MMFR3_EL1 232 ubfx x1, x1, #ID_AA64MMFR3_EL1_S1POE_SHIFT, #4 233 cbz x1, .Lskip_poe_fgt_\@ 234 235 /* Disable trapping of POR_EL0 */ 236 orr x0, x0, #HFGRTR_EL2_nPOR_EL0 237 238 .Lskip_poe_fgt_\@: 239 /* GCS depends on PIE so we don't check it if PIE is absent */ 240 mrs_s x1, SYS_ID_AA64PFR1_EL1 241 ubfx x1, x1, #ID_AA64PFR1_EL1_GCS_SHIFT, #4 242 cbz x1, .Lskip_gce_fgt_\@ 243 244 /* Disable traps of access to GCS registers at EL0 and EL1 */ 245 orr x0, x0, #HFGRTR_EL2_nGCS_EL1_MASK 246 orr x0, x0, #HFGRTR_EL2_nGCS_EL0_MASK 247 248 .Lskip_gce_fgt_\@: 249 250 .Lset_fgt_\@: 251 msr_s SYS_HFGRTR_EL2, x0 252 msr_s SYS_HFGWTR_EL2, x0 253 msr_s SYS_HFGITR_EL2, xzr 254 255 mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU 256 ubfx x1, x1, #ID_AA64PFR0_EL1_AMU_SHIFT, #4 257 cbz x1, .Lskip_amu_fgt_\@ 258 259 msr_s SYS_HAFGRTR_EL2, xzr 260 261 .Lskip_amu_fgt_\@: 262 263 .Lskip_fgt_\@: 264 .endm 265 266 .macro __init_el2_fgt2 267 mrs x1, id_aa64mmfr0_el1 268 ubfx x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4 269 cmp x1, #ID_AA64MMFR0_EL1_FGT_FGT2 270 b.lt .Lskip_fgt2_\@ 271 272 mov x0, xzr 273 mrs x1, id_aa64dfr0_el1 274 ubfx x1, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4 275 cmp x1, #ID_AA64DFR0_EL1_PMUVer_V3P9 276 b.lt .Lskip_pmuv3p9_\@ 277 278 orr x0, x0, #HDFGRTR2_EL2_nPMICNTR_EL0 279 orr x0, x0, #HDFGRTR2_EL2_nPMICFILTR_EL0 280 orr x0, x0, #HDFGRTR2_EL2_nPMUACR_EL1 281 .Lskip_pmuv3p9_\@: 282 msr_s SYS_HDFGRTR2_EL2, x0 283 msr_s SYS_HDFGWTR2_EL2, x0 284 msr_s SYS_HFGRTR2_EL2, xzr 285 msr_s SYS_HFGWTR2_EL2, xzr 286 msr_s SYS_HFGITR2_EL2, xzr 287 .Lskip_fgt2_\@: 288 .endm 289 290 .macro __init_el2_gcs 291 mrs_s x1, SYS_ID_AA64PFR1_EL1 292 ubfx x1, x1, #ID_AA64PFR1_EL1_GCS_SHIFT, #4 293 cbz x1, .Lskip_gcs_\@ 294 295 /* Ensure GCS is not enabled when we start trying to do BLs */ 296 msr_s SYS_GCSCR_EL1, xzr 297 msr_s SYS_GCSCRE0_EL1, xzr 298 .Lskip_gcs_\@: 299 .endm 300 301 /** 302 * Initialize EL2 registers to sane values. This should be called early on all 303 * cores that were booted in EL2. Note that everything gets initialised as 304 * if VHE was not available. The kernel context will be upgraded to VHE 305 * if possible later on in the boot process 306 * 307 * Regs: x0, x1 and x2 are clobbered. 308 */ 309 .macro init_el2_state 310 __init_el2_sctlr 311 __init_el2_hcrx 312 __init_el2_timers 313 __init_el2_debug 314 __init_el2_lor 315 __init_el2_stage2 316 __init_el2_gicv3 317 __init_el2_hstr 318 __init_el2_nvhe_idregs 319 __init_el2_cptr 320 __init_el2_fgt 321 __init_el2_fgt2 322 __init_el2_gcs 323 .endm 324 325 #ifndef __KVM_NVHE_HYPERVISOR__ 326 // This will clobber tmp1 and tmp2, and expect tmp1 to contain 327 // the id register value as read from the HW 328 .macro __check_override idreg, fld, width, pass, fail, tmp1, tmp2 329 ubfx \tmp1, \tmp1, #\fld, #\width 330 cbz \tmp1, \fail 331 332 adr_l \tmp1, \idreg\()_override 333 ldr \tmp2, [\tmp1, FTR_OVR_VAL_OFFSET] 334 ldr \tmp1, [\tmp1, FTR_OVR_MASK_OFFSET] 335 ubfx \tmp2, \tmp2, #\fld, #\width 336 ubfx \tmp1, \tmp1, #\fld, #\width 337 cmp \tmp1, xzr 338 and \tmp2, \tmp2, \tmp1 339 csinv \tmp2, \tmp2, xzr, ne 340 cbnz \tmp2, \pass 341 b \fail 342 .endm 343 344 // This will clobber tmp1 and tmp2 345 .macro check_override idreg, fld, pass, fail, tmp1, tmp2 346 mrs \tmp1, \idreg\()_el1 347 __check_override \idreg \fld 4 \pass \fail \tmp1 \tmp2 348 .endm 349 #else 350 // This will clobber tmp 351 .macro __check_override idreg, fld, width, pass, fail, tmp, ignore 352 ldr_l \tmp, \idreg\()_el1_sys_val 353 ubfx \tmp, \tmp, #\fld, #\width 354 cbnz \tmp, \pass 355 b \fail 356 .endm 357 358 .macro check_override idreg, fld, pass, fail, tmp, ignore 359 __check_override \idreg \fld 4 \pass \fail \tmp \ignore 360 .endm 361 #endif 362 363 .macro finalise_el2_state 364 check_override id_aa64pfr0, ID_AA64PFR0_EL1_MPAM_SHIFT, .Linit_mpam_\@, .Lskip_mpam_\@, x1, x2 365 366 .Linit_mpam_\@: 367 msr_s SYS_MPAM2_EL2, xzr // use the default partition 368 // and disable lower traps 369 mrs_s x0, SYS_MPAMIDR_EL1 370 tbz x0, #MPAMIDR_EL1_HAS_HCR_SHIFT, .Lskip_mpam_\@ // skip if no MPAMHCR reg 371 msr_s SYS_MPAMHCR_EL2, xzr // clear TRAP_MPAMIDR_EL1 -> EL2 372 373 .Lskip_mpam_\@: 374 check_override id_aa64pfr0, ID_AA64PFR0_EL1_SVE_SHIFT, .Linit_sve_\@, .Lskip_sve_\@, x1, x2 375 376 .Linit_sve_\@: /* SVE register access */ 377 __check_hvhe .Lcptr_nvhe_\@, x1 378 379 // (h)VHE case 380 mrs x0, cpacr_el1 // Disable SVE traps 381 orr x0, x0, #CPACR_EL1_ZEN 382 msr cpacr_el1, x0 383 b .Lskip_set_cptr_\@ 384 385 .Lcptr_nvhe_\@: // nVHE case 386 mrs x0, cptr_el2 // Disable SVE traps 387 bic x0, x0, #CPTR_EL2_TZ 388 msr cptr_el2, x0 389 .Lskip_set_cptr_\@: 390 isb 391 mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector 392 msr_s SYS_ZCR_EL2, x1 // length for EL1. 393 394 .Lskip_sve_\@: 395 check_override id_aa64pfr1, ID_AA64PFR1_EL1_SME_SHIFT, .Linit_sme_\@, .Lskip_sme_\@, x1, x2 396 397 .Linit_sme_\@: /* SME register access and priority mapping */ 398 __check_hvhe .Lcptr_nvhe_sme_\@, x1 399 400 // (h)VHE case 401 mrs x0, cpacr_el1 // Disable SME traps 402 orr x0, x0, #CPACR_EL1_SMEN 403 msr cpacr_el1, x0 404 b .Lskip_set_cptr_sme_\@ 405 406 .Lcptr_nvhe_sme_\@: // nVHE case 407 mrs x0, cptr_el2 // Disable SME traps 408 bic x0, x0, #CPTR_EL2_TSM 409 msr cptr_el2, x0 410 .Lskip_set_cptr_sme_\@: 411 isb 412 413 mrs x1, sctlr_el2 414 orr x1, x1, #SCTLR_ELx_ENTP2 // Disable TPIDR2 traps 415 msr sctlr_el2, x1 416 isb 417 418 mov x0, #0 // SMCR controls 419 420 // Full FP in SM? 421 mrs_s x1, SYS_ID_AA64SMFR0_EL1 422 __check_override id_aa64smfr0, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, .Linit_sme_fa64_\@, .Lskip_sme_fa64_\@, x1, x2 423 424 .Linit_sme_fa64_\@: 425 orr x0, x0, SMCR_ELx_FA64_MASK 426 .Lskip_sme_fa64_\@: 427 428 // ZT0 available? 429 mrs_s x1, SYS_ID_AA64SMFR0_EL1 430 __check_override id_aa64smfr0, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, .Linit_sme_zt0_\@, .Lskip_sme_zt0_\@, x1, x2 431 .Linit_sme_zt0_\@: 432 orr x0, x0, SMCR_ELx_EZT0_MASK 433 .Lskip_sme_zt0_\@: 434 435 orr x0, x0, #SMCR_ELx_LEN_MASK // Enable full SME vector 436 msr_s SYS_SMCR_EL2, x0 // length for EL1. 437 438 mrs_s x1, SYS_SMIDR_EL1 // Priority mapping supported? 439 ubfx x1, x1, #SMIDR_EL1_SMPS_SHIFT, #1 440 cbz x1, .Lskip_sme_\@ 441 442 msr_s SYS_SMPRIMAP_EL2, xzr // Make all priorities equal 443 .Lskip_sme_\@: 444 .endm 445 446 #endif /* __ARM_KVM_INIT_H__ */ 447