1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 64 <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 65 interconnect-names = "dma-mem", "write"; 66 iommus = <&smmu TEGRA186_SID_EQOS>; 67 status = "disabled"; 68 69 snps,write-requests = <1>; 70 snps,read-requests = <3>; 71 snps,burst-map = <0x7>; 72 snps,txpbl = <32>; 73 snps,rxpbl = <8>; 74 }; 75 76 gpcdma: dma-controller@2600000 { 77 compatible = "nvidia,tegra186-gpcdma"; 78 reg = <0x0 0x2600000 0x0 0x210000>; 79 resets = <&bpmp TEGRA186_RESET_GPCDMA>; 80 reset-names = "gpcdma"; 81 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 113 #dma-cells = <1>; 114 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 115 dma-coherent; 116 dma-channel-mask = <0xfffffffe>; 117 status = "okay"; 118 }; 119 120 aconnect@2900000 { 121 compatible = "nvidia,tegra186-aconnect", 122 "nvidia,tegra210-aconnect"; 123 clocks = <&bpmp TEGRA186_CLK_APE>, 124 <&bpmp TEGRA186_CLK_APB2APE>; 125 clock-names = "ape", "apb2ape"; 126 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 127 #address-cells = <2>; 128 #size-cells = <2>; 129 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 130 status = "disabled"; 131 132 tegra_ahub: ahub@2900800 { 133 compatible = "nvidia,tegra186-ahub"; 134 reg = <0x0 0x02900800 0x0 0x800>; 135 clocks = <&bpmp TEGRA186_CLK_AHUB>; 136 clock-names = "ahub"; 137 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; 138 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 139 assigned-clock-rates = <81600000>; 140 #address-cells = <2>; 141 #size-cells = <2>; 142 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 143 status = "disabled"; 144 145 tegra_i2s1: i2s@2901000 { 146 compatible = "nvidia,tegra186-i2s", 147 "nvidia,tegra210-i2s"; 148 reg = <0x0 0x2901000 0x0 0x100>; 149 clocks = <&bpmp TEGRA186_CLK_I2S1>, 150 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; 151 clock-names = "i2s", "sync_input"; 152 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; 153 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 154 assigned-clock-rates = <1536000>; 155 sound-name-prefix = "I2S1"; 156 status = "disabled"; 157 }; 158 159 tegra_i2s2: i2s@2901100 { 160 compatible = "nvidia,tegra186-i2s", 161 "nvidia,tegra210-i2s"; 162 reg = <0x0 0x2901100 0x0 0x100>; 163 clocks = <&bpmp TEGRA186_CLK_I2S2>, 164 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; 165 clock-names = "i2s", "sync_input"; 166 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; 167 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 168 assigned-clock-rates = <1536000>; 169 sound-name-prefix = "I2S2"; 170 status = "disabled"; 171 }; 172 173 tegra_i2s3: i2s@2901200 { 174 compatible = "nvidia,tegra186-i2s", 175 "nvidia,tegra210-i2s"; 176 reg = <0x0 0x2901200 0x0 0x100>; 177 clocks = <&bpmp TEGRA186_CLK_I2S3>, 178 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; 179 clock-names = "i2s", "sync_input"; 180 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; 181 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 182 assigned-clock-rates = <1536000>; 183 sound-name-prefix = "I2S3"; 184 status = "disabled"; 185 }; 186 187 tegra_i2s4: i2s@2901300 { 188 compatible = "nvidia,tegra186-i2s", 189 "nvidia,tegra210-i2s"; 190 reg = <0x0 0x2901300 0x0 0x100>; 191 clocks = <&bpmp TEGRA186_CLK_I2S4>, 192 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; 193 clock-names = "i2s", "sync_input"; 194 assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; 195 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 196 assigned-clock-rates = <1536000>; 197 sound-name-prefix = "I2S4"; 198 status = "disabled"; 199 }; 200 201 tegra_i2s5: i2s@2901400 { 202 compatible = "nvidia,tegra186-i2s", 203 "nvidia,tegra210-i2s"; 204 reg = <0x0 0x2901400 0x0 0x100>; 205 clocks = <&bpmp TEGRA186_CLK_I2S5>, 206 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; 207 clock-names = "i2s", "sync_input"; 208 assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; 209 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 210 assigned-clock-rates = <1536000>; 211 sound-name-prefix = "I2S5"; 212 status = "disabled"; 213 }; 214 215 tegra_i2s6: i2s@2901500 { 216 compatible = "nvidia,tegra186-i2s", 217 "nvidia,tegra210-i2s"; 218 reg = <0x0 0x2901500 0x0 0x100>; 219 clocks = <&bpmp TEGRA186_CLK_I2S6>, 220 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; 221 clock-names = "i2s", "sync_input"; 222 assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; 223 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 224 assigned-clock-rates = <1536000>; 225 sound-name-prefix = "I2S6"; 226 status = "disabled"; 227 }; 228 229 tegra_sfc1: sfc@2902000 { 230 compatible = "nvidia,tegra186-sfc", 231 "nvidia,tegra210-sfc"; 232 reg = <0x0 0x2902000 0x0 0x200>; 233 sound-name-prefix = "SFC1"; 234 status = "disabled"; 235 }; 236 237 tegra_sfc2: sfc@2902200 { 238 compatible = "nvidia,tegra186-sfc", 239 "nvidia,tegra210-sfc"; 240 reg = <0x0 0x2902200 0x0 0x200>; 241 sound-name-prefix = "SFC2"; 242 status = "disabled"; 243 }; 244 245 tegra_sfc3: sfc@2902400 { 246 compatible = "nvidia,tegra186-sfc", 247 "nvidia,tegra210-sfc"; 248 reg = <0x0 0x2902400 0x0 0x200>; 249 sound-name-prefix = "SFC3"; 250 status = "disabled"; 251 }; 252 253 tegra_sfc4: sfc@2902600 { 254 compatible = "nvidia,tegra186-sfc", 255 "nvidia,tegra210-sfc"; 256 reg = <0x0 0x2902600 0x0 0x200>; 257 sound-name-prefix = "SFC4"; 258 status = "disabled"; 259 }; 260 261 tegra_amx1: amx@2903000 { 262 compatible = "nvidia,tegra186-amx", 263 "nvidia,tegra210-amx"; 264 reg = <0x0 0x2903000 0x0 0x100>; 265 sound-name-prefix = "AMX1"; 266 status = "disabled"; 267 }; 268 269 tegra_amx2: amx@2903100 { 270 compatible = "nvidia,tegra186-amx", 271 "nvidia,tegra210-amx"; 272 reg = <0x0 0x2903100 0x0 0x100>; 273 sound-name-prefix = "AMX2"; 274 status = "disabled"; 275 }; 276 277 tegra_amx3: amx@2903200 { 278 compatible = "nvidia,tegra186-amx", 279 "nvidia,tegra210-amx"; 280 reg = <0x0 0x2903200 0x0 0x100>; 281 sound-name-prefix = "AMX3"; 282 status = "disabled"; 283 }; 284 285 tegra_amx4: amx@2903300 { 286 compatible = "nvidia,tegra186-amx", 287 "nvidia,tegra210-amx"; 288 reg = <0x0 0x2903300 0x0 0x100>; 289 sound-name-prefix = "AMX4"; 290 status = "disabled"; 291 }; 292 293 tegra_adx1: adx@2903800 { 294 compatible = "nvidia,tegra186-adx", 295 "nvidia,tegra210-adx"; 296 reg = <0x0 0x2903800 0x0 0x100>; 297 sound-name-prefix = "ADX1"; 298 status = "disabled"; 299 }; 300 301 tegra_adx2: adx@2903900 { 302 compatible = "nvidia,tegra186-adx", 303 "nvidia,tegra210-adx"; 304 reg = <0x0 0x2903900 0x0 0x100>; 305 sound-name-prefix = "ADX2"; 306 status = "disabled"; 307 }; 308 309 tegra_adx3: adx@2903a00 { 310 compatible = "nvidia,tegra186-adx", 311 "nvidia,tegra210-adx"; 312 reg = <0x0 0x2903a00 0x0 0x100>; 313 sound-name-prefix = "ADX3"; 314 status = "disabled"; 315 }; 316 317 tegra_adx4: adx@2903b00 { 318 compatible = "nvidia,tegra186-adx", 319 "nvidia,tegra210-adx"; 320 reg = <0x0 0x2903b00 0x0 0x100>; 321 sound-name-prefix = "ADX4"; 322 status = "disabled"; 323 }; 324 325 tegra_dmic1: dmic@2904000 { 326 compatible = "nvidia,tegra210-dmic"; 327 reg = <0x0 0x2904000 0x0 0x100>; 328 clocks = <&bpmp TEGRA186_CLK_DMIC1>; 329 clock-names = "dmic"; 330 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; 331 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 332 assigned-clock-rates = <3072000>; 333 sound-name-prefix = "DMIC1"; 334 status = "disabled"; 335 }; 336 337 tegra_dmic2: dmic@2904100 { 338 compatible = "nvidia,tegra210-dmic"; 339 reg = <0x0 0x2904100 0x0 0x100>; 340 clocks = <&bpmp TEGRA186_CLK_DMIC2>; 341 clock-names = "dmic"; 342 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; 343 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 344 assigned-clock-rates = <3072000>; 345 sound-name-prefix = "DMIC2"; 346 status = "disabled"; 347 }; 348 349 tegra_dmic3: dmic@2904200 { 350 compatible = "nvidia,tegra210-dmic"; 351 reg = <0x0 0x2904200 0x0 0x100>; 352 clocks = <&bpmp TEGRA186_CLK_DMIC3>; 353 clock-names = "dmic"; 354 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; 355 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 356 assigned-clock-rates = <3072000>; 357 sound-name-prefix = "DMIC3"; 358 status = "disabled"; 359 }; 360 361 tegra_dmic4: dmic@2904300 { 362 compatible = "nvidia,tegra210-dmic"; 363 reg = <0x0 0x2904300 0x0 0x100>; 364 clocks = <&bpmp TEGRA186_CLK_DMIC4>; 365 clock-names = "dmic"; 366 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; 367 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 368 assigned-clock-rates = <3072000>; 369 sound-name-prefix = "DMIC4"; 370 status = "disabled"; 371 }; 372 373 tegra_dspk1: dspk@2905000 { 374 compatible = "nvidia,tegra186-dspk"; 375 reg = <0x0 0x2905000 0x0 0x100>; 376 clocks = <&bpmp TEGRA186_CLK_DSPK1>; 377 clock-names = "dspk"; 378 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; 379 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 380 assigned-clock-rates = <12288000>; 381 sound-name-prefix = "DSPK1"; 382 status = "disabled"; 383 }; 384 385 tegra_dspk2: dspk@2905100 { 386 compatible = "nvidia,tegra186-dspk"; 387 reg = <0x0 0x2905100 0x0 0x100>; 388 clocks = <&bpmp TEGRA186_CLK_DSPK2>; 389 clock-names = "dspk"; 390 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; 391 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 392 assigned-clock-rates = <12288000>; 393 sound-name-prefix = "DSPK2"; 394 status = "disabled"; 395 }; 396 397 tegra_ope1: processing-engine@2908000 { 398 compatible = "nvidia,tegra186-ope", 399 "nvidia,tegra210-ope"; 400 reg = <0x0 0x2908000 0x0 0x100>; 401 #address-cells = <2>; 402 #size-cells = <2>; 403 ranges; 404 sound-name-prefix = "OPE1"; 405 status = "disabled"; 406 407 equalizer@2908100 { 408 compatible = "nvidia,tegra186-peq", 409 "nvidia,tegra210-peq"; 410 reg = <0x0 0x2908100 0x0 0x100>; 411 }; 412 413 dynamic-range-compressor@2908200 { 414 compatible = "nvidia,tegra186-mbdrc", 415 "nvidia,tegra210-mbdrc"; 416 reg = <0x0 0x2908200 0x0 0x200>; 417 }; 418 }; 419 420 tegra_mvc1: mvc@290a000 { 421 compatible = "nvidia,tegra186-mvc", 422 "nvidia,tegra210-mvc"; 423 reg = <0x0 0x290a000 0x0 0x200>; 424 sound-name-prefix = "MVC1"; 425 status = "disabled"; 426 }; 427 428 tegra_mvc2: mvc@290a200 { 429 compatible = "nvidia,tegra186-mvc", 430 "nvidia,tegra210-mvc"; 431 reg = <0x0 0x290a200 0x0 0x200>; 432 sound-name-prefix = "MVC2"; 433 status = "disabled"; 434 }; 435 436 tegra_amixer: amixer@290bb00 { 437 compatible = "nvidia,tegra186-amixer", 438 "nvidia,tegra210-amixer"; 439 reg = <0x0 0x290bb00 0x0 0x800>; 440 sound-name-prefix = "MIXER1"; 441 status = "disabled"; 442 }; 443 444 tegra_admaif: admaif@290f000 { 445 compatible = "nvidia,tegra186-admaif"; 446 reg = <0x0 0x0290f000 0x0 0x1000>; 447 dmas = <&adma 1>, <&adma 1>, 448 <&adma 2>, <&adma 2>, 449 <&adma 3>, <&adma 3>, 450 <&adma 4>, <&adma 4>, 451 <&adma 5>, <&adma 5>, 452 <&adma 6>, <&adma 6>, 453 <&adma 7>, <&adma 7>, 454 <&adma 8>, <&adma 8>, 455 <&adma 9>, <&adma 9>, 456 <&adma 10>, <&adma 10>, 457 <&adma 11>, <&adma 11>, 458 <&adma 12>, <&adma 12>, 459 <&adma 13>, <&adma 13>, 460 <&adma 14>, <&adma 14>, 461 <&adma 15>, <&adma 15>, 462 <&adma 16>, <&adma 16>, 463 <&adma 17>, <&adma 17>, 464 <&adma 18>, <&adma 18>, 465 <&adma 19>, <&adma 19>, 466 <&adma 20>, <&adma 20>; 467 dma-names = "rx1", "tx1", 468 "rx2", "tx2", 469 "rx3", "tx3", 470 "rx4", "tx4", 471 "rx5", "tx5", 472 "rx6", "tx6", 473 "rx7", "tx7", 474 "rx8", "tx8", 475 "rx9", "tx9", 476 "rx10", "tx10", 477 "rx11", "tx11", 478 "rx12", "tx12", 479 "rx13", "tx13", 480 "rx14", "tx14", 481 "rx15", "tx15", 482 "rx16", "tx16", 483 "rx17", "tx17", 484 "rx18", "tx18", 485 "rx19", "tx19", 486 "rx20", "tx20"; 487 status = "disabled"; 488 }; 489 490 tegra_asrc: asrc@2910000 { 491 compatible = "nvidia,tegra186-asrc"; 492 reg = <0x0 0x2910000 0x0 0x2000>; 493 sound-name-prefix = "ASRC1"; 494 status = "disabled"; 495 }; 496 }; 497 498 adma: dma-controller@2930000 { 499 compatible = "nvidia,tegra186-adma"; 500 reg = <0x0 0x02930000 0x0 0x20000>; 501 interrupt-parent = <&agic>; 502 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 534 #dma-cells = <1>; 535 clocks = <&bpmp TEGRA186_CLK_AHUB>; 536 clock-names = "d_audio"; 537 status = "disabled"; 538 }; 539 540 agic: interrupt-controller@2a40000 { 541 compatible = "nvidia,tegra186-agic", 542 "nvidia,tegra210-agic"; 543 #interrupt-cells = <3>; 544 interrupt-controller; 545 reg = <0x0 0x02a41000 0x0 0x1000>, 546 <0x0 0x02a42000 0x0 0x2000>; 547 interrupts = <GIC_SPI 145 548 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 549 clocks = <&bpmp TEGRA186_CLK_APE>; 550 clock-names = "clk"; 551 status = "disabled"; 552 }; 553 }; 554 555 mc: memory-controller@2c00000 { 556 compatible = "nvidia,tegra186-mc"; 557 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 558 <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ 559 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 560 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 561 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 562 <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ 563 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; 564 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 565 status = "disabled"; 566 567 #interconnect-cells = <1>; 568 #address-cells = <2>; 569 #size-cells = <2>; 570 571 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 572 573 /* 574 * Memory clients have access to all 40 bits that the memory 575 * controller can address. 576 */ 577 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 578 579 emc: external-memory-controller@2c60000 { 580 compatible = "nvidia,tegra186-emc"; 581 reg = <0x0 0x02c60000 0x0 0x50000>; 582 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&bpmp TEGRA186_CLK_EMC>; 584 clock-names = "emc"; 585 586 #interconnect-cells = <0>; 587 588 nvidia,bpmp = <&bpmp>; 589 }; 590 }; 591 592 timer@3010000 { 593 compatible = "nvidia,tegra186-timer"; 594 reg = <0x0 0x03010000 0x0 0x000e0000>; 595 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 605 status = "okay"; 606 }; 607 608 uarta: serial@3100000 { 609 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 610 reg = <0x0 0x03100000 0x0 0x40>; 611 reg-shift = <2>; 612 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&bpmp TEGRA186_CLK_UARTA>; 614 resets = <&bpmp TEGRA186_RESET_UARTA>; 615 dmas = <&gpcdma 8>, <&gpcdma 8>; 616 dma-names = "rx", "tx"; 617 status = "disabled"; 618 }; 619 620 uartb: serial@3110000 { 621 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 622 reg = <0x0 0x03110000 0x0 0x40>; 623 reg-shift = <2>; 624 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 625 clocks = <&bpmp TEGRA186_CLK_UARTB>; 626 resets = <&bpmp TEGRA186_RESET_UARTB>; 627 dmas = <&gpcdma 9>, <&gpcdma 9>; 628 dma-names = "rx", "tx"; 629 status = "disabled"; 630 }; 631 632 uartd: serial@3130000 { 633 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 634 reg = <0x0 0x03130000 0x0 0x40>; 635 reg-shift = <2>; 636 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 637 clocks = <&bpmp TEGRA186_CLK_UARTD>; 638 resets = <&bpmp TEGRA186_RESET_UARTD>; 639 dmas = <&gpcdma 19>, <&gpcdma 19>; 640 dma-names = "rx", "tx"; 641 status = "disabled"; 642 }; 643 644 uarte: serial@3140000 { 645 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 646 reg = <0x0 0x03140000 0x0 0x40>; 647 reg-shift = <2>; 648 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 649 clocks = <&bpmp TEGRA186_CLK_UARTE>; 650 resets = <&bpmp TEGRA186_RESET_UARTE>; 651 dmas = <&gpcdma 20>, <&gpcdma 20>; 652 dma-names = "rx", "tx"; 653 status = "disabled"; 654 }; 655 656 uartf: serial@3150000 { 657 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 658 reg = <0x0 0x03150000 0x0 0x40>; 659 reg-shift = <2>; 660 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 661 clocks = <&bpmp TEGRA186_CLK_UARTF>; 662 resets = <&bpmp TEGRA186_RESET_UARTF>; 663 dmas = <&gpcdma 12>, <&gpcdma 12>; 664 dma-names = "rx", "tx"; 665 status = "disabled"; 666 }; 667 668 gen1_i2c: i2c@3160000 { 669 compatible = "nvidia,tegra186-i2c"; 670 reg = <0x0 0x03160000 0x0 0x10000>; 671 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 672 #address-cells = <1>; 673 #size-cells = <0>; 674 clocks = <&bpmp TEGRA186_CLK_I2C1>; 675 clock-names = "div-clk"; 676 resets = <&bpmp TEGRA186_RESET_I2C1>; 677 reset-names = "i2c"; 678 dmas = <&gpcdma 21>, <&gpcdma 21>; 679 dma-names = "rx", "tx"; 680 status = "disabled"; 681 }; 682 683 cam_i2c: i2c@3180000 { 684 compatible = "nvidia,tegra186-i2c"; 685 reg = <0x0 0x03180000 0x0 0x10000>; 686 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 687 #address-cells = <1>; 688 #size-cells = <0>; 689 clocks = <&bpmp TEGRA186_CLK_I2C3>; 690 clock-names = "div-clk"; 691 resets = <&bpmp TEGRA186_RESET_I2C3>; 692 reset-names = "i2c"; 693 dmas = <&gpcdma 23>, <&gpcdma 23>; 694 dma-names = "rx", "tx"; 695 status = "disabled"; 696 }; 697 698 /* shares pads with dpaux1 */ 699 dp_aux_ch1_i2c: i2c@3190000 { 700 compatible = "nvidia,tegra186-i2c"; 701 reg = <0x0 0x03190000 0x0 0x10000>; 702 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 703 #address-cells = <1>; 704 #size-cells = <0>; 705 clocks = <&bpmp TEGRA186_CLK_I2C4>; 706 clock-names = "div-clk"; 707 resets = <&bpmp TEGRA186_RESET_I2C4>; 708 reset-names = "i2c"; 709 pinctrl-names = "default", "idle"; 710 pinctrl-0 = <&state_dpaux1_i2c>; 711 pinctrl-1 = <&state_dpaux1_off>; 712 dmas = <&gpcdma 26>, <&gpcdma 26>; 713 dma-names = "rx", "tx"; 714 status = "disabled"; 715 }; 716 717 /* controlled by BPMP, should not be enabled */ 718 pwr_i2c: i2c@31a0000 { 719 compatible = "nvidia,tegra186-i2c"; 720 reg = <0x0 0x031a0000 0x0 0x10000>; 721 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 722 #address-cells = <1>; 723 #size-cells = <0>; 724 clocks = <&bpmp TEGRA186_CLK_I2C5>; 725 clock-names = "div-clk"; 726 resets = <&bpmp TEGRA186_RESET_I2C5>; 727 reset-names = "i2c"; 728 status = "disabled"; 729 }; 730 731 /* shares pads with dpaux0 */ 732 dp_aux_ch0_i2c: i2c@31b0000 { 733 compatible = "nvidia,tegra186-i2c"; 734 reg = <0x0 0x031b0000 0x0 0x10000>; 735 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 736 #address-cells = <1>; 737 #size-cells = <0>; 738 clocks = <&bpmp TEGRA186_CLK_I2C6>; 739 clock-names = "div-clk"; 740 resets = <&bpmp TEGRA186_RESET_I2C6>; 741 reset-names = "i2c"; 742 pinctrl-names = "default", "idle"; 743 pinctrl-0 = <&state_dpaux_i2c>; 744 pinctrl-1 = <&state_dpaux_off>; 745 dmas = <&gpcdma 30>, <&gpcdma 30>; 746 dma-names = "rx", "tx"; 747 status = "disabled"; 748 }; 749 750 gen7_i2c: i2c@31c0000 { 751 compatible = "nvidia,tegra186-i2c"; 752 reg = <0x0 0x031c0000 0x0 0x10000>; 753 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 754 #address-cells = <1>; 755 #size-cells = <0>; 756 clocks = <&bpmp TEGRA186_CLK_I2C7>; 757 clock-names = "div-clk"; 758 resets = <&bpmp TEGRA186_RESET_I2C7>; 759 reset-names = "i2c"; 760 dmas = <&gpcdma 27>, <&gpcdma 27>; 761 dma-names = "rx", "tx"; 762 status = "disabled"; 763 }; 764 765 gen9_i2c: i2c@31e0000 { 766 compatible = "nvidia,tegra186-i2c"; 767 reg = <0x0 0x031e0000 0x0 0x10000>; 768 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 769 #address-cells = <1>; 770 #size-cells = <0>; 771 clocks = <&bpmp TEGRA186_CLK_I2C9>; 772 clock-names = "div-clk"; 773 resets = <&bpmp TEGRA186_RESET_I2C9>; 774 reset-names = "i2c"; 775 dmas = <&gpcdma 31>, <&gpcdma 31>; 776 dma-names = "rx", "tx"; 777 status = "disabled"; 778 }; 779 780 pwm1: pwm@3280000 { 781 compatible = "nvidia,tegra186-pwm"; 782 reg = <0x0 0x3280000 0x0 0x10000>; 783 clocks = <&bpmp TEGRA186_CLK_PWM1>; 784 resets = <&bpmp TEGRA186_RESET_PWM1>; 785 reset-names = "pwm"; 786 status = "disabled"; 787 #pwm-cells = <2>; 788 }; 789 790 pwm2: pwm@3290000 { 791 compatible = "nvidia,tegra186-pwm"; 792 reg = <0x0 0x3290000 0x0 0x10000>; 793 clocks = <&bpmp TEGRA186_CLK_PWM2>; 794 resets = <&bpmp TEGRA186_RESET_PWM2>; 795 reset-names = "pwm"; 796 status = "disabled"; 797 #pwm-cells = <2>; 798 }; 799 800 pwm3: pwm@32a0000 { 801 compatible = "nvidia,tegra186-pwm"; 802 reg = <0x0 0x32a0000 0x0 0x10000>; 803 clocks = <&bpmp TEGRA186_CLK_PWM3>; 804 resets = <&bpmp TEGRA186_RESET_PWM3>; 805 reset-names = "pwm"; 806 status = "disabled"; 807 #pwm-cells = <2>; 808 }; 809 810 pwm5: pwm@32c0000 { 811 compatible = "nvidia,tegra186-pwm"; 812 reg = <0x0 0x32c0000 0x0 0x10000>; 813 clocks = <&bpmp TEGRA186_CLK_PWM5>; 814 resets = <&bpmp TEGRA186_RESET_PWM5>; 815 reset-names = "pwm"; 816 status = "disabled"; 817 #pwm-cells = <2>; 818 }; 819 820 pwm6: pwm@32d0000 { 821 compatible = "nvidia,tegra186-pwm"; 822 reg = <0x0 0x32d0000 0x0 0x10000>; 823 clocks = <&bpmp TEGRA186_CLK_PWM6>; 824 resets = <&bpmp TEGRA186_RESET_PWM6>; 825 reset-names = "pwm"; 826 status = "disabled"; 827 #pwm-cells = <2>; 828 }; 829 830 pwm7: pwm@32e0000 { 831 compatible = "nvidia,tegra186-pwm"; 832 reg = <0x0 0x32e0000 0x0 0x10000>; 833 clocks = <&bpmp TEGRA186_CLK_PWM7>; 834 resets = <&bpmp TEGRA186_RESET_PWM7>; 835 reset-names = "pwm"; 836 status = "disabled"; 837 #pwm-cells = <2>; 838 }; 839 840 pwm8: pwm@32f0000 { 841 compatible = "nvidia,tegra186-pwm"; 842 reg = <0x0 0x32f0000 0x0 0x10000>; 843 clocks = <&bpmp TEGRA186_CLK_PWM8>; 844 resets = <&bpmp TEGRA186_RESET_PWM8>; 845 reset-names = "pwm"; 846 status = "disabled"; 847 #pwm-cells = <2>; 848 }; 849 850 sdmmc1: mmc@3400000 { 851 compatible = "nvidia,tegra186-sdhci"; 852 reg = <0x0 0x03400000 0x0 0x10000>; 853 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 854 clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 855 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 856 clock-names = "sdhci", "tmclk"; 857 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 858 reset-names = "sdhci"; 859 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 860 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 861 interconnect-names = "dma-mem", "write"; 862 iommus = <&smmu TEGRA186_SID_SDMMC1>; 863 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 864 pinctrl-0 = <&sdmmc1_3v3>; 865 pinctrl-1 = <&sdmmc1_1v8>; 866 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 867 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 868 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 869 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 870 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 871 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 872 nvidia,default-tap = <0x5>; 873 nvidia,default-trim = <0xb>; 874 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 875 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 876 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 877 status = "disabled"; 878 }; 879 880 sdmmc2: mmc@3420000 { 881 compatible = "nvidia,tegra186-sdhci"; 882 reg = <0x0 0x03420000 0x0 0x10000>; 883 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 884 clocks = <&bpmp TEGRA186_CLK_SDMMC2>, 885 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 886 clock-names = "sdhci", "tmclk"; 887 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 888 reset-names = "sdhci"; 889 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 890 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 891 interconnect-names = "dma-mem", "write"; 892 iommus = <&smmu TEGRA186_SID_SDMMC2>; 893 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 894 pinctrl-0 = <&sdmmc2_3v3>; 895 pinctrl-1 = <&sdmmc2_1v8>; 896 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 897 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 898 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 899 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 900 nvidia,default-tap = <0x5>; 901 nvidia,default-trim = <0xb>; 902 status = "disabled"; 903 }; 904 905 sdmmc3: mmc@3440000 { 906 compatible = "nvidia,tegra186-sdhci"; 907 reg = <0x0 0x03440000 0x0 0x10000>; 908 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 909 clocks = <&bpmp TEGRA186_CLK_SDMMC3>, 910 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 911 clock-names = "sdhci", "tmclk"; 912 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 913 reset-names = "sdhci"; 914 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 915 <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 916 interconnect-names = "dma-mem", "write"; 917 iommus = <&smmu TEGRA186_SID_SDMMC3>; 918 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 919 pinctrl-0 = <&sdmmc3_3v3>; 920 pinctrl-1 = <&sdmmc3_1v8>; 921 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 922 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 923 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 924 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 925 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 926 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 927 nvidia,default-tap = <0x5>; 928 nvidia,default-trim = <0xb>; 929 status = "disabled"; 930 }; 931 932 sdmmc4: mmc@3460000 { 933 compatible = "nvidia,tegra186-sdhci"; 934 reg = <0x0 0x03460000 0x0 0x10000>; 935 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 936 clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 937 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 938 clock-names = "sdhci", "tmclk"; 939 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 940 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 941 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 942 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 943 reset-names = "sdhci"; 944 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 945 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 946 interconnect-names = "dma-mem", "write"; 947 iommus = <&smmu TEGRA186_SID_SDMMC4>; 948 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 949 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 950 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 951 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 952 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 953 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 954 nvidia,default-tap = <0x9>; 955 nvidia,default-trim = <0x5>; 956 nvidia,dqs-trim = <63>; 957 mmc-hs400-1_8v; 958 supports-cqe; 959 status = "disabled"; 960 }; 961 962 sata@3507000 { 963 compatible = "nvidia,tegra186-ahci"; 964 reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ 965 <0x0 0x03500000 0x0 0x00007000>, /* SATA */ 966 <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ 967 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 968 969 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; 970 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, 971 <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; 972 interconnect-names = "dma-mem", "write"; 973 iommus = <&smmu TEGRA186_SID_SATA>; 974 975 clocks = <&bpmp TEGRA186_CLK_SATA>, 976 <&bpmp TEGRA186_CLK_SATA_OOB>; 977 clock-names = "sata", "sata-oob"; 978 assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, 979 <&bpmp TEGRA186_CLK_SATA_OOB>; 980 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, 981 <&bpmp TEGRA186_CLK_PLLP>; 982 assigned-clock-rates = <102000000>, 983 <204000000>; 984 resets = <&bpmp TEGRA186_RESET_SATA>, 985 <&bpmp TEGRA186_RESET_SATACOLD>; 986 reset-names = "sata", "sata-cold"; 987 status = "disabled"; 988 }; 989 990 hda@3510000 { 991 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 992 reg = <0x0 0x03510000 0x0 0x10000>; 993 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 994 clocks = <&bpmp TEGRA186_CLK_HDA>, 995 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 996 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 997 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 998 resets = <&bpmp TEGRA186_RESET_HDA>, 999 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 1000 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 1001 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 1002 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1003 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 1004 <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 1005 interconnect-names = "dma-mem", "write"; 1006 iommus = <&smmu TEGRA186_SID_HDA>; 1007 status = "disabled"; 1008 }; 1009 1010 padctl: padctl@3520000 { 1011 compatible = "nvidia,tegra186-xusb-padctl"; 1012 reg = <0x0 0x03520000 0x0 0x1000>, 1013 <0x0 0x03540000 0x0 0x1000>; 1014 reg-names = "padctl", "ao"; 1015 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1016 1017 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 1018 reset-names = "padctl"; 1019 1020 status = "disabled"; 1021 1022 pads { 1023 usb2 { 1024 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 1025 clock-names = "trk"; 1026 status = "disabled"; 1027 1028 lanes { 1029 usb2-0 { 1030 status = "disabled"; 1031 #phy-cells = <0>; 1032 }; 1033 1034 usb2-1 { 1035 status = "disabled"; 1036 #phy-cells = <0>; 1037 }; 1038 1039 usb2-2 { 1040 status = "disabled"; 1041 #phy-cells = <0>; 1042 }; 1043 }; 1044 }; 1045 1046 hsic { 1047 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 1048 clock-names = "trk"; 1049 status = "disabled"; 1050 1051 lanes { 1052 hsic-0 { 1053 status = "disabled"; 1054 #phy-cells = <0>; 1055 }; 1056 }; 1057 }; 1058 1059 usb3 { 1060 status = "disabled"; 1061 1062 lanes { 1063 usb3-0 { 1064 status = "disabled"; 1065 #phy-cells = <0>; 1066 }; 1067 1068 usb3-1 { 1069 status = "disabled"; 1070 #phy-cells = <0>; 1071 }; 1072 1073 usb3-2 { 1074 status = "disabled"; 1075 #phy-cells = <0>; 1076 }; 1077 }; 1078 }; 1079 }; 1080 1081 ports { 1082 usb2-0 { 1083 status = "disabled"; 1084 }; 1085 1086 usb2-1 { 1087 status = "disabled"; 1088 }; 1089 1090 usb2-2 { 1091 status = "disabled"; 1092 }; 1093 1094 hsic-0 { 1095 status = "disabled"; 1096 }; 1097 1098 usb3-0 { 1099 status = "disabled"; 1100 }; 1101 1102 usb3-1 { 1103 status = "disabled"; 1104 }; 1105 1106 usb3-2 { 1107 status = "disabled"; 1108 }; 1109 }; 1110 }; 1111 1112 usb@3530000 { 1113 compatible = "nvidia,tegra186-xusb"; 1114 reg = <0x0 0x03530000 0x0 0x8000>, 1115 <0x0 0x03538000 0x0 0x1000>; 1116 reg-names = "hcd", "fpci"; 1117 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1119 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 1120 <&bpmp TEGRA186_CLK_XUSB_FALCON>, 1121 <&bpmp TEGRA186_CLK_XUSB_SS>, 1122 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1123 <&bpmp TEGRA186_CLK_CLK_M>, 1124 <&bpmp TEGRA186_CLK_XUSB_FS>, 1125 <&bpmp TEGRA186_CLK_PLLU>, 1126 <&bpmp TEGRA186_CLK_CLK_M>, 1127 <&bpmp TEGRA186_CLK_PLLE>; 1128 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 1129 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 1130 "pll_u_480m", "clk_m", "pll_e"; 1131 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 1132 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1133 power-domain-names = "xusb_host", "xusb_ss"; 1134 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1135 <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1136 interconnect-names = "dma-mem", "write"; 1137 iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 status = "disabled"; 1141 1142 nvidia,xusb-padctl = <&padctl>; 1143 }; 1144 1145 usb@3550000 { 1146 compatible = "nvidia,tegra186-xudc"; 1147 reg = <0x0 0x03550000 0x0 0x8000>, 1148 <0x0 0x03558000 0x0 0x1000>; 1149 reg-names = "base", "fpci"; 1150 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1151 clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 1152 <&bpmp TEGRA186_CLK_XUSB_SS>, 1153 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1154 <&bpmp TEGRA186_CLK_XUSB_FS>; 1155 clock-names = "dev", "ss", "ss_src", "fs_src"; 1156 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>, 1157 <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>; 1158 interconnect-names = "dma-mem", "write"; 1159 iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 1160 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 1161 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1162 power-domain-names = "dev", "ss"; 1163 nvidia,xusb-padctl = <&padctl>; 1164 status = "disabled"; 1165 }; 1166 1167 fuse@3820000 { 1168 compatible = "nvidia,tegra186-efuse"; 1169 reg = <0x0 0x03820000 0x0 0x10000>; 1170 clocks = <&bpmp TEGRA186_CLK_FUSE>; 1171 clock-names = "fuse"; 1172 }; 1173 1174 gic: interrupt-controller@3881000 { 1175 compatible = "arm,gic-400"; 1176 #interrupt-cells = <3>; 1177 interrupt-controller; 1178 reg = <0x0 0x03881000 0x0 0x1000>, 1179 <0x0 0x03882000 0x0 0x2000>, 1180 <0x0 0x03884000 0x0 0x2000>, 1181 <0x0 0x03886000 0x0 0x2000>; 1182 interrupts = <GIC_PPI 9 1183 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1184 interrupt-parent = <&gic>; 1185 }; 1186 1187 cec@3960000 { 1188 compatible = "nvidia,tegra186-cec", "nvidia,tegra210-cec"; 1189 reg = <0x0 0x03960000 0x0 0x10000>; 1190 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1191 clocks = <&bpmp TEGRA186_CLK_CEC>; 1192 clock-names = "cec"; 1193 status = "disabled"; 1194 }; 1195 1196 hsp_top0: hsp@3c00000 { 1197 compatible = "nvidia,tegra186-hsp"; 1198 reg = <0x0 0x03c00000 0x0 0xa0000>; 1199 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1200 interrupt-names = "doorbell"; 1201 #mbox-cells = <2>; 1202 status = "disabled"; 1203 }; 1204 1205 gen2_i2c: i2c@c240000 { 1206 compatible = "nvidia,tegra186-i2c"; 1207 reg = <0x0 0x0c240000 0x0 0x10000>; 1208 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1209 #address-cells = <1>; 1210 #size-cells = <0>; 1211 clocks = <&bpmp TEGRA186_CLK_I2C2>; 1212 clock-names = "div-clk"; 1213 resets = <&bpmp TEGRA186_RESET_I2C2>; 1214 reset-names = "i2c"; 1215 dmas = <&gpcdma 22>, <&gpcdma 22>; 1216 dma-names = "rx", "tx"; 1217 status = "disabled"; 1218 }; 1219 1220 gen8_i2c: i2c@c250000 { 1221 compatible = "nvidia,tegra186-i2c"; 1222 reg = <0x0 0x0c250000 0x0 0x10000>; 1223 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1224 #address-cells = <1>; 1225 #size-cells = <0>; 1226 clocks = <&bpmp TEGRA186_CLK_I2C8>; 1227 clock-names = "div-clk"; 1228 resets = <&bpmp TEGRA186_RESET_I2C8>; 1229 reset-names = "i2c"; 1230 dmas = <&gpcdma 0>, <&gpcdma 0>; 1231 dma-names = "rx", "tx"; 1232 status = "disabled"; 1233 }; 1234 1235 uartc: serial@c280000 { 1236 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1237 reg = <0x0 0x0c280000 0x0 0x40>; 1238 reg-shift = <2>; 1239 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1240 clocks = <&bpmp TEGRA186_CLK_UARTC>; 1241 resets = <&bpmp TEGRA186_RESET_UARTC>; 1242 dmas = <&gpcdma 3>, <&gpcdma 3>; 1243 dma-names = "rx", "tx"; 1244 status = "disabled"; 1245 }; 1246 1247 uartg: serial@c290000 { 1248 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1249 reg = <0x0 0x0c290000 0x0 0x40>; 1250 reg-shift = <2>; 1251 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1252 clocks = <&bpmp TEGRA186_CLK_UARTG>; 1253 resets = <&bpmp TEGRA186_RESET_UARTG>; 1254 dmas = <&gpcdma 2>, <&gpcdma 2>; 1255 dma-names = "rx", "tx"; 1256 status = "disabled"; 1257 }; 1258 1259 rtc: rtc@c2a0000 { 1260 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 1261 reg = <0 0x0c2a0000 0 0x10000>; 1262 interrupt-parent = <&pmc>; 1263 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1264 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 1265 clock-names = "rtc"; 1266 status = "disabled"; 1267 }; 1268 1269 gpio_aon: gpio@c2f0000 { 1270 compatible = "nvidia,tegra186-gpio-aon"; 1271 reg-names = "security", "gpio"; 1272 reg = <0x0 0xc2f0000 0x0 0x1000>, 1273 <0x0 0xc2f1000 0x0 0x1000>; 1274 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1275 gpio-controller; 1276 #gpio-cells = <2>; 1277 interrupt-controller; 1278 #interrupt-cells = <2>; 1279 }; 1280 1281 pwm4: pwm@c340000 { 1282 compatible = "nvidia,tegra186-pwm"; 1283 reg = <0x0 0xc340000 0x0 0x10000>; 1284 clocks = <&bpmp TEGRA186_CLK_PWM4>; 1285 resets = <&bpmp TEGRA186_RESET_PWM4>; 1286 reset-names = "pwm"; 1287 status = "disabled"; 1288 #pwm-cells = <2>; 1289 }; 1290 1291 pmc: pmc@c360000 { 1292 compatible = "nvidia,tegra186-pmc"; 1293 reg = <0 0x0c360000 0 0x10000>, 1294 <0 0x0c370000 0 0x10000>, 1295 <0 0x0c380000 0 0x10000>, 1296 <0 0x0c390000 0 0x10000>; 1297 reg-names = "pmc", "wake", "aotag", "scratch"; 1298 1299 #interrupt-cells = <2>; 1300 interrupt-controller; 1301 1302 sdmmc1_1v8: sdmmc1-1v8 { 1303 pins = "sdmmc1-hv"; 1304 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1305 }; 1306 1307 sdmmc1_3v3: sdmmc1-3v3 { 1308 pins = "sdmmc1-hv"; 1309 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1310 }; 1311 1312 sdmmc2_1v8: sdmmc2-1v8 { 1313 pins = "sdmmc2-hv"; 1314 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1315 }; 1316 1317 sdmmc2_3v3: sdmmc2-3v3 { 1318 pins = "sdmmc2-hv"; 1319 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1320 }; 1321 1322 sdmmc3_1v8: sdmmc3-1v8 { 1323 pins = "sdmmc3-hv"; 1324 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1325 }; 1326 1327 sdmmc3_3v3: sdmmc3-3v3 { 1328 pins = "sdmmc3-hv"; 1329 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1330 }; 1331 }; 1332 1333 ccplex@e000000 { 1334 compatible = "nvidia,tegra186-ccplex-cluster"; 1335 reg = <0x0 0x0e000000 0x0 0x400000>; 1336 1337 nvidia,bpmp = <&bpmp>; 1338 }; 1339 1340 pcie@10003000 { 1341 compatible = "nvidia,tegra186-pcie"; 1342 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 1343 device_type = "pci"; 1344 reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 1345 <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 1346 <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 1347 reg-names = "pads", "afi", "cs"; 1348 1349 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1350 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1351 interrupt-names = "intr", "msi"; 1352 1353 #interrupt-cells = <1>; 1354 interrupt-map-mask = <0 0 0 0>; 1355 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1356 1357 bus-range = <0x00 0xff>; 1358 #address-cells = <3>; 1359 #size-cells = <2>; 1360 1361 ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 1362 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 1363 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 1364 <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 1365 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 1366 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 1367 1368 clocks = <&bpmp TEGRA186_CLK_PCIE>, 1369 <&bpmp TEGRA186_CLK_AFI>, 1370 <&bpmp TEGRA186_CLK_PLLE>; 1371 clock-names = "pex", "afi", "pll_e"; 1372 1373 resets = <&bpmp TEGRA186_RESET_PCIE>, 1374 <&bpmp TEGRA186_RESET_AFI>, 1375 <&bpmp TEGRA186_RESET_PCIEXCLK>; 1376 reset-names = "pex", "afi", "pcie_x"; 1377 1378 interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 1379 <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 1380 interconnect-names = "dma-mem", "write"; 1381 1382 iommus = <&smmu TEGRA186_SID_AFI>; 1383 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 1384 iommu-map-mask = <0x0>; 1385 1386 status = "disabled"; 1387 1388 pci@1,0 { 1389 device_type = "pci"; 1390 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 1391 reg = <0x000800 0 0 0 0>; 1392 status = "disabled"; 1393 1394 #address-cells = <3>; 1395 #size-cells = <2>; 1396 ranges; 1397 1398 nvidia,num-lanes = <2>; 1399 }; 1400 1401 pci@2,0 { 1402 device_type = "pci"; 1403 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 1404 reg = <0x001000 0 0 0 0>; 1405 status = "disabled"; 1406 1407 #address-cells = <3>; 1408 #size-cells = <2>; 1409 ranges; 1410 1411 nvidia,num-lanes = <1>; 1412 }; 1413 1414 pci@3,0 { 1415 device_type = "pci"; 1416 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 1417 reg = <0x001800 0 0 0 0>; 1418 status = "disabled"; 1419 1420 #address-cells = <3>; 1421 #size-cells = <2>; 1422 ranges; 1423 1424 nvidia,num-lanes = <1>; 1425 }; 1426 }; 1427 1428 smmu: iommu@12000000 { 1429 compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500"; 1430 reg = <0 0x12000000 0 0x800000>; 1431 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1436 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1437 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1438 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1439 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1440 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1441 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1493 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1496 stream-match-mask = <0x7f80>; 1497 #global-interrupts = <1>; 1498 #iommu-cells = <1>; 1499 1500 nvidia,memory-controller = <&mc>; 1501 }; 1502 1503 host1x@13e00000 { 1504 compatible = "nvidia,tegra186-host1x"; 1505 reg = <0x0 0x13e00000 0x0 0x10000>, 1506 <0x0 0x13e10000 0x0 0x10000>; 1507 reg-names = "hypervisor", "vm"; 1508 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1510 interrupt-names = "syncpt", "host1x"; 1511 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 1512 clock-names = "host1x"; 1513 resets = <&bpmp TEGRA186_RESET_HOST1X>; 1514 reset-names = "host1x"; 1515 1516 #address-cells = <2>; 1517 #size-cells = <2>; 1518 1519 ranges = <0x0 0x15000000 0x0 0x15000000 0x0 0x01000000>; 1520 1521 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 1522 interconnect-names = "dma-mem"; 1523 1524 iommus = <&smmu TEGRA186_SID_HOST1X>; 1525 1526 /* Context isolation domains */ 1527 iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>, 1528 <1 &smmu TEGRA186_SID_HOST1X_CTX1 1>, 1529 <2 &smmu TEGRA186_SID_HOST1X_CTX2 1>, 1530 <3 &smmu TEGRA186_SID_HOST1X_CTX3 1>, 1531 <4 &smmu TEGRA186_SID_HOST1X_CTX4 1>, 1532 <5 &smmu TEGRA186_SID_HOST1X_CTX5 1>, 1533 <6 &smmu TEGRA186_SID_HOST1X_CTX6 1>, 1534 <7 &smmu TEGRA186_SID_HOST1X_CTX7 1>; 1535 1536 dpaux1: dpaux@15040000 { 1537 compatible = "nvidia,tegra186-dpaux"; 1538 reg = <0x0 0x15040000 0x0 0x10000>; 1539 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1540 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 1541 <&bpmp TEGRA186_CLK_PLLDP>; 1542 clock-names = "dpaux", "parent"; 1543 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 1544 reset-names = "dpaux"; 1545 status = "disabled"; 1546 1547 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1548 1549 state_dpaux1_aux: pinmux-aux { 1550 groups = "dpaux-io"; 1551 function = "aux"; 1552 }; 1553 1554 state_dpaux1_i2c: pinmux-i2c { 1555 groups = "dpaux-io"; 1556 function = "i2c"; 1557 }; 1558 1559 state_dpaux1_off: pinmux-off { 1560 groups = "dpaux-io"; 1561 function = "off"; 1562 }; 1563 1564 i2c-bus { 1565 #address-cells = <1>; 1566 #size-cells = <0>; 1567 }; 1568 }; 1569 1570 display-hub@15200000 { 1571 compatible = "nvidia,tegra186-display"; 1572 reg = <0x0 0x15200000 0x0 0x00040000>; 1573 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 1574 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 1575 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 1576 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 1577 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1578 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1579 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1580 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1581 "wgrp3", "wgrp4", "wgrp5"; 1582 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1583 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1584 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1585 clock-names = "disp", "dsc", "hub"; 1586 status = "disabled"; 1587 1588 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1589 1590 #address-cells = <2>; 1591 #size-cells = <2>; 1592 1593 ranges = <0x0 0x15200000 0x0 0x15200000 0x0 0x40000>; 1594 1595 display@15200000 { 1596 compatible = "nvidia,tegra186-dc"; 1597 reg = <0x0 0x15200000 0x0 0x10000>; 1598 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1599 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1600 clock-names = "dc"; 1601 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1602 reset-names = "dc"; 1603 1604 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1605 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1606 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1607 interconnect-names = "dma-mem", "read-1"; 1608 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1609 1610 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1611 nvidia,head = <0>; 1612 }; 1613 1614 display@15210000 { 1615 compatible = "nvidia,tegra186-dc"; 1616 reg = <0x0 0x15210000 0x0 0x10000>; 1617 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1618 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1619 clock-names = "dc"; 1620 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1621 reset-names = "dc"; 1622 1623 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1624 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1625 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1626 interconnect-names = "dma-mem", "read-1"; 1627 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1628 1629 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1630 nvidia,head = <1>; 1631 }; 1632 1633 display@15220000 { 1634 compatible = "nvidia,tegra186-dc"; 1635 reg = <0x0 0x15220000 0x0 0x10000>; 1636 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1637 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1638 clock-names = "dc"; 1639 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1640 reset-names = "dc"; 1641 1642 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1643 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1644 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1645 interconnect-names = "dma-mem", "read-1"; 1646 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1647 1648 nvidia,outputs = <&sor0 &sor1>; 1649 nvidia,head = <2>; 1650 }; 1651 }; 1652 1653 dsia: dsi@15300000 { 1654 compatible = "nvidia,tegra186-dsi"; 1655 reg = <0x0 0x15300000 0x0 0x10000>; 1656 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1657 clocks = <&bpmp TEGRA186_CLK_DSI>, 1658 <&bpmp TEGRA186_CLK_DSIA_LP>, 1659 <&bpmp TEGRA186_CLK_PLLD>; 1660 clock-names = "dsi", "lp", "parent"; 1661 resets = <&bpmp TEGRA186_RESET_DSI>; 1662 reset-names = "dsi"; 1663 status = "disabled"; 1664 1665 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1666 }; 1667 1668 vic@15340000 { 1669 compatible = "nvidia,tegra186-vic"; 1670 reg = <0x0 0x15340000 0x0 0x40000>; 1671 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1672 clocks = <&bpmp TEGRA186_CLK_VIC>; 1673 clock-names = "vic"; 1674 resets = <&bpmp TEGRA186_RESET_VIC>; 1675 reset-names = "vic"; 1676 1677 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1678 interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1679 <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1680 interconnect-names = "dma-mem", "write"; 1681 iommus = <&smmu TEGRA186_SID_VIC>; 1682 }; 1683 1684 nvjpg@15380000 { 1685 compatible = "nvidia,tegra186-nvjpg"; 1686 reg = <0x0 0x15380000 0x0 0x40000>; 1687 clocks = <&bpmp TEGRA186_CLK_NVJPG>; 1688 clock-names = "nvjpg"; 1689 resets = <&bpmp TEGRA186_RESET_NVJPG>; 1690 reset-names = "nvjpg"; 1691 1692 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; 1693 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, 1694 <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; 1695 interconnect-names = "dma-mem", "write"; 1696 iommus = <&smmu TEGRA186_SID_NVJPG>; 1697 }; 1698 1699 dsib: dsi@15400000 { 1700 compatible = "nvidia,tegra186-dsi"; 1701 reg = <0x0 0x15400000 0x0 0x10000>; 1702 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1703 clocks = <&bpmp TEGRA186_CLK_DSIB>, 1704 <&bpmp TEGRA186_CLK_DSIB_LP>, 1705 <&bpmp TEGRA186_CLK_PLLD>; 1706 clock-names = "dsi", "lp", "parent"; 1707 resets = <&bpmp TEGRA186_RESET_DSIB>; 1708 reset-names = "dsi"; 1709 status = "disabled"; 1710 1711 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1712 }; 1713 1714 nvdec@15480000 { 1715 compatible = "nvidia,tegra186-nvdec"; 1716 reg = <0x0 0x15480000 0x0 0x40000>; 1717 clocks = <&bpmp TEGRA186_CLK_NVDEC>; 1718 clock-names = "nvdec"; 1719 resets = <&bpmp TEGRA186_RESET_NVDEC>; 1720 reset-names = "nvdec"; 1721 1722 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>; 1723 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>, 1724 <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>, 1725 <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>; 1726 interconnect-names = "dma-mem", "read-1", "write"; 1727 iommus = <&smmu TEGRA186_SID_NVDEC>; 1728 }; 1729 1730 nvenc@154c0000 { 1731 compatible = "nvidia,tegra186-nvenc"; 1732 reg = <0x0 0x154c0000 0x0 0x40000>; 1733 clocks = <&bpmp TEGRA186_CLK_NVENC>; 1734 clock-names = "nvenc"; 1735 resets = <&bpmp TEGRA186_RESET_NVENC>; 1736 reset-names = "nvenc"; 1737 1738 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; 1739 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, 1740 <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; 1741 interconnect-names = "dma-mem", "write"; 1742 iommus = <&smmu TEGRA186_SID_NVENC>; 1743 }; 1744 1745 sor0: sor@15540000 { 1746 compatible = "nvidia,tegra186-sor"; 1747 reg = <0x0 0x15540000 0x0 0x10000>; 1748 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1749 clocks = <&bpmp TEGRA186_CLK_SOR0>, 1750 <&bpmp TEGRA186_CLK_SOR0_OUT>, 1751 <&bpmp TEGRA186_CLK_PLLD2>, 1752 <&bpmp TEGRA186_CLK_PLLDP>, 1753 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1754 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1755 clock-names = "sor", "out", "parent", "dp", "safe", 1756 "pad"; 1757 resets = <&bpmp TEGRA186_RESET_SOR0>; 1758 reset-names = "sor"; 1759 pinctrl-0 = <&state_dpaux_aux>; 1760 pinctrl-1 = <&state_dpaux_i2c>; 1761 pinctrl-2 = <&state_dpaux_off>; 1762 pinctrl-names = "aux", "i2c", "off"; 1763 status = "disabled"; 1764 1765 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1766 nvidia,interface = <0>; 1767 }; 1768 1769 sor1: sor@15580000 { 1770 compatible = "nvidia,tegra186-sor"; 1771 reg = <0x0 0x15580000 0x0 0x10000>; 1772 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1773 clocks = <&bpmp TEGRA186_CLK_SOR1>, 1774 <&bpmp TEGRA186_CLK_SOR1_OUT>, 1775 <&bpmp TEGRA186_CLK_PLLD3>, 1776 <&bpmp TEGRA186_CLK_PLLDP>, 1777 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1778 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1779 clock-names = "sor", "out", "parent", "dp", "safe", 1780 "pad"; 1781 resets = <&bpmp TEGRA186_RESET_SOR1>; 1782 reset-names = "sor"; 1783 pinctrl-0 = <&state_dpaux1_aux>; 1784 pinctrl-1 = <&state_dpaux1_i2c>; 1785 pinctrl-2 = <&state_dpaux1_off>; 1786 pinctrl-names = "aux", "i2c", "off"; 1787 status = "disabled"; 1788 1789 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1790 nvidia,interface = <1>; 1791 }; 1792 1793 dpaux: dpaux@155c0000 { 1794 compatible = "nvidia,tegra186-dpaux"; 1795 reg = <0x0 0x155c0000 0x0 0x10000>; 1796 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1797 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1798 <&bpmp TEGRA186_CLK_PLLDP>; 1799 clock-names = "dpaux", "parent"; 1800 resets = <&bpmp TEGRA186_RESET_DPAUX>; 1801 reset-names = "dpaux"; 1802 status = "disabled"; 1803 1804 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1805 1806 state_dpaux_aux: pinmux-aux { 1807 groups = "dpaux-io"; 1808 function = "aux"; 1809 }; 1810 1811 state_dpaux_i2c: pinmux-i2c { 1812 groups = "dpaux-io"; 1813 function = "i2c"; 1814 }; 1815 1816 state_dpaux_off: pinmux-off { 1817 groups = "dpaux-io"; 1818 function = "off"; 1819 }; 1820 1821 i2c-bus { 1822 #address-cells = <1>; 1823 #size-cells = <0>; 1824 }; 1825 }; 1826 1827 padctl@15880000 { 1828 compatible = "nvidia,tegra186-dsi-padctl"; 1829 reg = <0x0 0x15880000 0x0 0x10000>; 1830 resets = <&bpmp TEGRA186_RESET_DSI>; 1831 reset-names = "dsi"; 1832 status = "disabled"; 1833 }; 1834 1835 dsic: dsi@15900000 { 1836 compatible = "nvidia,tegra186-dsi"; 1837 reg = <0x0 0x15900000 0x0 0x10000>; 1838 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1839 clocks = <&bpmp TEGRA186_CLK_DSIC>, 1840 <&bpmp TEGRA186_CLK_DSIC_LP>, 1841 <&bpmp TEGRA186_CLK_PLLD>; 1842 clock-names = "dsi", "lp", "parent"; 1843 resets = <&bpmp TEGRA186_RESET_DSIC>; 1844 reset-names = "dsi"; 1845 status = "disabled"; 1846 1847 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1848 }; 1849 1850 dsid: dsi@15940000 { 1851 compatible = "nvidia,tegra186-dsi"; 1852 reg = <0x0 0x15940000 0x0 0x10000>; 1853 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1854 clocks = <&bpmp TEGRA186_CLK_DSID>, 1855 <&bpmp TEGRA186_CLK_DSID_LP>, 1856 <&bpmp TEGRA186_CLK_PLLD>; 1857 clock-names = "dsi", "lp", "parent"; 1858 resets = <&bpmp TEGRA186_RESET_DSID>; 1859 reset-names = "dsi"; 1860 status = "disabled"; 1861 1862 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1863 }; 1864 }; 1865 1866 gpu@17000000 { 1867 compatible = "nvidia,gp10b"; 1868 reg = <0x0 0x17000000 0x0 0x1000000>, 1869 <0x0 0x18000000 0x0 0x1000000>; 1870 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1872 interrupt-names = "stall", "nonstall"; 1873 1874 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1875 <&bpmp TEGRA186_CLK_GPU>; 1876 clock-names = "gpu", "pwr"; 1877 resets = <&bpmp TEGRA186_RESET_GPU>; 1878 reset-names = "gpu"; 1879 status = "disabled"; 1880 1881 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1882 interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1883 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1884 <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1885 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1886 interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1887 }; 1888 1889 sram@30000000 { 1890 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 1891 reg = <0x0 0x30000000 0x0 0x50000>; 1892 #address-cells = <1>; 1893 #size-cells = <1>; 1894 ranges = <0x0 0x0 0x30000000 0x50000>; 1895 no-memory-wc; 1896 1897 cpu_bpmp_tx: sram@4e000 { 1898 reg = <0x4e000 0x1000>; 1899 label = "cpu-bpmp-tx"; 1900 pool; 1901 }; 1902 1903 cpu_bpmp_rx: sram@4f000 { 1904 reg = <0x4f000 0x1000>; 1905 label = "cpu-bpmp-rx"; 1906 pool; 1907 }; 1908 }; 1909 1910 bpmp: bpmp { 1911 compatible = "nvidia,tegra186-bpmp"; 1912 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1913 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1914 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1915 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1916 interconnect-names = "read", "write", "dma-mem", "dma-write"; 1917 iommus = <&smmu TEGRA186_SID_BPMP>; 1918 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1919 TEGRA_HSP_DB_MASTER_BPMP>; 1920 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 1921 #clock-cells = <1>; 1922 #reset-cells = <1>; 1923 #power-domain-cells = <1>; 1924 1925 bpmp_i2c: i2c { 1926 compatible = "nvidia,tegra186-bpmp-i2c"; 1927 nvidia,bpmp-bus-id = <5>; 1928 #address-cells = <1>; 1929 #size-cells = <0>; 1930 status = "disabled"; 1931 }; 1932 1933 bpmp_thermal: thermal { 1934 compatible = "nvidia,tegra186-bpmp-thermal"; 1935 #thermal-sensor-cells = <1>; 1936 }; 1937 }; 1938 1939 cpus { 1940 #address-cells = <1>; 1941 #size-cells = <0>; 1942 1943 denver_0: cpu@0 { 1944 compatible = "nvidia,tegra186-denver"; 1945 device_type = "cpu"; 1946 i-cache-size = <0x20000>; 1947 i-cache-line-size = <64>; 1948 i-cache-sets = <512>; 1949 d-cache-size = <0x10000>; 1950 d-cache-line-size = <64>; 1951 d-cache-sets = <256>; 1952 next-level-cache = <&L2_DENVER>; 1953 reg = <0x000>; 1954 }; 1955 1956 denver_1: cpu@1 { 1957 compatible = "nvidia,tegra186-denver"; 1958 device_type = "cpu"; 1959 i-cache-size = <0x20000>; 1960 i-cache-line-size = <64>; 1961 i-cache-sets = <512>; 1962 d-cache-size = <0x10000>; 1963 d-cache-line-size = <64>; 1964 d-cache-sets = <256>; 1965 next-level-cache = <&L2_DENVER>; 1966 reg = <0x001>; 1967 }; 1968 1969 ca57_0: cpu@2 { 1970 compatible = "arm,cortex-a57"; 1971 device_type = "cpu"; 1972 i-cache-size = <0xC000>; 1973 i-cache-line-size = <64>; 1974 i-cache-sets = <256>; 1975 d-cache-size = <0x8000>; 1976 d-cache-line-size = <64>; 1977 d-cache-sets = <256>; 1978 next-level-cache = <&L2_A57>; 1979 reg = <0x100>; 1980 }; 1981 1982 ca57_1: cpu@3 { 1983 compatible = "arm,cortex-a57"; 1984 device_type = "cpu"; 1985 i-cache-size = <0xC000>; 1986 i-cache-line-size = <64>; 1987 i-cache-sets = <256>; 1988 d-cache-size = <0x8000>; 1989 d-cache-line-size = <64>; 1990 d-cache-sets = <256>; 1991 next-level-cache = <&L2_A57>; 1992 reg = <0x101>; 1993 }; 1994 1995 ca57_2: cpu@4 { 1996 compatible = "arm,cortex-a57"; 1997 device_type = "cpu"; 1998 i-cache-size = <0xC000>; 1999 i-cache-line-size = <64>; 2000 i-cache-sets = <256>; 2001 d-cache-size = <0x8000>; 2002 d-cache-line-size = <64>; 2003 d-cache-sets = <256>; 2004 next-level-cache = <&L2_A57>; 2005 reg = <0x102>; 2006 }; 2007 2008 ca57_3: cpu@5 { 2009 compatible = "arm,cortex-a57"; 2010 device_type = "cpu"; 2011 i-cache-size = <0xC000>; 2012 i-cache-line-size = <64>; 2013 i-cache-sets = <256>; 2014 d-cache-size = <0x8000>; 2015 d-cache-line-size = <64>; 2016 d-cache-sets = <256>; 2017 next-level-cache = <&L2_A57>; 2018 reg = <0x103>; 2019 }; 2020 2021 L2_DENVER: l2-cache0 { 2022 compatible = "cache"; 2023 cache-unified; 2024 cache-level = <2>; 2025 cache-size = <0x200000>; 2026 cache-line-size = <64>; 2027 cache-sets = <2048>; 2028 }; 2029 2030 L2_A57: l2-cache1 { 2031 compatible = "cache"; 2032 cache-unified; 2033 cache-level = <2>; 2034 cache-size = <0x200000>; 2035 cache-line-size = <64>; 2036 cache-sets = <2048>; 2037 }; 2038 }; 2039 2040 pmu-a57 { 2041 compatible = "arm,cortex-a57-pmu"; 2042 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 2043 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 2044 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 2045 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 2046 interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; 2047 }; 2048 2049 pmu-denver { 2050 compatible = "nvidia,denver-pmu"; 2051 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2052 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2053 interrupt-affinity = <&denver_0 &denver_1>; 2054 }; 2055 2056 sound { 2057 status = "disabled"; 2058 2059 clocks = <&bpmp TEGRA186_CLK_PLLA>, 2060 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2061 clock-names = "pll_a", "plla_out0"; 2062 assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>, 2063 <&bpmp TEGRA186_CLK_PLL_A_OUT0>, 2064 <&bpmp TEGRA186_CLK_AUD_MCLK>; 2065 assigned-clock-parents = <0>, 2066 <&bpmp TEGRA186_CLK_PLLA>, 2067 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2068 /* 2069 * PLLA supports dynamic ramp. Below initial rate is chosen 2070 * for this to work and oscillate between base rates required 2071 * for 8x and 11.025x sample rate streams. 2072 */ 2073 assigned-clock-rates = <258000000>; 2074 2075 iommus = <&smmu TEGRA186_SID_APE>; 2076 }; 2077 2078 thermal-zones { 2079 /* Cortex-A57 cluster */ 2080 cpu-thermal { 2081 polling-delay = <0>; 2082 polling-delay-passive = <1000>; 2083 2084 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 2085 2086 trips { 2087 critical { 2088 temperature = <101000>; 2089 hysteresis = <0>; 2090 type = "critical"; 2091 }; 2092 }; 2093 2094 cooling-maps { 2095 }; 2096 }; 2097 2098 /* Denver cluster */ 2099 aux-thermal { 2100 polling-delay = <0>; 2101 polling-delay-passive = <1000>; 2102 2103 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 2104 2105 trips { 2106 critical { 2107 temperature = <101000>; 2108 hysteresis = <0>; 2109 type = "critical"; 2110 }; 2111 }; 2112 2113 cooling-maps { 2114 }; 2115 }; 2116 2117 gpu-thermal { 2118 polling-delay = <0>; 2119 polling-delay-passive = <1000>; 2120 2121 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 2122 2123 trips { 2124 critical { 2125 temperature = <101000>; 2126 hysteresis = <0>; 2127 type = "critical"; 2128 }; 2129 }; 2130 2131 cooling-maps { 2132 }; 2133 }; 2134 2135 pll-thermal { 2136 polling-delay = <0>; 2137 polling-delay-passive = <1000>; 2138 2139 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 2140 2141 trips { 2142 critical { 2143 temperature = <101000>; 2144 hysteresis = <0>; 2145 type = "critical"; 2146 }; 2147 }; 2148 2149 cooling-maps { 2150 }; 2151 }; 2152 2153 ao-thermal { 2154 polling-delay = <0>; 2155 polling-delay-passive = <1000>; 2156 2157 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 2158 2159 trips { 2160 critical { 2161 temperature = <101000>; 2162 hysteresis = <0>; 2163 type = "critical"; 2164 }; 2165 }; 2166 2167 cooling-maps { 2168 }; 2169 }; 2170 }; 2171 2172 timer { 2173 compatible = "arm,armv8-timer"; 2174 interrupts = <GIC_PPI 13 2175 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2176 <GIC_PPI 14 2177 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2178 <GIC_PPI 11 2179 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2180 <GIC_PPI 10 2181 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2182 interrupt-parent = <&gic>; 2183 always-on; 2184 }; 2185}; 2186