1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 BayLibre, SAS 4 * Author: Neil Armstrong <narmstrong@baylibre.com> 5 */ 6 7/dts-v1/; 8 9#include "meson-sm1.dtsi" 10#include "meson-khadas-vim3.dtsi" 11#include <dt-bindings/sound/meson-g12a-tohdmitx.h> 12 13/ { 14 compatible = "khadas,vim3l", "amlogic,sm1"; 15 model = "Khadas VIM3L"; 16 17 vddcpu: regulator-vddcpu { 18 /* 19 * Silergy SY8030DEC Regulator. 20 */ 21 compatible = "pwm-regulator"; 22 23 regulator-name = "VDDCPU"; 24 regulator-min-microvolt = <690000>; 25 regulator-max-microvolt = <1050000>; 26 27 pwm-supply = <&vsys_3v3>; 28 29 pwms = <&pwm_AO_cd 1 1250 0>; 30 pwm-dutycycle-range = <100 0>; 31 32 regulator-boot-on; 33 regulator-always-on; 34 }; 35 36 sound { 37 model = "G12B-KHADAS-VIM3L"; 38 audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", 39 "TDMOUT_A IN 1", "FRDDR_B OUT 0", 40 "TDMOUT_A IN 2", "FRDDR_C OUT 0", 41 "TDM_A Playback", "TDMOUT_A OUT", 42 "TDMIN_A IN 0", "TDM_A Capture", 43 "TDMIN_A IN 13", "TDM_A Loopback", 44 "TODDR_A IN 0", "TDMIN_A OUT", 45 "TODDR_B IN 0", "TDMIN_A OUT", 46 "TODDR_C IN 0", "TDMIN_A OUT"; 47 }; 48}; 49 50&cpu0 { 51 cpu-supply = <&vddcpu>; 52 operating-points-v2 = <&cpu_opp_table>; 53 clocks = <&clkc CLKID_CPU_CLK>; 54}; 55 56&cpu1 { 57 cpu-supply = <&vddcpu>; 58 operating-points-v2 = <&cpu_opp_table>; 59 clocks = <&clkc CLKID_CPU1_CLK>; 60}; 61 62&cpu2 { 63 cpu-supply = <&vddcpu>; 64 operating-points-v2 = <&cpu_opp_table>; 65 clocks = <&clkc CLKID_CPU2_CLK>; 66}; 67 68&cpu3 { 69 cpu-supply = <&vddcpu>; 70 operating-points-v2 = <&cpu_opp_table>; 71 clocks = <&clkc CLKID_CPU3_CLK>; 72}; 73 74&pwm_AO_cd { 75 pinctrl-0 = <&pwm_ao_d_e_pins>; 76 pinctrl-names = "default"; 77 status = "okay"; 78}; 79 80/* 81 * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential 82 * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between 83 * an USB3.0 Type A connector and a M.2 Key M slot. 84 * The PHY driving these differential lines is shared between 85 * the USB3.0 controller and the PCIe Controller, thus only 86 * a single controller can use it. 87 * If the MCU is configured to mux the PCIe/USB3.0 differential lines 88 * to the M.2 Key M slot, uncomment the following block to disable 89 * USB3.0 from the USB Complex and enable the PCIe controller. 90 * The End User is not expected to uncomment the following except for 91 * testing purposes, but instead rely on the firmware/bootloader to 92 * update these nodes accordingly if PCIe mode is selected by the MCU. 93 */ 94/* 95&pcie { 96 status = "okay"; 97}; 98 99&usb { 100 phys = <&usb2_phy0>, <&usb2_phy1>; 101 phy-names = "usb2-phy0", "usb2-phy1"; 102}; 103 */ 104 105&sd_emmc_a { 106 sd-uhs-sdr50; 107}; 108