1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 Broadcom Ltd. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/interrupt-controller/irq.h> 8 9/ { 10 compatible = "brcm,bcm63178", "brcm,bcmbca"; 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 interrupt-parent = <&gic>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 CA7_0: cpu@0 { 21 device_type = "cpu"; 22 compatible = "arm,cortex-a7"; 23 reg = <0x0>; 24 next-level-cache = <&L2_0>; 25 enable-method = "psci"; 26 }; 27 28 CA7_1: cpu@1 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-a7"; 31 reg = <0x1>; 32 next-level-cache = <&L2_0>; 33 enable-method = "psci"; 34 }; 35 36 CA7_2: cpu@2 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a7"; 39 reg = <0x2>; 40 next-level-cache = <&L2_0>; 41 enable-method = "psci"; 42 }; 43 44 L2_0: l2-cache0 { 45 compatible = "cache"; 46 cache-level = <2>; 47 cache-unified; 48 }; 49 }; 50 51 timer { 52 compatible = "arm,armv7-timer"; 53 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, 54 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, 55 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, 56 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>; 57 arm,cpu-registers-not-fw-configured; 58 }; 59 60 pmu: pmu { 61 compatible = "arm,cortex-a7-pmu"; 62 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 65 interrupt-affinity = <&CA7_0>, <&CA7_1>, 66 <&CA7_2>; 67 }; 68 69 clocks: clocks { 70 periph_clk: periph-clk { 71 compatible = "fixed-clock"; 72 #clock-cells = <0>; 73 clock-frequency = <200000000>; 74 }; 75 76 uart_clk: uart-clk { 77 compatible = "fixed-factor-clock"; 78 #clock-cells = <0>; 79 clocks = <&periph_clk>; 80 clock-div = <4>; 81 clock-mult = <1>; 82 }; 83 84 hsspi_pll: hsspi-pll { 85 compatible = "fixed-clock"; 86 #clock-cells = <0>; 87 clock-frequency = <200000000>; 88 }; 89 }; 90 91 psci { 92 compatible = "arm,psci-0.2"; 93 method = "smc"; 94 }; 95 96 axi@81000000 { 97 compatible = "simple-bus"; 98 #address-cells = <1>; 99 #size-cells = <1>; 100 ranges = <0 0x81000000 0x8000>; 101 102 gic: interrupt-controller@1000 { 103 compatible = "arm,cortex-a7-gic"; 104 #interrupt-cells = <3>; 105 interrupt-controller; 106 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>; 107 reg = <0x1000 0x1000>, 108 <0x2000 0x2000>, 109 <0x4000 0x2000>, 110 <0x6000 0x2000>; 111 }; 112 }; 113 114 bus@ff800000 { 115 compatible = "simple-bus"; 116 #address-cells = <1>; 117 #size-cells = <1>; 118 ranges = <0 0xff800000 0x800000>; 119 120 watchdog@480 { 121 compatible = "brcm,bcm6345-wdt"; 122 reg = <0x480 0x10>; 123 }; 124 125 /* GPIOs 0 .. 31 */ 126 gpio0: gpio@500 { 127 compatible = "brcm,bcm6345-gpio"; 128 reg = <0x500 0x04>, <0x520 0x04>; 129 reg-names = "dirout", "dat"; 130 gpio-controller; 131 #gpio-cells = <2>; 132 status = "disabled"; 133 }; 134 135 /* GPIOs 32 .. 63 */ 136 gpio1: gpio@504 { 137 compatible = "brcm,bcm6345-gpio"; 138 reg = <0x504 0x04>, <0x524 0x04>; 139 reg-names = "dirout", "dat"; 140 gpio-controller; 141 #gpio-cells = <2>; 142 status = "disabled"; 143 }; 144 145 /* GPIOs 64 .. 95 */ 146 gpio2: gpio@508 { 147 compatible = "brcm,bcm6345-gpio"; 148 reg = <0x508 0x04>, <0x528 0x04>; 149 reg-names = "dirout", "dat"; 150 gpio-controller; 151 #gpio-cells = <2>; 152 status = "disabled"; 153 }; 154 155 /* GPIOs 96 .. 127 */ 156 gpio3: gpio@50c { 157 compatible = "brcm,bcm6345-gpio"; 158 reg = <0x50c 0x04>, <0x52c 0x04>; 159 reg-names = "dirout", "dat"; 160 gpio-controller; 161 #gpio-cells = <2>; 162 status = "disabled"; 163 }; 164 165 /* GPIOs 128 .. 159 */ 166 gpio4: gpio@510 { 167 compatible = "brcm,bcm6345-gpio"; 168 reg = <0x510 0x04>, <0x530 0x04>; 169 reg-names = "dirout", "dat"; 170 gpio-controller; 171 #gpio-cells = <2>; 172 status = "disabled"; 173 }; 174 175 /* GPIOs 160 .. 191 */ 176 gpio5: gpio@514 { 177 compatible = "brcm,bcm6345-gpio"; 178 reg = <0x514 0x04>, <0x534 0x04>; 179 reg-names = "dirout", "dat"; 180 gpio-controller; 181 #gpio-cells = <2>; 182 status = "disabled"; 183 }; 184 185 /* GPIOs 192 .. 223 */ 186 gpio6: gpio@518 { 187 compatible = "brcm,bcm6345-gpio"; 188 reg = <0x518 0x04>, <0x538 0x04>; 189 reg-names = "dirout", "dat"; 190 gpio-controller; 191 #gpio-cells = <2>; 192 status = "disabled"; 193 }; 194 195 /* GPIOs 224 .. 255 */ 196 gpio7: gpio@51c { 197 compatible = "brcm,bcm6345-gpio"; 198 reg = <0x51c 0x04>, <0x53c 0x04>; 199 reg-names = "dirout", "dat"; 200 gpio-controller; 201 #gpio-cells = <2>; 202 status = "disabled"; 203 }; 204 205 rng@b80 { 206 compatible = "brcm,iproc-rng200"; 207 reg = <0xb80 0x28>; 208 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 209 }; 210 211 hsspi: spi@1000 { 212 #address-cells = <1>; 213 #size-cells = <0>; 214 compatible = "brcm,bcm63178-hsspi", "brcm,bcmbca-hsspi-v1.0"; 215 reg = <0x1000 0x600>; 216 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 217 clocks = <&hsspi_pll &hsspi_pll>; 218 clock-names = "hsspi", "pll"; 219 num-cs = <8>; 220 status = "disabled"; 221 }; 222 223 nand_controller: nand-controller@1800 { 224 #address-cells = <1>; 225 #size-cells = <0>; 226 compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; 227 reg = <0x1800 0x600>, <0x2000 0x10>; 228 reg-names = "nand", "nand-int-base"; 229 status = "disabled"; 230 231 nandcs: nand@0 { 232 compatible = "brcm,nandcs"; 233 reg = <0>; 234 }; 235 }; 236 237 leds: led-controller@3000 { 238 #address-cells = <1>; 239 #size-cells = <0>; 240 compatible = "brcm,bcm63138-leds"; 241 reg = <0x3000 0xdc>; 242 status = "disabled"; 243 }; 244 245 pl081_dma: dma-controller@11000 { 246 compatible = "arm,pl081", "arm,primecell"; 247 // The magic B105F00D info is missing 248 arm,primecell-periphid = <0x00041081>; 249 reg = <0x11000 0x1000>; 250 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 251 memcpy-burst-size = <256>; 252 memcpy-bus-width = <32>; 253 clocks = <&periph_clk>; 254 clock-names = "apb_pclk"; 255 #dma-cells = <2>; 256 }; 257 258 uart0: serial@12000 { 259 compatible = "arm,pl011", "arm,primecell"; 260 reg = <0x12000 0x1000>; 261 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&uart_clk>, <&uart_clk>; 263 clock-names = "uartclk", "apb_pclk"; 264 status = "disabled"; 265 }; 266 }; 267}; 268