1.. SPDX-License-Identifier: GPL-2.0-only
2
3=============
4AD7191 driver
5=============
6
7Device driver for Analog Devices AD7191 ADC.
8
9Supported devices
10=================
11
12* `AD7191 <https://www.analog.com/AD7191>`_
13
14The AD7191 is a high precision, low noise, 24-bit Σ-Δ ADC with integrated PGA.
15It features two differential input channels, an internal temperature sensor, and
16configurable sampling rates.
17
18Devicetree
19==========
20
21Pin Configuration
22-----------------
23
24The driver supports both pin-strapped and GPIO-controlled configurations for ODR
25(Output Data Rate) and PGA (Programmable Gain Amplifier) settings. These
26configurations are mutually exclusive - you must use either pin-strapped or GPIO
27control for each setting, not both.
28
29ODR Configuration
30^^^^^^^^^^^^^^^^^
31
32The ODR can be configured either through GPIO control or pin-strapping:
33
34- When using GPIO control, specify the "odr-gpios" property in the device tree
35- For pin-strapped configuration, specify the "adi,odr-value" property in the
36  device tree
37
38Available ODR settings:
39
40  - 120 Hz (ODR1=0, ODR2=0)
41  - 60 Hz (ODR1=0, ODR2=1)
42  - 50 Hz (ODR1=1, ODR2=0)
43  - 10 Hz (ODR1=1, ODR2=1)
44
45PGA Configuration
46^^^^^^^^^^^^^^^^^
47
48The PGA can be configured either through GPIO control or pin-strapping:
49
50- When using GPIO control, specify the "pga-gpios" property in the device tree
51- For pin-strapped configuration, specify the "adi,pga-value" property in the
52  device tree
53
54Available PGA gain settings:
55
56  - 1x (PGA1=0, PGA2=0)
57  - 8x (PGA1=0, PGA2=1)
58  - 64x (PGA1=1, PGA2=0)
59  - 128x (PGA1=1, PGA2=1)
60
61Clock Configuration
62-------------------
63
64The AD7191 supports both internal and external clock sources:
65
66- When CLKSEL pin is tied LOW: Uses internal 4.92MHz clock (no clock property
67  needed)
68- When CLKSEL pin is tied HIGH: Requires external clock source
69  - Can be a crystal between MCLK1 and MCLK2 pins
70  - Or a CMOS-compatible clock driving MCLK2 pin
71  - Must specify the "clocks" property in device tree when using external clock
72
73SPI Interface Requirements
74--------------------------
75
76The AD7191 has specific SPI interface requirements:
77
78- The DOUT/RDY output is dual-purpose and requires SPI bus locking
79- DOUT/RDY must be connected to an interrupt-capable GPIO
80- The SPI controller's chip select must be connected to the PDOWN pin of the ADC
81- When CS (PDOWN) is high, the device powers down and resets internal circuitry
82- SPI mode 3 operation (CPOL=1, CPHA=1) is required
83
84Power Supply Requirements
85-------------------------
86
87The device requires the following power supplies:
88
89- AVdd: Analog power supply
90- DVdd: Digital power supply
91- Vref: Reference voltage supply (external)
92
93All power supplies must be specified in the device tree.
94
95Channel Configuration
96=====================
97
98The device provides three channels:
99
1001. Temperature Sensor
101   - 24-bit unsigned
102   - Internal temperature measurement
103   - Temperature in millidegrees Celsius
104
1052. Differential Input (AIN1-AIN2)
106   - 24-bit unsigned
107   - Differential voltage measurement
108   - Configurable gain via PGA
109
1103. Differential Input (AIN3-AIN4)
111   - 24-bit unsigned
112   - Differential voltage measurement
113   - Configurable gain via PGA
114
115Buffer Support
116==============
117
118This driver supports IIO triggered buffers. See Documentation/iio/iio_devbuf.rst
119for more information about IIO triggered buffers.
120