1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sound/fsl,imx-asrc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale Asynchronous Sample Rate Converter (ASRC) Controller
8
9description:
10  The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of
11  a signal associated with an input clock into a signal associated with a
12  different output clock. The driver currently works as a Front End of DPCM
13  with other Back Ends Audio controller such as ESAI, SSI and SAI. It has
14  three pairs to support three substreams within totally 10 channels.
15
16maintainers:
17  - Shawn Guo <shawnguo@kernel.org>
18  - Sascha Hauer <s.hauer@pengutronix.de>
19
20properties:
21  compatible:
22    oneOf:
23      - enum:
24          - fsl,imx35-asrc
25          - fsl,imx53-asrc
26          - fsl,imx8qm-asrc
27          - fsl,imx8qxp-asrc
28      - items:
29          - enum:
30              - fsl,imx6sx-asrc
31              - fsl,imx6ul-asrc
32          - const: fsl,imx53-asrc
33
34  reg:
35    maxItems: 1
36
37  interrupts:
38    maxItems: 1
39
40  dmas:
41    maxItems: 6
42
43  dma-names:
44    items:
45      - const: rxa
46      - const: rxb
47      - const: rxc
48      - const: txa
49      - const: txb
50      - const: txc
51
52  clocks:
53    maxItems: 19
54
55  clock-names:
56    items:
57      - const: mem
58      - const: ipg
59      - const: asrck_0
60      - const: asrck_1
61      - const: asrck_2
62      - const: asrck_3
63      - const: asrck_4
64      - const: asrck_5
65      - const: asrck_6
66      - const: asrck_7
67      - const: asrck_8
68      - const: asrck_9
69      - const: asrck_a
70      - const: asrck_b
71      - const: asrck_c
72      - const: asrck_d
73      - const: asrck_e
74      - const: asrck_f
75      - const: spba
76
77  power-domains:
78    maxItems: 1
79
80  port:
81    $ref: audio-graph-port.yaml#
82    unevaluatedProperties: false
83
84  fsl,asrc-rate:
85    $ref: /schemas/types.yaml#/definitions/uint32
86    description: The mutual sample rate used by DPCM Back Ends
87
88  fsl,asrc-width:
89    $ref: /schemas/types.yaml#/definitions/uint32
90    description: The mutual sample width used by DPCM Back Ends
91    enum: [16, 24]
92
93  fsl,asrc-clk-map:
94    $ref: /schemas/types.yaml#/definitions/uint32
95    description:
96      Defines clock map used in driver
97      <0> - select the map for asrc0 in imx8qm/imx8qxp
98      <1> - select the map for asrc1 in imx8qm/imx8qxp
99    enum: [0, 1]
100
101  big-endian:
102    type: boolean
103    description:
104      If this property is absent, the little endian mode will be in use as
105      default. Otherwise, the big endian mode will be in use for all the
106      device registers.
107
108  fsl,asrc-format:
109    $ref: /schemas/types.yaml#/definitions/uint32
110    description:
111      Defines a mutual sample format used by DPCM Back Ends, which can
112      replace the fsl,asrc-width. The value is 2 (S16_LE), or 6 (S24_LE).
113    enum: [2, 6]
114
115required:
116  - compatible
117  - reg
118  - interrupts
119  - dmas
120  - dma-names
121  - clocks
122  - clock-names
123  - fsl,asrc-rate
124  - fsl,asrc-width
125
126allOf:
127  - $ref: dai-common.yaml#
128  - if:
129      properties:
130        compatible:
131          contains:
132            enum:
133              - fsl,imx8qm-asrc
134              - fsl,imx8qxp-asrc
135    then:
136      required:
137        - fsl,asrc-clk-map
138    else:
139      properties:
140        fsl,asrc-clk-map: false
141
142  - if:
143      properties:
144        compatible:
145          contains:
146            enum:
147              - fsl,imx8qm-asrc
148              - fsl,imx8qxp-asrc
149    then:
150      required:
151        - power-domains
152
153unevaluatedProperties: false
154
155examples:
156  - |
157    #include <dt-bindings/interrupt-controller/irq.h>
158    #include <dt-bindings/clock/imx6qdl-clock.h>
159    asrc: asrc@2034000 {
160        compatible = "fsl,imx53-asrc";
161        reg = <0x02034000 0x4000>;
162        interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
163        clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
164                 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
165                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
166                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
167                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
168                 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
169                 <&clks IMX6QDL_CLK_SPBA>;
170        clock-names = "mem", "ipg", "asrck_0",
171                "asrck_1", "asrck_2", "asrck_3", "asrck_4",
172                "asrck_5", "asrck_6", "asrck_7", "asrck_8",
173                "asrck_9", "asrck_a", "asrck_b", "asrck_c",
174                "asrck_d", "asrck_e", "asrck_f", "spba";
175        dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
176               <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
177        dma-names = "rxa", "rxb", "rxc",
178                    "txa", "txb", "txc";
179        fsl,asrc-rate  = <48000>;
180        fsl,asrc-width = <16>;
181
182        port {
183            playback-only;
184
185            asrc_endpoint: endpoint {
186                remote-endpoint = <&fe00_ep>;
187            };
188       };
189    };
190