xref: /linux/Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml (revision 115e74a29b530d121891238e9551c4bcdf7b04b5) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/power/allwinner,sun20i-d1-ppu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Allwinner SoCs PPU power domain controller
8
9maintainers:
10  - Samuel Holland <samuel@sholland.org>
11
12description:
13  D1 and related SoCs contain a power domain controller for the CPUs, GPU, and
14  video-related hardware.
15
16properties:
17  compatible:
18    enum:
19      - allwinner,sun8i-v853-ppu
20      - allwinner,sun20i-d1-ppu
21      - allwinner,sun55i-a523-pck-600
22      - allwinner,sun55i-a523-ppu
23
24  reg:
25    maxItems: 1
26
27  clocks:
28    description: Bus Clock
29    maxItems: 1
30
31  resets:
32    maxItems: 1
33
34  '#power-domain-cells':
35    const: 1
36
37required:
38  - compatible
39  - reg
40  - clocks
41  - resets
42  - '#power-domain-cells'
43
44additionalProperties: false
45
46examples:
47  - |
48    #include <dt-bindings/clock/sun20i-d1-r-ccu.h>
49    #include <dt-bindings/reset/sun20i-d1-r-ccu.h>
50
51    ppu: power-controller@7001000 {
52        compatible = "allwinner,sun20i-d1-ppu";
53        reg = <0x7001000 0x1000>;
54        clocks = <&r_ccu CLK_BUS_R_PPU>;
55        resets = <&r_ccu RST_BUS_R_PPU>;
56        #power-domain-cells = <1>;
57    };
58