xref: /linux/Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml (revision 4f9786035f9e519db41375818e1d0b5f20da2f10) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/rockchip,rk3588-mipi-dcphy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip MIPI D-/C-PHY with Samsung IP block
8
9maintainers:
10  - Guochun Huang <hero.huang@rock-chips.com>
11  - Heiko Stuebner <heiko@sntech.de>
12
13properties:
14  compatible:
15    enum:
16      - rockchip,rk3576-mipi-dcphy
17      - rockchip,rk3588-mipi-dcphy
18
19  reg:
20    maxItems: 1
21
22  "#phy-cells":
23    const: 1
24    description: |
25      Argument is mode to operate in. Supported modes are:
26        - PHY_TYPE_DPHY
27        - PHY_TYPE_CPHY
28      See include/dt-bindings/phy/phy.h for constants.
29
30  clocks:
31    maxItems: 2
32
33  clock-names:
34    items:
35      - const: pclk
36      - const: ref
37
38  resets:
39    maxItems: 4
40
41  reset-names:
42    items:
43      - const: m_phy
44      - const: apb
45      - const: grf
46      - const: s_phy
47
48  rockchip,grf:
49    $ref: /schemas/types.yaml#/definitions/phandle
50    description:
51      Phandle to the syscon managing the 'mipi dcphy general register files'.
52
53required:
54  - compatible
55  - reg
56  - clocks
57  - clock-names
58  - resets
59  - reset-names
60  - "#phy-cells"
61
62additionalProperties: false
63
64examples:
65  - |
66    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
67    #include <dt-bindings/reset/rockchip,rk3588-cru.h>
68
69    soc {
70      #address-cells = <2>;
71      #size-cells = <2>;
72
73      phy@feda0000 {
74        compatible = "rockchip,rk3588-mipi-dcphy";
75        reg = <0x0 0xfeda0000 0x0 0x10000>;
76        clocks = <&cru PCLK_MIPI_DCPHY0>,
77                 <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>;
78        clock-names = "pclk", "ref";
79        resets = <&cru SRST_M_MIPI_DCPHY0>,
80                 <&cru SRST_P_MIPI_DCPHY0>,
81                 <&cru SRST_P_MIPI_DCPHY0_GRF>,
82                 <&cru SRST_S_MIPI_DCPHY0>;
83        reset-names = "m_phy", "apb", "grf", "s_phy";
84        rockchip,grf = <&mipidcphy0_grf>;
85        #phy-cells = <1>;
86      };
87    };
88