1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/apm,xgene-pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: AppliedMicro X-Gene PCIe interface 8 9maintainers: 10 - Toan Le <toan@os.amperecomputing.com> 11 12allOf: 13 - $ref: /schemas/pci/pci-host-bridge.yaml# 14 15properties: 16 compatible: 17 oneOf: 18 - items: 19 - const: apm,xgene-storm-pcie 20 - const: apm,xgene-pcie 21 - items: 22 - const: apm,xgene-pcie 23 24 reg: 25 items: 26 - description: Controller configuration registers 27 - description: PCI configuration space registers 28 29 reg-names: 30 items: 31 - const: csr 32 - const: cfg 33 34 clocks: 35 maxItems: 1 36 37 clock-names: 38 items: 39 - const: pcie 40 41 dma-coherent: true 42 43 msi-parent: 44 maxItems: 1 45 46required: 47 - compatible 48 - reg 49 - reg-names 50 - '#interrupt-cells' 51 - interrupt-map-mask 52 - interrupt-map 53 - clocks 54 55unevaluatedProperties: false 56 57examples: 58 - | 59 bus { 60 #address-cells = <2>; 61 #size-cells = <2>; 62 63 pcie@1f2b0000 { 64 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 65 device_type = "pci"; 66 #interrupt-cells = <1>; 67 #size-cells = <2>; 68 #address-cells = <3>; 69 reg = <0x00 0x1f2b0000 0x0 0x00010000>, /* Controller registers */ 70 <0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 71 reg-names = "csr", "cfg"; 72 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000>, /* io */ 73 <0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */ 74 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000>, 75 <0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 76 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 77 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1>, 78 <0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1>, 79 <0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1>, 80 <0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; 81 dma-coherent; 82 clocks = <&pcie0clk 0>; 83 }; 84 }; 85