xref: /linux/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml (revision d53320aeef18ece4999c0cf07cb802d1dd990885) ! 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/renesas,rzv2h-gbeth.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: GBETH glue layer for Renesas RZ/V2H(P) (and similar SoCs)
8
9maintainers:
10  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
11
12select:
13  properties:
14    compatible:
15      contains:
16        enum:
17          - renesas,r9a09g047-gbeth
18          - renesas,r9a09g056-gbeth
19          - renesas,r9a09g057-gbeth
20          - renesas,rzv2h-gbeth
21  required:
22    - compatible
23
24properties:
25  compatible:
26    items:
27      - enum:
28          - renesas,r9a09g047-gbeth # RZ/G3E
29          - renesas,r9a09g056-gbeth # RZ/V2N
30          - renesas,r9a09g057-gbeth # RZ/V2H(P)
31      - const: renesas,rzv2h-gbeth
32      - const: snps,dwmac-5.20
33
34  reg:
35    maxItems: 1
36
37  clocks:
38    items:
39      - description: CSR clock
40      - description: AXI system clock
41      - description: PTP clock
42      - description: TX clock
43      - description: RX clock
44      - description: TX clock phase-shifted by 180 degrees
45      - description: RX clock phase-shifted by 180 degrees
46
47  clock-names:
48    items:
49      - const: stmmaceth
50      - const: pclk
51      - const: ptp_ref
52      - const: tx
53      - const: rx
54      - const: tx-180
55      - const: rx-180
56
57  interrupts:
58    minItems: 11
59
60  interrupt-names:
61    items:
62      - const: macirq
63      - const: eth_wake_irq
64      - const: eth_lpi
65      - const: rx-queue-0
66      - const: rx-queue-1
67      - const: rx-queue-2
68      - const: rx-queue-3
69      - const: tx-queue-0
70      - const: tx-queue-1
71      - const: tx-queue-2
72      - const: tx-queue-3
73
74  resets:
75    items:
76      - description: AXI power-on system reset
77
78required:
79  - compatible
80  - reg
81  - clocks
82  - clock-names
83  - interrupts
84  - interrupt-names
85  - resets
86
87allOf:
88  - $ref: snps,dwmac.yaml#
89
90unevaluatedProperties: false
91
92examples:
93  - |
94    #include <dt-bindings/clock/renesas-cpg-mssr.h>
95    #include <dt-bindings/interrupt-controller/arm-gic.h>
96
97    ethernet@15c30000 {
98        compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth", "snps,dwmac-5.20";
99        reg = <0x15c30000 0x10000>;
100        clocks =  <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>,
101                  <&ptp_clock>, <&cpg CPG_MOD 0xb8>,
102                  <&cpg CPG_MOD 0xb9>, <&cpg CPG_MOD 0xba>,
103                  <&cpg CPG_MOD 0xbb>;
104        clock-names = "stmmaceth", "pclk", "ptp_ref",
105                      "tx", "rx", "tx-180", "rx-180";
106        resets = <&cpg 0xb0>;
107        interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
108                     <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
109                     <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
110                     <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
111                     <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
112                     <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
113                     <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,
114                     <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
115                     <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
116                     <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
117                     <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>;
118        interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
119                          "rx-queue-0", "rx-queue-1", "rx-queue-2",
120                          "rx-queue-3", "tx-queue-0", "tx-queue-1",
121                          "tx-queue-2", "tx-queue-3";
122        phy-mode = "rgmii-id";
123        snps,multicast-filter-bins = <256>;
124        snps,perfect-filter-entries = <128>;
125        rx-fifo-depth = <8192>;
126        tx-fifo-depth = <8192>;
127        snps,fixed-burst;
128        snps,force_thresh_dma_mode;
129        snps,axi-config = <&stmmac_axi_setup>;
130        snps,mtl-rx-config = <&mtl_rx_setup>;
131        snps,mtl-tx-config = <&mtl_tx_setup>;
132        snps,txpbl = <32>;
133        snps,rxpbl = <32>;
134        phy-handle = <&phy0>;
135
136        stmmac_axi_setup: stmmac-axi-config {
137            snps,lpi_en;
138            snps,wr_osr_lmt = <0xf>;
139            snps,rd_osr_lmt = <0xf>;
140            snps,blen = <16 8 4 0 0 0 0>;
141        };
142
143        mtl_rx_setup: rx-queues-config {
144            snps,rx-queues-to-use = <4>;
145            snps,rx-sched-sp;
146
147            queue0 {
148                snps,dcb-algorithm;
149                snps,priority = <0x1>;
150                snps,map-to-dma-channel = <0>;
151            };
152
153            queue1 {
154                snps,dcb-algorithm;
155                snps,priority = <0x2>;
156                snps,map-to-dma-channel = <1>;
157            };
158
159            queue2 {
160                snps,dcb-algorithm;
161                snps,priority = <0x4>;
162                snps,map-to-dma-channel = <2>;
163            };
164
165            queue3 {
166                snps,dcb-algorithm;
167                snps,priority = <0x8>;
168                snps,map-to-dma-channel = <3>;
169            };
170        };
171
172        mtl_tx_setup: tx-queues-config {
173            snps,tx-queues-to-use = <4>;
174
175            queue0 {
176                snps,dcb-algorithm;
177                snps,priority = <0x1>;
178            };
179
180            queue1 {
181                snps,dcb-algorithm;
182                snps,priority = <0x2>;
183            };
184
185            queue2 {
186                snps,dcb-algorithm;
187                snps,priority = <0x4>;
188            };
189
190            queue3 {
191                snps,dcb-algorithm;
192                snps,priority = <0x1>;
193            };
194        };
195
196        mdio {
197            #address-cells = <1>;
198            #size-cells = <0>;
199            compatible = "snps,dwmac-mdio";
200
201            phy0: ethernet-phy@0 {
202                reg = <0>;
203            };
204        };
205    };
206