1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/dsa/mediatek,mt7530.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Mediatek MT7530 and MT7531 Ethernet Switches 8 9maintainers: 10 - Arınç ÜNAL <arinc.unal@arinc9.com> 11 - Landen Chao <Landen.Chao@mediatek.com> 12 - DENG Qingfang <dqfext@gmail.com> 13 - Sean Wang <sean.wang@mediatek.com> 14 - Daniel Golle <daniel@makrotopia.org> 15 16description: | 17 There are three versions of MT7530, standalone, in a multi-chip module and 18 built-into a SoC. 19 20 MT7530 is a part of the multi-chip module in MT7620AN, MT7620DA, MT7620DAN, 21 MT7620NN, MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs. 22 23 The MT7988 SoC comes with a built-in switch similar to MT7531 as well as four 24 Gigabit Ethernet PHYs. The switch registers are directly mapped into the SoC's 25 memory map rather than using MDIO. The switch has an internally connected 10G 26 CPU port and 4 user ports connected to the built-in Gigabit Ethernet PHYs. 27 28 The MT7530 in MT7620AN, MT7620DA, MT7620DAN and MT7620NN SoCs has 10/100 PHYs 29 and the switch registers are directly mapped into SoC's memory map rather than 30 using MDIO. The DSA driver currently doesn't support MT7620 variants. 31 32 There is only the standalone version of MT7531. 33 34 Port 5 on MT7530 supports various configurations: 35 36 - Port 5 can be used as a CPU port. 37 38 - PHY 0 or 4 of the switch can be muxed to gmac5 of the switch. Therefore, 39 the gmac of the SoC which is wired to port 5 can connect to the PHY. 40 This is usually used for connecting the wan port directly to the CPU to 41 achieve 2 Gbps routing in total. 42 43 The driver looks up the reg on the ethernet-phy node, which the phy-handle 44 property on the gmac node refers to, to mux the specified phy. 45 46 The driver requires the gmac of the SoC to have "mediatek,eth-mac" as the 47 compatible string and the reg must be 1. So, for now, only gmac1 of a 48 MediaTek SoC can benefit this. Banana Pi BPI-R2 suits this. 49 50 For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. 51 52 Check out example 5. 53 54 - For the multi-chip module MT7530, in case of an external phy wired to 55 gmac1 of the SoC, port 5 must not be enabled. 56 57 In case of muxing PHY 0 or 4, the external phy must not be enabled. 58 59 For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. 60 61 Check out example 6. 62 63 - Port 5 can be wired to an external phy. Port 5 becomes a DSA user port. 64 65 For the multi-chip module MT7530, the external phy must be wired TX to TX 66 to gmac1 of the SoC for this to work. Ubiquiti EdgeRouter X SFP is wired 67 this way. 68 69 For the multi-chip module MT7530, muxing PHY 0 or 4 won't work when the 70 external phy is connected TX to TX. 71 72 For the MT7621 SoCs, rgmii2 group must be claimed with gpio function. 73 74 Check out example 7. 75 76properties: 77 compatible: 78 oneOf: 79 - description: 80 Standalone MT7530 and multi-chip module MT7530 in MT7623AI SoC 81 const: mediatek,mt7530 82 83 - description: 84 Standalone MT7531 85 const: mediatek,mt7531 86 87 - description: 88 Multi-chip module MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs 89 const: mediatek,mt7621 90 91 - description: 92 Built-in switch of the MT7988 SoC 93 const: mediatek,mt7988-switch 94 95 - description: 96 Built-in switch of the Airoha EN7581 SoC 97 const: airoha,en7581-switch 98 99 - description: 100 Built-in switch of the Airoha AN7583 SoC 101 const: airoha,an7583-switch 102 103 reg: 104 maxItems: 1 105 106 core-supply: 107 description: 108 Phandle to the regulator node necessary for the core power. 109 110 "#gpio-cells": 111 const: 2 112 113 gpio-controller: 114 type: boolean 115 description: | 116 If defined, LED controller of the MT7530 switch will run on GPIO mode. 117 118 There are 15 controllable pins. 119 port 0 LED 0..2 as GPIO 0..2 120 port 1 LED 0..2 as GPIO 3..5 121 port 2 LED 0..2 as GPIO 6..8 122 port 3 LED 0..2 as GPIO 9..11 123 port 4 LED 0..2 as GPIO 12..14 124 125 "#interrupt-cells": 126 const: 1 127 128 interrupt-controller: true 129 130 interrupts: 131 maxItems: 1 132 133 io-supply: 134 description: | 135 Phandle to the regulator node necessary for the I/O power. 136 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt for 137 details for the regulator setup on these boards. 138 139 mdio: 140 $ref: /schemas/net/mdio.yaml# 141 unevaluatedProperties: false 142 143 properties: 144 mediatek,pio: 145 $ref: /schemas/types.yaml#/definitions/phandle 146 description: 147 Phandle pointing to the mediatek pinctrl node. 148 149 mediatek,mcm: 150 type: boolean 151 description: 152 Used for MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs which the MT7530 153 switch is a part of the multi-chip module. 154 155 reset-gpios: 156 description: | 157 GPIO to reset the switch. Use this if mediatek,mcm is not used. 158 This property is optional because some boards share the reset line with 159 other components which makes it impossible to probe the switch if the 160 reset line is used. 161 maxItems: 1 162 163 reset-names: 164 const: mcm 165 166 resets: 167 description: 168 Phandle pointing to the system reset controller with line index for the 169 ethsys. 170 maxItems: 1 171 172patternProperties: 173 "^(ethernet-)?ports$": 174 type: object 175 additionalProperties: true 176 177 patternProperties: 178 "^(ethernet-)?port@[0-6]$": 179 type: object 180 additionalProperties: true 181 182 properties: 183 reg: 184 description: 185 Port address described must be 5 or 6 for CPU port and from 0 to 5 186 for user ports. 187 188 allOf: 189 - if: 190 required: [ ethernet ] 191 then: 192 properties: 193 reg: 194 enum: 195 - 5 196 - 6 197 198required: 199 - compatible 200 - reg 201 202$defs: 203 builtin-dsa-port: 204 patternProperties: 205 "^(ethernet-)?ports$": 206 patternProperties: 207 "^(ethernet-)?port@[0-6]$": 208 if: 209 required: [ ethernet ] 210 then: 211 properties: 212 phy-mode: 213 const: internal 214 215 mt7530-dsa-port: 216 patternProperties: 217 "^(ethernet-)?ports$": 218 patternProperties: 219 "^(ethernet-)?port@[0-6]$": 220 if: 221 required: [ ethernet ] 222 then: 223 if: 224 properties: 225 reg: 226 const: 5 227 then: 228 properties: 229 phy-mode: 230 enum: 231 - gmii 232 - mii 233 - rgmii 234 else: 235 properties: 236 phy-mode: 237 enum: 238 - rgmii 239 - trgmii 240 241 mt7531-dsa-port: 242 patternProperties: 243 "^(ethernet-)?ports$": 244 patternProperties: 245 "^(ethernet-)?port@[0-6]$": 246 if: 247 required: [ ethernet ] 248 then: 249 if: 250 properties: 251 reg: 252 const: 5 253 then: 254 properties: 255 phy-mode: 256 enum: 257 - 1000base-x 258 - 2500base-x 259 - rgmii 260 - sgmii 261 else: 262 properties: 263 phy-mode: 264 enum: 265 - 1000base-x 266 - 2500base-x 267 - sgmii 268 269allOf: 270 - $ref: dsa.yaml#/$defs/ethernet-ports 271 - if: 272 required: 273 - mediatek,mcm 274 then: 275 properties: 276 reset-gpios: false 277 278 required: 279 - resets 280 - reset-names 281 282 - dependencies: 283 interrupt-controller: [ interrupts ] 284 285 - if: 286 properties: 287 compatible: 288 const: mediatek,mt7530 289 then: 290 $ref: "#/$defs/mt7530-dsa-port" 291 required: 292 - core-supply 293 - io-supply 294 295 - if: 296 properties: 297 compatible: 298 const: mediatek,mt7531 299 then: 300 $ref: "#/$defs/mt7531-dsa-port" 301 properties: 302 gpio-controller: false 303 mediatek,mcm: false 304 305 - if: 306 properties: 307 compatible: 308 const: mediatek,mt7621 309 then: 310 $ref: "#/$defs/mt7530-dsa-port" 311 required: 312 - mediatek,mcm 313 314 - if: 315 properties: 316 compatible: 317 enum: 318 - mediatek,mt7988-switch 319 - airoha,en7581-switch 320 - airoha,an7583-switch 321 then: 322 $ref: "#/$defs/builtin-dsa-port" 323 properties: 324 gpio-controller: false 325 mediatek,mcm: false 326 reset-names: false 327 328unevaluatedProperties: false 329 330examples: 331 # Example 1: Standalone MT7530 332 - | 333 #include <dt-bindings/gpio/gpio.h> 334 335 mdio { 336 #address-cells = <1>; 337 #size-cells = <0>; 338 339 switch@1f { 340 compatible = "mediatek,mt7530"; 341 reg = <0x1f>; 342 343 reset-gpios = <&pio 33 0>; 344 345 core-supply = <&mt6323_vpa_reg>; 346 io-supply = <&mt6323_vemc3v3_reg>; 347 348 ethernet-ports { 349 #address-cells = <1>; 350 #size-cells = <0>; 351 352 port@0 { 353 reg = <0>; 354 label = "lan1"; 355 }; 356 357 port@1 { 358 reg = <1>; 359 label = "lan2"; 360 }; 361 362 port@2 { 363 reg = <2>; 364 label = "lan3"; 365 }; 366 367 port@3 { 368 reg = <3>; 369 label = "lan4"; 370 }; 371 372 port@4 { 373 reg = <4>; 374 label = "wan"; 375 }; 376 377 port@6 { 378 reg = <6>; 379 ethernet = <&gmac0>; 380 phy-mode = "rgmii"; 381 382 fixed-link { 383 speed = <1000>; 384 full-duplex; 385 pause; 386 }; 387 }; 388 }; 389 }; 390 }; 391 392 # Example 2: MT7530 in MT7623AI SoC 393 - | 394 #include <dt-bindings/reset/mt2701-resets.h> 395 396 mdio { 397 #address-cells = <1>; 398 #size-cells = <0>; 399 400 switch@1f { 401 compatible = "mediatek,mt7530"; 402 reg = <0x1f>; 403 404 mediatek,mcm; 405 resets = <ðsys MT2701_ETHSYS_MCM_RST>; 406 reset-names = "mcm"; 407 408 core-supply = <&mt6323_vpa_reg>; 409 io-supply = <&mt6323_vemc3v3_reg>; 410 411 ethernet-ports { 412 #address-cells = <1>; 413 #size-cells = <0>; 414 415 port@0 { 416 reg = <0>; 417 label = "lan1"; 418 }; 419 420 port@1 { 421 reg = <1>; 422 label = "lan2"; 423 }; 424 425 port@2 { 426 reg = <2>; 427 label = "lan3"; 428 }; 429 430 port@3 { 431 reg = <3>; 432 label = "lan4"; 433 }; 434 435 port@4 { 436 reg = <4>; 437 label = "wan"; 438 }; 439 440 port@6 { 441 reg = <6>; 442 ethernet = <&gmac0>; 443 phy-mode = "trgmii"; 444 445 fixed-link { 446 speed = <1000>; 447 full-duplex; 448 pause; 449 }; 450 }; 451 }; 452 }; 453 }; 454 455 # Example 3: Standalone MT7531 456 - | 457 #include <dt-bindings/gpio/gpio.h> 458 #include <dt-bindings/interrupt-controller/irq.h> 459 460 mdio { 461 #address-cells = <1>; 462 #size-cells = <0>; 463 464 switch@0 { 465 compatible = "mediatek,mt7531"; 466 reg = <0>; 467 468 reset-gpios = <&pio 54 0>; 469 470 interrupt-controller; 471 #interrupt-cells = <1>; 472 interrupt-parent = <&pio>; 473 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; 474 475 ethernet-ports { 476 #address-cells = <1>; 477 #size-cells = <0>; 478 479 port@0 { 480 reg = <0>; 481 label = "lan1"; 482 }; 483 484 port@1 { 485 reg = <1>; 486 label = "lan2"; 487 }; 488 489 port@2 { 490 reg = <2>; 491 label = "lan3"; 492 }; 493 494 port@3 { 495 reg = <3>; 496 label = "lan4"; 497 }; 498 499 port@4 { 500 reg = <4>; 501 label = "wan"; 502 }; 503 504 port@6 { 505 reg = <6>; 506 ethernet = <&gmac0>; 507 phy-mode = "2500base-x"; 508 509 fixed-link { 510 speed = <2500>; 511 full-duplex; 512 pause; 513 }; 514 }; 515 }; 516 }; 517 }; 518 519 # Example 4: MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs 520 - | 521 #include <dt-bindings/interrupt-controller/mips-gic.h> 522 #include <dt-bindings/reset/mt7621-reset.h> 523 524 mdio { 525 #address-cells = <1>; 526 #size-cells = <0>; 527 528 switch@1f { 529 compatible = "mediatek,mt7621"; 530 reg = <0x1f>; 531 532 mediatek,mcm; 533 resets = <&sysc MT7621_RST_MCM>; 534 reset-names = "mcm"; 535 536 interrupt-controller; 537 #interrupt-cells = <1>; 538 interrupt-parent = <&gic>; 539 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 540 541 ethernet-ports { 542 #address-cells = <1>; 543 #size-cells = <0>; 544 545 port@0 { 546 reg = <0>; 547 label = "lan1"; 548 }; 549 550 port@1 { 551 reg = <1>; 552 label = "lan2"; 553 }; 554 555 port@2 { 556 reg = <2>; 557 label = "lan3"; 558 }; 559 560 port@3 { 561 reg = <3>; 562 label = "lan4"; 563 }; 564 565 port@4 { 566 reg = <4>; 567 label = "wan"; 568 }; 569 570 port@6 { 571 reg = <6>; 572 ethernet = <&gmac0>; 573 phy-mode = "trgmii"; 574 575 fixed-link { 576 speed = <1000>; 577 full-duplex; 578 pause; 579 }; 580 }; 581 }; 582 }; 583 }; 584 585 # Example 5: MT7621: mux MT7530's phy4 to SoC's gmac1 586 - | 587 #include <dt-bindings/interrupt-controller/mips-gic.h> 588 #include <dt-bindings/reset/mt7621-reset.h> 589 590 ethernet { 591 #address-cells = <1>; 592 #size-cells = <0>; 593 594 pinctrl-names = "default"; 595 pinctrl-0 = <&rgmii2_pins>; 596 597 mac@1 { 598 compatible = "mediatek,eth-mac"; 599 reg = <1>; 600 601 phy-mode = "rgmii"; 602 phy-handle = <&example5_ethphy4>; 603 }; 604 605 mdio { 606 #address-cells = <1>; 607 #size-cells = <0>; 608 609 /* MT7530's phy4 */ 610 example5_ethphy4: ethernet-phy@4 { 611 reg = <4>; 612 }; 613 614 switch@1f { 615 compatible = "mediatek,mt7621"; 616 reg = <0x1f>; 617 618 mediatek,mcm; 619 resets = <&sysc MT7621_RST_MCM>; 620 reset-names = "mcm"; 621 622 interrupt-controller; 623 #interrupt-cells = <1>; 624 interrupt-parent = <&gic>; 625 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 626 627 ethernet-ports { 628 #address-cells = <1>; 629 #size-cells = <0>; 630 631 port@0 { 632 reg = <0>; 633 label = "lan1"; 634 }; 635 636 port@1 { 637 reg = <1>; 638 label = "lan2"; 639 }; 640 641 port@2 { 642 reg = <2>; 643 label = "lan3"; 644 }; 645 646 port@3 { 647 reg = <3>; 648 label = "lan4"; 649 }; 650 651 /* Commented out, phy4 is connected to gmac1. 652 port@4 { 653 reg = <4>; 654 label = "wan"; 655 }; 656 */ 657 658 port@6 { 659 reg = <6>; 660 ethernet = <&gmac0>; 661 phy-mode = "trgmii"; 662 663 fixed-link { 664 speed = <1000>; 665 full-duplex; 666 pause; 667 }; 668 }; 669 }; 670 }; 671 }; 672 }; 673 674 # Example 6: MT7621: mux external phy to SoC's gmac1 675 - | 676 #include <dt-bindings/interrupt-controller/mips-gic.h> 677 #include <dt-bindings/reset/mt7621-reset.h> 678 679 ethernet { 680 #address-cells = <1>; 681 #size-cells = <0>; 682 683 pinctrl-names = "default"; 684 pinctrl-0 = <&rgmii2_pins>; 685 686 mac@1 { 687 compatible = "mediatek,eth-mac"; 688 reg = <1>; 689 690 phy-mode = "rgmii"; 691 phy-handle = <&example6_ethphy7>; 692 }; 693 694 mdio { 695 #address-cells = <1>; 696 #size-cells = <0>; 697 698 /* External PHY */ 699 example6_ethphy7: ethernet-phy@7 { 700 reg = <7>; 701 phy-mode = "rgmii"; 702 }; 703 704 switch@1f { 705 compatible = "mediatek,mt7621"; 706 reg = <0x1f>; 707 708 mediatek,mcm; 709 resets = <&sysc MT7621_RST_MCM>; 710 reset-names = "mcm"; 711 712 interrupt-controller; 713 #interrupt-cells = <1>; 714 interrupt-parent = <&gic>; 715 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 716 717 ethernet-ports { 718 #address-cells = <1>; 719 #size-cells = <0>; 720 721 port@0 { 722 reg = <0>; 723 label = "lan1"; 724 }; 725 726 port@1 { 727 reg = <1>; 728 label = "lan2"; 729 }; 730 731 port@2 { 732 reg = <2>; 733 label = "lan3"; 734 }; 735 736 port@3 { 737 reg = <3>; 738 label = "lan4"; 739 }; 740 741 port@4 { 742 reg = <4>; 743 label = "wan"; 744 }; 745 746 port@6 { 747 reg = <6>; 748 ethernet = <&gmac0>; 749 phy-mode = "trgmii"; 750 751 fixed-link { 752 speed = <1000>; 753 full-duplex; 754 pause; 755 }; 756 }; 757 }; 758 }; 759 }; 760 }; 761 762 # Example 7: MT7621: mux external phy to MT7530's port 5 763 - | 764 #include <dt-bindings/interrupt-controller/mips-gic.h> 765 #include <dt-bindings/reset/mt7621-reset.h> 766 767 ethernet { 768 #address-cells = <1>; 769 #size-cells = <0>; 770 771 pinctrl-names = "default"; 772 pinctrl-0 = <&rgmii2_pins>; 773 774 mdio { 775 #address-cells = <1>; 776 #size-cells = <0>; 777 778 /* External PHY */ 779 example7_ethphy7: ethernet-phy@7 { 780 reg = <7>; 781 phy-mode = "rgmii"; 782 }; 783 784 switch@1f { 785 compatible = "mediatek,mt7621"; 786 reg = <0x1f>; 787 788 mediatek,mcm; 789 resets = <&sysc MT7621_RST_MCM>; 790 reset-names = "mcm"; 791 792 interrupt-controller; 793 #interrupt-cells = <1>; 794 interrupt-parent = <&gic>; 795 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 796 797 ethernet-ports { 798 #address-cells = <1>; 799 #size-cells = <0>; 800 801 port@0 { 802 reg = <0>; 803 label = "lan1"; 804 }; 805 806 port@1 { 807 reg = <1>; 808 label = "lan2"; 809 }; 810 811 port@2 { 812 reg = <2>; 813 label = "lan3"; 814 }; 815 816 port@3 { 817 reg = <3>; 818 label = "lan4"; 819 }; 820 821 port@4 { 822 reg = <4>; 823 label = "wan"; 824 }; 825 826 port@5 { 827 reg = <5>; 828 label = "extphy"; 829 phy-mode = "rgmii-txid"; 830 phy-handle = <&example7_ethphy7>; 831 }; 832 833 port@6 { 834 reg = <6>; 835 ethernet = <&gmac0>; 836 phy-mode = "trgmii"; 837 838 fixed-link { 839 speed = <1000>; 840 full-duplex; 841 pause; 842 }; 843 }; 844 }; 845 }; 846 }; 847 }; 848