1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mtd/qcom,nandc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm NAND controller
8
9maintainers:
10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
12properties:
13  compatible:
14    oneOf:
15      - items:
16          - enum:
17              - qcom,sdx75-nand
18          - const: qcom,sdx55-nand
19      - items:
20          - enum:
21              - qcom,ipq806x-nand
22              - qcom,ipq4019-nand
23              - qcom,ipq6018-nand
24              - qcom,ipq8074-nand
25              - qcom,sdx55-nand
26
27  reg:
28    maxItems: 1
29
30  clocks:
31    items:
32      - description: Core Clock
33      - description: Always ON Clock
34
35  clock-names:
36    items:
37      - const: core
38      - const: aon
39
40  qcom,cmd-crci:
41    $ref: /schemas/types.yaml#/definitions/uint32
42    description:
43      Must contain the ADM command type CRCI block instance number specified for
44      the NAND controller on the given platform
45
46  qcom,data-crci:
47    $ref: /schemas/types.yaml#/definitions/uint32
48    description:
49      Must contain the ADM data type CRCI block instance number specified for
50      the NAND controller on the given platform
51
52patternProperties:
53  "^nand@[a-f0-9]$":
54    type: object
55    $ref: raw-nand-chip.yaml
56    properties:
57
58      nand-bus-width:
59        const: 8
60
61      nand-ecc-strength:
62        enum: [1, 4, 8]
63
64      nand-ecc-step-size:
65        enum:
66          - 512
67
68      qcom,boot-partitions:
69        $ref: /schemas/types.yaml#/definitions/uint32-matrix
70        items:
71          items:
72            - description: offset
73            - description: size
74        description:
75          Boot partition use a different layout where the 4 bytes of spare
76          data are not protected by ECC. Use this to declare these special
77          partitions by defining first the offset and then the size.
78
79          It's in the form of <offset1 size1 offset2 size2 offset3 ...>
80          and should be declared in ascending order.
81
82          Refer to the ipq8064 example on how to use this special binding.
83
84    unevaluatedProperties: false
85
86allOf:
87  - $ref: nand-controller.yaml#
88
89  - if:
90      properties:
91        compatible:
92          contains:
93            const: qcom,ipq806x-nand
94    then:
95      properties:
96        dmas:
97          items:
98            - description: rxtx DMA channel
99
100        dma-names:
101          items:
102            - const: rxtx
103
104  - if:
105      properties:
106        compatible:
107          contains:
108            enum:
109              - qcom,sdx75-nand
110
111    then:
112      properties:
113        iommus:
114          maxItems: 1
115
116  - if:
117      properties:
118        compatible:
119          contains:
120            enum:
121              - qcom,ipq4019-nand
122              - qcom,ipq6018-nand
123              - qcom,ipq8074-nand
124              - qcom,sdx55-nand
125
126    then:
127      properties:
128        dmas:
129          items:
130            - description: tx DMA channel
131            - description: rx DMA channel
132            - description: cmd DMA channel
133
134        dma-names:
135          items:
136            - const: tx
137            - const: rx
138            - const: cmd
139
140        qcom,cmd-crci: false
141        qcom,data-crci: false
142
143      patternProperties:
144        "^nand@[a-f0-9]$":
145          properties:
146            qcom,boot-partitions: false
147
148required:
149  - compatible
150  - reg
151  - clocks
152  - clock-names
153
154unevaluatedProperties: false
155
156examples:
157  - |
158    #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
159    nand-controller@1ac00000 {
160        compatible = "qcom,ipq806x-nand";
161        reg = <0x1ac00000 0x800>;
162
163        clocks = <&gcc EBI2_CLK>,
164                 <&gcc EBI2_AON_CLK>;
165        clock-names = "core", "aon";
166
167        dmas = <&adm_dma 3>;
168        dma-names = "rxtx";
169        qcom,cmd-crci = <15>;
170        qcom,data-crci = <3>;
171
172        #address-cells = <1>;
173        #size-cells = <0>;
174
175        nand@0 {
176            reg = <0>;
177
178            nand-ecc-strength = <4>;
179            nand-bus-width = <8>;
180
181            qcom,boot-partitions = <0x0 0x58a0000>;
182
183            partitions {
184                compatible = "fixed-partitions";
185                #address-cells = <1>;
186                #size-cells = <1>;
187
188                partition@0 {
189                    label = "boot-nand";
190                    reg = <0 0x58a0000>;
191                };
192
193                partition@58a0000 {
194                    label = "fs-nand";
195                    reg = <0x58a0000 0x4000000>;
196                };
197            };
198        };
199    };
200
201    #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
202    nand-controller@79b0000 {
203        compatible = "qcom,ipq4019-nand";
204        reg = <0x79b0000 0x1000>;
205
206        clocks = <&gcc GCC_QPIC_CLK>,
207                 <&gcc GCC_QPIC_AHB_CLK>;
208        clock-names = "core", "aon";
209
210        dmas = <&qpicbam 0>,
211               <&qpicbam 1>,
212               <&qpicbam 2>;
213        dma-names = "tx", "rx", "cmd";
214
215        #address-cells = <1>;
216        #size-cells = <0>;
217
218        nand@0 {
219            reg = <0>;
220            nand-ecc-strength = <4>;
221            nand-bus-width = <8>;
222
223            partitions {
224                compatible = "fixed-partitions";
225                #address-cells = <1>;
226                #size-cells = <1>;
227
228                partition@0 {
229                    label = "boot-nand";
230                    reg = <0 0x58a0000>;
231                };
232
233                partition@58a0000 {
234                    label = "fs-nand";
235                    reg = <0x58a0000 0x4000000>;
236                };
237            };
238        };
239    };
240
241...
242