1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MediaTek IOMMU Architecture Implementation 8 9maintainers: 10 - Yong Wu <yong.wu@mediatek.com> 11 12description: |+ 13 Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and 14 this M4U have two generations of HW architecture. Generation one uses flat 15 pagetable, and only supports 4K size page mapping. Generation two uses the 16 ARM Short-Descriptor translation table format for address translation. 17 18 About the M4U Hardware Block Diagram, please check below: 19 20 EMI (External Memory Interface) 21 | 22 m4u (Multimedia Memory Management Unit) 23 | 24 +--------+ 25 | | 26 gals0-rx gals1-rx (Global Async Local Sync rx) 27 | | 28 | | 29 gals0-tx gals1-tx (Global Async Local Sync tx) 30 | | Some SoCs may have GALS. 31 +--------+ 32 | 33 SMI Common(Smart Multimedia Interface Common) 34 | 35 +----------------+------- 36 | | 37 | gals-rx There may be GALS in some larbs. 38 | | 39 | | 40 | gals-tx 41 | | 42 SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb). 43 (display) (vdec) 44 | | 45 | | 46 +-----+-----+ +----+----+ 47 | | | | | | 48 | | |... | | | ... There are different ports in each larb. 49 | | | | | | 50 OVL0 RDMA0 WDMA0 MC PP VLD 51 52 As above, The Multimedia HW will go through SMI and M4U while it 53 access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain 54 smi local arbiter and smi common. It will control whether the Multimedia 55 HW should go though the m4u for translation or bypass it and talk 56 directly with EMI. And also SMI help control the power domain and clocks for 57 each local arbiter. 58 59 Normally we specify a local arbiter(larb) for each multimedia HW 60 like display, video decode, and camera. And there are different ports 61 in each larb. Take a example, There are many ports like MC, PP, VLD in the 62 video decode local arbiter, all these ports are according to the video HW. 63 64 In some SoCs, there may be a GALS(Global Async Local Sync) module between 65 smi-common and m4u, and additional GALS module between smi-larb and 66 smi-common. GALS can been seen as a "asynchronous fifo" which could help 67 synchronize for the modules in different clock frequency. 68 69properties: 70 compatible: 71 oneOf: 72 - enum: 73 - mediatek,mt2701-m4u # generation one 74 - mediatek,mt2712-m4u # generation two 75 - mediatek,mt6779-m4u # generation two 76 - mediatek,mt6795-m4u # generation two 77 - mediatek,mt6893-iommu-mm # generation two 78 - mediatek,mt8167-m4u # generation two 79 - mediatek,mt8173-m4u # generation two 80 - mediatek,mt8183-m4u # generation two 81 - mediatek,mt8186-iommu-mm # generation two 82 - mediatek,mt8188-iommu-vdo # generation two 83 - mediatek,mt8188-iommu-vpp # generation two 84 - mediatek,mt8188-iommu-infra # generation two 85 - mediatek,mt8192-m4u # generation two 86 - mediatek,mt8195-iommu-vdo # generation two 87 - mediatek,mt8195-iommu-vpp # generation two 88 - mediatek,mt8195-iommu-infra # generation two 89 - mediatek,mt8365-m4u # generation two 90 91 - description: mt7623 generation one 92 items: 93 - const: mediatek,mt7623-m4u 94 - const: mediatek,mt2701-m4u 95 96 reg: 97 maxItems: 1 98 99 interrupts: 100 maxItems: 1 101 102 clocks: 103 items: 104 - description: bclk is the block clock. 105 106 clock-names: 107 items: 108 - const: bclk 109 110 mediatek,infracfg: 111 $ref: /schemas/types.yaml#/definitions/phandle 112 description: The phandle to the mediatek infracfg syscon 113 114 mediatek,larbs: 115 $ref: /schemas/types.yaml#/definitions/phandle-array 116 minItems: 1 117 maxItems: 32 118 items: 119 maxItems: 1 120 description: | 121 List of phandle to the local arbiters in the current Socs. 122 Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort 123 according to the local arbiter index, like larb0, larb1, larb2... 124 125 '#iommu-cells': 126 const: 1 127 description: | 128 This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as 129 defined in 130 dt-binding/memory/mediatek,mt8188-memory-port.h for mt8188, 131 dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623, 132 dt-binding/memory/mt2712-larb-port.h for mt2712, 133 dt-binding/memory/mt6779-larb-port.h for mt6779, 134 dt-binding/memory/mt6795-larb-port.h for mt6795, 135 dt-binding/memory/mediatek,mt6893-memory-port.h for mt6893, 136 dt-binding/memory/mt8167-larb-port.h for mt8167, 137 dt-binding/memory/mt8173-larb-port.h for mt8173, 138 dt-binding/memory/mt8183-larb-port.h for mt8183, 139 dt-binding/memory/mt8186-memory-port.h for mt8186, 140 dt-binding/memory/mt8192-larb-port.h for mt8192. 141 dt-binding/memory/mt8195-memory-port.h for mt8195. 142 dt-binding/memory/mediatek,mt8365-larb-port.h for mt8365. 143 144 power-domains: 145 maxItems: 1 146 147required: 148 - compatible 149 - reg 150 - interrupts 151 - '#iommu-cells' 152 153allOf: 154 - if: 155 properties: 156 compatible: 157 contains: 158 enum: 159 - mediatek,mt2701-m4u 160 - mediatek,mt2712-m4u 161 - mediatek,mt6795-m4u 162 - mediatek,mt6893-iommu-mm 163 - mediatek,mt8173-m4u 164 - mediatek,mt8186-iommu-mm 165 - mediatek,mt8188-iommu-vdo 166 - mediatek,mt8188-iommu-vpp 167 - mediatek,mt8192-m4u 168 - mediatek,mt8195-iommu-vdo 169 - mediatek,mt8195-iommu-vpp 170 171 then: 172 required: 173 - clocks 174 175 - if: 176 properties: 177 compatible: 178 enum: 179 - mediatek,mt6893-iommu-mm 180 - mediatek,mt8186-iommu-mm 181 - mediatek,mt8188-iommu-vdo 182 - mediatek,mt8188-iommu-vpp 183 - mediatek,mt8192-m4u 184 - mediatek,mt8195-iommu-vdo 185 - mediatek,mt8195-iommu-vpp 186 187 then: 188 required: 189 - power-domains 190 191 - if: 192 properties: 193 compatible: 194 contains: 195 enum: 196 - mediatek,mt2712-m4u 197 - mediatek,mt6795-m4u 198 - mediatek,mt8173-m4u 199 200 then: 201 required: 202 - mediatek,infracfg 203 204 - if: # The IOMMUs don't have larbs. 205 not: 206 properties: 207 compatible: 208 contains: 209 enum: 210 - mediatek,mt8188-iommu-infra 211 - mediatek,mt8195-iommu-infra 212 213 then: 214 required: 215 - mediatek,larbs 216 217additionalProperties: false 218 219examples: 220 - | 221 #include <dt-bindings/clock/mt8173-clk.h> 222 #include <dt-bindings/interrupt-controller/arm-gic.h> 223 224 iommu: iommu@10205000 { 225 compatible = "mediatek,mt8173-m4u"; 226 reg = <0x10205000 0x1000>; 227 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 228 clocks = <&infracfg CLK_INFRA_M4U>; 229 clock-names = "bclk"; 230 mediatek,infracfg = <&infracfg>; 231 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 232 <&larb3>, <&larb4>, <&larb5>; 233 #iommu-cells = <1>; 234 }; 235