1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/crypto/qcom-qce.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm crypto engine driver
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Konrad Dybcio <konradybcio@kernel.org>
12
13description:
14  This document defines the binding for the QCE crypto
15  controller found on Qualcomm parts.
16
17properties:
18  compatible:
19    oneOf:
20      - const: qcom,crypto-v5.1
21        deprecated: true
22        description: Kept only for ABI backward compatibility
23
24      - const: qcom,crypto-v5.4
25        deprecated: true
26        description: Kept only for ABI backward compatibility
27
28      - items:
29          - enum:
30              - qcom,ipq4019-qce
31              - qcom,sm8150-qce
32          - const: qcom,qce
33
34      - items:
35          - enum:
36              - qcom,ipq6018-qce
37              - qcom,ipq8074-qce
38              - qcom,ipq9574-qce
39              - qcom,msm8996-qce
40              - qcom,qcm2290-qce
41              - qcom,sdm845-qce
42              - qcom,sm6115-qce
43          - const: qcom,ipq4019-qce
44          - const: qcom,qce
45
46      - items:
47          - enum:
48              - qcom,qcs615-qce
49              - qcom,qcs8300-qce
50              - qcom,sa8775p-qce
51              - qcom,sc7280-qce
52              - qcom,sm6350-qce
53              - qcom,sm8250-qce
54              - qcom,sm8350-qce
55              - qcom,sm8450-qce
56              - qcom,sm8550-qce
57              - qcom,sm8650-qce
58              - qcom,sm8750-qce
59              - qcom,x1e80100-qce
60          - const: qcom,sm8150-qce
61          - const: qcom,qce
62
63  reg:
64    maxItems: 1
65
66  clocks:
67    minItems: 1
68    maxItems: 3
69
70  clock-names:
71    minItems: 1
72    maxItems: 3
73
74  iommus:
75    minItems: 1
76    maxItems: 8
77    description:
78      phandle to apps_smmu node with sid mask.
79
80  interconnects:
81    maxItems: 1
82    description:
83      Interconnect path between qce crypto and main memory.
84
85  interconnect-names:
86    const: memory
87
88  dmas:
89    items:
90      - description: DMA specifiers for rx dma channel.
91      - description: DMA specifiers for tx dma channel.
92
93  dma-names:
94    items:
95      - const: rx
96      - const: tx
97
98allOf:
99  - if:
100      properties:
101        compatible:
102          contains:
103            enum:
104              - qcom,crypto-v5.1
105              - qcom,crypto-v5.4
106              - qcom,ipq6018-qce
107              - qcom,ipq8074-qce
108              - qcom,ipq9574-qce
109              - qcom,msm8996-qce
110              - qcom,sdm845-qce
111    then:
112      properties:
113        clocks:
114          maxItems: 3
115        clock-names:
116          items:
117            - const: iface
118            - const: bus
119            - const: core
120      required:
121        - clocks
122        - clock-names
123
124  - if:
125      properties:
126        compatible:
127          contains:
128            enum:
129              - qcom,qcm2290-qce
130              - qcom,sm6115-qce
131    then:
132      properties:
133        clocks:
134          maxItems: 1
135        clock-names:
136          items:
137            - const: core
138      required:
139        - clocks
140        - clock-names
141
142  - if:
143      properties:
144        compatible:
145          contains:
146            enum:
147              - qcom,sm8150-qce
148    then:
149      properties:
150        clocks: false
151        clock-names: false
152
153required:
154  - compatible
155  - reg
156  - dmas
157  - dma-names
158
159additionalProperties: false
160
161examples:
162  - |
163    #include <dt-bindings/clock/qcom,gcc-apq8084.h>
164    crypto-engine@fd45a000 {
165        compatible = "qcom,ipq6018-qce", "qcom,ipq4019-qce", "qcom,qce";
166        reg = <0xfd45a000 0x6000>;
167        clocks = <&gcc GCC_CE2_AHB_CLK>,
168                 <&gcc GCC_CE2_AXI_CLK>,
169                 <&gcc GCC_CE2_CLK>;
170        clock-names = "iface", "bus", "core";
171        dmas = <&cryptobam 2>, <&cryptobam 3>;
172        dma-names = "rx", "tx";
173        iommus = <&apps_smmu 0x584 0x0011>,
174                 <&apps_smmu 0x586 0x0011>,
175                 <&apps_smmu 0x594 0x0011>,
176                 <&apps_smmu 0x596 0x0011>;
177    };
178