xref: /linux/Documentation/devicetree/bindings/clock/qcom,qcs615-gpucc.yaml (revision 2d945dde7fa3f17f46349360a9f97614de9f47da) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Graphics Clock & Reset Controller on QCS615
8
9maintainers:
10  - Taniya Das <quic_tdas@quicinc.com>
11
12description: |
13  Qualcomm graphics clock control module provides clocks, resets and power
14  domains on QCS615 Qualcomm SoCs.
15
16  See also: include/dt-bindings/clock/qcom,qcs615-gpucc.h
17
18properties:
19  compatible:
20    const: qcom,qcs615-gpucc
21
22  clocks:
23    items:
24      - description: Board XO source
25      - description: GPLL0 main branch source
26      - description: GPLL0 GPUCC div branch source
27
28allOf:
29  - $ref: qcom,gcc.yaml#
30
31unevaluatedProperties: false
32
33examples:
34  - |
35    #include <dt-bindings/clock/qcom,rpmh.h>
36    #include <dt-bindings/clock/qcom,qcs615-gcc.h>
37
38    clock-controller@5090000 {
39      compatible = "qcom,qcs615-gpucc";
40      reg = <0x5090000 0x9000>;
41      clocks = <&rpmhcc RPMH_CXO_CLK>,
42               <&gcc GPLL0>,
43               <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
44
45      #clock-cells = <1>;
46      #reset-cells = <1>;
47      #power-domain-cells = <1>;
48    };
49...
50