1What:		/sys/bus/edac/devices/<dev-name>/ecs_fruX
2Date:		March 2025
3KernelVersion:	6.15
4Contact:	linux-edac@vger.kernel.org
5Description:
6		The sysfs EDAC bus devices /<dev-name>/ecs_fruX subdirectory
7		pertains to the memory media ECS (Error Check Scrub) control
8		feature, where <dev-name> directory corresponds to a device
9		registered with the EDAC device driver for the ECS feature.
10		/ecs_fruX belongs to the media FRUs (Field Replaceable Unit)
11		under the memory device.
12
13		The sysfs ECS attr nodes are only present if the parent
14		driver has implemented the corresponding attr callback
15		function and provided the necessary operations to the EDAC
16		device driver during registration.
17
18What:		/sys/bus/edac/devices/<dev-name>/ecs_fruX/log_entry_type
19Date:		March 2025
20KernelVersion:	6.15
21Contact:	linux-edac@vger.kernel.org
22Description:
23		(RW) The log entry type of how the DDR5 ECS log is reported.
24
25		- 0 - per DRAM.
26
27		- 1 - per memory media FRU.
28
29		- All other values are reserved.
30
31What:		/sys/bus/edac/devices/<dev-name>/ecs_fruX/mode
32Date:		March 2025
33KernelVersion:	6.15
34Contact:	linux-edac@vger.kernel.org
35Description:
36		(RW) The mode of how the DDR5 ECS counts the errors.
37		Error count is tracked based on two different modes
38		selected by DDR5 ECS Control Feature - Codeword mode and
39		Row Count mode. If the ECS is under Codeword mode, then
40		the error count increments each time a codeword with check
41		bit errors is detected. If the ECS is under Row Count mode,
42		then the error counter increments each time a row with
43		check bit errors is detected.
44
45		- 0 - ECS counts rows in the memory media that have ECC errors.
46
47		- 1 - ECS counts codewords with errors, specifically, it counts
48		      the number of ECC-detected errors in the memory media.
49
50		- All other values are reserved.
51
52What:		/sys/bus/edac/devices/<dev-name>/ecs_fruX/reset
53Date:		March 2025
54KernelVersion:	6.15
55Contact:	linux-edac@vger.kernel.org
56Description:
57		(WO) ECS reset ECC counter.
58
59		- 1 - reset ECC counter to the default value.
60
61		- All other values are reserved.
62
63What:		/sys/bus/edac/devices/<dev-name>/ecs_fruX/threshold
64Date:		March 2025
65KernelVersion:	6.15
66Contact:	linux-edac@vger.kernel.org
67Description:
68		(RW) DDR5 ECS threshold count per gigabits of memory cells.
69		The ECS error count is subject to the ECS Threshold count
70		per Gbit, which masks error counts less than the Threshold.
71
72		Supported values are 256, 1024 and 4096.
73
74		All other values are reserved.
75