1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * set_id_regs - Test for setting ID register from usersapce.
4 *
5 * Copyright (c) 2023 Google LLC.
6 *
7 *
8 * Test that KVM supports setting ID registers from userspace and handles the
9 * feature set correctly.
10 */
11
12 #include <stdint.h>
13 #include "kvm_util.h"
14 #include "processor.h"
15 #include "test_util.h"
16 #include <linux/bitfield.h>
17
18 enum ftr_type {
19 FTR_EXACT, /* Use a predefined safe value */
20 FTR_LOWER_SAFE, /* Smaller value is safe */
21 FTR_HIGHER_SAFE, /* Bigger value is safe */
22 FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */
23 FTR_END, /* Mark the last ftr bits */
24 };
25
26 #define FTR_SIGNED true /* Value should be treated as signed */
27 #define FTR_UNSIGNED false /* Value should be treated as unsigned */
28
29 struct reg_ftr_bits {
30 char *name;
31 bool sign;
32 enum ftr_type type;
33 uint8_t shift;
34 uint64_t mask;
35 int64_t safe_val;
36 };
37
38 struct test_feature_reg {
39 uint32_t reg;
40 const struct reg_ftr_bits *ftr_bits;
41 };
42
43 #define __REG_FTR_BITS(NAME, SIGNED, TYPE, SHIFT, MASK, SAFE_VAL) \
44 { \
45 .name = #NAME, \
46 .sign = SIGNED, \
47 .type = TYPE, \
48 .shift = SHIFT, \
49 .mask = MASK, \
50 .safe_val = SAFE_VAL, \
51 }
52
53 #define REG_FTR_BITS(type, reg, field, safe_val) \
54 __REG_FTR_BITS(reg##_##field, FTR_UNSIGNED, type, reg##_##field##_SHIFT, \
55 reg##_##field##_MASK, safe_val)
56
57 #define S_REG_FTR_BITS(type, reg, field, safe_val) \
58 __REG_FTR_BITS(reg##_##field, FTR_SIGNED, type, reg##_##field##_SHIFT, \
59 reg##_##field##_MASK, safe_val)
60
61 #define REG_FTR_END \
62 { \
63 .type = FTR_END, \
64 }
65
66 static const struct reg_ftr_bits ftr_id_aa64dfr0_el1[] = {
67 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, PMUVer, 0),
68 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DebugVer, 0),
69 REG_FTR_END,
70 };
71
72 static const struct reg_ftr_bits ftr_id_dfr0_el1[] = {
73 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, PerfMon, 0),
74 REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, CopDbg, 0),
75 REG_FTR_END,
76 };
77
78 static const struct reg_ftr_bits ftr_id_aa64isar0_el1[] = {
79 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RNDR, 0),
80 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TLB, 0),
81 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TS, 0),
82 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, FHM, 0),
83 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, DP, 0),
84 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM4, 0),
85 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM3, 0),
86 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA3, 0),
87 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RDM, 0),
88 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TME, 0),
89 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, ATOMIC, 0),
90 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, CRC32, 0),
91 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA2, 0),
92 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA1, 0),
93 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, AES, 0),
94 REG_FTR_END,
95 };
96
97 static const struct reg_ftr_bits ftr_id_aa64isar1_el1[] = {
98 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LS64, 0),
99 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, XS, 0),
100 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, I8MM, 0),
101 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DGH, 0),
102 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, BF16, 0),
103 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SPECRES, 0),
104 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SB, 0),
105 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FRINTTS, 0),
106 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LRCPC, 0),
107 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FCMA, 0),
108 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, JSCVT, 0),
109 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DPB, 0),
110 REG_FTR_END,
111 };
112
113 static const struct reg_ftr_bits ftr_id_aa64isar2_el1[] = {
114 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, BC, 0),
115 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, RPRES, 0),
116 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, WFxT, 0),
117 REG_FTR_END,
118 };
119
120 static const struct reg_ftr_bits ftr_id_aa64pfr0_el1[] = {
121 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV3, 0),
122 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV2, 0),
123 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, DIT, 0),
124 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, SEL2, 0),
125 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL3, 0),
126 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL2, 0),
127 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL1, 0),
128 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL0, 0),
129 REG_FTR_END,
130 };
131
132 static const struct reg_ftr_bits ftr_id_aa64mmfr0_el1[] = {
133 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, ECV, 0),
134 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, EXS, 0),
135 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN4, 0),
136 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN64, 0),
137 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN16, 0),
138 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGENDEL0, 0),
139 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, SNSMEM, 0),
140 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGEND, 0),
141 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, ASIDBITS, 0),
142 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, PARANGE, 0),
143 REG_FTR_END,
144 };
145
146 static const struct reg_ftr_bits ftr_id_aa64mmfr1_el1[] = {
147 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, TIDCP1, 0),
148 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, AFP, 0),
149 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, ETS, 0),
150 REG_FTR_BITS(FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1, SpecSEI, 0),
151 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, PAN, 0),
152 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, LO, 0),
153 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HPDS, 0),
154 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HAFDBS, 0),
155 REG_FTR_END,
156 };
157
158 static const struct reg_ftr_bits ftr_id_aa64mmfr2_el1[] = {
159 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, E0PD, 0),
160 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, BBM, 0),
161 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, TTL, 0),
162 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, AT, 0),
163 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, ST, 0),
164 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, VARange, 0),
165 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, IESB, 0),
166 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, LSM, 0),
167 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, UAO, 0),
168 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, CnP, 0),
169 REG_FTR_END,
170 };
171
172 static const struct reg_ftr_bits ftr_id_aa64zfr0_el1[] = {
173 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F64MM, 0),
174 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F32MM, 0),
175 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, I8MM, 0),
176 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SM4, 0),
177 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SHA3, 0),
178 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BF16, 0),
179 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BitPerm, 0),
180 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, AES, 0),
181 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SVEver, 0),
182 REG_FTR_END,
183 };
184
185 #define TEST_REG(id, table) \
186 { \
187 .reg = id, \
188 .ftr_bits = &((table)[0]), \
189 }
190
191 static struct test_feature_reg test_regs[] = {
192 TEST_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0_el1),
193 TEST_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0_el1),
194 TEST_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0_el1),
195 TEST_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1_el1),
196 TEST_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2_el1),
197 TEST_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0_el1),
198 TEST_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0_el1),
199 TEST_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1_el1),
200 TEST_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2_el1),
201 TEST_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0_el1),
202 };
203
204 #define GUEST_REG_SYNC(id) GUEST_SYNC_ARGS(0, id, read_sysreg_s(id), 0, 0);
205
guest_code(void)206 static void guest_code(void)
207 {
208 GUEST_REG_SYNC(SYS_ID_AA64DFR0_EL1);
209 GUEST_REG_SYNC(SYS_ID_DFR0_EL1);
210 GUEST_REG_SYNC(SYS_ID_AA64ISAR0_EL1);
211 GUEST_REG_SYNC(SYS_ID_AA64ISAR1_EL1);
212 GUEST_REG_SYNC(SYS_ID_AA64ISAR2_EL1);
213 GUEST_REG_SYNC(SYS_ID_AA64PFR0_EL1);
214 GUEST_REG_SYNC(SYS_ID_AA64MMFR0_EL1);
215 GUEST_REG_SYNC(SYS_ID_AA64MMFR1_EL1);
216 GUEST_REG_SYNC(SYS_ID_AA64MMFR2_EL1);
217 GUEST_REG_SYNC(SYS_ID_AA64ZFR0_EL1);
218
219 GUEST_DONE();
220 }
221
222 /* Return a safe value to a given ftr_bits an ftr value */
get_safe_value(const struct reg_ftr_bits * ftr_bits,uint64_t ftr)223 uint64_t get_safe_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
224 {
225 uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0);
226
227 if (ftr_bits->type == FTR_UNSIGNED) {
228 switch (ftr_bits->type) {
229 case FTR_EXACT:
230 ftr = ftr_bits->safe_val;
231 break;
232 case FTR_LOWER_SAFE:
233 if (ftr > 0)
234 ftr--;
235 break;
236 case FTR_HIGHER_SAFE:
237 if (ftr < ftr_max)
238 ftr++;
239 break;
240 case FTR_HIGHER_OR_ZERO_SAFE:
241 if (ftr == ftr_max)
242 ftr = 0;
243 else if (ftr != 0)
244 ftr++;
245 break;
246 default:
247 break;
248 }
249 } else if (ftr != ftr_max) {
250 switch (ftr_bits->type) {
251 case FTR_EXACT:
252 ftr = ftr_bits->safe_val;
253 break;
254 case FTR_LOWER_SAFE:
255 if (ftr > 0)
256 ftr--;
257 break;
258 case FTR_HIGHER_SAFE:
259 if (ftr < ftr_max - 1)
260 ftr++;
261 break;
262 case FTR_HIGHER_OR_ZERO_SAFE:
263 if (ftr != 0 && ftr != ftr_max - 1)
264 ftr++;
265 break;
266 default:
267 break;
268 }
269 }
270
271 return ftr;
272 }
273
274 /* Return an invalid value to a given ftr_bits an ftr value */
get_invalid_value(const struct reg_ftr_bits * ftr_bits,uint64_t ftr)275 uint64_t get_invalid_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
276 {
277 uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0);
278
279 if (ftr_bits->type == FTR_UNSIGNED) {
280 switch (ftr_bits->type) {
281 case FTR_EXACT:
282 ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1);
283 break;
284 case FTR_LOWER_SAFE:
285 ftr++;
286 break;
287 case FTR_HIGHER_SAFE:
288 ftr--;
289 break;
290 case FTR_HIGHER_OR_ZERO_SAFE:
291 if (ftr == 0)
292 ftr = ftr_max;
293 else
294 ftr--;
295 break;
296 default:
297 break;
298 }
299 } else if (ftr != ftr_max) {
300 switch (ftr_bits->type) {
301 case FTR_EXACT:
302 ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1);
303 break;
304 case FTR_LOWER_SAFE:
305 ftr++;
306 break;
307 case FTR_HIGHER_SAFE:
308 ftr--;
309 break;
310 case FTR_HIGHER_OR_ZERO_SAFE:
311 if (ftr == 0)
312 ftr = ftr_max - 1;
313 else
314 ftr--;
315 break;
316 default:
317 break;
318 }
319 } else {
320 ftr = 0;
321 }
322
323 return ftr;
324 }
325
test_reg_set_success(struct kvm_vcpu * vcpu,uint64_t reg,const struct reg_ftr_bits * ftr_bits)326 static void test_reg_set_success(struct kvm_vcpu *vcpu, uint64_t reg,
327 const struct reg_ftr_bits *ftr_bits)
328 {
329 uint8_t shift = ftr_bits->shift;
330 uint64_t mask = ftr_bits->mask;
331 uint64_t val, new_val, ftr;
332
333 vcpu_get_reg(vcpu, reg, &val);
334 ftr = (val & mask) >> shift;
335
336 ftr = get_safe_value(ftr_bits, ftr);
337
338 ftr <<= shift;
339 val &= ~mask;
340 val |= ftr;
341
342 vcpu_set_reg(vcpu, reg, val);
343 vcpu_get_reg(vcpu, reg, &new_val);
344 TEST_ASSERT_EQ(new_val, val);
345 }
346
test_reg_set_fail(struct kvm_vcpu * vcpu,uint64_t reg,const struct reg_ftr_bits * ftr_bits)347 static void test_reg_set_fail(struct kvm_vcpu *vcpu, uint64_t reg,
348 const struct reg_ftr_bits *ftr_bits)
349 {
350 uint8_t shift = ftr_bits->shift;
351 uint64_t mask = ftr_bits->mask;
352 uint64_t val, old_val, ftr;
353 int r;
354
355 vcpu_get_reg(vcpu, reg, &val);
356 ftr = (val & mask) >> shift;
357
358 ftr = get_invalid_value(ftr_bits, ftr);
359
360 old_val = val;
361 ftr <<= shift;
362 val &= ~mask;
363 val |= ftr;
364
365 r = __vcpu_set_reg(vcpu, reg, val);
366 TEST_ASSERT(r < 0 && errno == EINVAL,
367 "Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno);
368
369 vcpu_get_reg(vcpu, reg, &val);
370 TEST_ASSERT_EQ(val, old_val);
371 }
372
test_user_set_reg(struct kvm_vcpu * vcpu,bool aarch64_only)373 static void test_user_set_reg(struct kvm_vcpu *vcpu, bool aarch64_only)
374 {
375 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
376 struct reg_mask_range range = {
377 .addr = (__u64)masks,
378 };
379 int ret;
380
381 /* KVM should return error when reserved field is not zero */
382 range.reserved[0] = 1;
383 ret = __vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
384 TEST_ASSERT(ret, "KVM doesn't check invalid parameters.");
385
386 /* Get writable masks for feature ID registers */
387 memset(range.reserved, 0, sizeof(range.reserved));
388 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
389
390 for (int i = 0; i < ARRAY_SIZE(test_regs); i++) {
391 const struct reg_ftr_bits *ftr_bits = test_regs[i].ftr_bits;
392 uint32_t reg_id = test_regs[i].reg;
393 uint64_t reg = KVM_ARM64_SYS_REG(reg_id);
394 int idx;
395
396 /* Get the index to masks array for the idreg */
397 idx = KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(reg_id), sys_reg_Op1(reg_id),
398 sys_reg_CRn(reg_id), sys_reg_CRm(reg_id),
399 sys_reg_Op2(reg_id));
400
401 for (int j = 0; ftr_bits[j].type != FTR_END; j++) {
402 /* Skip aarch32 reg on aarch64 only system, since they are RAZ/WI. */
403 if (aarch64_only && sys_reg_CRm(reg_id) < 4) {
404 ksft_test_result_skip("%s on AARCH64 only system\n",
405 ftr_bits[j].name);
406 continue;
407 }
408
409 /* Make sure the feature field is writable */
410 TEST_ASSERT_EQ(masks[idx] & ftr_bits[j].mask, ftr_bits[j].mask);
411
412 test_reg_set_fail(vcpu, reg, &ftr_bits[j]);
413 test_reg_set_success(vcpu, reg, &ftr_bits[j]);
414
415 ksft_test_result_pass("%s\n", ftr_bits[j].name);
416 }
417 }
418 }
419
test_guest_reg_read(struct kvm_vcpu * vcpu)420 static void test_guest_reg_read(struct kvm_vcpu *vcpu)
421 {
422 bool done = false;
423 struct ucall uc;
424 uint64_t val;
425
426 while (!done) {
427 vcpu_run(vcpu);
428
429 switch (get_ucall(vcpu, &uc)) {
430 case UCALL_ABORT:
431 REPORT_GUEST_ASSERT(uc);
432 break;
433 case UCALL_SYNC:
434 /* Make sure the written values are seen by guest */
435 vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(uc.args[2]), &val);
436 TEST_ASSERT_EQ(val, uc.args[3]);
437 break;
438 case UCALL_DONE:
439 done = true;
440 break;
441 default:
442 TEST_FAIL("Unexpected ucall: %lu", uc.cmd);
443 }
444 }
445 }
446
main(void)447 int main(void)
448 {
449 struct kvm_vcpu *vcpu;
450 struct kvm_vm *vm;
451 bool aarch64_only;
452 uint64_t val, el0;
453 int ftr_cnt;
454
455 TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES));
456
457 vm = vm_create_with_one_vcpu(&vcpu, guest_code);
458
459 /* Check for AARCH64 only system */
460 vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), &val);
461 el0 = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), val);
462 aarch64_only = (el0 == ID_AA64PFR0_EL1_ELx_64BIT_ONLY);
463
464 ksft_print_header();
465
466 ftr_cnt = ARRAY_SIZE(ftr_id_aa64dfr0_el1) + ARRAY_SIZE(ftr_id_dfr0_el1) +
467 ARRAY_SIZE(ftr_id_aa64isar0_el1) + ARRAY_SIZE(ftr_id_aa64isar1_el1) +
468 ARRAY_SIZE(ftr_id_aa64isar2_el1) + ARRAY_SIZE(ftr_id_aa64pfr0_el1) +
469 ARRAY_SIZE(ftr_id_aa64mmfr0_el1) + ARRAY_SIZE(ftr_id_aa64mmfr1_el1) +
470 ARRAY_SIZE(ftr_id_aa64mmfr2_el1) + ARRAY_SIZE(ftr_id_aa64zfr0_el1) -
471 ARRAY_SIZE(test_regs);
472
473 ksft_set_plan(ftr_cnt);
474
475 test_user_set_reg(vcpu, aarch64_only);
476 test_guest_reg_read(vcpu);
477
478 kvm_vm_free(vm);
479
480 ksft_finished();
481 }
482