1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // Copyright 2021-2022 NXP
4 //
5 // Author: Peng Zhang <peng.zhang_8@nxp.com>
6 //
7 // Hardware interface for audio DSP on i.MX8ULP
8
9 #include <linux/arm-smccc.h>
10 #include <linux/clk.h>
11 #include <linux/firmware.h>
12 #include <linux/firmware/imx/dsp.h>
13 #include <linux/firmware/imx/ipc.h>
14 #include <linux/firmware/imx/svc/misc.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/module.h>
17 #include <linux/of_address.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_platform.h>
20 #include <linux/of_reserved_mem.h>
21
22 #include <sound/sof.h>
23 #include <sound/sof/xtensa.h>
24
25 #include "../ops.h"
26 #include "../sof-of-dev.h"
27 #include "imx-common.h"
28
29 #define FSL_SIP_HIFI_XRDC 0xc200000e
30
31 /* SIM Domain register */
32 #define SYSCTRL0 0x8
33 #define EXECUTE_BIT BIT(13)
34 #define RESET_BIT BIT(16)
35 #define HIFI4_CLK_BIT BIT(17)
36 #define PB_CLK_BIT BIT(18)
37 #define PLAT_CLK_BIT BIT(19)
38 #define DEBUG_LOGIC_BIT BIT(25)
39
40 #define MBOX_OFFSET 0x800000
41 #define MBOX_SIZE 0x1000
42
43 static struct clk_bulk_data imx8ulp_dsp_clks[] = {
44 { .id = "core" },
45 { .id = "ipg" },
46 { .id = "ocram" },
47 { .id = "mu" },
48 };
49
50 struct imx8ulp_priv {
51 struct device *dev;
52 struct snd_sof_dev *sdev;
53
54 /* DSP IPC handler */
55 struct imx_dsp_ipc *dsp_ipc;
56 struct platform_device *ipc_dev;
57
58 struct regmap *regmap;
59 struct imx_clocks *clks;
60 };
61
imx8ulp_sim_lpav_start(struct imx8ulp_priv * priv)62 static void imx8ulp_sim_lpav_start(struct imx8ulp_priv *priv)
63 {
64 /* Controls the HiFi4 DSP Reset: 1 in reset, 0 out of reset */
65 regmap_update_bits(priv->regmap, SYSCTRL0, RESET_BIT, 0);
66
67 /* Reset HiFi4 DSP Debug logic: 1 debug reset, 0 out of reset*/
68 regmap_update_bits(priv->regmap, SYSCTRL0, DEBUG_LOGIC_BIT, 0);
69
70 /* Stall HIFI4 DSP Execution: 1 stall, 0 run */
71 regmap_update_bits(priv->regmap, SYSCTRL0, EXECUTE_BIT, 0);
72 }
73
imx8ulp_get_mailbox_offset(struct snd_sof_dev * sdev)74 static int imx8ulp_get_mailbox_offset(struct snd_sof_dev *sdev)
75 {
76 return MBOX_OFFSET;
77 }
78
imx8ulp_get_window_offset(struct snd_sof_dev * sdev,u32 id)79 static int imx8ulp_get_window_offset(struct snd_sof_dev *sdev, u32 id)
80 {
81 return MBOX_OFFSET;
82 }
83
imx8ulp_dsp_handle_reply(struct imx_dsp_ipc * ipc)84 static void imx8ulp_dsp_handle_reply(struct imx_dsp_ipc *ipc)
85 {
86 struct imx8ulp_priv *priv = imx_dsp_get_data(ipc);
87 unsigned long flags;
88
89 spin_lock_irqsave(&priv->sdev->ipc_lock, flags);
90
91 snd_sof_ipc_process_reply(priv->sdev, 0);
92
93 spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags);
94 }
95
imx8ulp_dsp_handle_request(struct imx_dsp_ipc * ipc)96 static void imx8ulp_dsp_handle_request(struct imx_dsp_ipc *ipc)
97 {
98 struct imx8ulp_priv *priv = imx_dsp_get_data(ipc);
99 u32 p; /* panic code */
100
101 /* Read the message from the debug box. */
102 sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4, &p, sizeof(p));
103
104 /* Check to see if the message is a panic code (0x0dead***) */
105 if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC)
106 snd_sof_dsp_panic(priv->sdev, p, true);
107 else
108 snd_sof_ipc_msgs_rx(priv->sdev);
109 }
110
111 static struct imx_dsp_ops dsp_ops = {
112 .handle_reply = imx8ulp_dsp_handle_reply,
113 .handle_request = imx8ulp_dsp_handle_request,
114 };
115
imx8ulp_send_msg(struct snd_sof_dev * sdev,struct snd_sof_ipc_msg * msg)116 static int imx8ulp_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
117 {
118 struct imx8ulp_priv *priv = sdev->pdata->hw_pdata;
119
120 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
121 msg->msg_size);
122 imx_dsp_ring_doorbell(priv->dsp_ipc, 0);
123
124 return 0;
125 }
126
imx8ulp_run(struct snd_sof_dev * sdev)127 static int imx8ulp_run(struct snd_sof_dev *sdev)
128 {
129 struct imx8ulp_priv *priv = sdev->pdata->hw_pdata;
130
131 imx8ulp_sim_lpav_start(priv);
132
133 return 0;
134 }
135
imx8ulp_reset(struct snd_sof_dev * sdev)136 static int imx8ulp_reset(struct snd_sof_dev *sdev)
137 {
138 struct imx8ulp_priv *priv = sdev->pdata->hw_pdata;
139 struct arm_smccc_res smc_resource;
140
141 /* HiFi4 Platform Clock Enable: 1 enabled, 0 disabled */
142 regmap_update_bits(priv->regmap, SYSCTRL0, PLAT_CLK_BIT, PLAT_CLK_BIT);
143
144 /* HiFi4 PBCLK clock enable: 1 enabled, 0 disabled */
145 regmap_update_bits(priv->regmap, SYSCTRL0, PB_CLK_BIT, PB_CLK_BIT);
146
147 /* HiFi4 Clock Enable: 1 enabled, 0 disabled */
148 regmap_update_bits(priv->regmap, SYSCTRL0, HIFI4_CLK_BIT, HIFI4_CLK_BIT);
149
150 regmap_update_bits(priv->regmap, SYSCTRL0, RESET_BIT, RESET_BIT);
151 usleep_range(1, 2);
152
153 /* Stall HIFI4 DSP Execution: 1 stall, 0 not stall */
154 regmap_update_bits(priv->regmap, SYSCTRL0, EXECUTE_BIT, EXECUTE_BIT);
155 usleep_range(1, 2);
156
157 arm_smccc_smc(FSL_SIP_HIFI_XRDC, 0, 0, 0, 0, 0, 0, 0, &smc_resource);
158
159 return 0;
160 }
161
imx8ulp_probe(struct snd_sof_dev * sdev)162 static int imx8ulp_probe(struct snd_sof_dev *sdev)
163 {
164 struct platform_device *pdev =
165 container_of(sdev->dev, struct platform_device, dev);
166 struct device_node *np = pdev->dev.of_node;
167 struct device_node *res_node;
168 struct resource *mmio;
169 struct imx8ulp_priv *priv;
170 struct resource res;
171 u32 base, size;
172 int ret = 0;
173
174 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
175 if (!priv)
176 return -ENOMEM;
177
178 priv->clks = devm_kzalloc(&pdev->dev, sizeof(*priv->clks), GFP_KERNEL);
179 if (!priv->clks)
180 return -ENOMEM;
181
182 sdev->num_cores = 1;
183 sdev->pdata->hw_pdata = priv;
184 priv->dev = sdev->dev;
185 priv->sdev = sdev;
186
187 /* System integration module(SIM) control dsp configuration */
188 priv->regmap = syscon_regmap_lookup_by_phandle(np, "fsl,dsp-ctrl");
189 if (IS_ERR(priv->regmap))
190 return PTR_ERR(priv->regmap);
191
192 priv->ipc_dev = platform_device_register_data(sdev->dev, "imx-dsp",
193 PLATFORM_DEVID_NONE,
194 pdev, sizeof(*pdev));
195 if (IS_ERR(priv->ipc_dev))
196 return PTR_ERR(priv->ipc_dev);
197
198 priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev);
199 if (!priv->dsp_ipc) {
200 /* DSP IPC driver not probed yet, try later */
201 ret = -EPROBE_DEFER;
202 dev_err(sdev->dev, "Failed to get drvdata\n");
203 goto exit_pdev_unregister;
204 }
205
206 imx_dsp_set_data(priv->dsp_ipc, priv);
207 priv->dsp_ipc->ops = &dsp_ops;
208
209 /* DSP base */
210 mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
211 if (mmio) {
212 base = mmio->start;
213 size = resource_size(mmio);
214 } else {
215 dev_err(sdev->dev, "error: failed to get DSP base at idx 0\n");
216 ret = -EINVAL;
217 goto exit_pdev_unregister;
218 }
219
220 sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev, base, size);
221 if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) {
222 dev_err(sdev->dev, "failed to ioremap base 0x%x size 0x%x\n",
223 base, size);
224 ret = -ENODEV;
225 goto exit_pdev_unregister;
226 }
227 sdev->mmio_bar = SOF_FW_BLK_TYPE_IRAM;
228
229 res_node = of_parse_phandle(np, "memory-reserved", 0);
230 if (!res_node) {
231 dev_err(&pdev->dev, "failed to get memory region node\n");
232 ret = -ENODEV;
233 goto exit_pdev_unregister;
234 }
235
236 ret = of_address_to_resource(res_node, 0, &res);
237 of_node_put(res_node);
238 if (ret) {
239 dev_err(&pdev->dev, "failed to get reserved region address\n");
240 goto exit_pdev_unregister;
241 }
242
243 sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev, res.start,
244 resource_size(&res));
245 if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) {
246 dev_err(sdev->dev, "failed to ioremap mem 0x%x size 0x%x\n",
247 base, size);
248 ret = -ENOMEM;
249 goto exit_pdev_unregister;
250 }
251 sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;
252
253 /* set default mailbox offset for FW ready message */
254 sdev->dsp_box.offset = MBOX_OFFSET;
255
256 ret = of_reserved_mem_device_init(sdev->dev);
257 if (ret) {
258 dev_err(&pdev->dev, "failed to init reserved memory region %d\n", ret);
259 goto exit_pdev_unregister;
260 }
261
262 priv->clks->dsp_clks = imx8ulp_dsp_clks;
263 priv->clks->num_dsp_clks = ARRAY_SIZE(imx8ulp_dsp_clks);
264
265 ret = imx8_parse_clocks(sdev, priv->clks);
266 if (ret < 0)
267 goto exit_pdev_unregister;
268
269 ret = imx8_enable_clocks(sdev, priv->clks);
270 if (ret < 0)
271 goto exit_pdev_unregister;
272
273 return 0;
274
275 exit_pdev_unregister:
276 platform_device_unregister(priv->ipc_dev);
277
278 return ret;
279 }
280
imx8ulp_remove(struct snd_sof_dev * sdev)281 static void imx8ulp_remove(struct snd_sof_dev *sdev)
282 {
283 struct imx8ulp_priv *priv = sdev->pdata->hw_pdata;
284
285 imx8_disable_clocks(sdev, priv->clks);
286 platform_device_unregister(priv->ipc_dev);
287 }
288
289 /* on i.MX8 there is 1 to 1 match between type and BAR idx */
imx8ulp_get_bar_index(struct snd_sof_dev * sdev,u32 type)290 static int imx8ulp_get_bar_index(struct snd_sof_dev *sdev, u32 type)
291 {
292 return type;
293 }
294
imx8ulp_suspend(struct snd_sof_dev * sdev)295 static int imx8ulp_suspend(struct snd_sof_dev *sdev)
296 {
297 int i;
298 struct imx8ulp_priv *priv = (struct imx8ulp_priv *)sdev->pdata->hw_pdata;
299
300 /*Stall DSP, release in .run() */
301 regmap_update_bits(priv->regmap, SYSCTRL0, EXECUTE_BIT, EXECUTE_BIT);
302
303 for (i = 0; i < DSP_MU_CHAN_NUM; i++)
304 imx_dsp_free_channel(priv->dsp_ipc, i);
305
306 imx8_disable_clocks(sdev, priv->clks);
307
308 return 0;
309 }
310
imx8ulp_resume(struct snd_sof_dev * sdev)311 static int imx8ulp_resume(struct snd_sof_dev *sdev)
312 {
313 struct imx8ulp_priv *priv = (struct imx8ulp_priv *)sdev->pdata->hw_pdata;
314 int i;
315
316 imx8_enable_clocks(sdev, priv->clks);
317
318 for (i = 0; i < DSP_MU_CHAN_NUM; i++)
319 imx_dsp_request_channel(priv->dsp_ipc, i);
320
321 return 0;
322 }
323
imx8ulp_dsp_runtime_resume(struct snd_sof_dev * sdev)324 static int imx8ulp_dsp_runtime_resume(struct snd_sof_dev *sdev)
325 {
326 const struct sof_dsp_power_state target_dsp_state = {
327 .state = SOF_DSP_PM_D0,
328 .substate = 0,
329 };
330
331 imx8ulp_resume(sdev);
332
333 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
334 }
335
imx8ulp_dsp_runtime_suspend(struct snd_sof_dev * sdev)336 static int imx8ulp_dsp_runtime_suspend(struct snd_sof_dev *sdev)
337 {
338 const struct sof_dsp_power_state target_dsp_state = {
339 .state = SOF_DSP_PM_D3,
340 .substate = 0,
341 };
342
343 imx8ulp_suspend(sdev);
344
345 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
346 }
347
imx8ulp_dsp_suspend(struct snd_sof_dev * sdev,unsigned int target_state)348 static int imx8ulp_dsp_suspend(struct snd_sof_dev *sdev, unsigned int target_state)
349 {
350 const struct sof_dsp_power_state target_dsp_state = {
351 .state = target_state,
352 .substate = 0,
353 };
354
355 if (!pm_runtime_suspended(sdev->dev))
356 imx8ulp_suspend(sdev);
357
358 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
359 }
360
imx8ulp_dsp_resume(struct snd_sof_dev * sdev)361 static int imx8ulp_dsp_resume(struct snd_sof_dev *sdev)
362 {
363 const struct sof_dsp_power_state target_dsp_state = {
364 .state = SOF_DSP_PM_D0,
365 .substate = 0,
366 };
367
368 imx8ulp_resume(sdev);
369
370 if (pm_runtime_suspended(sdev->dev)) {
371 pm_runtime_disable(sdev->dev);
372 pm_runtime_set_active(sdev->dev);
373 pm_runtime_mark_last_busy(sdev->dev);
374 pm_runtime_enable(sdev->dev);
375 pm_runtime_idle(sdev->dev);
376 }
377
378 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
379 }
380
381 static struct snd_soc_dai_driver imx8ulp_dai[] = {
382 {
383 .name = "sai5",
384 .playback = {
385 .channels_min = 1,
386 .channels_max = 32,
387 },
388 .capture = {
389 .channels_min = 1,
390 .channels_max = 32,
391 },
392 },
393 {
394 .name = "sai6",
395 .playback = {
396 .channels_min = 1,
397 .channels_max = 32,
398 },
399 .capture = {
400 .channels_min = 1,
401 .channels_max = 32,
402 },
403 },
404 };
405
imx8ulp_dsp_set_power_state(struct snd_sof_dev * sdev,const struct sof_dsp_power_state * target_state)406 static int imx8ulp_dsp_set_power_state(struct snd_sof_dev *sdev,
407 const struct sof_dsp_power_state *target_state)
408 {
409 sdev->dsp_power_state = *target_state;
410
411 return 0;
412 }
413
414 /* i.MX8 ops */
415 static struct snd_sof_dsp_ops sof_imx8ulp_ops = {
416 /* probe and remove */
417 .probe = imx8ulp_probe,
418 .remove = imx8ulp_remove,
419 /* DSP core boot */
420 .run = imx8ulp_run,
421 .reset = imx8ulp_reset,
422
423 /* Block IO */
424 .block_read = sof_block_read,
425 .block_write = sof_block_write,
426
427 /* Module IO */
428 .read64 = sof_io_read64,
429
430 /* Mailbox IO */
431 .mailbox_read = sof_mailbox_read,
432 .mailbox_write = sof_mailbox_write,
433
434 /* ipc */
435 .send_msg = imx8ulp_send_msg,
436 .get_mailbox_offset = imx8ulp_get_mailbox_offset,
437 .get_window_offset = imx8ulp_get_window_offset,
438
439 .ipc_msg_data = sof_ipc_msg_data,
440 .set_stream_data_offset = sof_set_stream_data_offset,
441
442 /* stream callbacks */
443 .pcm_open = sof_stream_pcm_open,
444 .pcm_close = sof_stream_pcm_close,
445
446 /* module loading */
447 .get_bar_index = imx8ulp_get_bar_index,
448 /* firmware loading */
449 .load_firmware = snd_sof_load_firmware_memcpy,
450
451 /* Debug information */
452 .dbg_dump = imx8_dump,
453
454 /* Firmware ops */
455 .dsp_arch_ops = &sof_xtensa_arch_ops,
456
457 /* DAI drivers */
458 .drv = imx8ulp_dai,
459 .num_drv = ARRAY_SIZE(imx8ulp_dai),
460
461 /* ALSA HW info flags */
462 .hw_info = SNDRV_PCM_INFO_MMAP |
463 SNDRV_PCM_INFO_MMAP_VALID |
464 SNDRV_PCM_INFO_INTERLEAVED |
465 SNDRV_PCM_INFO_PAUSE |
466 SNDRV_PCM_INFO_BATCH |
467 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
468
469 /* PM */
470 .runtime_suspend = imx8ulp_dsp_runtime_suspend,
471 .runtime_resume = imx8ulp_dsp_runtime_resume,
472
473 .suspend = imx8ulp_dsp_suspend,
474 .resume = imx8ulp_dsp_resume,
475
476 .set_power_state = imx8ulp_dsp_set_power_state,
477 };
478
479 static struct sof_dev_desc sof_of_imx8ulp_desc = {
480 .ipc_supported_mask = BIT(SOF_IPC_TYPE_3),
481 .ipc_default = SOF_IPC_TYPE_3,
482 .default_fw_path = {
483 [SOF_IPC_TYPE_3] = "imx/sof",
484 },
485 .default_tplg_path = {
486 [SOF_IPC_TYPE_3] = "imx/sof-tplg",
487 },
488 .default_fw_filename = {
489 [SOF_IPC_TYPE_3] = "sof-imx8ulp.ri",
490 },
491 .nocodec_tplg_filename = "sof-imx8ulp-nocodec.tplg",
492 .ops = &sof_imx8ulp_ops,
493 };
494
495 static const struct of_device_id sof_of_imx8ulp_ids[] = {
496 { .compatible = "fsl,imx8ulp-dsp", .data = &sof_of_imx8ulp_desc},
497 { }
498 };
499 MODULE_DEVICE_TABLE(of, sof_of_imx8ulp_ids);
500
501 /* DT driver definition */
502 static struct platform_driver snd_sof_of_imx8ulp_driver = {
503 .probe = sof_of_probe,
504 .remove_new = sof_of_remove,
505 .driver = {
506 .name = "sof-audio-of-imx8ulp",
507 .pm = &sof_of_pm,
508 .of_match_table = sof_of_imx8ulp_ids,
509 },
510 };
511 module_platform_driver(snd_sof_of_imx8ulp_driver);
512
513 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
514 MODULE_LICENSE("Dual BSD/GPL");
515