1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
5 //
6 // Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
7 //
8 // Authors: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
9 // Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
10
11 /*
12 * Hardware interface for generic AMD ACP processor
13 */
14
15 #include <linux/io.h>
16 #include <linux/module.h>
17 #include <linux/pci.h>
18
19 #include "../ops.h"
20 #include "acp.h"
21 #include "acp-dsp-offset.h"
22
23 #define SECURED_FIRMWARE 1
24
25 static bool enable_fw_debug;
26 module_param(enable_fw_debug, bool, 0444);
27 MODULE_PARM_DESC(enable_fw_debug, "Enable Firmware debug");
28
29 const struct dmi_system_id acp_sof_quirk_table[] = {
30 {
31 /* Valve Jupiter device */
32 .matches = {
33 DMI_MATCH(DMI_SYS_VENDOR, "Valve"),
34 DMI_MATCH(DMI_PRODUCT_NAME, "Galileo"),
35 DMI_MATCH(DMI_PRODUCT_FAMILY, "Sephiroth"),
36 },
37 .driver_data = (void *)SECURED_FIRMWARE,
38 },
39 {}
40 };
41 EXPORT_SYMBOL_GPL(acp_sof_quirk_table);
42
smn_write(struct pci_dev * dev,u32 smn_addr,u32 data)43 static int smn_write(struct pci_dev *dev, u32 smn_addr, u32 data)
44 {
45 pci_write_config_dword(dev, 0x60, smn_addr);
46 pci_write_config_dword(dev, 0x64, data);
47
48 return 0;
49 }
50
smn_read(struct pci_dev * dev,u32 smn_addr)51 static int smn_read(struct pci_dev *dev, u32 smn_addr)
52 {
53 u32 data = 0;
54
55 pci_write_config_dword(dev, 0x60, smn_addr);
56 pci_read_config_dword(dev, 0x64, &data);
57
58 return data;
59 }
60
init_dma_descriptor(struct acp_dev_data * adata)61 static void init_dma_descriptor(struct acp_dev_data *adata)
62 {
63 struct snd_sof_dev *sdev = adata->dev;
64 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
65 unsigned int addr;
66
67 addr = desc->sram_pte_offset + sdev->debug_box.offset +
68 offsetof(struct scratch_reg_conf, dma_desc);
69
70 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DESC_BASE_ADDR, addr);
71 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DESC_MAX_NUM_DSCR, ACP_MAX_DESC_CNT);
72 }
73
configure_dma_descriptor(struct acp_dev_data * adata,unsigned short idx,struct dma_descriptor * dscr_info)74 static void configure_dma_descriptor(struct acp_dev_data *adata, unsigned short idx,
75 struct dma_descriptor *dscr_info)
76 {
77 struct snd_sof_dev *sdev = adata->dev;
78 unsigned int offset;
79
80 offset = ACP_SCRATCH_REG_0 + sdev->debug_box.offset +
81 offsetof(struct scratch_reg_conf, dma_desc) +
82 idx * sizeof(struct dma_descriptor);
83
84 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset, dscr_info->src_addr);
85 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x4, dscr_info->dest_addr);
86 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x8, dscr_info->tx_cnt.u32_all);
87 }
88
config_dma_channel(struct acp_dev_data * adata,unsigned int ch,unsigned int idx,unsigned int dscr_count)89 static int config_dma_channel(struct acp_dev_data *adata, unsigned int ch,
90 unsigned int idx, unsigned int dscr_count)
91 {
92 struct snd_sof_dev *sdev = adata->dev;
93 unsigned int val, status;
94 int ret;
95
96 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32),
97 ACP_DMA_CH_RST | ACP_DMA_CH_GRACEFUL_RST_EN);
98
99 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_DMA_CH_RST_STS, val,
100 val & (1 << ch), ACP_REG_POLL_INTERVAL,
101 ACP_REG_POLL_TIMEOUT_US);
102 if (ret < 0) {
103 status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_ERROR_STATUS);
104 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_ERR_STS_0 + ch * sizeof(u32));
105
106 dev_err(sdev->dev, "ACP_DMA_ERR_STS :0x%x ACP_ERROR_STATUS :0x%x\n", val, status);
107 return ret;
108 }
109
110 snd_sof_dsp_write(sdev, ACP_DSP_BAR, (ACP_DMA_CNTL_0 + ch * sizeof(u32)), 0);
111 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DSCR_CNT_0 + ch * sizeof(u32), dscr_count);
112 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DSCR_STRT_IDX_0 + ch * sizeof(u32), idx);
113 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_PRIO_0 + ch * sizeof(u32), 0);
114 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32), ACP_DMA_CH_RUN);
115
116 return ret;
117 }
118
acpbus_dma_start(struct acp_dev_data * adata,unsigned int ch,unsigned int dscr_count,struct dma_descriptor * dscr_info)119 static int acpbus_dma_start(struct acp_dev_data *adata, unsigned int ch,
120 unsigned int dscr_count, struct dma_descriptor *dscr_info)
121 {
122 struct snd_sof_dev *sdev = adata->dev;
123 int ret;
124 u16 dscr;
125
126 if (!dscr_info || !dscr_count)
127 return -EINVAL;
128
129 for (dscr = 0; dscr < dscr_count; dscr++)
130 configure_dma_descriptor(adata, dscr, dscr_info++);
131
132 ret = config_dma_channel(adata, ch, 0, dscr_count);
133 if (ret < 0)
134 dev_err(sdev->dev, "config dma ch failed:%d\n", ret);
135
136 return ret;
137 }
138
configure_and_run_dma(struct acp_dev_data * adata,unsigned int src_addr,unsigned int dest_addr,int dsp_data_size)139 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr,
140 unsigned int dest_addr, int dsp_data_size)
141 {
142 struct snd_sof_dev *sdev = adata->dev;
143 unsigned int desc_count, index;
144 int ret;
145
146 for (desc_count = 0; desc_count < ACP_MAX_DESC && dsp_data_size >= 0;
147 desc_count++, dsp_data_size -= ACP_PAGE_SIZE) {
148 adata->dscr_info[desc_count].src_addr = src_addr + desc_count * ACP_PAGE_SIZE;
149 adata->dscr_info[desc_count].dest_addr = dest_addr + desc_count * ACP_PAGE_SIZE;
150 adata->dscr_info[desc_count].tx_cnt.bits.count = ACP_PAGE_SIZE;
151 if (dsp_data_size < ACP_PAGE_SIZE)
152 adata->dscr_info[desc_count].tx_cnt.bits.count = dsp_data_size;
153 }
154
155 ret = acpbus_dma_start(adata, 0, desc_count, adata->dscr_info);
156 if (ret)
157 dev_err(sdev->dev, "acpbus_dma_start failed\n");
158
159 /* Clear descriptor array */
160 for (index = 0; index < desc_count; index++)
161 memset(&adata->dscr_info[index], 0x00, sizeof(struct dma_descriptor));
162
163 return ret;
164 }
165
166 /*
167 * psp_mbox_ready- function to poll ready bit of psp mbox
168 * @adata: acp device data
169 * @ack: bool variable to check ready bit status or psp ack
170 */
171
psp_mbox_ready(struct acp_dev_data * adata,bool ack)172 static int psp_mbox_ready(struct acp_dev_data *adata, bool ack)
173 {
174 struct snd_sof_dev *sdev = adata->dev;
175 int ret;
176 u32 data;
177
178 ret = read_poll_timeout(smn_read, data, data & MBOX_READY_MASK, MBOX_DELAY_US,
179 ACP_PSP_TIMEOUT_US, false, adata->smn_dev, MP0_C2PMSG_114_REG);
180 if (!ret)
181 return 0;
182
183 dev_err(sdev->dev, "PSP error status %x\n", data & MBOX_STATUS_MASK);
184
185 if (ack)
186 return -ETIMEDOUT;
187
188 return -EBUSY;
189 }
190
191 /*
192 * psp_send_cmd - function to send psp command over mbox
193 * @adata: acp device data
194 * @cmd: non zero integer value for command type
195 */
196
psp_send_cmd(struct acp_dev_data * adata,int cmd)197 static int psp_send_cmd(struct acp_dev_data *adata, int cmd)
198 {
199 struct snd_sof_dev *sdev = adata->dev;
200 int ret;
201 u32 data;
202
203 if (!cmd)
204 return -EINVAL;
205
206 /* Get a non-zero Doorbell value from PSP */
207 ret = read_poll_timeout(smn_read, data, data, MBOX_DELAY_US, ACP_PSP_TIMEOUT_US, false,
208 adata->smn_dev, MP0_C2PMSG_73_REG);
209
210 if (ret) {
211 dev_err(sdev->dev, "Failed to get Doorbell from MBOX %x\n", MP0_C2PMSG_73_REG);
212 return ret;
213 }
214
215 /* Check if PSP is ready for new command */
216 ret = psp_mbox_ready(adata, 0);
217 if (ret)
218 return ret;
219
220 smn_write(adata->smn_dev, MP0_C2PMSG_114_REG, cmd);
221
222 /* Ring the Doorbell for PSP */
223 smn_write(adata->smn_dev, MP0_C2PMSG_73_REG, data);
224
225 /* Check MBOX ready as PSP ack */
226 ret = psp_mbox_ready(adata, 1);
227
228 return ret;
229 }
230
configure_and_run_sha_dma(struct acp_dev_data * adata,void * image_addr,unsigned int start_addr,unsigned int dest_addr,unsigned int image_length)231 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr,
232 unsigned int start_addr, unsigned int dest_addr,
233 unsigned int image_length)
234 {
235 struct snd_sof_dev *sdev = adata->dev;
236 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
237 unsigned int tx_count, fw_qualifier, val;
238 int ret;
239
240 if (!image_addr) {
241 dev_err(sdev->dev, "SHA DMA image address is NULL\n");
242 return -EINVAL;
243 }
244
245 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD);
246 if (val & ACP_SHA_RUN) {
247 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RESET);
248 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD_STS,
249 val, val & ACP_SHA_RESET,
250 ACP_REG_POLL_INTERVAL,
251 ACP_REG_POLL_TIMEOUT_US);
252 if (ret < 0) {
253 dev_err(sdev->dev, "SHA DMA Failed to Reset\n");
254 return ret;
255 }
256 }
257
258 if (adata->signed_fw_image)
259 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_INCLUDE_HDR, ACP_SHA_HEADER);
260
261 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_STRT_ADDR, start_addr);
262 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_DESTINATION_ADDR, dest_addr);
263 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_MSG_LENGTH, image_length);
264 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RUN);
265
266 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_TRANSFER_BYTE_CNT,
267 tx_count, tx_count == image_length,
268 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US);
269 if (ret < 0) {
270 dev_err(sdev->dev, "SHA DMA Failed to Transfer Length %x\n", tx_count);
271 return ret;
272 }
273
274 /* psp_send_cmd only required for renoir platform (rev - 3) */
275 if (desc->rev == 3) {
276 ret = psp_send_cmd(adata, MBOX_ACP_SHA_DMA_COMMAND);
277 if (ret)
278 return ret;
279 }
280
281 /* psp_send_cmd only required for vangogh platform (rev - 5) */
282 if (desc->rev == 5) {
283 /* Modify IRAM and DRAM size */
284 ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | IRAM_DRAM_FENCE_2);
285 if (ret)
286 return ret;
287 ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | MBOX_ISREADY_FLAG);
288 if (ret)
289 return ret;
290 }
291
292 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DSP_FW_QUALIFIER,
293 fw_qualifier, fw_qualifier & DSP_FW_RUN_ENABLE,
294 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US);
295 if (ret < 0) {
296 dev_err(sdev->dev, "PSP validation failed\n");
297 return ret;
298 }
299
300 return 0;
301 }
302
acp_dma_status(struct acp_dev_data * adata,unsigned char ch)303 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch)
304 {
305 struct snd_sof_dev *sdev = adata->dev;
306 unsigned int val;
307 int ret = 0;
308
309 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32));
310 if (val & ACP_DMA_CH_RUN) {
311 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_DMA_CH_STS, val, !val,
312 ACP_REG_POLL_INTERVAL,
313 ACP_DMA_COMPLETE_TIMEOUT_US);
314 if (ret < 0)
315 dev_err(sdev->dev, "DMA_CHANNEL %d status timeout\n", ch);
316 }
317
318 return ret;
319 }
320
memcpy_from_scratch(struct snd_sof_dev * sdev,u32 offset,unsigned int * dst,size_t bytes)321 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes)
322 {
323 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0;
324 int i, j;
325
326 for (i = 0, j = 0; i < bytes; i = i + 4, j++)
327 dst[j] = snd_sof_dsp_read(sdev, ACP_DSP_BAR, reg_offset + i);
328 }
329
memcpy_to_scratch(struct snd_sof_dev * sdev,u32 offset,unsigned int * src,size_t bytes)330 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes)
331 {
332 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0;
333 int i, j;
334
335 for (i = 0, j = 0; i < bytes; i = i + 4, j++)
336 snd_sof_dsp_write(sdev, ACP_DSP_BAR, reg_offset + i, src[j]);
337 }
338
acp_memory_init(struct snd_sof_dev * sdev)339 static int acp_memory_init(struct snd_sof_dev *sdev)
340 {
341 struct acp_dev_data *adata = sdev->pdata->hw_pdata;
342 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
343
344 snd_sof_dsp_update_bits(sdev, ACP_DSP_BAR, desc->dsp_intr_base + DSP_SW_INTR_CNTL_OFFSET,
345 ACP_DSP_INTR_EN_MASK, ACP_DSP_INTR_EN_MASK);
346 init_dma_descriptor(adata);
347
348 return 0;
349 }
350
acp_irq_thread(int irq,void * context)351 static irqreturn_t acp_irq_thread(int irq, void *context)
352 {
353 struct snd_sof_dev *sdev = context;
354 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
355 unsigned int count = ACP_HW_SEM_RETRY_COUNT;
356
357 spin_lock_irq(&sdev->ipc_lock);
358 /* Wait until acquired HW Semaphore lock or timeout */
359 while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset) && --count)
360 ;
361 spin_unlock_irq(&sdev->ipc_lock);
362
363 if (!count) {
364 dev_err(sdev->dev, "%s: Failed to acquire HW lock\n", __func__);
365 return IRQ_NONE;
366 }
367
368 sof_ops(sdev)->irq_thread(irq, sdev);
369 /* Unlock or Release HW Semaphore */
370 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset, 0x0);
371
372 return IRQ_HANDLED;
373 };
374
acp_irq_handler(int irq,void * dev_id)375 static irqreturn_t acp_irq_handler(int irq, void *dev_id)
376 {
377 struct snd_sof_dev *sdev = dev_id;
378 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
379 unsigned int base = desc->dsp_intr_base;
380 unsigned int val;
381
382 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET);
383 if (val & ACP_DSP_TO_HOST_IRQ) {
384 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET,
385 ACP_DSP_TO_HOST_IRQ);
386 return IRQ_WAKE_THREAD;
387 }
388
389 return IRQ_NONE;
390 }
391
acp_power_on(struct snd_sof_dev * sdev)392 static int acp_power_on(struct snd_sof_dev *sdev)
393 {
394 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
395 unsigned int base = desc->pgfsm_base;
396 unsigned int val;
397 int ret;
398
399 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET);
400
401 if (val == ACP_POWERED_ON)
402 return 0;
403
404 if (val & ACP_PGFSM_STATUS_MASK)
405 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + PGFSM_CONTROL_OFFSET,
406 ACP_PGFSM_CNTL_POWER_ON_MASK);
407
408 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET, val,
409 !val, ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);
410 if (ret < 0)
411 dev_err(sdev->dev, "timeout in ACP_PGFSM_STATUS read\n");
412
413 return ret;
414 }
415
acp_reset(struct snd_sof_dev * sdev)416 static int acp_reset(struct snd_sof_dev *sdev)
417 {
418 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
419 unsigned int val;
420 int ret;
421
422 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_ASSERT_RESET);
423
424 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val,
425 val & ACP_SOFT_RESET_DONE_MASK,
426 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);
427 if (ret < 0) {
428 dev_err(sdev->dev, "timeout asserting reset\n");
429 return ret;
430 }
431
432 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_RELEASE_RESET);
433
434 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val,
435 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);
436 if (ret < 0)
437 dev_err(sdev->dev, "timeout in releasing reset\n");
438
439 if (desc->acp_clkmux_sel)
440 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACLK);
441
442 if (desc->ext_intr_enb)
443 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_enb, 0x01);
444
445 return ret;
446 }
447
acp_init(struct snd_sof_dev * sdev)448 static int acp_init(struct snd_sof_dev *sdev)
449 {
450 int ret;
451
452 /* power on */
453 ret = acp_power_on(sdev);
454 if (ret) {
455 dev_err(sdev->dev, "ACP power on failed\n");
456 return ret;
457 }
458
459 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x01);
460 /* Reset */
461 return acp_reset(sdev);
462 }
463
amd_sof_acp_suspend(struct snd_sof_dev * sdev,u32 target_state)464 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state)
465 {
466 int ret;
467
468 ret = acp_reset(sdev);
469 if (ret) {
470 dev_err(sdev->dev, "ACP Reset failed\n");
471 return ret;
472 }
473
474 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x00);
475
476 return 0;
477 }
478 EXPORT_SYMBOL_NS(amd_sof_acp_suspend, SND_SOC_SOF_AMD_COMMON);
479
amd_sof_acp_resume(struct snd_sof_dev * sdev)480 int amd_sof_acp_resume(struct snd_sof_dev *sdev)
481 {
482 int ret;
483
484 ret = acp_init(sdev);
485 if (ret) {
486 dev_err(sdev->dev, "ACP Init failed\n");
487 return ret;
488 }
489 return acp_memory_init(sdev);
490 }
491 EXPORT_SYMBOL_NS(amd_sof_acp_resume, SND_SOC_SOF_AMD_COMMON);
492
amd_sof_acp_probe(struct snd_sof_dev * sdev)493 int amd_sof_acp_probe(struct snd_sof_dev *sdev)
494 {
495 struct pci_dev *pci = to_pci_dev(sdev->dev);
496 struct snd_sof_pdata *plat_data = sdev->pdata;
497 struct acp_dev_data *adata;
498 const struct sof_amd_acp_desc *chip;
499 const struct dmi_system_id *dmi_id;
500 unsigned int addr;
501 int ret;
502
503 chip = get_chip_info(sdev->pdata);
504 if (!chip) {
505 dev_err(sdev->dev, "no such device supported, chip id:%x\n", pci->device);
506 return -EIO;
507 }
508 adata = devm_kzalloc(sdev->dev, sizeof(struct acp_dev_data),
509 GFP_KERNEL);
510 if (!adata)
511 return -ENOMEM;
512
513 adata->dev = sdev;
514 adata->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec",
515 PLATFORM_DEVID_NONE, NULL, 0);
516 if (IS_ERR(adata->dmic_dev)) {
517 dev_err(sdev->dev, "failed to register platform for dmic codec\n");
518 return PTR_ERR(adata->dmic_dev);
519 }
520 addr = pci_resource_start(pci, ACP_DSP_BAR);
521 sdev->bar[ACP_DSP_BAR] = devm_ioremap(sdev->dev, addr, pci_resource_len(pci, ACP_DSP_BAR));
522 if (!sdev->bar[ACP_DSP_BAR]) {
523 dev_err(sdev->dev, "ioremap error\n");
524 ret = -ENXIO;
525 goto unregister_dev;
526 }
527
528 pci_set_master(pci);
529
530 sdev->pdata->hw_pdata = adata;
531 adata->smn_dev = pci_get_device(PCI_VENDOR_ID_AMD, chip->host_bridge_id, NULL);
532 if (!adata->smn_dev) {
533 dev_err(sdev->dev, "Failed to get host bridge device\n");
534 ret = -ENODEV;
535 goto unregister_dev;
536 }
537
538 sdev->ipc_irq = pci->irq;
539 ret = request_threaded_irq(sdev->ipc_irq, acp_irq_handler, acp_irq_thread,
540 IRQF_SHARED, "AudioDSP", sdev);
541 if (ret < 0) {
542 dev_err(sdev->dev, "failed to register IRQ %d\n",
543 sdev->ipc_irq);
544 goto free_smn_dev;
545 }
546
547 ret = acp_init(sdev);
548 if (ret < 0)
549 goto free_ipc_irq;
550
551 sdev->dsp_box.offset = 0;
552 sdev->dsp_box.size = BOX_SIZE_512;
553
554 sdev->host_box.offset = sdev->dsp_box.offset + sdev->dsp_box.size;
555 sdev->host_box.size = BOX_SIZE_512;
556
557 sdev->debug_box.offset = sdev->host_box.offset + sdev->host_box.size;
558 sdev->debug_box.size = BOX_SIZE_1024;
559
560 adata->signed_fw_image = false;
561 dmi_id = dmi_first_match(acp_sof_quirk_table);
562 if (dmi_id && dmi_id->driver_data) {
563 adata->fw_code_bin = kasprintf(GFP_KERNEL, "%s/sof-%s-code.bin",
564 plat_data->fw_filename_prefix,
565 chip->name);
566 adata->fw_data_bin = kasprintf(GFP_KERNEL, "%s/sof-%s-data.bin",
567 plat_data->fw_filename_prefix,
568 chip->name);
569 adata->signed_fw_image = dmi_id->driver_data;
570
571 dev_dbg(sdev->dev, "fw_code_bin:%s, fw_data_bin:%s\n", adata->fw_code_bin,
572 adata->fw_data_bin);
573 }
574 adata->enable_fw_debug = enable_fw_debug;
575 acp_memory_init(sdev);
576
577 acp_dsp_stream_init(sdev);
578
579 return 0;
580
581 free_ipc_irq:
582 free_irq(sdev->ipc_irq, sdev);
583 free_smn_dev:
584 pci_dev_put(adata->smn_dev);
585 unregister_dev:
586 platform_device_unregister(adata->dmic_dev);
587 return ret;
588 }
589 EXPORT_SYMBOL_NS(amd_sof_acp_probe, SND_SOC_SOF_AMD_COMMON);
590
amd_sof_acp_remove(struct snd_sof_dev * sdev)591 void amd_sof_acp_remove(struct snd_sof_dev *sdev)
592 {
593 struct acp_dev_data *adata = sdev->pdata->hw_pdata;
594
595 if (adata->smn_dev)
596 pci_dev_put(adata->smn_dev);
597
598 if (sdev->ipc_irq)
599 free_irq(sdev->ipc_irq, sdev);
600
601 if (adata->dmic_dev)
602 platform_device_unregister(adata->dmic_dev);
603
604 acp_reset(sdev);
605 }
606 EXPORT_SYMBOL_NS(amd_sof_acp_remove, SND_SOC_SOF_AMD_COMMON);
607
608 MODULE_DESCRIPTION("AMD ACP sof driver");
609 MODULE_LICENSE("Dual BSD/GPL");
610