1 // SPDX-License-Identifier: GPL-2.0-only
2 // ALSA SoC Audio Layer - Rockchip I2S/TDM Controller driver
3
4 // Copyright (c) 2018 Rockchip Electronics Co. Ltd.
5 // Author: Sugar Zhang <sugar.zhang@rock-chips.com>
6 // Author: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
7
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regmap.h>
16 #include <linux/reset.h>
17 #include <linux/spinlock.h>
18 #include <sound/dmaengine_pcm.h>
19 #include <sound/pcm_params.h>
20
21 #include "rockchip_i2s_tdm.h"
22
23 #define DRV_NAME "rockchip-i2s-tdm"
24
25 #define DEFAULT_MCLK_FS 256
26 #define CH_GRP_MAX 4 /* The max channel 8 / 2 */
27 #define MULTIPLEX_CH_MAX 10
28 #define CLK_PPM_MIN -1000
29 #define CLK_PPM_MAX 1000
30
31 #define TRCM_TXRX 0
32 #define TRCM_TX 1
33 #define TRCM_RX 2
34
35 struct txrx_config {
36 u32 addr;
37 u32 reg;
38 u32 txonly;
39 u32 rxonly;
40 };
41
42 struct rk_i2s_soc_data {
43 u32 softrst_offset;
44 u32 grf_reg_offset;
45 u32 grf_shift;
46 int config_count;
47 const struct txrx_config *configs;
48 int (*init)(struct device *dev, u32 addr);
49 };
50
51 struct rk_i2s_tdm_dev {
52 struct device *dev;
53 struct clk *hclk;
54 struct clk *mclk_tx;
55 struct clk *mclk_rx;
56 /* The mclk_tx_src is parent of mclk_tx */
57 struct clk *mclk_tx_src;
58 /* The mclk_rx_src is parent of mclk_rx */
59 struct clk *mclk_rx_src;
60 /*
61 * The mclk_root0 and mclk_root1 are root parent and supplies for
62 * the different FS.
63 *
64 * e.g:
65 * mclk_root0 is VPLL0, used for FS=48000Hz
66 * mclk_root1 is VPLL1, used for FS=44100Hz
67 */
68 struct clk *mclk_root0;
69 struct clk *mclk_root1;
70 struct regmap *regmap;
71 struct regmap *grf;
72 struct snd_dmaengine_dai_dma_data capture_dma_data;
73 struct snd_dmaengine_dai_dma_data playback_dma_data;
74 struct reset_control *tx_reset;
75 struct reset_control *rx_reset;
76 const struct rk_i2s_soc_data *soc_data;
77 bool is_master_mode;
78 bool io_multiplex;
79 bool mclk_calibrate;
80 bool tdm_mode;
81 unsigned int mclk_rx_freq;
82 unsigned int mclk_tx_freq;
83 unsigned int mclk_root0_freq;
84 unsigned int mclk_root1_freq;
85 unsigned int mclk_root0_initial_freq;
86 unsigned int mclk_root1_initial_freq;
87 unsigned int frame_width;
88 unsigned int clk_trcm;
89 unsigned int i2s_sdis[CH_GRP_MAX];
90 unsigned int i2s_sdos[CH_GRP_MAX];
91 int clk_ppm;
92 int refcount;
93 spinlock_t lock; /* xfer lock */
94 bool has_playback;
95 bool has_capture;
96 struct snd_soc_dai_driver *dai;
97 };
98
to_ch_num(unsigned int val)99 static int to_ch_num(unsigned int val)
100 {
101 switch (val) {
102 case I2S_CHN_4:
103 return 4;
104 case I2S_CHN_6:
105 return 6;
106 case I2S_CHN_8:
107 return 8;
108 default:
109 return 2;
110 }
111 }
112
i2s_tdm_disable_unprepare_mclk(struct rk_i2s_tdm_dev * i2s_tdm)113 static void i2s_tdm_disable_unprepare_mclk(struct rk_i2s_tdm_dev *i2s_tdm)
114 {
115 clk_disable_unprepare(i2s_tdm->mclk_tx);
116 clk_disable_unprepare(i2s_tdm->mclk_rx);
117 if (i2s_tdm->mclk_calibrate) {
118 clk_disable_unprepare(i2s_tdm->mclk_tx_src);
119 clk_disable_unprepare(i2s_tdm->mclk_rx_src);
120 clk_disable_unprepare(i2s_tdm->mclk_root0);
121 clk_disable_unprepare(i2s_tdm->mclk_root1);
122 }
123 }
124
125 /**
126 * i2s_tdm_prepare_enable_mclk - prepare to enable all mclks, disable them on
127 * failure.
128 * @i2s_tdm: rk_i2s_tdm_dev struct
129 *
130 * This function attempts to enable all mclk clocks, but cleans up after
131 * itself on failure. Guarantees to balance its calls.
132 *
133 * Returns success (0) or negative errno.
134 */
i2s_tdm_prepare_enable_mclk(struct rk_i2s_tdm_dev * i2s_tdm)135 static int i2s_tdm_prepare_enable_mclk(struct rk_i2s_tdm_dev *i2s_tdm)
136 {
137 int ret = 0;
138
139 ret = clk_prepare_enable(i2s_tdm->mclk_tx);
140 if (ret)
141 goto err_mclk_tx;
142 ret = clk_prepare_enable(i2s_tdm->mclk_rx);
143 if (ret)
144 goto err_mclk_rx;
145 if (i2s_tdm->mclk_calibrate) {
146 ret = clk_prepare_enable(i2s_tdm->mclk_tx_src);
147 if (ret)
148 goto err_mclk_rx;
149 ret = clk_prepare_enable(i2s_tdm->mclk_rx_src);
150 if (ret)
151 goto err_mclk_rx_src;
152 ret = clk_prepare_enable(i2s_tdm->mclk_root0);
153 if (ret)
154 goto err_mclk_root0;
155 ret = clk_prepare_enable(i2s_tdm->mclk_root1);
156 if (ret)
157 goto err_mclk_root1;
158 }
159
160 return 0;
161
162 err_mclk_root1:
163 clk_disable_unprepare(i2s_tdm->mclk_root0);
164 err_mclk_root0:
165 clk_disable_unprepare(i2s_tdm->mclk_rx_src);
166 err_mclk_rx_src:
167 clk_disable_unprepare(i2s_tdm->mclk_tx_src);
168 err_mclk_rx:
169 clk_disable_unprepare(i2s_tdm->mclk_tx);
170 err_mclk_tx:
171 return ret;
172 }
173
i2s_tdm_runtime_suspend(struct device * dev)174 static int __maybe_unused i2s_tdm_runtime_suspend(struct device *dev)
175 {
176 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
177
178 regcache_cache_only(i2s_tdm->regmap, true);
179 i2s_tdm_disable_unprepare_mclk(i2s_tdm);
180
181 clk_disable_unprepare(i2s_tdm->hclk);
182
183 return 0;
184 }
185
i2s_tdm_runtime_resume(struct device * dev)186 static int __maybe_unused i2s_tdm_runtime_resume(struct device *dev)
187 {
188 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
189 int ret;
190
191 ret = clk_prepare_enable(i2s_tdm->hclk);
192 if (ret)
193 goto err_hclk;
194
195 ret = i2s_tdm_prepare_enable_mclk(i2s_tdm);
196 if (ret)
197 goto err_mclk;
198
199 regcache_cache_only(i2s_tdm->regmap, false);
200 regcache_mark_dirty(i2s_tdm->regmap);
201
202 ret = regcache_sync(i2s_tdm->regmap);
203 if (ret)
204 goto err_regcache;
205
206 return 0;
207
208 err_regcache:
209 i2s_tdm_disable_unprepare_mclk(i2s_tdm);
210 err_mclk:
211 clk_disable_unprepare(i2s_tdm->hclk);
212 err_hclk:
213 return ret;
214 }
215
to_info(struct snd_soc_dai * dai)216 static inline struct rk_i2s_tdm_dev *to_info(struct snd_soc_dai *dai)
217 {
218 return snd_soc_dai_get_drvdata(dai);
219 }
220
221 /*
222 * Makes sure that both tx and rx are reset at the same time to sync lrck
223 * when clk_trcm > 0.
224 */
rockchip_snd_xfer_sync_reset(struct rk_i2s_tdm_dev * i2s_tdm)225 static void rockchip_snd_xfer_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm)
226 {
227 /* This is technically race-y.
228 *
229 * In an ideal world, we could atomically assert both resets at the
230 * same time, through an atomic bulk reset API. This API however does
231 * not exist, so what the downstream vendor code used to do was
232 * implement half a reset controller here and require the CRU to be
233 * passed to the driver as a device tree node. Violating abstractions
234 * like that is bad, especially when it influences something like the
235 * bindings which are supposed to describe the hardware, not whatever
236 * workarounds the driver needs, so it was dropped.
237 *
238 * In practice, asserting the resets one by one appears to work just
239 * fine for playback. During duplex (playback + capture) operation,
240 * this might become an issue, but that should be solved by the
241 * implementation of the aforementioned API, not by shoving a reset
242 * controller into an audio driver.
243 */
244
245 reset_control_assert(i2s_tdm->tx_reset);
246 reset_control_assert(i2s_tdm->rx_reset);
247 udelay(10);
248 reset_control_deassert(i2s_tdm->tx_reset);
249 reset_control_deassert(i2s_tdm->rx_reset);
250 udelay(10);
251 }
252
rockchip_snd_reset(struct reset_control * rc)253 static void rockchip_snd_reset(struct reset_control *rc)
254 {
255 reset_control_assert(rc);
256 udelay(10);
257 reset_control_deassert(rc);
258 udelay(10);
259 }
260
rockchip_snd_xfer_clear(struct rk_i2s_tdm_dev * i2s_tdm,unsigned int clr)261 static void rockchip_snd_xfer_clear(struct rk_i2s_tdm_dev *i2s_tdm,
262 unsigned int clr)
263 {
264 unsigned int xfer_mask = 0;
265 unsigned int xfer_val = 0;
266 unsigned int val;
267 int retry = 10;
268 bool tx = clr & I2S_CLR_TXC;
269 bool rx = clr & I2S_CLR_RXC;
270
271 if (!(rx || tx))
272 return;
273
274 if (tx) {
275 xfer_mask = I2S_XFER_TXS_START;
276 xfer_val = I2S_XFER_TXS_STOP;
277 }
278 if (rx) {
279 xfer_mask |= I2S_XFER_RXS_START;
280 xfer_val |= I2S_XFER_RXS_STOP;
281 }
282
283 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, xfer_mask, xfer_val);
284 udelay(150);
285 regmap_update_bits(i2s_tdm->regmap, I2S_CLR, clr, clr);
286
287 regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
288 /* Wait on the clear operation to finish */
289 while (val) {
290 udelay(15);
291 regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
292 retry--;
293 if (!retry) {
294 dev_warn(i2s_tdm->dev, "clear failed, reset %s%s\n",
295 tx ? "tx" : "", rx ? "rx" : "");
296 if (rx && tx)
297 rockchip_snd_xfer_sync_reset(i2s_tdm);
298 else if (tx)
299 rockchip_snd_reset(i2s_tdm->tx_reset);
300 else if (rx)
301 rockchip_snd_reset(i2s_tdm->rx_reset);
302 break;
303 }
304 }
305 }
306
rockchip_enable_tde(struct regmap * regmap)307 static inline void rockchip_enable_tde(struct regmap *regmap)
308 {
309 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE,
310 I2S_DMACR_TDE_ENABLE);
311 }
312
rockchip_disable_tde(struct regmap * regmap)313 static inline void rockchip_disable_tde(struct regmap *regmap)
314 {
315 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE,
316 I2S_DMACR_TDE_DISABLE);
317 }
318
rockchip_enable_rde(struct regmap * regmap)319 static inline void rockchip_enable_rde(struct regmap *regmap)
320 {
321 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE,
322 I2S_DMACR_RDE_ENABLE);
323 }
324
rockchip_disable_rde(struct regmap * regmap)325 static inline void rockchip_disable_rde(struct regmap *regmap)
326 {
327 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE,
328 I2S_DMACR_RDE_DISABLE);
329 }
330
331 /* only used when clk_trcm > 0 */
rockchip_snd_txrxctrl(struct snd_pcm_substream * substream,struct snd_soc_dai * dai,int on)332 static void rockchip_snd_txrxctrl(struct snd_pcm_substream *substream,
333 struct snd_soc_dai *dai, int on)
334 {
335 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
336 unsigned long flags;
337
338 spin_lock_irqsave(&i2s_tdm->lock, flags);
339 if (on) {
340 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
341 rockchip_enable_tde(i2s_tdm->regmap);
342 else
343 rockchip_enable_rde(i2s_tdm->regmap);
344
345 if (++i2s_tdm->refcount == 1) {
346 rockchip_snd_xfer_sync_reset(i2s_tdm);
347 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
348 I2S_XFER_TXS_START |
349 I2S_XFER_RXS_START,
350 I2S_XFER_TXS_START |
351 I2S_XFER_RXS_START);
352 }
353 } else {
354 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
355 rockchip_disable_tde(i2s_tdm->regmap);
356 else
357 rockchip_disable_rde(i2s_tdm->regmap);
358
359 if (--i2s_tdm->refcount == 0) {
360 rockchip_snd_xfer_clear(i2s_tdm,
361 I2S_CLR_TXC | I2S_CLR_RXC);
362 }
363 }
364 spin_unlock_irqrestore(&i2s_tdm->lock, flags);
365 }
366
rockchip_snd_txctrl(struct rk_i2s_tdm_dev * i2s_tdm,int on)367 static void rockchip_snd_txctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
368 {
369 if (on) {
370 rockchip_enable_tde(i2s_tdm->regmap);
371
372 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
373 I2S_XFER_TXS_START,
374 I2S_XFER_TXS_START);
375 } else {
376 rockchip_disable_tde(i2s_tdm->regmap);
377
378 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC);
379 }
380 }
381
rockchip_snd_rxctrl(struct rk_i2s_tdm_dev * i2s_tdm,int on)382 static void rockchip_snd_rxctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
383 {
384 if (on) {
385 rockchip_enable_rde(i2s_tdm->regmap);
386
387 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
388 I2S_XFER_RXS_START,
389 I2S_XFER_RXS_START);
390 } else {
391 rockchip_disable_rde(i2s_tdm->regmap);
392
393 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_RXC);
394 }
395 }
396
rockchip_i2s_tdm_set_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)397 static int rockchip_i2s_tdm_set_fmt(struct snd_soc_dai *cpu_dai,
398 unsigned int fmt)
399 {
400 struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai);
401 unsigned int mask, val, tdm_val, txcr_val, rxcr_val;
402 int ret;
403 bool is_tdm = i2s_tdm->tdm_mode;
404
405 ret = pm_runtime_resume_and_get(cpu_dai->dev);
406 if (ret < 0 && ret != -EACCES)
407 return ret;
408
409 mask = I2S_CKR_MSS_MASK;
410 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
411 case SND_SOC_DAIFMT_BP_FP:
412 val = I2S_CKR_MSS_MASTER;
413 i2s_tdm->is_master_mode = true;
414 break;
415 case SND_SOC_DAIFMT_BC_FC:
416 val = I2S_CKR_MSS_SLAVE;
417 i2s_tdm->is_master_mode = false;
418 break;
419 default:
420 ret = -EINVAL;
421 goto err_pm_put;
422 }
423
424 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val);
425
426 mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK;
427 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
428 case SND_SOC_DAIFMT_NB_NF:
429 val = I2S_CKR_CKP_NORMAL |
430 I2S_CKR_TLP_NORMAL |
431 I2S_CKR_RLP_NORMAL;
432 break;
433 case SND_SOC_DAIFMT_NB_IF:
434 val = I2S_CKR_CKP_NORMAL |
435 I2S_CKR_TLP_INVERTED |
436 I2S_CKR_RLP_INVERTED;
437 break;
438 case SND_SOC_DAIFMT_IB_NF:
439 val = I2S_CKR_CKP_INVERTED |
440 I2S_CKR_TLP_NORMAL |
441 I2S_CKR_RLP_NORMAL;
442 break;
443 case SND_SOC_DAIFMT_IB_IF:
444 val = I2S_CKR_CKP_INVERTED |
445 I2S_CKR_TLP_INVERTED |
446 I2S_CKR_RLP_INVERTED;
447 break;
448 default:
449 ret = -EINVAL;
450 goto err_pm_put;
451 }
452
453 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val);
454
455 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
456 case SND_SOC_DAIFMT_RIGHT_J:
457 txcr_val = I2S_TXCR_IBM_RSJM;
458 rxcr_val = I2S_RXCR_IBM_RSJM;
459 break;
460 case SND_SOC_DAIFMT_LEFT_J:
461 txcr_val = I2S_TXCR_IBM_LSJM;
462 rxcr_val = I2S_RXCR_IBM_LSJM;
463 break;
464 case SND_SOC_DAIFMT_I2S:
465 txcr_val = I2S_TXCR_IBM_NORMAL;
466 rxcr_val = I2S_RXCR_IBM_NORMAL;
467 break;
468 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 mode */
469 txcr_val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
470 rxcr_val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
471 break;
472 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
473 txcr_val = I2S_TXCR_TFS_PCM;
474 rxcr_val = I2S_RXCR_TFS_PCM;
475 break;
476 default:
477 ret = -EINVAL;
478 goto err_pm_put;
479 }
480
481 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
482 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, txcr_val);
483
484 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
485 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, rxcr_val);
486
487 if (is_tdm) {
488 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
489 case SND_SOC_DAIFMT_RIGHT_J:
490 val = I2S_TXCR_TFS_TDM_I2S;
491 tdm_val = TDM_SHIFT_CTRL(2);
492 break;
493 case SND_SOC_DAIFMT_LEFT_J:
494 val = I2S_TXCR_TFS_TDM_I2S;
495 tdm_val = TDM_SHIFT_CTRL(1);
496 break;
497 case SND_SOC_DAIFMT_I2S:
498 val = I2S_TXCR_TFS_TDM_I2S;
499 tdm_val = TDM_SHIFT_CTRL(0);
500 break;
501 case SND_SOC_DAIFMT_DSP_A:
502 val = I2S_TXCR_TFS_TDM_PCM;
503 tdm_val = TDM_SHIFT_CTRL(0);
504 break;
505 case SND_SOC_DAIFMT_DSP_B:
506 val = I2S_TXCR_TFS_TDM_PCM;
507 tdm_val = TDM_SHIFT_CTRL(2);
508 break;
509 default:
510 ret = -EINVAL;
511 goto err_pm_put;
512 }
513
514 tdm_val |= TDM_FSYNC_WIDTH_SEL1(1);
515 tdm_val |= TDM_FSYNC_WIDTH_HALF_FRAME;
516
517 mask = I2S_TXCR_TFS_MASK;
518 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, val);
519 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, val);
520
521 mask = TDM_FSYNC_WIDTH_SEL1_MSK | TDM_FSYNC_WIDTH_SEL0_MSK |
522 TDM_SHIFT_CTRL_MSK;
523 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR,
524 mask, tdm_val);
525 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR,
526 mask, tdm_val);
527 }
528
529 err_pm_put:
530 pm_runtime_put(cpu_dai->dev);
531
532 return ret;
533 }
534
rockchip_i2s_tdm_xfer_pause(struct snd_pcm_substream * substream,struct rk_i2s_tdm_dev * i2s_tdm)535 static void rockchip_i2s_tdm_xfer_pause(struct snd_pcm_substream *substream,
536 struct rk_i2s_tdm_dev *i2s_tdm)
537 {
538 int stream;
539
540 stream = SNDRV_PCM_STREAM_LAST - substream->stream;
541 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
542 rockchip_disable_tde(i2s_tdm->regmap);
543 else
544 rockchip_disable_rde(i2s_tdm->regmap);
545
546 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC | I2S_CLR_RXC);
547 }
548
rockchip_i2s_tdm_xfer_resume(struct snd_pcm_substream * substream,struct rk_i2s_tdm_dev * i2s_tdm)549 static void rockchip_i2s_tdm_xfer_resume(struct snd_pcm_substream *substream,
550 struct rk_i2s_tdm_dev *i2s_tdm)
551 {
552 int stream;
553
554 stream = SNDRV_PCM_STREAM_LAST - substream->stream;
555 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
556 rockchip_enable_tde(i2s_tdm->regmap);
557 else
558 rockchip_enable_rde(i2s_tdm->regmap);
559
560 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
561 I2S_XFER_TXS_START |
562 I2S_XFER_RXS_START,
563 I2S_XFER_TXS_START |
564 I2S_XFER_RXS_START);
565 }
566
rockchip_i2s_tdm_clk_set_rate(struct rk_i2s_tdm_dev * i2s_tdm,struct clk * clk,unsigned long rate,int ppm)567 static int rockchip_i2s_tdm_clk_set_rate(struct rk_i2s_tdm_dev *i2s_tdm,
568 struct clk *clk, unsigned long rate,
569 int ppm)
570 {
571 unsigned long rate_target;
572 int delta, ret;
573
574 if (ppm == i2s_tdm->clk_ppm)
575 return 0;
576
577 if (ppm < 0)
578 delta = -1;
579 else
580 delta = 1;
581
582 delta *= (int)div64_u64((u64)rate * (u64)abs(ppm) + 500000,
583 1000000);
584
585 rate_target = rate + delta;
586
587 if (!rate_target)
588 return -EINVAL;
589
590 ret = clk_set_rate(clk, rate_target);
591 if (ret)
592 return ret;
593
594 i2s_tdm->clk_ppm = ppm;
595
596 return 0;
597 }
598
rockchip_i2s_tdm_calibrate_mclk(struct rk_i2s_tdm_dev * i2s_tdm,struct snd_pcm_substream * substream,unsigned int lrck_freq)599 static int rockchip_i2s_tdm_calibrate_mclk(struct rk_i2s_tdm_dev *i2s_tdm,
600 struct snd_pcm_substream *substream,
601 unsigned int lrck_freq)
602 {
603 struct clk *mclk_root;
604 struct clk *mclk_parent;
605 unsigned int mclk_root_freq;
606 unsigned int mclk_root_initial_freq;
607 unsigned int mclk_parent_freq;
608 unsigned int div, delta;
609 u64 ppm;
610 int ret;
611
612 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
613 mclk_parent = i2s_tdm->mclk_tx_src;
614 else
615 mclk_parent = i2s_tdm->mclk_rx_src;
616
617 switch (lrck_freq) {
618 case 8000:
619 case 16000:
620 case 24000:
621 case 32000:
622 case 48000:
623 case 64000:
624 case 96000:
625 case 192000:
626 mclk_root = i2s_tdm->mclk_root0;
627 mclk_root_freq = i2s_tdm->mclk_root0_freq;
628 mclk_root_initial_freq = i2s_tdm->mclk_root0_initial_freq;
629 mclk_parent_freq = DEFAULT_MCLK_FS * 192000;
630 break;
631 case 11025:
632 case 22050:
633 case 44100:
634 case 88200:
635 case 176400:
636 mclk_root = i2s_tdm->mclk_root1;
637 mclk_root_freq = i2s_tdm->mclk_root1_freq;
638 mclk_root_initial_freq = i2s_tdm->mclk_root1_initial_freq;
639 mclk_parent_freq = DEFAULT_MCLK_FS * 176400;
640 break;
641 default:
642 dev_err(i2s_tdm->dev, "Invalid LRCK frequency: %u Hz\n",
643 lrck_freq);
644 return -EINVAL;
645 }
646
647 ret = clk_set_parent(mclk_parent, mclk_root);
648 if (ret)
649 return ret;
650
651 ret = rockchip_i2s_tdm_clk_set_rate(i2s_tdm, mclk_root,
652 mclk_root_freq, 0);
653 if (ret)
654 return ret;
655
656 delta = abs(mclk_root_freq % mclk_parent_freq - mclk_parent_freq);
657 ppm = div64_u64((uint64_t)delta * 1000000, (uint64_t)mclk_root_freq);
658
659 if (ppm) {
660 div = DIV_ROUND_CLOSEST(mclk_root_initial_freq, mclk_parent_freq);
661 if (!div)
662 return -EINVAL;
663
664 mclk_root_freq = mclk_parent_freq * round_up(div, 2);
665
666 ret = clk_set_rate(mclk_root, mclk_root_freq);
667 if (ret)
668 return ret;
669
670 i2s_tdm->mclk_root0_freq = clk_get_rate(i2s_tdm->mclk_root0);
671 i2s_tdm->mclk_root1_freq = clk_get_rate(i2s_tdm->mclk_root1);
672 }
673
674 return clk_set_rate(mclk_parent, mclk_parent_freq);
675 }
676
rockchip_i2s_tdm_set_mclk(struct rk_i2s_tdm_dev * i2s_tdm,struct snd_pcm_substream * substream,struct clk ** mclk)677 static int rockchip_i2s_tdm_set_mclk(struct rk_i2s_tdm_dev *i2s_tdm,
678 struct snd_pcm_substream *substream,
679 struct clk **mclk)
680 {
681 unsigned int mclk_freq;
682 int ret;
683
684 if (i2s_tdm->clk_trcm) {
685 if (i2s_tdm->mclk_tx_freq != i2s_tdm->mclk_rx_freq) {
686 dev_err(i2s_tdm->dev,
687 "clk_trcm, tx: %d and rx: %d should be the same\n",
688 i2s_tdm->mclk_tx_freq,
689 i2s_tdm->mclk_rx_freq);
690 return -EINVAL;
691 }
692
693 ret = clk_set_rate(i2s_tdm->mclk_tx, i2s_tdm->mclk_tx_freq);
694 if (ret)
695 return ret;
696
697 ret = clk_set_rate(i2s_tdm->mclk_rx, i2s_tdm->mclk_rx_freq);
698 if (ret)
699 return ret;
700
701 /* mclk_rx is also ok. */
702 *mclk = i2s_tdm->mclk_tx;
703 } else {
704 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
705 *mclk = i2s_tdm->mclk_tx;
706 mclk_freq = i2s_tdm->mclk_tx_freq;
707 } else {
708 *mclk = i2s_tdm->mclk_rx;
709 mclk_freq = i2s_tdm->mclk_rx_freq;
710 }
711
712 ret = clk_set_rate(*mclk, mclk_freq);
713 if (ret)
714 return ret;
715 }
716
717 return 0;
718 }
719
rockchip_i2s_ch_to_io(unsigned int ch,bool substream_capture)720 static int rockchip_i2s_ch_to_io(unsigned int ch, bool substream_capture)
721 {
722 if (substream_capture) {
723 switch (ch) {
724 case I2S_CHN_4:
725 return I2S_IO_6CH_OUT_4CH_IN;
726 case I2S_CHN_6:
727 return I2S_IO_4CH_OUT_6CH_IN;
728 case I2S_CHN_8:
729 return I2S_IO_2CH_OUT_8CH_IN;
730 default:
731 return I2S_IO_8CH_OUT_2CH_IN;
732 }
733 } else {
734 switch (ch) {
735 case I2S_CHN_4:
736 return I2S_IO_4CH_OUT_6CH_IN;
737 case I2S_CHN_6:
738 return I2S_IO_6CH_OUT_4CH_IN;
739 case I2S_CHN_8:
740 return I2S_IO_8CH_OUT_2CH_IN;
741 default:
742 return I2S_IO_2CH_OUT_8CH_IN;
743 }
744 }
745 }
746
rockchip_i2s_io_multiplex(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)747 static int rockchip_i2s_io_multiplex(struct snd_pcm_substream *substream,
748 struct snd_soc_dai *dai)
749 {
750 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
751 int usable_chs = MULTIPLEX_CH_MAX;
752 unsigned int val = 0;
753
754 if (!i2s_tdm->io_multiplex)
755 return 0;
756
757 if (IS_ERR_OR_NULL(i2s_tdm->grf)) {
758 dev_err(i2s_tdm->dev,
759 "io multiplex not supported for this device\n");
760 return -EINVAL;
761 }
762
763 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
764 struct snd_pcm_str *playback_str =
765 &substream->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK];
766
767 if (playback_str->substream_opened) {
768 regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
769 val &= I2S_TXCR_CSR_MASK;
770 usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val);
771 }
772
773 regmap_read(i2s_tdm->regmap, I2S_RXCR, &val);
774 val &= I2S_RXCR_CSR_MASK;
775
776 if (to_ch_num(val) > usable_chs) {
777 dev_err(i2s_tdm->dev,
778 "Capture channels (%d) > usable channels (%d)\n",
779 to_ch_num(val), usable_chs);
780 return -EINVAL;
781 }
782
783 rockchip_i2s_ch_to_io(val, true);
784 } else {
785 struct snd_pcm_str *capture_str =
786 &substream->pcm->streams[SNDRV_PCM_STREAM_CAPTURE];
787
788 if (capture_str->substream_opened) {
789 regmap_read(i2s_tdm->regmap, I2S_RXCR, &val);
790 val &= I2S_RXCR_CSR_MASK;
791 usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val);
792 }
793
794 regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
795 val &= I2S_TXCR_CSR_MASK;
796
797 if (to_ch_num(val) > usable_chs) {
798 dev_err(i2s_tdm->dev,
799 "Playback channels (%d) > usable channels (%d)\n",
800 to_ch_num(val), usable_chs);
801 return -EINVAL;
802 }
803 }
804
805 val <<= i2s_tdm->soc_data->grf_shift;
806 val |= (I2S_IO_DIRECTION_MASK << i2s_tdm->soc_data->grf_shift) << 16;
807 regmap_write(i2s_tdm->grf, i2s_tdm->soc_data->grf_reg_offset, val);
808
809 return 0;
810 }
811
rockchip_i2s_trcm_mode(struct snd_pcm_substream * substream,struct snd_soc_dai * dai,unsigned int div_bclk,unsigned int div_lrck,unsigned int fmt)812 static int rockchip_i2s_trcm_mode(struct snd_pcm_substream *substream,
813 struct snd_soc_dai *dai,
814 unsigned int div_bclk,
815 unsigned int div_lrck,
816 unsigned int fmt)
817 {
818 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
819 unsigned long flags;
820
821 if (!i2s_tdm->clk_trcm)
822 return 0;
823
824 spin_lock_irqsave(&i2s_tdm->lock, flags);
825 if (i2s_tdm->refcount)
826 rockchip_i2s_tdm_xfer_pause(substream, i2s_tdm);
827
828 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
829 I2S_CLKDIV_TXM_MASK | I2S_CLKDIV_RXM_MASK,
830 I2S_CLKDIV_TXM(div_bclk) | I2S_CLKDIV_RXM(div_bclk));
831 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
832 I2S_CKR_TSD_MASK | I2S_CKR_RSD_MASK,
833 I2S_CKR_TSD(div_lrck) | I2S_CKR_RSD(div_lrck));
834
835 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
836 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
837 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
838 fmt);
839 else
840 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
841 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
842 fmt);
843
844 if (i2s_tdm->refcount)
845 rockchip_i2s_tdm_xfer_resume(substream, i2s_tdm);
846 spin_unlock_irqrestore(&i2s_tdm->lock, flags);
847
848 return 0;
849 }
850
rockchip_i2s_tdm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)851 static int rockchip_i2s_tdm_hw_params(struct snd_pcm_substream *substream,
852 struct snd_pcm_hw_params *params,
853 struct snd_soc_dai *dai)
854 {
855 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
856 struct clk *mclk;
857 int ret = 0;
858 unsigned int val = 0;
859 unsigned int mclk_rate, bclk_rate, div_bclk = 4, div_lrck = 64;
860
861 if (i2s_tdm->is_master_mode) {
862 if (i2s_tdm->mclk_calibrate)
863 rockchip_i2s_tdm_calibrate_mclk(i2s_tdm, substream,
864 params_rate(params));
865
866 ret = rockchip_i2s_tdm_set_mclk(i2s_tdm, substream, &mclk);
867 if (ret)
868 return ret;
869
870 mclk_rate = clk_get_rate(mclk);
871 bclk_rate = i2s_tdm->frame_width * params_rate(params);
872 if (!bclk_rate)
873 return -EINVAL;
874
875 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
876 div_lrck = bclk_rate / params_rate(params);
877 }
878
879 switch (params_format(params)) {
880 case SNDRV_PCM_FORMAT_S8:
881 val |= I2S_TXCR_VDW(8);
882 break;
883 case SNDRV_PCM_FORMAT_S16_LE:
884 val |= I2S_TXCR_VDW(16);
885 break;
886 case SNDRV_PCM_FORMAT_S20_3LE:
887 val |= I2S_TXCR_VDW(20);
888 break;
889 case SNDRV_PCM_FORMAT_S24_LE:
890 val |= I2S_TXCR_VDW(24);
891 break;
892 case SNDRV_PCM_FORMAT_S32_LE:
893 val |= I2S_TXCR_VDW(32);
894 break;
895 default:
896 return -EINVAL;
897 }
898
899 switch (params_channels(params)) {
900 case 8:
901 val |= I2S_CHN_8;
902 break;
903 case 6:
904 val |= I2S_CHN_6;
905 break;
906 case 4:
907 val |= I2S_CHN_4;
908 break;
909 case 2:
910 val |= I2S_CHN_2;
911 break;
912 default:
913 return -EINVAL;
914 }
915
916 if (i2s_tdm->clk_trcm) {
917 rockchip_i2s_trcm_mode(substream, dai, div_bclk, div_lrck, val);
918 } else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
919 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
920 I2S_CLKDIV_TXM_MASK,
921 I2S_CLKDIV_TXM(div_bclk));
922 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
923 I2S_CKR_TSD_MASK,
924 I2S_CKR_TSD(div_lrck));
925 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
926 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
927 val);
928 } else {
929 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
930 I2S_CLKDIV_RXM_MASK,
931 I2S_CLKDIV_RXM(div_bclk));
932 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
933 I2S_CKR_RSD_MASK,
934 I2S_CKR_RSD(div_lrck));
935 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
936 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
937 val);
938 }
939
940 return rockchip_i2s_io_multiplex(substream, dai);
941 }
942
rockchip_i2s_tdm_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)943 static int rockchip_i2s_tdm_trigger(struct snd_pcm_substream *substream,
944 int cmd, struct snd_soc_dai *dai)
945 {
946 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
947
948 switch (cmd) {
949 case SNDRV_PCM_TRIGGER_START:
950 case SNDRV_PCM_TRIGGER_RESUME:
951 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
952 if (i2s_tdm->clk_trcm)
953 rockchip_snd_txrxctrl(substream, dai, 1);
954 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
955 rockchip_snd_rxctrl(i2s_tdm, 1);
956 else
957 rockchip_snd_txctrl(i2s_tdm, 1);
958 break;
959 case SNDRV_PCM_TRIGGER_SUSPEND:
960 case SNDRV_PCM_TRIGGER_STOP:
961 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
962 if (i2s_tdm->clk_trcm)
963 rockchip_snd_txrxctrl(substream, dai, 0);
964 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
965 rockchip_snd_rxctrl(i2s_tdm, 0);
966 else
967 rockchip_snd_txctrl(i2s_tdm, 0);
968 break;
969 default:
970 return -EINVAL;
971 }
972
973 return 0;
974 }
975
rockchip_i2s_tdm_set_sysclk(struct snd_soc_dai * cpu_dai,int stream,unsigned int freq,int dir)976 static int rockchip_i2s_tdm_set_sysclk(struct snd_soc_dai *cpu_dai, int stream,
977 unsigned int freq, int dir)
978 {
979 struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai);
980
981 /* Put set mclk rate into rockchip_i2s_tdm_set_mclk() */
982 if (i2s_tdm->clk_trcm) {
983 i2s_tdm->mclk_tx_freq = freq;
984 i2s_tdm->mclk_rx_freq = freq;
985 } else {
986 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
987 i2s_tdm->mclk_tx_freq = freq;
988 else
989 i2s_tdm->mclk_rx_freq = freq;
990 }
991
992 dev_dbg(i2s_tdm->dev, "The target mclk_%s freq is: %d\n",
993 stream ? "rx" : "tx", freq);
994
995 return 0;
996 }
997
rockchip_i2s_tdm_clk_compensation_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)998 static int rockchip_i2s_tdm_clk_compensation_info(struct snd_kcontrol *kcontrol,
999 struct snd_ctl_elem_info *uinfo)
1000 {
1001 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1002 uinfo->count = 1;
1003 uinfo->value.integer.min = CLK_PPM_MIN;
1004 uinfo->value.integer.max = CLK_PPM_MAX;
1005 uinfo->value.integer.step = 1;
1006
1007 return 0;
1008 }
1009
rockchip_i2s_tdm_clk_compensation_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1010 static int rockchip_i2s_tdm_clk_compensation_get(struct snd_kcontrol *kcontrol,
1011 struct snd_ctl_elem_value *ucontrol)
1012 {
1013 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
1014 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1015
1016 ucontrol->value.integer.value[0] = i2s_tdm->clk_ppm;
1017
1018 return 0;
1019 }
1020
rockchip_i2s_tdm_clk_compensation_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1021 static int rockchip_i2s_tdm_clk_compensation_put(struct snd_kcontrol *kcontrol,
1022 struct snd_ctl_elem_value *ucontrol)
1023 {
1024 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
1025 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1026 int ret = 0, ppm = 0;
1027 int changed = 0;
1028 unsigned long old_rate;
1029
1030 if (ucontrol->value.integer.value[0] < CLK_PPM_MIN ||
1031 ucontrol->value.integer.value[0] > CLK_PPM_MAX)
1032 return -EINVAL;
1033
1034 ppm = ucontrol->value.integer.value[0];
1035
1036 old_rate = clk_get_rate(i2s_tdm->mclk_root0);
1037 ret = rockchip_i2s_tdm_clk_set_rate(i2s_tdm, i2s_tdm->mclk_root0,
1038 i2s_tdm->mclk_root0_freq, ppm);
1039 if (ret)
1040 return ret;
1041 if (old_rate != clk_get_rate(i2s_tdm->mclk_root0))
1042 changed = 1;
1043
1044 if (clk_is_match(i2s_tdm->mclk_root0, i2s_tdm->mclk_root1))
1045 return changed;
1046
1047 old_rate = clk_get_rate(i2s_tdm->mclk_root1);
1048 ret = rockchip_i2s_tdm_clk_set_rate(i2s_tdm, i2s_tdm->mclk_root1,
1049 i2s_tdm->mclk_root1_freq, ppm);
1050 if (ret)
1051 return ret;
1052 if (old_rate != clk_get_rate(i2s_tdm->mclk_root1))
1053 changed = 1;
1054
1055 return changed;
1056 }
1057
1058 static struct snd_kcontrol_new rockchip_i2s_tdm_compensation_control = {
1059 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1060 .name = "PCM Clock Compensation in PPM",
1061 .info = rockchip_i2s_tdm_clk_compensation_info,
1062 .get = rockchip_i2s_tdm_clk_compensation_get,
1063 .put = rockchip_i2s_tdm_clk_compensation_put,
1064 };
1065
rockchip_i2s_tdm_dai_probe(struct snd_soc_dai * dai)1066 static int rockchip_i2s_tdm_dai_probe(struct snd_soc_dai *dai)
1067 {
1068 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1069
1070 if (i2s_tdm->has_capture)
1071 snd_soc_dai_dma_data_set_capture(dai, &i2s_tdm->capture_dma_data);
1072 if (i2s_tdm->has_playback)
1073 snd_soc_dai_dma_data_set_playback(dai, &i2s_tdm->playback_dma_data);
1074
1075 if (i2s_tdm->mclk_calibrate)
1076 snd_soc_add_dai_controls(dai, &rockchip_i2s_tdm_compensation_control, 1);
1077
1078 return 0;
1079 }
1080
rockchip_dai_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)1081 static int rockchip_dai_tdm_slot(struct snd_soc_dai *dai,
1082 unsigned int tx_mask, unsigned int rx_mask,
1083 int slots, int slot_width)
1084 {
1085 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1086 unsigned int mask, val;
1087
1088 i2s_tdm->tdm_mode = true;
1089 i2s_tdm->frame_width = slots * slot_width;
1090 mask = TDM_SLOT_BIT_WIDTH_MSK | TDM_FRAME_WIDTH_MSK;
1091 val = TDM_SLOT_BIT_WIDTH(slot_width) |
1092 TDM_FRAME_WIDTH(slots * slot_width);
1093 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR,
1094 mask, val);
1095 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR,
1096 mask, val);
1097
1098 return 0;
1099 }
1100
rockchip_i2s_tdm_set_bclk_ratio(struct snd_soc_dai * dai,unsigned int ratio)1101 static int rockchip_i2s_tdm_set_bclk_ratio(struct snd_soc_dai *dai,
1102 unsigned int ratio)
1103 {
1104 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1105
1106 if (ratio < 32 || ratio > 512 || ratio % 2 == 1)
1107 return -EINVAL;
1108
1109 i2s_tdm->frame_width = ratio;
1110
1111 return 0;
1112 }
1113
1114 static const struct snd_soc_dai_ops rockchip_i2s_tdm_dai_ops = {
1115 .probe = rockchip_i2s_tdm_dai_probe,
1116 .hw_params = rockchip_i2s_tdm_hw_params,
1117 .set_bclk_ratio = rockchip_i2s_tdm_set_bclk_ratio,
1118 .set_sysclk = rockchip_i2s_tdm_set_sysclk,
1119 .set_fmt = rockchip_i2s_tdm_set_fmt,
1120 .set_tdm_slot = rockchip_dai_tdm_slot,
1121 .trigger = rockchip_i2s_tdm_trigger,
1122 };
1123
1124 static const struct snd_soc_component_driver rockchip_i2s_tdm_component = {
1125 .name = DRV_NAME,
1126 .legacy_dai_naming = 1,
1127 };
1128
rockchip_i2s_tdm_wr_reg(struct device * dev,unsigned int reg)1129 static bool rockchip_i2s_tdm_wr_reg(struct device *dev, unsigned int reg)
1130 {
1131 switch (reg) {
1132 case I2S_TXCR:
1133 case I2S_RXCR:
1134 case I2S_CKR:
1135 case I2S_DMACR:
1136 case I2S_INTCR:
1137 case I2S_XFER:
1138 case I2S_CLR:
1139 case I2S_TXDR:
1140 case I2S_TDM_TXCR:
1141 case I2S_TDM_RXCR:
1142 case I2S_CLKDIV:
1143 return true;
1144 default:
1145 return false;
1146 }
1147 }
1148
rockchip_i2s_tdm_rd_reg(struct device * dev,unsigned int reg)1149 static bool rockchip_i2s_tdm_rd_reg(struct device *dev, unsigned int reg)
1150 {
1151 switch (reg) {
1152 case I2S_TXCR:
1153 case I2S_RXCR:
1154 case I2S_CKR:
1155 case I2S_DMACR:
1156 case I2S_INTCR:
1157 case I2S_XFER:
1158 case I2S_CLR:
1159 case I2S_TXDR:
1160 case I2S_RXDR:
1161 case I2S_TXFIFOLR:
1162 case I2S_INTSR:
1163 case I2S_RXFIFOLR:
1164 case I2S_TDM_TXCR:
1165 case I2S_TDM_RXCR:
1166 case I2S_CLKDIV:
1167 return true;
1168 default:
1169 return false;
1170 }
1171 }
1172
rockchip_i2s_tdm_volatile_reg(struct device * dev,unsigned int reg)1173 static bool rockchip_i2s_tdm_volatile_reg(struct device *dev, unsigned int reg)
1174 {
1175 switch (reg) {
1176 case I2S_TXFIFOLR:
1177 case I2S_INTSR:
1178 case I2S_CLR:
1179 case I2S_TXDR:
1180 case I2S_RXDR:
1181 case I2S_RXFIFOLR:
1182 return true;
1183 default:
1184 return false;
1185 }
1186 }
1187
rockchip_i2s_tdm_precious_reg(struct device * dev,unsigned int reg)1188 static bool rockchip_i2s_tdm_precious_reg(struct device *dev, unsigned int reg)
1189 {
1190 if (reg == I2S_RXDR)
1191 return true;
1192 return false;
1193 }
1194
1195 static const struct reg_default rockchip_i2s_tdm_reg_defaults[] = {
1196 {0x00, 0x7200000f},
1197 {0x04, 0x01c8000f},
1198 {0x08, 0x00001f1f},
1199 {0x10, 0x001f0000},
1200 {0x14, 0x01f00000},
1201 {0x30, 0x00003eff},
1202 {0x34, 0x00003eff},
1203 {0x38, 0x00000707},
1204 };
1205
1206 static const struct regmap_config rockchip_i2s_tdm_regmap_config = {
1207 .reg_bits = 32,
1208 .reg_stride = 4,
1209 .val_bits = 32,
1210 .max_register = I2S_CLKDIV,
1211 .reg_defaults = rockchip_i2s_tdm_reg_defaults,
1212 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_tdm_reg_defaults),
1213 .writeable_reg = rockchip_i2s_tdm_wr_reg,
1214 .readable_reg = rockchip_i2s_tdm_rd_reg,
1215 .volatile_reg = rockchip_i2s_tdm_volatile_reg,
1216 .precious_reg = rockchip_i2s_tdm_precious_reg,
1217 .cache_type = REGCACHE_FLAT,
1218 };
1219
common_soc_init(struct device * dev,u32 addr)1220 static int common_soc_init(struct device *dev, u32 addr)
1221 {
1222 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
1223 const struct txrx_config *configs = i2s_tdm->soc_data->configs;
1224 u32 reg = 0, val = 0, trcm = i2s_tdm->clk_trcm;
1225 int i;
1226
1227 if (trcm == TRCM_TXRX)
1228 return 0;
1229
1230 if (IS_ERR_OR_NULL(i2s_tdm->grf)) {
1231 dev_err(i2s_tdm->dev,
1232 "no grf present but non-txrx TRCM specified\n");
1233 return -EINVAL;
1234 }
1235
1236 for (i = 0; i < i2s_tdm->soc_data->config_count; i++) {
1237 if (addr != configs[i].addr)
1238 continue;
1239 reg = configs[i].reg;
1240 if (trcm == TRCM_TX)
1241 val = configs[i].txonly;
1242 else
1243 val = configs[i].rxonly;
1244
1245 if (reg)
1246 regmap_write(i2s_tdm->grf, reg, val);
1247 }
1248
1249 return 0;
1250 }
1251
1252 static const struct txrx_config px30_txrx_config[] = {
1253 { 0xff060000, 0x184, PX30_I2S0_CLK_TXONLY, PX30_I2S0_CLK_RXONLY },
1254 };
1255
1256 static const struct txrx_config rk1808_txrx_config[] = {
1257 { 0xff7e0000, 0x190, RK1808_I2S0_CLK_TXONLY, RK1808_I2S0_CLK_RXONLY },
1258 };
1259
1260 static const struct txrx_config rk3308_txrx_config[] = {
1261 { 0xff300000, 0x308, RK3308_I2S0_CLK_TXONLY, RK3308_I2S0_CLK_RXONLY },
1262 { 0xff310000, 0x308, RK3308_I2S1_CLK_TXONLY, RK3308_I2S1_CLK_RXONLY },
1263 };
1264
1265 static const struct txrx_config rk3568_txrx_config[] = {
1266 { 0xfe410000, 0x504, RK3568_I2S1_CLK_TXONLY, RK3568_I2S1_CLK_RXONLY },
1267 { 0xfe410000, 0x508, RK3568_I2S1_MCLK_TX_OE, RK3568_I2S1_MCLK_RX_OE },
1268 { 0xfe420000, 0x508, RK3568_I2S2_MCLK_OE, RK3568_I2S2_MCLK_OE },
1269 { 0xfe430000, 0x504, RK3568_I2S3_CLK_TXONLY, RK3568_I2S3_CLK_RXONLY },
1270 { 0xfe430000, 0x508, RK3568_I2S3_MCLK_TXONLY, RK3568_I2S3_MCLK_RXONLY },
1271 { 0xfe430000, 0x508, RK3568_I2S3_MCLK_OE, RK3568_I2S3_MCLK_OE },
1272 };
1273
1274 static const struct txrx_config rv1126_txrx_config[] = {
1275 { 0xff800000, 0x10260, RV1126_I2S0_CLK_TXONLY, RV1126_I2S0_CLK_RXONLY },
1276 };
1277
1278 static const struct rk_i2s_soc_data px30_i2s_soc_data = {
1279 .softrst_offset = 0x0300,
1280 .configs = px30_txrx_config,
1281 .config_count = ARRAY_SIZE(px30_txrx_config),
1282 .init = common_soc_init,
1283 };
1284
1285 static const struct rk_i2s_soc_data rk1808_i2s_soc_data = {
1286 .softrst_offset = 0x0300,
1287 .configs = rk1808_txrx_config,
1288 .config_count = ARRAY_SIZE(rk1808_txrx_config),
1289 .init = common_soc_init,
1290 };
1291
1292 static const struct rk_i2s_soc_data rk3308_i2s_soc_data = {
1293 .softrst_offset = 0x0400,
1294 .grf_reg_offset = 0x0308,
1295 .grf_shift = 5,
1296 .configs = rk3308_txrx_config,
1297 .config_count = ARRAY_SIZE(rk3308_txrx_config),
1298 .init = common_soc_init,
1299 };
1300
1301 static const struct rk_i2s_soc_data rk3568_i2s_soc_data = {
1302 .softrst_offset = 0x0400,
1303 .configs = rk3568_txrx_config,
1304 .config_count = ARRAY_SIZE(rk3568_txrx_config),
1305 .init = common_soc_init,
1306 };
1307
1308 static const struct rk_i2s_soc_data rv1126_i2s_soc_data = {
1309 .softrst_offset = 0x0300,
1310 .configs = rv1126_txrx_config,
1311 .config_count = ARRAY_SIZE(rv1126_txrx_config),
1312 .init = common_soc_init,
1313 };
1314
1315 static const struct of_device_id rockchip_i2s_tdm_match[] = {
1316 { .compatible = "rockchip,px30-i2s-tdm", .data = &px30_i2s_soc_data },
1317 { .compatible = "rockchip,rk1808-i2s-tdm", .data = &rk1808_i2s_soc_data },
1318 { .compatible = "rockchip,rk3308-i2s-tdm", .data = &rk3308_i2s_soc_data },
1319 { .compatible = "rockchip,rk3568-i2s-tdm", .data = &rk3568_i2s_soc_data },
1320 { .compatible = "rockchip,rk3588-i2s-tdm" },
1321 { .compatible = "rockchip,rv1126-i2s-tdm", .data = &rv1126_i2s_soc_data },
1322 {},
1323 };
1324
1325 static const struct snd_soc_dai_driver i2s_tdm_dai = {
1326 .ops = &rockchip_i2s_tdm_dai_ops,
1327 };
1328
rockchip_i2s_tdm_init_dai(struct rk_i2s_tdm_dev * i2s_tdm)1329 static int rockchip_i2s_tdm_init_dai(struct rk_i2s_tdm_dev *i2s_tdm)
1330 {
1331 struct snd_soc_dai_driver *dai;
1332 struct property *dma_names;
1333 const char *dma_name;
1334 u64 formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |
1335 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |
1336 SNDRV_PCM_FMTBIT_S32_LE);
1337 struct device_node *node = i2s_tdm->dev->of_node;
1338
1339 of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
1340 if (!strcmp(dma_name, "tx"))
1341 i2s_tdm->has_playback = true;
1342 if (!strcmp(dma_name, "rx"))
1343 i2s_tdm->has_capture = true;
1344 }
1345
1346 dai = devm_kmemdup(i2s_tdm->dev, &i2s_tdm_dai,
1347 sizeof(*dai), GFP_KERNEL);
1348 if (!dai)
1349 return -ENOMEM;
1350
1351 if (i2s_tdm->has_playback) {
1352 dai->playback.stream_name = "Playback";
1353 dai->playback.channels_min = 2;
1354 dai->playback.channels_max = 8;
1355 dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
1356 dai->playback.formats = formats;
1357 }
1358
1359 if (i2s_tdm->has_capture) {
1360 dai->capture.stream_name = "Capture";
1361 dai->capture.channels_min = 2;
1362 dai->capture.channels_max = 8;
1363 dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
1364 dai->capture.formats = formats;
1365 }
1366
1367 if (i2s_tdm->clk_trcm != TRCM_TXRX)
1368 dai->symmetric_rate = 1;
1369
1370 i2s_tdm->dai = dai;
1371
1372 return 0;
1373 }
1374
rockchip_i2s_tdm_path_check(struct rk_i2s_tdm_dev * i2s_tdm,int num,bool is_rx_path)1375 static int rockchip_i2s_tdm_path_check(struct rk_i2s_tdm_dev *i2s_tdm,
1376 int num,
1377 bool is_rx_path)
1378 {
1379 unsigned int *i2s_data;
1380 int i, j;
1381
1382 if (is_rx_path)
1383 i2s_data = i2s_tdm->i2s_sdis;
1384 else
1385 i2s_data = i2s_tdm->i2s_sdos;
1386
1387 for (i = 0; i < num; i++) {
1388 if (i2s_data[i] > CH_GRP_MAX - 1) {
1389 dev_err(i2s_tdm->dev,
1390 "%s path i2s_data[%d]: %d is too high, max is: %d\n",
1391 is_rx_path ? "RX" : "TX",
1392 i, i2s_data[i], CH_GRP_MAX);
1393 return -EINVAL;
1394 }
1395
1396 for (j = 0; j < num; j++) {
1397 if (i == j)
1398 continue;
1399
1400 if (i2s_data[i] == i2s_data[j]) {
1401 dev_err(i2s_tdm->dev,
1402 "%s path invalid routed i2s_data: [%d]%d == [%d]%d\n",
1403 is_rx_path ? "RX" : "TX",
1404 i, i2s_data[i],
1405 j, i2s_data[j]);
1406 return -EINVAL;
1407 }
1408 }
1409 }
1410
1411 return 0;
1412 }
1413
rockchip_i2s_tdm_tx_path_config(struct rk_i2s_tdm_dev * i2s_tdm,int num)1414 static void rockchip_i2s_tdm_tx_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1415 int num)
1416 {
1417 int idx;
1418
1419 for (idx = 0; idx < num; idx++) {
1420 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
1421 I2S_TXCR_PATH_MASK(idx),
1422 I2S_TXCR_PATH(idx, i2s_tdm->i2s_sdos[idx]));
1423 }
1424 }
1425
rockchip_i2s_tdm_rx_path_config(struct rk_i2s_tdm_dev * i2s_tdm,int num)1426 static void rockchip_i2s_tdm_rx_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1427 int num)
1428 {
1429 int idx;
1430
1431 for (idx = 0; idx < num; idx++) {
1432 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
1433 I2S_RXCR_PATH_MASK(idx),
1434 I2S_RXCR_PATH(idx, i2s_tdm->i2s_sdis[idx]));
1435 }
1436 }
1437
rockchip_i2s_tdm_path_config(struct rk_i2s_tdm_dev * i2s_tdm,int num,bool is_rx_path)1438 static void rockchip_i2s_tdm_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1439 int num, bool is_rx_path)
1440 {
1441 if (is_rx_path)
1442 rockchip_i2s_tdm_rx_path_config(i2s_tdm, num);
1443 else
1444 rockchip_i2s_tdm_tx_path_config(i2s_tdm, num);
1445 }
1446
rockchip_i2s_tdm_get_calibrate_mclks(struct rk_i2s_tdm_dev * i2s_tdm)1447 static int rockchip_i2s_tdm_get_calibrate_mclks(struct rk_i2s_tdm_dev *i2s_tdm)
1448 {
1449 int num_mclks = 0;
1450
1451 i2s_tdm->mclk_tx_src = devm_clk_get(i2s_tdm->dev, "mclk_tx_src");
1452 if (!IS_ERR(i2s_tdm->mclk_tx_src))
1453 num_mclks++;
1454
1455 i2s_tdm->mclk_rx_src = devm_clk_get(i2s_tdm->dev, "mclk_rx_src");
1456 if (!IS_ERR(i2s_tdm->mclk_rx_src))
1457 num_mclks++;
1458
1459 i2s_tdm->mclk_root0 = devm_clk_get(i2s_tdm->dev, "mclk_root0");
1460 if (!IS_ERR(i2s_tdm->mclk_root0))
1461 num_mclks++;
1462
1463 i2s_tdm->mclk_root1 = devm_clk_get(i2s_tdm->dev, "mclk_root1");
1464 if (!IS_ERR(i2s_tdm->mclk_root1))
1465 num_mclks++;
1466
1467 if (num_mclks < 4 && num_mclks != 0)
1468 return -ENOENT;
1469
1470 if (num_mclks == 4)
1471 i2s_tdm->mclk_calibrate = 1;
1472
1473 return 0;
1474 }
1475
rockchip_i2s_tdm_path_prepare(struct rk_i2s_tdm_dev * i2s_tdm,struct device_node * np,bool is_rx_path)1476 static int rockchip_i2s_tdm_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1477 struct device_node *np,
1478 bool is_rx_path)
1479 {
1480 char *i2s_tx_path_prop = "rockchip,i2s-tx-route";
1481 char *i2s_rx_path_prop = "rockchip,i2s-rx-route";
1482 char *i2s_path_prop;
1483 unsigned int *i2s_data;
1484 int num, ret = 0;
1485
1486 if (is_rx_path) {
1487 i2s_path_prop = i2s_rx_path_prop;
1488 i2s_data = i2s_tdm->i2s_sdis;
1489 } else {
1490 i2s_path_prop = i2s_tx_path_prop;
1491 i2s_data = i2s_tdm->i2s_sdos;
1492 }
1493
1494 num = of_count_phandle_with_args(np, i2s_path_prop, NULL);
1495 if (num < 0) {
1496 if (num != -ENOENT) {
1497 dev_err(i2s_tdm->dev,
1498 "Failed to read '%s' num: %d\n",
1499 i2s_path_prop, num);
1500 ret = num;
1501 }
1502 return ret;
1503 } else if (num != CH_GRP_MAX) {
1504 dev_err(i2s_tdm->dev,
1505 "The num: %d should be: %d\n", num, CH_GRP_MAX);
1506 return -EINVAL;
1507 }
1508
1509 ret = of_property_read_u32_array(np, i2s_path_prop,
1510 i2s_data, num);
1511 if (ret < 0) {
1512 dev_err(i2s_tdm->dev,
1513 "Failed to read '%s': %d\n",
1514 i2s_path_prop, ret);
1515 return ret;
1516 }
1517
1518 ret = rockchip_i2s_tdm_path_check(i2s_tdm, num, is_rx_path);
1519 if (ret < 0) {
1520 dev_err(i2s_tdm->dev,
1521 "Failed to check i2s data bus: %d\n", ret);
1522 return ret;
1523 }
1524
1525 rockchip_i2s_tdm_path_config(i2s_tdm, num, is_rx_path);
1526
1527 return 0;
1528 }
1529
rockchip_i2s_tdm_tx_path_prepare(struct rk_i2s_tdm_dev * i2s_tdm,struct device_node * np)1530 static int rockchip_i2s_tdm_tx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1531 struct device_node *np)
1532 {
1533 return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 0);
1534 }
1535
rockchip_i2s_tdm_rx_path_prepare(struct rk_i2s_tdm_dev * i2s_tdm,struct device_node * np)1536 static int rockchip_i2s_tdm_rx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1537 struct device_node *np)
1538 {
1539 return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 1);
1540 }
1541
rockchip_i2s_tdm_probe(struct platform_device * pdev)1542 static int rockchip_i2s_tdm_probe(struct platform_device *pdev)
1543 {
1544 struct device_node *node = pdev->dev.of_node;
1545 struct rk_i2s_tdm_dev *i2s_tdm;
1546 struct resource *res;
1547 void __iomem *regs;
1548 int ret;
1549
1550 i2s_tdm = devm_kzalloc(&pdev->dev, sizeof(*i2s_tdm), GFP_KERNEL);
1551 if (!i2s_tdm)
1552 return -ENOMEM;
1553
1554 i2s_tdm->dev = &pdev->dev;
1555
1556 spin_lock_init(&i2s_tdm->lock);
1557 i2s_tdm->soc_data = device_get_match_data(&pdev->dev);
1558 i2s_tdm->frame_width = 64;
1559
1560 i2s_tdm->clk_trcm = TRCM_TXRX;
1561 if (of_property_read_bool(node, "rockchip,trcm-sync-tx-only"))
1562 i2s_tdm->clk_trcm = TRCM_TX;
1563 if (of_property_read_bool(node, "rockchip,trcm-sync-rx-only")) {
1564 if (i2s_tdm->clk_trcm) {
1565 dev_err(i2s_tdm->dev, "invalid trcm-sync configuration\n");
1566 return -EINVAL;
1567 }
1568 i2s_tdm->clk_trcm = TRCM_RX;
1569 }
1570
1571 ret = rockchip_i2s_tdm_init_dai(i2s_tdm);
1572 if (ret)
1573 return ret;
1574
1575 i2s_tdm->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
1576 i2s_tdm->tx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
1577 "tx-m");
1578 if (IS_ERR(i2s_tdm->tx_reset)) {
1579 ret = PTR_ERR(i2s_tdm->tx_reset);
1580 return dev_err_probe(i2s_tdm->dev, ret,
1581 "Error in tx-m reset control\n");
1582 }
1583
1584 i2s_tdm->rx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
1585 "rx-m");
1586 if (IS_ERR(i2s_tdm->rx_reset)) {
1587 ret = PTR_ERR(i2s_tdm->rx_reset);
1588 return dev_err_probe(i2s_tdm->dev, ret,
1589 "Error in rx-m reset control\n");
1590 }
1591
1592 i2s_tdm->hclk = devm_clk_get(&pdev->dev, "hclk");
1593 if (IS_ERR(i2s_tdm->hclk)) {
1594 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->hclk),
1595 "Failed to get clock hclk\n");
1596 }
1597
1598 i2s_tdm->mclk_tx = devm_clk_get(&pdev->dev, "mclk_tx");
1599 if (IS_ERR(i2s_tdm->mclk_tx)) {
1600 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_tx),
1601 "Failed to get clock mclk_tx\n");
1602 }
1603
1604 i2s_tdm->mclk_rx = devm_clk_get(&pdev->dev, "mclk_rx");
1605 if (IS_ERR(i2s_tdm->mclk_rx)) {
1606 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_rx),
1607 "Failed to get clock mclk_rx\n");
1608 }
1609
1610 i2s_tdm->io_multiplex =
1611 of_property_read_bool(node, "rockchip,io-multiplex");
1612
1613 ret = rockchip_i2s_tdm_get_calibrate_mclks(i2s_tdm);
1614 if (ret)
1615 return dev_err_probe(i2s_tdm->dev, ret,
1616 "mclk-calibrate clocks missing");
1617
1618 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1619 if (IS_ERR(regs)) {
1620 return dev_err_probe(i2s_tdm->dev, PTR_ERR(regs),
1621 "Failed to get resource IORESOURCE_MEM\n");
1622 }
1623
1624 i2s_tdm->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1625 &rockchip_i2s_tdm_regmap_config);
1626 if (IS_ERR(i2s_tdm->regmap)) {
1627 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->regmap),
1628 "Failed to initialise regmap\n");
1629 }
1630
1631 if (i2s_tdm->has_playback) {
1632 i2s_tdm->playback_dma_data.addr = res->start + I2S_TXDR;
1633 i2s_tdm->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1634 i2s_tdm->playback_dma_data.maxburst = 8;
1635 }
1636
1637 if (i2s_tdm->has_capture) {
1638 i2s_tdm->capture_dma_data.addr = res->start + I2S_RXDR;
1639 i2s_tdm->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1640 i2s_tdm->capture_dma_data.maxburst = 8;
1641 }
1642
1643 ret = rockchip_i2s_tdm_tx_path_prepare(i2s_tdm, node);
1644 if (ret < 0) {
1645 dev_err(&pdev->dev, "I2S TX path prepare failed: %d\n", ret);
1646 return ret;
1647 }
1648
1649 ret = rockchip_i2s_tdm_rx_path_prepare(i2s_tdm, node);
1650 if (ret < 0) {
1651 dev_err(&pdev->dev, "I2S RX path prepare failed: %d\n", ret);
1652 return ret;
1653 }
1654
1655 dev_set_drvdata(&pdev->dev, i2s_tdm);
1656
1657 ret = clk_prepare_enable(i2s_tdm->hclk);
1658 if (ret) {
1659 return dev_err_probe(i2s_tdm->dev, ret,
1660 "Failed to enable clock hclk\n");
1661 }
1662
1663 ret = i2s_tdm_prepare_enable_mclk(i2s_tdm);
1664 if (ret) {
1665 ret = dev_err_probe(i2s_tdm->dev, ret,
1666 "Failed to enable one or more mclks\n");
1667 goto err_disable_hclk;
1668 }
1669
1670 if (i2s_tdm->mclk_calibrate) {
1671 i2s_tdm->mclk_root0_initial_freq = clk_get_rate(i2s_tdm->mclk_root0);
1672 i2s_tdm->mclk_root1_initial_freq = clk_get_rate(i2s_tdm->mclk_root1);
1673 i2s_tdm->mclk_root0_freq = i2s_tdm->mclk_root0_initial_freq;
1674 i2s_tdm->mclk_root1_freq = i2s_tdm->mclk_root1_initial_freq;
1675 }
1676
1677 pm_runtime_enable(&pdev->dev);
1678
1679 regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
1680 I2S_DMACR_TDL(16));
1681 regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
1682 I2S_DMACR_RDL(16));
1683 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, I2S_CKR_TRCM_MASK,
1684 i2s_tdm->clk_trcm << I2S_CKR_TRCM_SHIFT);
1685
1686 if (i2s_tdm->soc_data && i2s_tdm->soc_data->init)
1687 i2s_tdm->soc_data->init(&pdev->dev, res->start);
1688
1689 ret = devm_snd_soc_register_component(&pdev->dev,
1690 &rockchip_i2s_tdm_component,
1691 i2s_tdm->dai, 1);
1692
1693 if (ret) {
1694 dev_err(&pdev->dev, "Could not register DAI\n");
1695 goto err_suspend;
1696 }
1697
1698 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1699 if (ret) {
1700 dev_err(&pdev->dev, "Could not register PCM\n");
1701 goto err_suspend;
1702 }
1703
1704 return 0;
1705
1706 err_suspend:
1707 if (!pm_runtime_status_suspended(&pdev->dev))
1708 i2s_tdm_runtime_suspend(&pdev->dev);
1709 pm_runtime_disable(&pdev->dev);
1710
1711 err_disable_hclk:
1712 clk_disable_unprepare(i2s_tdm->hclk);
1713
1714 return ret;
1715 }
1716
rockchip_i2s_tdm_remove(struct platform_device * pdev)1717 static void rockchip_i2s_tdm_remove(struct platform_device *pdev)
1718 {
1719 if (!pm_runtime_status_suspended(&pdev->dev))
1720 i2s_tdm_runtime_suspend(&pdev->dev);
1721
1722 pm_runtime_disable(&pdev->dev);
1723 }
1724
rockchip_i2s_tdm_suspend(struct device * dev)1725 static int __maybe_unused rockchip_i2s_tdm_suspend(struct device *dev)
1726 {
1727 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
1728
1729 regcache_mark_dirty(i2s_tdm->regmap);
1730
1731 return 0;
1732 }
1733
rockchip_i2s_tdm_resume(struct device * dev)1734 static int __maybe_unused rockchip_i2s_tdm_resume(struct device *dev)
1735 {
1736 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
1737 int ret;
1738
1739 ret = pm_runtime_resume_and_get(dev);
1740 if (ret < 0)
1741 return ret;
1742 ret = regcache_sync(i2s_tdm->regmap);
1743 pm_runtime_put(dev);
1744
1745 return ret;
1746 }
1747
1748 static const struct dev_pm_ops rockchip_i2s_tdm_pm_ops = {
1749 SET_RUNTIME_PM_OPS(i2s_tdm_runtime_suspend, i2s_tdm_runtime_resume,
1750 NULL)
1751 SET_SYSTEM_SLEEP_PM_OPS(rockchip_i2s_tdm_suspend,
1752 rockchip_i2s_tdm_resume)
1753 };
1754
1755 static struct platform_driver rockchip_i2s_tdm_driver = {
1756 .probe = rockchip_i2s_tdm_probe,
1757 .remove_new = rockchip_i2s_tdm_remove,
1758 .driver = {
1759 .name = DRV_NAME,
1760 .of_match_table = rockchip_i2s_tdm_match,
1761 .pm = &rockchip_i2s_tdm_pm_ops,
1762 },
1763 };
1764 module_platform_driver(rockchip_i2s_tdm_driver);
1765
1766 MODULE_DESCRIPTION("ROCKCHIP I2S/TDM ASoC Interface");
1767 MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");
1768 MODULE_LICENSE("GPL v2");
1769 MODULE_ALIAS("platform:" DRV_NAME);
1770 MODULE_DEVICE_TABLE(of, rockchip_i2s_tdm_match);
1771