1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2023 MediaTek Inc.
4 * Author: Balsam CHIHI <bchihi@baylibre.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/delay.h>
10 #include <linux/debugfs.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/iopoll.h>
14 #include <linux/kernel.h>
15 #include <linux/nvmem-consumer.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/reset.h>
19 #include <linux/thermal.h>
20 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
21
22 #include "../thermal_hwmon.h"
23
24 #define LVTS_MONCTL0(__base) (__base + 0x0000)
25 #define LVTS_MONCTL1(__base) (__base + 0x0004)
26 #define LVTS_MONCTL2(__base) (__base + 0x0008)
27 #define LVTS_MONINT(__base) (__base + 0x000C)
28 #define LVTS_MONINTSTS(__base) (__base + 0x0010)
29 #define LVTS_MONIDET0(__base) (__base + 0x0014)
30 #define LVTS_MONIDET1(__base) (__base + 0x0018)
31 #define LVTS_MONIDET2(__base) (__base + 0x001C)
32 #define LVTS_MONIDET3(__base) (__base + 0x0020)
33 #define LVTS_H2NTHRE(__base) (__base + 0x0024)
34 #define LVTS_HTHRE(__base) (__base + 0x0028)
35 #define LVTS_OFFSETH(__base) (__base + 0x0030)
36 #define LVTS_OFFSETL(__base) (__base + 0x0034)
37 #define LVTS_MSRCTL0(__base) (__base + 0x0038)
38 #define LVTS_MSRCTL1(__base) (__base + 0x003C)
39 #define LVTS_TSSEL(__base) (__base + 0x0040)
40 #define LVTS_CALSCALE(__base) (__base + 0x0048)
41 #define LVTS_ID(__base) (__base + 0x004C)
42 #define LVTS_CONFIG(__base) (__base + 0x0050)
43 #define LVTS_EDATA00(__base) (__base + 0x0054)
44 #define LVTS_EDATA01(__base) (__base + 0x0058)
45 #define LVTS_EDATA02(__base) (__base + 0x005C)
46 #define LVTS_EDATA03(__base) (__base + 0x0060)
47 #define LVTS_MSR0(__base) (__base + 0x0090)
48 #define LVTS_MSR1(__base) (__base + 0x0094)
49 #define LVTS_MSR2(__base) (__base + 0x0098)
50 #define LVTS_MSR3(__base) (__base + 0x009C)
51 #define LVTS_IMMD0(__base) (__base + 0x00A0)
52 #define LVTS_IMMD1(__base) (__base + 0x00A4)
53 #define LVTS_IMMD2(__base) (__base + 0x00A8)
54 #define LVTS_IMMD3(__base) (__base + 0x00AC)
55 #define LVTS_PROTCTL(__base) (__base + 0x00C0)
56 #define LVTS_PROTTA(__base) (__base + 0x00C4)
57 #define LVTS_PROTTB(__base) (__base + 0x00C8)
58 #define LVTS_PROTTC(__base) (__base + 0x00CC)
59 #define LVTS_CLKEN(__base) (__base + 0x00E4)
60
61 #define LVTS_PERIOD_UNIT 0
62 #define LVTS_GROUP_INTERVAL 0
63 #define LVTS_FILTER_INTERVAL 0
64 #define LVTS_SENSOR_INTERVAL 0
65 #define LVTS_HW_FILTER 0x0
66 #define LVTS_TSSEL_CONF 0x13121110
67 #define LVTS_CALSCALE_CONF 0x300
68 #define LVTS_MONINT_CONF 0x8300318C
69
70 #define LVTS_MONINT_OFFSET_SENSOR0 0xC
71 #define LVTS_MONINT_OFFSET_SENSOR1 0x180
72 #define LVTS_MONINT_OFFSET_SENSOR2 0x3000
73 #define LVTS_MONINT_OFFSET_SENSOR3 0x3000000
74
75 #define LVTS_INT_SENSOR0 0x0009001F
76 #define LVTS_INT_SENSOR1 0x001203E0
77 #define LVTS_INT_SENSOR2 0x00247C00
78 #define LVTS_INT_SENSOR3 0x1FC00000
79
80 #define LVTS_SENSOR_MAX 4
81 #define LVTS_GOLDEN_TEMP_MAX 62
82 #define LVTS_GOLDEN_TEMP_DEFAULT 50
83 #define LVTS_COEFF_A_MT8195 -250460
84 #define LVTS_COEFF_B_MT8195 250460
85 #define LVTS_COEFF_A_MT7988 -204650
86 #define LVTS_COEFF_B_MT7988 204650
87
88 #define LVTS_MSR_IMMEDIATE_MODE 0
89 #define LVTS_MSR_FILTERED_MODE 1
90
91 #define LVTS_MSR_READ_TIMEOUT_US 400
92 #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2)
93
94 #define LVTS_HW_SHUTDOWN_MT7988 105000
95 #define LVTS_HW_SHUTDOWN_MT8192 105000
96 #define LVTS_HW_SHUTDOWN_MT8195 105000
97
98 #define LVTS_MINIMUM_THRESHOLD 20000
99
100 static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
101 static int golden_temp_offset;
102
103 struct lvts_sensor_data {
104 int dt_id;
105 };
106
107 struct lvts_ctrl_data {
108 struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX];
109 int cal_offset[LVTS_SENSOR_MAX];
110 int hw_tshut_temp;
111 int num_lvts_sensor;
112 int offset;
113 int mode;
114 };
115
116 struct lvts_data {
117 const struct lvts_ctrl_data *lvts_ctrl;
118 int num_lvts_ctrl;
119 int temp_factor;
120 int temp_offset;
121 };
122
123 struct lvts_sensor {
124 struct thermal_zone_device *tz;
125 void __iomem *msr;
126 void __iomem *base;
127 int id;
128 int dt_id;
129 int low_thresh;
130 int high_thresh;
131 };
132
133 struct lvts_ctrl {
134 struct lvts_sensor sensors[LVTS_SENSOR_MAX];
135 const struct lvts_data *lvts_data;
136 u32 calibration[LVTS_SENSOR_MAX];
137 u32 hw_tshut_raw_temp;
138 int num_lvts_sensor;
139 int mode;
140 void __iomem *base;
141 int low_thresh;
142 int high_thresh;
143 };
144
145 struct lvts_domain {
146 struct lvts_ctrl *lvts_ctrl;
147 struct reset_control *reset;
148 struct clk *clk;
149 int num_lvts_ctrl;
150 void __iomem *base;
151 size_t calib_len;
152 u8 *calib;
153 #ifdef CONFIG_DEBUG_FS
154 struct dentry *dom_dentry;
155 #endif
156 };
157
158 #ifdef CONFIG_MTK_LVTS_THERMAL_DEBUGFS
159
160 #define LVTS_DEBUG_FS_REGS(__reg) \
161 { \
162 .name = __stringify(__reg), \
163 .offset = __reg(0), \
164 }
165
166 static const struct debugfs_reg32 lvts_regs[] = {
167 LVTS_DEBUG_FS_REGS(LVTS_MONCTL0),
168 LVTS_DEBUG_FS_REGS(LVTS_MONCTL1),
169 LVTS_DEBUG_FS_REGS(LVTS_MONCTL2),
170 LVTS_DEBUG_FS_REGS(LVTS_MONINT),
171 LVTS_DEBUG_FS_REGS(LVTS_MONINTSTS),
172 LVTS_DEBUG_FS_REGS(LVTS_MONIDET0),
173 LVTS_DEBUG_FS_REGS(LVTS_MONIDET1),
174 LVTS_DEBUG_FS_REGS(LVTS_MONIDET2),
175 LVTS_DEBUG_FS_REGS(LVTS_MONIDET3),
176 LVTS_DEBUG_FS_REGS(LVTS_H2NTHRE),
177 LVTS_DEBUG_FS_REGS(LVTS_HTHRE),
178 LVTS_DEBUG_FS_REGS(LVTS_OFFSETH),
179 LVTS_DEBUG_FS_REGS(LVTS_OFFSETL),
180 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL0),
181 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL1),
182 LVTS_DEBUG_FS_REGS(LVTS_TSSEL),
183 LVTS_DEBUG_FS_REGS(LVTS_CALSCALE),
184 LVTS_DEBUG_FS_REGS(LVTS_ID),
185 LVTS_DEBUG_FS_REGS(LVTS_CONFIG),
186 LVTS_DEBUG_FS_REGS(LVTS_EDATA00),
187 LVTS_DEBUG_FS_REGS(LVTS_EDATA01),
188 LVTS_DEBUG_FS_REGS(LVTS_EDATA02),
189 LVTS_DEBUG_FS_REGS(LVTS_EDATA03),
190 LVTS_DEBUG_FS_REGS(LVTS_MSR0),
191 LVTS_DEBUG_FS_REGS(LVTS_MSR1),
192 LVTS_DEBUG_FS_REGS(LVTS_MSR2),
193 LVTS_DEBUG_FS_REGS(LVTS_MSR3),
194 LVTS_DEBUG_FS_REGS(LVTS_IMMD0),
195 LVTS_DEBUG_FS_REGS(LVTS_IMMD1),
196 LVTS_DEBUG_FS_REGS(LVTS_IMMD2),
197 LVTS_DEBUG_FS_REGS(LVTS_IMMD3),
198 LVTS_DEBUG_FS_REGS(LVTS_PROTCTL),
199 LVTS_DEBUG_FS_REGS(LVTS_PROTTA),
200 LVTS_DEBUG_FS_REGS(LVTS_PROTTB),
201 LVTS_DEBUG_FS_REGS(LVTS_PROTTC),
202 LVTS_DEBUG_FS_REGS(LVTS_CLKEN),
203 };
204
lvts_debugfs_init(struct device * dev,struct lvts_domain * lvts_td)205 static int lvts_debugfs_init(struct device *dev, struct lvts_domain *lvts_td)
206 {
207 struct debugfs_regset32 *regset;
208 struct lvts_ctrl *lvts_ctrl;
209 struct dentry *dentry;
210 char name[64];
211 int i;
212
213 lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL);
214 if (IS_ERR(lvts_td->dom_dentry))
215 return 0;
216
217 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
218
219 lvts_ctrl = &lvts_td->lvts_ctrl[i];
220
221 sprintf(name, "controller%d", i);
222 dentry = debugfs_create_dir(name, lvts_td->dom_dentry);
223 if (IS_ERR(dentry))
224 continue;
225
226 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
227 if (!regset)
228 continue;
229
230 regset->base = lvts_ctrl->base;
231 regset->regs = lvts_regs;
232 regset->nregs = ARRAY_SIZE(lvts_regs);
233
234 debugfs_create_regset32("registers", 0400, dentry, regset);
235 }
236
237 return 0;
238 }
239
lvts_debugfs_exit(struct lvts_domain * lvts_td)240 static void lvts_debugfs_exit(struct lvts_domain *lvts_td)
241 {
242 debugfs_remove_recursive(lvts_td->dom_dentry);
243 }
244
245 #else
246
lvts_debugfs_init(struct device * dev,struct lvts_domain * lvts_td)247 static inline int lvts_debugfs_init(struct device *dev,
248 struct lvts_domain *lvts_td)
249 {
250 return 0;
251 }
252
lvts_debugfs_exit(struct lvts_domain * lvts_td)253 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { }
254
255 #endif
256
lvts_raw_to_temp(u32 raw_temp,int temp_factor)257 static int lvts_raw_to_temp(u32 raw_temp, int temp_factor)
258 {
259 int temperature;
260
261 temperature = ((s64)(raw_temp & 0xFFFF) * temp_factor) >> 14;
262 temperature += golden_temp_offset;
263
264 return temperature;
265 }
266
lvts_temp_to_raw(int temperature,int temp_factor)267 static u32 lvts_temp_to_raw(int temperature, int temp_factor)
268 {
269 u32 raw_temp = ((s64)(golden_temp_offset - temperature)) << 14;
270
271 raw_temp = div_s64(raw_temp, -temp_factor);
272
273 return raw_temp;
274 }
275
lvts_get_temp(struct thermal_zone_device * tz,int * temp)276 static int lvts_get_temp(struct thermal_zone_device *tz, int *temp)
277 {
278 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
279 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl,
280 sensors[lvts_sensor->id]);
281 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
282 void __iomem *msr = lvts_sensor->msr;
283 u32 value;
284 int rc;
285
286 /*
287 * Measurement registers:
288 *
289 * LVTS_MSR[0-3] / LVTS_IMMD[0-3]
290 *
291 * Bits:
292 *
293 * 32-17: Unused
294 * 16 : Valid temperature
295 * 15-0 : Raw temperature
296 */
297 rc = readl_poll_timeout(msr, value, value & BIT(16),
298 LVTS_MSR_READ_WAIT_US, LVTS_MSR_READ_TIMEOUT_US);
299
300 /*
301 * As the thermal zone temperature will read before the
302 * hardware sensor is fully initialized, we have to check the
303 * validity of the temperature returned when reading the
304 * measurement register. The thermal controller will set the
305 * valid bit temperature only when it is totally initialized.
306 *
307 * Otherwise, we may end up with garbage values out of the
308 * functionning temperature and directly jump to a system
309 * shutdown.
310 */
311 if (rc)
312 return -EAGAIN;
313
314 *temp = lvts_raw_to_temp(value & 0xFFFF, lvts_data->temp_factor);
315
316 return 0;
317 }
318
lvts_update_irq_mask(struct lvts_ctrl * lvts_ctrl)319 static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl)
320 {
321 u32 masks[] = {
322 LVTS_MONINT_OFFSET_SENSOR0,
323 LVTS_MONINT_OFFSET_SENSOR1,
324 LVTS_MONINT_OFFSET_SENSOR2,
325 LVTS_MONINT_OFFSET_SENSOR3,
326 };
327 u32 value = 0;
328 int i;
329
330 value = readl(LVTS_MONINT(lvts_ctrl->base));
331
332 for (i = 0; i < ARRAY_SIZE(masks); i++) {
333 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh
334 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh)
335 value |= masks[i];
336 else
337 value &= ~masks[i];
338 }
339
340 writel(value, LVTS_MONINT(lvts_ctrl->base));
341 }
342
lvts_should_update_thresh(struct lvts_ctrl * lvts_ctrl,int high)343 static bool lvts_should_update_thresh(struct lvts_ctrl *lvts_ctrl, int high)
344 {
345 int i;
346
347 if (high > lvts_ctrl->high_thresh)
348 return true;
349
350 for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++)
351 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh
352 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh)
353 return false;
354
355 return true;
356 }
357
lvts_set_trips(struct thermal_zone_device * tz,int low,int high)358 static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high)
359 {
360 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
361 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl,
362 sensors[lvts_sensor->id]);
363 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
364 void __iomem *base = lvts_sensor->base;
365 u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD,
366 lvts_data->temp_factor);
367 u32 raw_high = lvts_temp_to_raw(high, lvts_data->temp_factor);
368 bool should_update_thresh;
369
370 lvts_sensor->low_thresh = low;
371 lvts_sensor->high_thresh = high;
372
373 should_update_thresh = lvts_should_update_thresh(lvts_ctrl, high);
374 if (should_update_thresh) {
375 lvts_ctrl->high_thresh = high;
376 lvts_ctrl->low_thresh = low;
377 }
378 lvts_update_irq_mask(lvts_ctrl);
379
380 if (!should_update_thresh)
381 return 0;
382
383 /*
384 * Low offset temperature threshold
385 *
386 * LVTS_OFFSETL
387 *
388 * Bits:
389 *
390 * 14-0 : Raw temperature for threshold
391 */
392 pr_debug("%s: Setting low limit temperature interrupt: %d\n",
393 thermal_zone_device_type(tz), low);
394 writel(raw_low, LVTS_OFFSETL(base));
395
396 /*
397 * High offset temperature threshold
398 *
399 * LVTS_OFFSETH
400 *
401 * Bits:
402 *
403 * 14-0 : Raw temperature for threshold
404 */
405 pr_debug("%s: Setting high limit temperature interrupt: %d\n",
406 thermal_zone_device_type(tz), high);
407 writel(raw_high, LVTS_OFFSETH(base));
408
409 return 0;
410 }
411
lvts_ctrl_irq_handler(struct lvts_ctrl * lvts_ctrl)412 static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl)
413 {
414 irqreturn_t iret = IRQ_NONE;
415 u32 value;
416 u32 masks[] = {
417 LVTS_INT_SENSOR0,
418 LVTS_INT_SENSOR1,
419 LVTS_INT_SENSOR2,
420 LVTS_INT_SENSOR3
421 };
422 int i;
423
424 /*
425 * Interrupt monitoring status
426 *
427 * LVTS_MONINTST
428 *
429 * Bits:
430 *
431 * 31 : Interrupt for stage 3
432 * 30 : Interrupt for stage 2
433 * 29 : Interrupt for state 1
434 * 28 : Interrupt using filter on sensor 3
435 *
436 * 27 : Interrupt using immediate on sensor 3
437 * 26 : Interrupt normal to hot on sensor 3
438 * 25 : Interrupt high offset on sensor 3
439 * 24 : Interrupt low offset on sensor 3
440 *
441 * 23 : Interrupt hot threshold on sensor 3
442 * 22 : Interrupt cold threshold on sensor 3
443 * 21 : Interrupt using filter on sensor 2
444 * 20 : Interrupt using filter on sensor 1
445 *
446 * 19 : Interrupt using filter on sensor 0
447 * 18 : Interrupt using immediate on sensor 2
448 * 17 : Interrupt using immediate on sensor 1
449 * 16 : Interrupt using immediate on sensor 0
450 *
451 * 15 : Interrupt device access timeout interrupt
452 * 14 : Interrupt normal to hot on sensor 2
453 * 13 : Interrupt high offset interrupt on sensor 2
454 * 12 : Interrupt low offset interrupt on sensor 2
455 *
456 * 11 : Interrupt hot threshold on sensor 2
457 * 10 : Interrupt cold threshold on sensor 2
458 * 9 : Interrupt normal to hot on sensor 1
459 * 8 : Interrupt high offset interrupt on sensor 1
460 *
461 * 7 : Interrupt low offset interrupt on sensor 1
462 * 6 : Interrupt hot threshold on sensor 1
463 * 5 : Interrupt cold threshold on sensor 1
464 * 4 : Interrupt normal to hot on sensor 0
465 *
466 * 3 : Interrupt high offset interrupt on sensor 0
467 * 2 : Interrupt low offset interrupt on sensor 0
468 * 1 : Interrupt hot threshold on sensor 0
469 * 0 : Interrupt cold threshold on sensor 0
470 *
471 * We are interested in the sensor(s) responsible of the
472 * interrupt event. We update the thermal framework with the
473 * thermal zone associated with the sensor. The framework will
474 * take care of the rest whatever the kind of interrupt, we
475 * are only interested in which sensor raised the interrupt.
476 *
477 * sensor 3 interrupt: 0001 1111 1100 0000 0000 0000 0000 0000
478 * => 0x1FC00000
479 * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000
480 * => 0x00247C00
481 * sensor 1 interrupt: 0000 0000 0001 0010 0000 0011 1110 0000
482 * => 0X001203E0
483 * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111
484 * => 0x0009001F
485 */
486 value = readl(LVTS_MONINTSTS(lvts_ctrl->base));
487
488 /*
489 * Let's figure out which sensors raised the interrupt
490 *
491 * NOTE: the masks array must be ordered with the index
492 * corresponding to the sensor id eg. index=0, mask for
493 * sensor0.
494 */
495 for (i = 0; i < ARRAY_SIZE(masks); i++) {
496
497 if (!(value & masks[i]))
498 continue;
499
500 thermal_zone_device_update(lvts_ctrl->sensors[i].tz,
501 THERMAL_TRIP_VIOLATED);
502 iret = IRQ_HANDLED;
503 }
504
505 /*
506 * Write back to clear the interrupt status (W1C)
507 */
508 writel(value, LVTS_MONINTSTS(lvts_ctrl->base));
509
510 return iret;
511 }
512
513 /*
514 * Temperature interrupt handler. Even if the driver supports more
515 * interrupt modes, we use the interrupt when the temperature crosses
516 * the hot threshold the way up and the way down (modulo the
517 * hysteresis).
518 *
519 * Each thermal domain has a couple of interrupts, one for hardware
520 * reset and another one for all the thermal events happening on the
521 * different sensors.
522 *
523 * The interrupt is configured for thermal events when crossing the
524 * hot temperature limit. At each interrupt, we check in every
525 * controller if there is an interrupt pending.
526 */
lvts_irq_handler(int irq,void * data)527 static irqreturn_t lvts_irq_handler(int irq, void *data)
528 {
529 struct lvts_domain *lvts_td = data;
530 irqreturn_t aux, iret = IRQ_NONE;
531 int i;
532
533 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
534
535 aux = lvts_ctrl_irq_handler(&lvts_td->lvts_ctrl[i]);
536 if (aux != IRQ_HANDLED)
537 continue;
538
539 iret = IRQ_HANDLED;
540 }
541
542 return iret;
543 }
544
545 static struct thermal_zone_device_ops lvts_ops = {
546 .get_temp = lvts_get_temp,
547 .set_trips = lvts_set_trips,
548 };
549
lvts_sensor_init(struct device * dev,struct lvts_ctrl * lvts_ctrl,const struct lvts_ctrl_data * lvts_ctrl_data)550 static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
551 const struct lvts_ctrl_data *lvts_ctrl_data)
552 {
553 struct lvts_sensor *lvts_sensor = lvts_ctrl->sensors;
554 void __iomem *msr_regs[] = {
555 LVTS_MSR0(lvts_ctrl->base),
556 LVTS_MSR1(lvts_ctrl->base),
557 LVTS_MSR2(lvts_ctrl->base),
558 LVTS_MSR3(lvts_ctrl->base)
559 };
560
561 void __iomem *imm_regs[] = {
562 LVTS_IMMD0(lvts_ctrl->base),
563 LVTS_IMMD1(lvts_ctrl->base),
564 LVTS_IMMD2(lvts_ctrl->base),
565 LVTS_IMMD3(lvts_ctrl->base)
566 };
567
568 int i;
569
570 for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) {
571
572 int dt_id = lvts_ctrl_data->lvts_sensor[i].dt_id;
573
574 /*
575 * At this point, we don't know which id matches which
576 * sensor. Let's set arbitrally the id from the index.
577 */
578 lvts_sensor[i].id = i;
579
580 /*
581 * The thermal zone registration will set the trip
582 * point interrupt in the thermal controller
583 * register. But this one will be reset in the
584 * initialization after. So we need to post pone the
585 * thermal zone creation after the controller is
586 * setup. For this reason, we store the device tree
587 * node id from the data in the sensor structure
588 */
589 lvts_sensor[i].dt_id = dt_id;
590
591 /*
592 * We assign the base address of the thermal
593 * controller as a back pointer. So it will be
594 * accessible from the different thermal framework ops
595 * as we pass the lvts_sensor pointer as thermal zone
596 * private data.
597 */
598 lvts_sensor[i].base = lvts_ctrl->base;
599
600 /*
601 * Each sensor has its own register address to read from.
602 */
603 lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ?
604 imm_regs[i] : msr_regs[i];
605
606 lvts_sensor[i].low_thresh = INT_MIN;
607 lvts_sensor[i].high_thresh = INT_MIN;
608 };
609
610 lvts_ctrl->num_lvts_sensor = lvts_ctrl_data->num_lvts_sensor;
611
612 return 0;
613 }
614
615 /*
616 * The efuse blob values follows the sensor enumeration per thermal
617 * controller. The decoding of the stream is as follow:
618 *
619 * MT8192 :
620 * Stream index map for MCU Domain mt8192 :
621 *
622 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
623 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B
624 *
625 * <-----sensor#2-----> <-----sensor#3----->
626 * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13
627 *
628 * <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
629 * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23
630 *
631 * Stream index map for AP Domain mt8192 :
632 *
633 * <-----sensor#0-----> <-----sensor#1----->
634 * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B
635 *
636 * <-----sensor#2-----> <-----sensor#3----->
637 * 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33
638 *
639 * <-----sensor#4-----> <-----sensor#5----->
640 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B
641 *
642 * <-----sensor#6-----> <-----sensor#7-----> <-----sensor#8----->
643 * 0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47
644 *
645 * MT8195 :
646 * Stream index map for MCU Domain mt8195 :
647 *
648 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
649 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09
650 *
651 * <-----mcu-tc#1-----> <-----sensor#2-----> <-----sensor#3----->
652 * 0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12
653 *
654 * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
655 * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21
656 *
657 * Stream index map for AP Domain mt8195 :
658 *
659 * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1----->
660 * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A
661 *
662 * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3----->
663 * 0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33
664 *
665 * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6----->
666 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F
667 *
668 * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8----->
669 * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48
670 *
671 * The data description gives the offset of the calibration data in
672 * this bytes stream for each sensor.
673 */
lvts_calibration_init(struct device * dev,struct lvts_ctrl * lvts_ctrl,const struct lvts_ctrl_data * lvts_ctrl_data,u8 * efuse_calibration)674 static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
675 const struct lvts_ctrl_data *lvts_ctrl_data,
676 u8 *efuse_calibration)
677 {
678 int i;
679
680 for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++)
681 memcpy(&lvts_ctrl->calibration[i],
682 efuse_calibration + lvts_ctrl_data->cal_offset[i], 2);
683
684 return 0;
685 }
686
687 /*
688 * The efuse bytes stream can be split into different chunk of
689 * nvmems. This function reads and concatenate those into a single
690 * buffer so it can be read sequentially when initializing the
691 * calibration data.
692 */
lvts_calibration_read(struct device * dev,struct lvts_domain * lvts_td,const struct lvts_data * lvts_data)693 static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td,
694 const struct lvts_data *lvts_data)
695 {
696 struct device_node *np = dev_of_node(dev);
697 struct nvmem_cell *cell;
698 struct property *prop;
699 const char *cell_name;
700
701 of_property_for_each_string(np, "nvmem-cell-names", prop, cell_name) {
702 size_t len;
703 u8 *efuse;
704
705 cell = of_nvmem_cell_get(np, cell_name);
706 if (IS_ERR(cell)) {
707 dev_err(dev, "Failed to get cell '%s'\n", cell_name);
708 return PTR_ERR(cell);
709 }
710
711 efuse = nvmem_cell_read(cell, &len);
712
713 nvmem_cell_put(cell);
714
715 if (IS_ERR(efuse)) {
716 dev_err(dev, "Failed to read cell '%s'\n", cell_name);
717 return PTR_ERR(efuse);
718 }
719
720 lvts_td->calib = devm_krealloc(dev, lvts_td->calib,
721 lvts_td->calib_len + len, GFP_KERNEL);
722 if (!lvts_td->calib)
723 return -ENOMEM;
724
725 memcpy(lvts_td->calib + lvts_td->calib_len, efuse, len);
726
727 lvts_td->calib_len += len;
728
729 kfree(efuse);
730 }
731
732 return 0;
733 }
734
lvts_golden_temp_init(struct device * dev,u32 * value,int temp_offset)735 static int lvts_golden_temp_init(struct device *dev, u32 *value, int temp_offset)
736 {
737 u32 gt;
738
739 gt = (*value) >> 24;
740
741 if (gt && gt < LVTS_GOLDEN_TEMP_MAX)
742 golden_temp = gt;
743
744 golden_temp_offset = golden_temp * 500 + temp_offset;
745
746 return 0;
747 }
748
lvts_ctrl_init(struct device * dev,struct lvts_domain * lvts_td,const struct lvts_data * lvts_data)749 static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td,
750 const struct lvts_data *lvts_data)
751 {
752 size_t size = sizeof(*lvts_td->lvts_ctrl) * lvts_data->num_lvts_ctrl;
753 struct lvts_ctrl *lvts_ctrl;
754 int i, ret;
755
756 /*
757 * Create the calibration bytes stream from efuse data
758 */
759 ret = lvts_calibration_read(dev, lvts_td, lvts_data);
760 if (ret)
761 return ret;
762
763 /*
764 * The golden temp information is contained in the first chunk
765 * of efuse data.
766 */
767 ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib, lvts_data->temp_offset);
768 if (ret)
769 return ret;
770
771 lvts_ctrl = devm_kzalloc(dev, size, GFP_KERNEL);
772 if (!lvts_ctrl)
773 return -ENOMEM;
774
775 for (i = 0; i < lvts_data->num_lvts_ctrl; i++) {
776
777 lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset;
778 lvts_ctrl[i].lvts_data = lvts_data;
779
780 ret = lvts_sensor_init(dev, &lvts_ctrl[i],
781 &lvts_data->lvts_ctrl[i]);
782 if (ret)
783 return ret;
784
785 ret = lvts_calibration_init(dev, &lvts_ctrl[i],
786 &lvts_data->lvts_ctrl[i],
787 lvts_td->calib);
788 if (ret)
789 return ret;
790
791 /*
792 * The mode the ctrl will use to read the temperature
793 * (filtered or immediate)
794 */
795 lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode;
796
797 /*
798 * The temperature to raw temperature must be done
799 * after initializing the calibration.
800 */
801 lvts_ctrl[i].hw_tshut_raw_temp =
802 lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp,
803 lvts_data->temp_factor);
804
805 lvts_ctrl[i].low_thresh = INT_MIN;
806 lvts_ctrl[i].high_thresh = INT_MIN;
807 }
808
809 /*
810 * We no longer need the efuse bytes stream, let's free it
811 */
812 devm_kfree(dev, lvts_td->calib);
813
814 lvts_td->lvts_ctrl = lvts_ctrl;
815 lvts_td->num_lvts_ctrl = lvts_data->num_lvts_ctrl;
816
817 return 0;
818 }
819
820 /*
821 * At this point the configuration register is the only place in the
822 * driver where we write multiple values. Per hardware constraint,
823 * each write in the configuration register must be separated by a
824 * delay of 2 us.
825 */
lvts_write_config(struct lvts_ctrl * lvts_ctrl,u32 * cmds,int nr_cmds)826 static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int nr_cmds)
827 {
828 int i;
829
830 /*
831 * Configuration register
832 */
833 for (i = 0; i < nr_cmds; i++) {
834 writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base));
835 usleep_range(2, 4);
836 }
837 }
838
lvts_irq_init(struct lvts_ctrl * lvts_ctrl)839 static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl)
840 {
841 /*
842 * LVTS_PROTCTL : Thermal Protection Sensor Selection
843 *
844 * Bits:
845 *
846 * 19-18 : Sensor to base the protection on
847 * 17-16 : Strategy:
848 * 00 : Average of 4 sensors
849 * 01 : Max of 4 sensors
850 * 10 : Selected sensor with bits 19-18
851 * 11 : Reserved
852 */
853 writel(BIT(16), LVTS_PROTCTL(lvts_ctrl->base));
854
855 /*
856 * LVTS_PROTTA : Stage 1 temperature threshold
857 * LVTS_PROTTB : Stage 2 temperature threshold
858 * LVTS_PROTTC : Stage 3 temperature threshold
859 *
860 * Bits:
861 *
862 * 14-0: Raw temperature threshold
863 *
864 * writel(0x0, LVTS_PROTTA(lvts_ctrl->base));
865 * writel(0x0, LVTS_PROTTB(lvts_ctrl->base));
866 */
867 writel(lvts_ctrl->hw_tshut_raw_temp, LVTS_PROTTC(lvts_ctrl->base));
868
869 /*
870 * LVTS_MONINT : Interrupt configuration register
871 *
872 * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS
873 * register, except we set the bits to enable the interrupt.
874 */
875 writel(LVTS_MONINT_CONF, LVTS_MONINT(lvts_ctrl->base));
876
877 return 0;
878 }
879
lvts_domain_reset(struct device * dev,struct reset_control * reset)880 static int lvts_domain_reset(struct device *dev, struct reset_control *reset)
881 {
882 int ret;
883
884 ret = reset_control_assert(reset);
885 if (ret)
886 return ret;
887
888 return reset_control_deassert(reset);
889 }
890
891 /*
892 * Enable or disable the clocks of a specified thermal controller
893 */
lvts_ctrl_set_enable(struct lvts_ctrl * lvts_ctrl,int enable)894 static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable)
895 {
896 /*
897 * LVTS_CLKEN : Internal LVTS clock
898 *
899 * Bits:
900 *
901 * 0 : enable / disable clock
902 */
903 writel(enable, LVTS_CLKEN(lvts_ctrl->base));
904
905 return 0;
906 }
907
lvts_ctrl_connect(struct device * dev,struct lvts_ctrl * lvts_ctrl)908 static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl)
909 {
910 u32 id, cmds[] = { 0xC103FFFF, 0xC502FF55 };
911
912 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds));
913
914 /*
915 * LVTS_ID : Get ID and status of the thermal controller
916 *
917 * Bits:
918 *
919 * 0-5 : thermal controller id
920 * 7 : thermal controller connection is valid
921 */
922 id = readl(LVTS_ID(lvts_ctrl->base));
923 if (!(id & BIT(7)))
924 return -EIO;
925
926 return 0;
927 }
928
lvts_ctrl_initialize(struct device * dev,struct lvts_ctrl * lvts_ctrl)929 static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl)
930 {
931 /*
932 * Write device mask: 0xC1030000
933 */
934 u32 cmds[] = {
935 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1,
936 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300,
937 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC,
938 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1
939 };
940
941 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds));
942
943 return 0;
944 }
945
lvts_ctrl_calibrate(struct device * dev,struct lvts_ctrl * lvts_ctrl)946 static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl)
947 {
948 int i;
949 void __iomem *lvts_edata[] = {
950 LVTS_EDATA00(lvts_ctrl->base),
951 LVTS_EDATA01(lvts_ctrl->base),
952 LVTS_EDATA02(lvts_ctrl->base),
953 LVTS_EDATA03(lvts_ctrl->base)
954 };
955
956 /*
957 * LVTS_EDATA0X : Efuse calibration reference value for sensor X
958 *
959 * Bits:
960 *
961 * 20-0 : Efuse value for normalization data
962 */
963 for (i = 0; i < LVTS_SENSOR_MAX; i++)
964 writel(lvts_ctrl->calibration[i], lvts_edata[i]);
965
966 return 0;
967 }
968
lvts_ctrl_configure(struct device * dev,struct lvts_ctrl * lvts_ctrl)969 static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl)
970 {
971 u32 value;
972
973 /*
974 * LVTS_TSSEL : Sensing point index numbering
975 *
976 * Bits:
977 *
978 * 31-24: ADC Sense 3
979 * 23-16: ADC Sense 2
980 * 15-8 : ADC Sense 1
981 * 7-0 : ADC Sense 0
982 */
983 value = LVTS_TSSEL_CONF;
984 writel(value, LVTS_TSSEL(lvts_ctrl->base));
985
986 /*
987 * LVTS_CALSCALE : ADC voltage round
988 */
989 value = 0x300;
990 value = LVTS_CALSCALE_CONF;
991
992 /*
993 * LVTS_MSRCTL0 : Sensor filtering strategy
994 *
995 * Filters:
996 *
997 * 000 : One sample
998 * 001 : Avg 2 samples
999 * 010 : 4 samples, drop min and max, avg 2 samples
1000 * 011 : 6 samples, drop min and max, avg 4 samples
1001 * 100 : 10 samples, drop min and max, avg 8 samples
1002 * 101 : 18 samples, drop min and max, avg 16 samples
1003 *
1004 * Bits:
1005 *
1006 * 0-2 : Sensor0 filter
1007 * 3-5 : Sensor1 filter
1008 * 6-8 : Sensor2 filter
1009 * 9-11 : Sensor3 filter
1010 */
1011 value = LVTS_HW_FILTER << 9 | LVTS_HW_FILTER << 6 |
1012 LVTS_HW_FILTER << 3 | LVTS_HW_FILTER;
1013 writel(value, LVTS_MSRCTL0(lvts_ctrl->base));
1014
1015 /*
1016 * LVTS_MONCTL1 : Period unit and group interval configuration
1017 *
1018 * The clock source of LVTS thermal controller is 26MHz.
1019 *
1020 * The period unit is a time base for all the interval delays
1021 * specified in the registers. By default we use 12. The time
1022 * conversion is done by multiplying by 256 and 1/26.10^6
1023 *
1024 * An interval delay multiplied by the period unit gives the
1025 * duration in seconds.
1026 *
1027 * - Filter interval delay is a delay between two samples of
1028 * the same sensor.
1029 *
1030 * - Sensor interval delay is a delay between two samples of
1031 * different sensors.
1032 *
1033 * - Group interval delay is a delay between different rounds.
1034 *
1035 * For example:
1036 * If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1,
1037 * and two sensors, TS1 and TS2, are in a LVTS thermal controller
1038 * and then
1039 * Period unit time = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us
1040 * Filter interval delay = 1 * Period unit = 118.149us
1041 * Sensor interval delay = 2 * Period unit = 236.298us
1042 * Group interval delay = 1 * Period unit = 118.149us
1043 *
1044 * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1...
1045 * <--> Filter interval delay
1046 * <--> Sensor interval delay
1047 * <--> Group interval delay
1048 * Bits:
1049 * 29 - 20 : Group interval
1050 * 16 - 13 : Send a single interrupt when crossing the hot threshold (1)
1051 * or an interrupt everytime the hot threshold is crossed (0)
1052 * 9 - 0 : Period unit
1053 *
1054 */
1055 value = LVTS_GROUP_INTERVAL << 20 | LVTS_PERIOD_UNIT;
1056 writel(value, LVTS_MONCTL1(lvts_ctrl->base));
1057
1058 /*
1059 * LVTS_MONCTL2 : Filtering and sensor interval
1060 *
1061 * Bits:
1062 *
1063 * 25-16 : Interval unit in PERIOD_UNIT between sample on
1064 * the same sensor, filter interval
1065 * 9-0 : Interval unit in PERIOD_UNIT between each sensor
1066 *
1067 */
1068 value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL;
1069 writel(value, LVTS_MONCTL2(lvts_ctrl->base));
1070
1071 return lvts_irq_init(lvts_ctrl);
1072 }
1073
lvts_ctrl_start(struct device * dev,struct lvts_ctrl * lvts_ctrl)1074 static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl)
1075 {
1076 struct lvts_sensor *lvts_sensors = lvts_ctrl->sensors;
1077 struct thermal_zone_device *tz;
1078 u32 sensor_map = 0;
1079 int i;
1080 /*
1081 * Bitmaps to enable each sensor on immediate and filtered modes, as
1082 * described in MSRCTL1 and MONCTL0 registers below, respectively.
1083 */
1084 u32 sensor_imm_bitmap[] = { BIT(4), BIT(5), BIT(6), BIT(9) };
1085 u32 sensor_filt_bitmap[] = { BIT(0), BIT(1), BIT(2), BIT(3) };
1086
1087 u32 *sensor_bitmap = lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE ?
1088 sensor_imm_bitmap : sensor_filt_bitmap;
1089
1090 for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) {
1091
1092 int dt_id = lvts_sensors[i].dt_id;
1093
1094 tz = devm_thermal_of_zone_register(dev, dt_id, &lvts_sensors[i],
1095 &lvts_ops);
1096 if (IS_ERR(tz)) {
1097 /*
1098 * This thermal zone is not described in the
1099 * device tree. It is not an error from the
1100 * thermal OF code POV, we just continue.
1101 */
1102 if (PTR_ERR(tz) == -ENODEV)
1103 continue;
1104
1105 return PTR_ERR(tz);
1106 }
1107
1108 devm_thermal_add_hwmon_sysfs(dev, tz);
1109
1110 /*
1111 * The thermal zone pointer will be needed in the
1112 * interrupt handler, we store it in the sensor
1113 * structure. The thermal domain structure will be
1114 * passed to the interrupt handler private data as the
1115 * interrupt is shared for all the controller
1116 * belonging to the thermal domain.
1117 */
1118 lvts_sensors[i].tz = tz;
1119
1120 /*
1121 * This sensor was correctly associated with a thermal
1122 * zone, let's set the corresponding bit in the sensor
1123 * map, so we can enable the temperature monitoring in
1124 * the hardware thermal controller.
1125 */
1126 sensor_map |= sensor_bitmap[i];
1127 }
1128
1129 /*
1130 * The initialization of the thermal zones give us
1131 * which sensor point to enable. If any thermal zone
1132 * was not described in the device tree, it won't be
1133 * enabled here in the sensor map.
1134 */
1135 if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) {
1136 /*
1137 * LVTS_MSRCTL1 : Measurement control
1138 *
1139 * Bits:
1140 *
1141 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3
1142 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2
1143 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1
1144 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0
1145 *
1146 * That configuration will ignore the filtering and the delays
1147 * introduced in MONCTL1 and MONCTL2
1148 */
1149 writel(sensor_map, LVTS_MSRCTL1(lvts_ctrl->base));
1150 } else {
1151 /*
1152 * Bits:
1153 * 9: Single point access flow
1154 * 0-3: Enable sensing point 0-3
1155 */
1156 writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base));
1157 }
1158
1159 return 0;
1160 }
1161
lvts_domain_init(struct device * dev,struct lvts_domain * lvts_td,const struct lvts_data * lvts_data)1162 static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td,
1163 const struct lvts_data *lvts_data)
1164 {
1165 struct lvts_ctrl *lvts_ctrl;
1166 int i, ret;
1167
1168 ret = lvts_ctrl_init(dev, lvts_td, lvts_data);
1169 if (ret)
1170 return ret;
1171
1172 ret = lvts_domain_reset(dev, lvts_td->reset);
1173 if (ret) {
1174 dev_dbg(dev, "Failed to reset domain");
1175 return ret;
1176 }
1177
1178 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
1179
1180 lvts_ctrl = &lvts_td->lvts_ctrl[i];
1181
1182 /*
1183 * Initialization steps:
1184 *
1185 * - Enable the clock
1186 * - Connect to the LVTS
1187 * - Initialize the LVTS
1188 * - Prepare the calibration data
1189 * - Select monitored sensors
1190 * [ Configure sampling ]
1191 * [ Configure the interrupt ]
1192 * - Start measurement
1193 */
1194 ret = lvts_ctrl_set_enable(lvts_ctrl, true);
1195 if (ret) {
1196 dev_dbg(dev, "Failed to enable LVTS clock");
1197 return ret;
1198 }
1199
1200 ret = lvts_ctrl_connect(dev, lvts_ctrl);
1201 if (ret) {
1202 dev_dbg(dev, "Failed to connect to LVTS controller");
1203 return ret;
1204 }
1205
1206 ret = lvts_ctrl_initialize(dev, lvts_ctrl);
1207 if (ret) {
1208 dev_dbg(dev, "Failed to initialize controller");
1209 return ret;
1210 }
1211
1212 ret = lvts_ctrl_calibrate(dev, lvts_ctrl);
1213 if (ret) {
1214 dev_dbg(dev, "Failed to calibrate controller");
1215 return ret;
1216 }
1217
1218 ret = lvts_ctrl_configure(dev, lvts_ctrl);
1219 if (ret) {
1220 dev_dbg(dev, "Failed to configure controller");
1221 return ret;
1222 }
1223
1224 ret = lvts_ctrl_start(dev, lvts_ctrl);
1225 if (ret) {
1226 dev_dbg(dev, "Failed to start controller");
1227 return ret;
1228 }
1229 }
1230
1231 return lvts_debugfs_init(dev, lvts_td);
1232 }
1233
lvts_probe(struct platform_device * pdev)1234 static int lvts_probe(struct platform_device *pdev)
1235 {
1236 const struct lvts_data *lvts_data;
1237 struct lvts_domain *lvts_td;
1238 struct device *dev = &pdev->dev;
1239 struct resource *res;
1240 int irq, ret;
1241
1242 lvts_td = devm_kzalloc(dev, sizeof(*lvts_td), GFP_KERNEL);
1243 if (!lvts_td)
1244 return -ENOMEM;
1245
1246 lvts_data = of_device_get_match_data(dev);
1247
1248 lvts_td->clk = devm_clk_get_enabled(dev, NULL);
1249 if (IS_ERR(lvts_td->clk))
1250 return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n");
1251
1252 res = platform_get_mem_or_io(pdev, 0);
1253 if (!res)
1254 return dev_err_probe(dev, (-ENXIO), "No IO resource\n");
1255
1256 lvts_td->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1257 if (IS_ERR(lvts_td->base))
1258 return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n");
1259
1260 lvts_td->reset = devm_reset_control_get_by_index(dev, 0);
1261 if (IS_ERR(lvts_td->reset))
1262 return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n");
1263
1264 irq = platform_get_irq(pdev, 0);
1265 if (irq < 0)
1266 return irq;
1267
1268 golden_temp_offset = lvts_data->temp_offset;
1269
1270 ret = lvts_domain_init(dev, lvts_td, lvts_data);
1271 if (ret)
1272 return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n");
1273
1274 /*
1275 * At this point the LVTS is initialized and enabled. We can
1276 * safely enable the interrupt.
1277 */
1278 ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler,
1279 IRQF_ONESHOT, dev_name(dev), lvts_td);
1280 if (ret)
1281 return dev_err_probe(dev, ret, "Failed to request interrupt\n");
1282
1283 platform_set_drvdata(pdev, lvts_td);
1284
1285 return 0;
1286 }
1287
lvts_remove(struct platform_device * pdev)1288 static void lvts_remove(struct platform_device *pdev)
1289 {
1290 struct lvts_domain *lvts_td;
1291 int i;
1292
1293 lvts_td = platform_get_drvdata(pdev);
1294
1295 for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
1296 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
1297
1298 lvts_debugfs_exit(lvts_td);
1299 }
1300
1301 static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = {
1302 {
1303 .cal_offset = { 0x00, 0x04, 0x08, 0x0c },
1304 .lvts_sensor = {
1305 { .dt_id = MT7988_CPU_0 },
1306 { .dt_id = MT7988_CPU_1 },
1307 { .dt_id = MT7988_ETH2P5G_0 },
1308 { .dt_id = MT7988_ETH2P5G_1 }
1309 },
1310 .num_lvts_sensor = 4,
1311 .offset = 0x0,
1312 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988,
1313 },
1314 {
1315 .cal_offset = { 0x14, 0x18, 0x1c, 0x20 },
1316 .lvts_sensor = {
1317 { .dt_id = MT7988_TOPS_0},
1318 { .dt_id = MT7988_TOPS_1},
1319 { .dt_id = MT7988_ETHWARP_0},
1320 { .dt_id = MT7988_ETHWARP_1}
1321 },
1322 .num_lvts_sensor = 4,
1323 .offset = 0x100,
1324 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988,
1325 }
1326 };
1327
lvts_suspend(struct device * dev)1328 static int lvts_suspend(struct device *dev)
1329 {
1330 struct lvts_domain *lvts_td;
1331 int i;
1332
1333 lvts_td = dev_get_drvdata(dev);
1334
1335 for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
1336 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
1337
1338 clk_disable_unprepare(lvts_td->clk);
1339
1340 return 0;
1341 }
1342
lvts_resume(struct device * dev)1343 static int lvts_resume(struct device *dev)
1344 {
1345 struct lvts_domain *lvts_td;
1346 int i, ret;
1347
1348 lvts_td = dev_get_drvdata(dev);
1349
1350 ret = clk_prepare_enable(lvts_td->clk);
1351 if (ret)
1352 return ret;
1353
1354 for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
1355 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true);
1356
1357 return 0;
1358 }
1359
1360 static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = {
1361 {
1362 .cal_offset = { 0x04, 0x08 },
1363 .lvts_sensor = {
1364 { .dt_id = MT8192_MCU_BIG_CPU0 },
1365 { .dt_id = MT8192_MCU_BIG_CPU1 }
1366 },
1367 .num_lvts_sensor = 2,
1368 .offset = 0x0,
1369 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
1370 .mode = LVTS_MSR_FILTERED_MODE,
1371 },
1372 {
1373 .cal_offset = { 0x0c, 0x10 },
1374 .lvts_sensor = {
1375 { .dt_id = MT8192_MCU_BIG_CPU2 },
1376 { .dt_id = MT8192_MCU_BIG_CPU3 }
1377 },
1378 .num_lvts_sensor = 2,
1379 .offset = 0x100,
1380 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
1381 .mode = LVTS_MSR_FILTERED_MODE,
1382 },
1383 {
1384 .cal_offset = { 0x14, 0x18, 0x1c, 0x20 },
1385 .lvts_sensor = {
1386 { .dt_id = MT8192_MCU_LITTLE_CPU0 },
1387 { .dt_id = MT8192_MCU_LITTLE_CPU1 },
1388 { .dt_id = MT8192_MCU_LITTLE_CPU2 },
1389 { .dt_id = MT8192_MCU_LITTLE_CPU3 }
1390 },
1391 .num_lvts_sensor = 4,
1392 .offset = 0x200,
1393 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
1394 .mode = LVTS_MSR_FILTERED_MODE,
1395 }
1396 };
1397
1398 static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = {
1399 {
1400 .cal_offset = { 0x24, 0x28 },
1401 .lvts_sensor = {
1402 { .dt_id = MT8192_AP_VPU0 },
1403 { .dt_id = MT8192_AP_VPU1 }
1404 },
1405 .num_lvts_sensor = 2,
1406 .offset = 0x0,
1407 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
1408 },
1409 {
1410 .cal_offset = { 0x2c, 0x30 },
1411 .lvts_sensor = {
1412 { .dt_id = MT8192_AP_GPU0 },
1413 { .dt_id = MT8192_AP_GPU1 }
1414 },
1415 .num_lvts_sensor = 2,
1416 .offset = 0x100,
1417 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
1418 },
1419 {
1420 .cal_offset = { 0x34, 0x38 },
1421 .lvts_sensor = {
1422 { .dt_id = MT8192_AP_INFRA },
1423 { .dt_id = MT8192_AP_CAM },
1424 },
1425 .num_lvts_sensor = 2,
1426 .offset = 0x200,
1427 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
1428 },
1429 {
1430 .cal_offset = { 0x3c, 0x40, 0x44 },
1431 .lvts_sensor = {
1432 { .dt_id = MT8192_AP_MD0 },
1433 { .dt_id = MT8192_AP_MD1 },
1434 { .dt_id = MT8192_AP_MD2 }
1435 },
1436 .num_lvts_sensor = 3,
1437 .offset = 0x300,
1438 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
1439 }
1440 };
1441
1442 static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
1443 {
1444 .cal_offset = { 0x04, 0x07 },
1445 .lvts_sensor = {
1446 { .dt_id = MT8195_MCU_BIG_CPU0 },
1447 { .dt_id = MT8195_MCU_BIG_CPU1 }
1448 },
1449 .num_lvts_sensor = 2,
1450 .offset = 0x0,
1451 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
1452 },
1453 {
1454 .cal_offset = { 0x0d, 0x10 },
1455 .lvts_sensor = {
1456 { .dt_id = MT8195_MCU_BIG_CPU2 },
1457 { .dt_id = MT8195_MCU_BIG_CPU3 }
1458 },
1459 .num_lvts_sensor = 2,
1460 .offset = 0x100,
1461 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
1462 },
1463 {
1464 .cal_offset = { 0x16, 0x19, 0x1c, 0x1f },
1465 .lvts_sensor = {
1466 { .dt_id = MT8195_MCU_LITTLE_CPU0 },
1467 { .dt_id = MT8195_MCU_LITTLE_CPU1 },
1468 { .dt_id = MT8195_MCU_LITTLE_CPU2 },
1469 { .dt_id = MT8195_MCU_LITTLE_CPU3 }
1470 },
1471 .num_lvts_sensor = 4,
1472 .offset = 0x200,
1473 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
1474 }
1475 };
1476
1477 static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = {
1478 {
1479 .cal_offset = { 0x25, 0x28 },
1480 .lvts_sensor = {
1481 { .dt_id = MT8195_AP_VPU0 },
1482 { .dt_id = MT8195_AP_VPU1 }
1483 },
1484 .num_lvts_sensor = 2,
1485 .offset = 0x0,
1486 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
1487 },
1488 {
1489 .cal_offset = { 0x2e, 0x31 },
1490 .lvts_sensor = {
1491 { .dt_id = MT8195_AP_GPU0 },
1492 { .dt_id = MT8195_AP_GPU1 }
1493 },
1494 .num_lvts_sensor = 2,
1495 .offset = 0x100,
1496 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
1497 },
1498 {
1499 .cal_offset = { 0x37, 0x3a, 0x3d },
1500 .lvts_sensor = {
1501 { .dt_id = MT8195_AP_VDEC },
1502 { .dt_id = MT8195_AP_IMG },
1503 { .dt_id = MT8195_AP_INFRA },
1504 },
1505 .num_lvts_sensor = 3,
1506 .offset = 0x200,
1507 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
1508 },
1509 {
1510 .cal_offset = { 0x43, 0x46 },
1511 .lvts_sensor = {
1512 { .dt_id = MT8195_AP_CAM0 },
1513 { .dt_id = MT8195_AP_CAM1 }
1514 },
1515 .num_lvts_sensor = 2,
1516 .offset = 0x300,
1517 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
1518 }
1519 };
1520
1521 static const struct lvts_data mt7988_lvts_ap_data = {
1522 .lvts_ctrl = mt7988_lvts_ap_data_ctrl,
1523 .num_lvts_ctrl = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl),
1524 .temp_factor = LVTS_COEFF_A_MT7988,
1525 .temp_offset = LVTS_COEFF_B_MT7988,
1526 };
1527
1528 static const struct lvts_data mt8192_lvts_mcu_data = {
1529 .lvts_ctrl = mt8192_lvts_mcu_data_ctrl,
1530 .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl),
1531 };
1532
1533 static const struct lvts_data mt8192_lvts_ap_data = {
1534 .lvts_ctrl = mt8192_lvts_ap_data_ctrl,
1535 .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl),
1536 };
1537
1538 static const struct lvts_data mt8195_lvts_mcu_data = {
1539 .lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
1540 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
1541 .temp_factor = LVTS_COEFF_A_MT8195,
1542 .temp_offset = LVTS_COEFF_B_MT8195,
1543 };
1544
1545 static const struct lvts_data mt8195_lvts_ap_data = {
1546 .lvts_ctrl = mt8195_lvts_ap_data_ctrl,
1547 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
1548 .temp_factor = LVTS_COEFF_A_MT8195,
1549 .temp_offset = LVTS_COEFF_B_MT8195,
1550 };
1551
1552 static const struct of_device_id lvts_of_match[] = {
1553 { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data },
1554 { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data },
1555 { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data },
1556 { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
1557 { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
1558 {},
1559 };
1560 MODULE_DEVICE_TABLE(of, lvts_of_match);
1561
1562 static const struct dev_pm_ops lvts_pm_ops = {
1563 NOIRQ_SYSTEM_SLEEP_PM_OPS(lvts_suspend, lvts_resume)
1564 };
1565
1566 static struct platform_driver lvts_driver = {
1567 .probe = lvts_probe,
1568 .remove_new = lvts_remove,
1569 .driver = {
1570 .name = "mtk-lvts-thermal",
1571 .of_match_table = lvts_of_match,
1572 .pm = &lvts_pm_ops,
1573 },
1574 };
1575 module_platform_driver(lvts_driver);
1576
1577 MODULE_AUTHOR("Balsam CHIHI <bchihi@baylibre.com>");
1578 MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver");
1579 MODULE_LICENSE("GPL");
1580