1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * drivers/soc/tegra/pmc.c
4 *
5 * Copyright (c) 2010 Google, Inc
6 * Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
7 *
8 * Author:
9 * Colin Cross <ccross@google.com>
10 */
11
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
13
14 #include <linux/arm-smccc.h>
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/clkdev.h>
18 #include <linux/clk/clk-conf.h>
19 #include <linux/clk/tegra.h>
20 #include <linux/debugfs.h>
21 #include <linux/delay.h>
22 #include <linux/device.h>
23 #include <linux/err.h>
24 #include <linux/export.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/io.h>
28 #include <linux/iopoll.h>
29 #include <linux/irqdomain.h>
30 #include <linux/irq.h>
31 #include <linux/kernel.h>
32 #include <linux/of_address.h>
33 #include <linux/of_clk.h>
34 #include <linux/of.h>
35 #include <linux/of_irq.h>
36 #include <linux/of_platform.h>
37 #include <linux/pinctrl/pinconf-generic.h>
38 #include <linux/pinctrl/pinconf.h>
39 #include <linux/pinctrl/pinctrl.h>
40 #include <linux/platform_device.h>
41 #include <linux/pm_domain.h>
42 #include <linux/pm_opp.h>
43 #include <linux/power_supply.h>
44 #include <linux/reboot.h>
45 #include <linux/regmap.h>
46 #include <linux/reset.h>
47 #include <linux/seq_file.h>
48 #include <linux/slab.h>
49 #include <linux/spinlock.h>
50 #include <linux/syscore_ops.h>
51
52 #include <soc/tegra/common.h>
53 #include <soc/tegra/fuse.h>
54 #include <soc/tegra/pmc.h>
55
56 #include <dt-bindings/interrupt-controller/arm-gic.h>
57 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
58 #include <dt-bindings/gpio/tegra186-gpio.h>
59 #include <dt-bindings/gpio/tegra194-gpio.h>
60 #include <dt-bindings/gpio/tegra234-gpio.h>
61 #include <dt-bindings/soc/tegra-pmc.h>
62
63 #define PMC_CNTRL 0x0
64 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
65 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
66 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */
67 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
68 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
69 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
70 #define PMC_CNTRL_PWRREQ_POLARITY BIT(8)
71 #define PMC_CNTRL_BLINK_EN 7
72 #define PMC_CNTRL_MAIN_RST BIT(4)
73
74 #define PMC_WAKE_MASK 0x0c
75 #define PMC_WAKE_LEVEL 0x10
76 #define PMC_WAKE_STATUS 0x14
77 #define PMC_SW_WAKE_STATUS 0x18
78 #define PMC_DPD_PADS_ORIDE 0x1c
79 #define PMC_DPD_PADS_ORIDE_BLINK 20
80
81 #define DPD_SAMPLE 0x020
82 #define DPD_SAMPLE_ENABLE BIT(0)
83 #define DPD_SAMPLE_DISABLE (0 << 0)
84
85 #define PWRGATE_TOGGLE 0x30
86 #define PWRGATE_TOGGLE_START BIT(8)
87
88 #define REMOVE_CLAMPING 0x34
89
90 #define PWRGATE_STATUS 0x38
91
92 #define PMC_BLINK_TIMER 0x40
93 #define PMC_IMPL_E_33V_PWR 0x40
94
95 #define PMC_PWR_DET 0x48
96
97 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
98 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
99 #define PMC_SCRATCH0_MODE_RCM BIT(1)
100 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
101 PMC_SCRATCH0_MODE_BOOTLOADER | \
102 PMC_SCRATCH0_MODE_RCM)
103
104 #define PMC_CPUPWRGOOD_TIMER 0xc8
105 #define PMC_CPUPWROFF_TIMER 0xcc
106 #define PMC_COREPWRGOOD_TIMER 0x3c
107 #define PMC_COREPWROFF_TIMER 0xe0
108
109 #define PMC_PWR_DET_VALUE 0xe4
110
111 #define PMC_USB_DEBOUNCE_DEL 0xec
112 #define PMC_USB_AO 0xf0
113
114 #define PMC_SCRATCH37 0x130
115 #define PMC_SCRATCH41 0x140
116
117 #define PMC_WAKE2_MASK 0x160
118 #define PMC_WAKE2_LEVEL 0x164
119 #define PMC_WAKE2_STATUS 0x168
120 #define PMC_SW_WAKE2_STATUS 0x16c
121
122 #define PMC_CLK_OUT_CNTRL 0x1a8
123 #define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0)
124 #define PMC_SENSOR_CTRL 0x1b0
125 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
126 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
127
128 #define PMC_RST_STATUS_POR 0
129 #define PMC_RST_STATUS_WATCHDOG 1
130 #define PMC_RST_STATUS_SENSOR 2
131 #define PMC_RST_STATUS_SW_MAIN 3
132 #define PMC_RST_STATUS_LP0 4
133 #define PMC_RST_STATUS_AOTAG 5
134
135 #define IO_DPD_REQ 0x1b8
136 #define IO_DPD_REQ_CODE_IDLE (0U << 30)
137 #define IO_DPD_REQ_CODE_OFF (1U << 30)
138 #define IO_DPD_REQ_CODE_ON (2U << 30)
139 #define IO_DPD_REQ_CODE_MASK (3U << 30)
140
141 #define IO_DPD_STATUS 0x1bc
142 #define IO_DPD2_REQ 0x1c0
143 #define IO_DPD2_STATUS 0x1c4
144 #define SEL_DPD_TIM 0x1c8
145
146 #define PMC_UTMIP_UHSIC_TRIGGERS 0x1ec
147 #define PMC_UTMIP_UHSIC_SAVED_STATE 0x1f0
148
149 #define PMC_UTMIP_TERM_PAD_CFG 0x1f8
150 #define PMC_UTMIP_UHSIC_SLEEP_CFG 0x1fc
151 #define PMC_UTMIP_UHSIC_FAKE 0x218
152
153 #define PMC_SCRATCH54 0x258
154 #define PMC_SCRATCH54_DATA_SHIFT 8
155 #define PMC_SCRATCH54_ADDR_SHIFT 0
156
157 #define PMC_SCRATCH55 0x25c
158 #define PMC_SCRATCH55_RESET_TEGRA BIT(31)
159 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
160 #define PMC_SCRATCH55_PINMUX_SHIFT 24
161 #define PMC_SCRATCH55_16BITOP BIT(15)
162 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16
163 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
164
165 #define PMC_UTMIP_UHSIC_LINE_WAKEUP 0x26c
166
167 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x270
168 #define PMC_UTMIP_MASTER_CONFIG 0x274
169 #define PMC_UTMIP_UHSIC2_TRIGGERS 0x27c
170 #define PMC_UTMIP_MASTER2_CONFIG 0x29c
171
172 #define GPU_RG_CNTRL 0x2d4
173
174 #define PMC_UTMIP_PAD_CFG0 0x4c0
175 #define PMC_UTMIP_UHSIC_SLEEP_CFG1 0x4d0
176 #define PMC_UTMIP_SLEEPWALK_P3 0x4e0
177 /* Tegra186 and later */
178 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2))
179 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3)
180 #define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN (1 << 1)
181 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2))
182 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2))
183 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2))
184 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2))
185 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2))
186 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2))
187 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2))
188 #define WAKE_AOWAKE_SW_STATUS_W_0 0x49c
189 #define WAKE_AOWAKE_SW_STATUS(x) (0x4a0 + ((x) << 2))
190 #define WAKE_LATCH_SW 0x498
191
192 #define WAKE_AOWAKE_CTRL 0x4f4
193 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
194
195 #define SW_WAKE_ID 83 /* wake83 */
196
197 /* for secure PMC */
198 #define TEGRA_SMC_PMC 0xc2fffe00
199 #define TEGRA_SMC_PMC_READ 0xaa
200 #define TEGRA_SMC_PMC_WRITE 0xbb
201
202 struct pmc_clk {
203 struct clk_hw hw;
204 unsigned long offs;
205 u32 mux_shift;
206 u32 force_en_shift;
207 };
208
209 #define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
210
211 struct pmc_clk_gate {
212 struct clk_hw hw;
213 unsigned long offs;
214 u32 shift;
215 };
216
217 #define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw)
218
219 struct pmc_clk_init_data {
220 char *name;
221 const char *const *parents;
222 int num_parents;
223 int clk_id;
224 u8 mux_shift;
225 u8 force_en_shift;
226 };
227
228 static const char * const clk_out1_parents[] = { "osc", "osc_div2",
229 "osc_div4", "extern1",
230 };
231
232 static const char * const clk_out2_parents[] = { "osc", "osc_div2",
233 "osc_div4", "extern2",
234 };
235
236 static const char * const clk_out3_parents[] = { "osc", "osc_div2",
237 "osc_div4", "extern3",
238 };
239
240 static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
241 {
242 .name = "pmc_clk_out_1",
243 .parents = clk_out1_parents,
244 .num_parents = ARRAY_SIZE(clk_out1_parents),
245 .clk_id = TEGRA_PMC_CLK_OUT_1,
246 .mux_shift = 6,
247 .force_en_shift = 2,
248 },
249 {
250 .name = "pmc_clk_out_2",
251 .parents = clk_out2_parents,
252 .num_parents = ARRAY_SIZE(clk_out2_parents),
253 .clk_id = TEGRA_PMC_CLK_OUT_2,
254 .mux_shift = 14,
255 .force_en_shift = 10,
256 },
257 {
258 .name = "pmc_clk_out_3",
259 .parents = clk_out3_parents,
260 .num_parents = ARRAY_SIZE(clk_out3_parents),
261 .clk_id = TEGRA_PMC_CLK_OUT_3,
262 .mux_shift = 22,
263 .force_en_shift = 18,
264 },
265 };
266
267 struct tegra_powergate {
268 struct generic_pm_domain genpd;
269 struct tegra_pmc *pmc;
270 unsigned int id;
271 struct clk **clks;
272 unsigned int num_clks;
273 unsigned long *clk_rates;
274 struct reset_control *reset;
275 };
276
277 struct tegra_io_pad_soc {
278 enum tegra_io_pad id;
279 unsigned int dpd;
280 unsigned int request;
281 unsigned int status;
282 unsigned int voltage;
283 const char *name;
284 };
285
286 struct tegra_pmc_regs {
287 unsigned int scratch0;
288 unsigned int rst_status;
289 unsigned int rst_source_shift;
290 unsigned int rst_source_mask;
291 unsigned int rst_level_shift;
292 unsigned int rst_level_mask;
293 };
294
295 struct tegra_wake_event {
296 const char *name;
297 unsigned int id;
298 unsigned int irq;
299 struct {
300 unsigned int instance;
301 unsigned int pin;
302 } gpio;
303 };
304
305 #define TEGRA_WAKE_SIMPLE(_name, _id) \
306 { \
307 .name = _name, \
308 .id = _id, \
309 .irq = 0, \
310 .gpio = { \
311 .instance = UINT_MAX, \
312 .pin = UINT_MAX, \
313 }, \
314 }
315
316 #define TEGRA_WAKE_IRQ(_name, _id, _irq) \
317 { \
318 .name = _name, \
319 .id = _id, \
320 .irq = _irq, \
321 .gpio = { \
322 .instance = UINT_MAX, \
323 .pin = UINT_MAX, \
324 }, \
325 }
326
327 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \
328 { \
329 .name = _name, \
330 .id = _id, \
331 .irq = 0, \
332 .gpio = { \
333 .instance = _instance, \
334 .pin = _pin, \
335 }, \
336 }
337
338 struct tegra_pmc_soc {
339 unsigned int num_powergates;
340 const char *const *powergates;
341 unsigned int num_cpu_powergates;
342 const u8 *cpu_powergates;
343
344 bool has_tsense_reset;
345 bool has_gpu_clamps;
346 bool needs_mbist_war;
347 bool has_impl_33v_pwr;
348 bool maybe_tz_only;
349
350 const struct tegra_io_pad_soc *io_pads;
351 unsigned int num_io_pads;
352
353 const struct pinctrl_pin_desc *pin_descs;
354 unsigned int num_pin_descs;
355
356 const struct tegra_pmc_regs *regs;
357 void (*init)(struct tegra_pmc *pmc);
358 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
359 struct device_node *np,
360 bool invert);
361 void (*set_wake_filters)(struct tegra_pmc *pmc);
362 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
363 int (*irq_set_type)(struct irq_data *data, unsigned int type);
364 int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id,
365 bool new_state);
366
367 const char * const *reset_sources;
368 unsigned int num_reset_sources;
369 const char * const *reset_levels;
370 unsigned int num_reset_levels;
371
372 /*
373 * These describe events that can wake the system from sleep (i.e.
374 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2)
375 * are dealt with in the LIC.
376 */
377 const struct tegra_wake_event *wake_events;
378 unsigned int num_wake_events;
379 unsigned int max_wake_events;
380 unsigned int max_wake_vectors;
381
382 const struct pmc_clk_init_data *pmc_clks_data;
383 unsigned int num_pmc_clks;
384 bool has_blink_output;
385 bool has_usb_sleepwalk;
386 bool supports_core_domain;
387 };
388
389 /**
390 * struct tegra_pmc - NVIDIA Tegra PMC
391 * @dev: pointer to PMC device structure
392 * @base: pointer to I/O remapped register region
393 * @wake: pointer to I/O remapped region for WAKE registers
394 * @aotag: pointer to I/O remapped region for AOTAG registers
395 * @scratch: pointer to I/O remapped region for scratch registers
396 * @clk: pointer to pclk clock
397 * @soc: pointer to SoC data structure
398 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone
399 * @rate: currently configured rate of pclk
400 * @suspend_mode: lowest suspend mode available
401 * @cpu_good_time: CPU power good time (in microseconds)
402 * @cpu_off_time: CPU power off time (in microsecends)
403 * @core_osc_time: core power good OSC time (in microseconds)
404 * @core_pmu_time: core power good PMU time (in microseconds)
405 * @core_off_time: core power off time (in microseconds)
406 * @corereq_high: core power request is active-high
407 * @sysclkreq_high: system clock request is active-high
408 * @combined_req: combined power request for CPU & core
409 * @cpu_pwr_good_en: CPU power good signal is enabled
410 * @lp0_vec_phys: physical base address of the LP0 warm boot code
411 * @lp0_vec_size: size of the LP0 warm boot code
412 * @powergates_available: Bitmap of available power gates
413 * @powergates_lock: mutex for power gate register access
414 * @pctl_dev: pin controller exposed by the PMC
415 * @domain: IRQ domain provided by the PMC
416 * @irq: chip implementation for the IRQ domain
417 * @clk_nb: pclk clock changes handler
418 * @core_domain_state_synced: flag marking the core domain's state as synced
419 * @core_domain_registered: flag marking the core domain as registered
420 * @wake_type_level_map: Bitmap indicating level type for non-dual edge wakes
421 * @wake_type_dual_edge_map: Bitmap indicating if a wake is dual-edge or not
422 * @wake_sw_status_map: Bitmap to hold raw status of wakes without mask
423 * @wake_cntrl_level_map: Bitmap to hold wake levels to be programmed in
424 * cntrl register associated with each wake during system suspend.
425 */
426 struct tegra_pmc {
427 struct device *dev;
428 void __iomem *base;
429 void __iomem *wake;
430 void __iomem *aotag;
431 void __iomem *scratch;
432 struct clk *clk;
433
434 const struct tegra_pmc_soc *soc;
435 bool tz_only;
436
437 unsigned long rate;
438
439 enum tegra_suspend_mode suspend_mode;
440 u32 cpu_good_time;
441 u32 cpu_off_time;
442 u32 core_osc_time;
443 u32 core_pmu_time;
444 u32 core_off_time;
445 bool corereq_high;
446 bool sysclkreq_high;
447 bool combined_req;
448 bool cpu_pwr_good_en;
449 u32 lp0_vec_phys;
450 u32 lp0_vec_size;
451 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
452
453 struct mutex powergates_lock;
454
455 struct pinctrl_dev *pctl_dev;
456
457 struct irq_domain *domain;
458 struct irq_chip irq;
459
460 struct notifier_block clk_nb;
461
462 bool core_domain_state_synced;
463 bool core_domain_registered;
464
465 unsigned long *wake_type_level_map;
466 unsigned long *wake_type_dual_edge_map;
467 unsigned long *wake_sw_status_map;
468 unsigned long *wake_cntrl_level_map;
469 struct syscore_ops syscore;
470 };
471
472 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
473 .base = NULL,
474 .suspend_mode = TEGRA_SUSPEND_NOT_READY,
475 };
476
477 static inline struct tegra_powergate *
to_powergate(struct generic_pm_domain * domain)478 to_powergate(struct generic_pm_domain *domain)
479 {
480 return container_of(domain, struct tegra_powergate, genpd);
481 }
482
tegra_pmc_readl(struct tegra_pmc * pmc,unsigned long offset)483 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset)
484 {
485 struct arm_smccc_res res;
486
487 if (pmc->tz_only) {
488 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
489 0, 0, 0, &res);
490 if (res.a0) {
491 if (pmc->dev)
492 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
493 __func__, res.a0);
494 else
495 pr_warn("%s(): SMC failed: %lu\n", __func__,
496 res.a0);
497 }
498
499 return res.a1;
500 }
501
502 return readl(pmc->base + offset);
503 }
504
tegra_pmc_writel(struct tegra_pmc * pmc,u32 value,unsigned long offset)505 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value,
506 unsigned long offset)
507 {
508 struct arm_smccc_res res;
509
510 if (pmc->tz_only) {
511 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
512 value, 0, 0, 0, 0, &res);
513 if (res.a0) {
514 if (pmc->dev)
515 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
516 __func__, res.a0);
517 else
518 pr_warn("%s(): SMC failed: %lu\n", __func__,
519 res.a0);
520 }
521 } else {
522 writel(value, pmc->base + offset);
523 }
524 }
525
tegra_pmc_scratch_readl(struct tegra_pmc * pmc,unsigned long offset)526 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset)
527 {
528 if (pmc->tz_only)
529 return tegra_pmc_readl(pmc, offset);
530
531 return readl(pmc->scratch + offset);
532 }
533
tegra_pmc_scratch_writel(struct tegra_pmc * pmc,u32 value,unsigned long offset)534 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value,
535 unsigned long offset)
536 {
537 if (pmc->tz_only)
538 tegra_pmc_writel(pmc, value, offset);
539 else
540 writel(value, pmc->scratch + offset);
541 }
542
543 /*
544 * TODO Figure out a way to call this with the struct tegra_pmc * passed in.
545 * This currently doesn't work because readx_poll_timeout() can only operate
546 * on functions that take a single argument.
547 */
tegra_powergate_state(int id)548 static inline bool tegra_powergate_state(int id)
549 {
550 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
551 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0;
552 else
553 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0;
554 }
555
tegra_powergate_is_valid(struct tegra_pmc * pmc,int id)556 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id)
557 {
558 return (pmc->soc && pmc->soc->powergates[id]);
559 }
560
tegra_powergate_is_available(struct tegra_pmc * pmc,int id)561 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id)
562 {
563 return test_bit(id, pmc->powergates_available);
564 }
565
tegra_powergate_lookup(struct tegra_pmc * pmc,const char * name)566 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
567 {
568 unsigned int i;
569
570 if (!pmc || !pmc->soc || !name)
571 return -EINVAL;
572
573 for (i = 0; i < pmc->soc->num_powergates; i++) {
574 if (!tegra_powergate_is_valid(pmc, i))
575 continue;
576
577 if (!strcmp(name, pmc->soc->powergates[i]))
578 return i;
579 }
580
581 return -ENODEV;
582 }
583
tegra20_powergate_set(struct tegra_pmc * pmc,unsigned int id,bool new_state)584 static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id,
585 bool new_state)
586 {
587 unsigned int retries = 100;
588 bool status;
589 int ret;
590
591 /*
592 * As per TRM documentation, the toggle command will be dropped by PMC
593 * if there is contention with a HW-initiated toggling (i.e. CPU core
594 * power-gated), the command should be retried in that case.
595 */
596 do {
597 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
598
599 /* wait for PMC to execute the command */
600 ret = readx_poll_timeout(tegra_powergate_state, id, status,
601 status == new_state, 1, 10);
602 } while (ret == -ETIMEDOUT && retries--);
603
604 return ret;
605 }
606
tegra_powergate_toggle_ready(struct tegra_pmc * pmc)607 static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc)
608 {
609 return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START);
610 }
611
tegra114_powergate_set(struct tegra_pmc * pmc,unsigned int id,bool new_state)612 static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id,
613 bool new_state)
614 {
615 bool status;
616 int err;
617
618 /* wait while PMC power gating is contended */
619 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
620 status == true, 1, 100);
621 if (err)
622 return err;
623
624 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
625
626 /* wait for PMC to accept the command */
627 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
628 status == true, 1, 100);
629 if (err)
630 return err;
631
632 /* wait for PMC to execute the command */
633 err = readx_poll_timeout(tegra_powergate_state, id, status,
634 status == new_state, 10, 100000);
635 if (err)
636 return err;
637
638 return 0;
639 }
640
641 /**
642 * tegra_powergate_set() - set the state of a partition
643 * @pmc: power management controller
644 * @id: partition ID
645 * @new_state: new state of the partition
646 */
tegra_powergate_set(struct tegra_pmc * pmc,unsigned int id,bool new_state)647 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id,
648 bool new_state)
649 {
650 int err;
651
652 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
653 return -EINVAL;
654
655 mutex_lock(&pmc->powergates_lock);
656
657 if (tegra_powergate_state(id) == new_state) {
658 mutex_unlock(&pmc->powergates_lock);
659 return 0;
660 }
661
662 err = pmc->soc->powergate_set(pmc, id, new_state);
663
664 mutex_unlock(&pmc->powergates_lock);
665
666 return err;
667 }
668
__tegra_powergate_remove_clamping(struct tegra_pmc * pmc,unsigned int id)669 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,
670 unsigned int id)
671 {
672 u32 mask;
673
674 mutex_lock(&pmc->powergates_lock);
675
676 /*
677 * On Tegra124 and later, the clamps for the GPU are controlled by a
678 * separate register (with different semantics).
679 */
680 if (id == TEGRA_POWERGATE_3D) {
681 if (pmc->soc->has_gpu_clamps) {
682 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL);
683 goto out;
684 }
685 }
686
687 /*
688 * Tegra 2 has a bug where PCIE and VDE clamping masks are
689 * swapped relatively to the partition ids
690 */
691 if (id == TEGRA_POWERGATE_VDEC)
692 mask = (1 << TEGRA_POWERGATE_PCIE);
693 else if (id == TEGRA_POWERGATE_PCIE)
694 mask = (1 << TEGRA_POWERGATE_VDEC);
695 else
696 mask = (1 << id);
697
698 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING);
699
700 out:
701 mutex_unlock(&pmc->powergates_lock);
702
703 return 0;
704 }
705
tegra_powergate_prepare_clocks(struct tegra_powergate * pg)706 static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg)
707 {
708 unsigned long safe_rate = 100 * 1000 * 1000;
709 unsigned int i;
710 int err;
711
712 for (i = 0; i < pg->num_clks; i++) {
713 pg->clk_rates[i] = clk_get_rate(pg->clks[i]);
714
715 if (!pg->clk_rates[i]) {
716 err = -EINVAL;
717 goto out;
718 }
719
720 if (pg->clk_rates[i] <= safe_rate)
721 continue;
722
723 /*
724 * We don't know whether voltage state is okay for the
725 * current clock rate, hence it's better to temporally
726 * switch clock to a safe rate which is suitable for
727 * all voltages, before enabling the clock.
728 */
729 err = clk_set_rate(pg->clks[i], safe_rate);
730 if (err)
731 goto out;
732 }
733
734 return 0;
735
736 out:
737 while (i--)
738 clk_set_rate(pg->clks[i], pg->clk_rates[i]);
739
740 return err;
741 }
742
tegra_powergate_unprepare_clocks(struct tegra_powergate * pg)743 static int tegra_powergate_unprepare_clocks(struct tegra_powergate *pg)
744 {
745 unsigned int i;
746 int err;
747
748 for (i = 0; i < pg->num_clks; i++) {
749 err = clk_set_rate(pg->clks[i], pg->clk_rates[i]);
750 if (err)
751 return err;
752 }
753
754 return 0;
755 }
756
tegra_powergate_disable_clocks(struct tegra_powergate * pg)757 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
758 {
759 unsigned int i;
760
761 for (i = 0; i < pg->num_clks; i++)
762 clk_disable_unprepare(pg->clks[i]);
763 }
764
tegra_powergate_enable_clocks(struct tegra_powergate * pg)765 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
766 {
767 unsigned int i;
768 int err;
769
770 for (i = 0; i < pg->num_clks; i++) {
771 err = clk_prepare_enable(pg->clks[i]);
772 if (err)
773 goto out;
774 }
775
776 return 0;
777
778 out:
779 while (i--)
780 clk_disable_unprepare(pg->clks[i]);
781
782 return err;
783 }
784
tegra_powergate_power_up(struct tegra_powergate * pg,bool disable_clocks)785 static int tegra_powergate_power_up(struct tegra_powergate *pg,
786 bool disable_clocks)
787 {
788 int err;
789
790 err = reset_control_assert(pg->reset);
791 if (err)
792 return err;
793
794 usleep_range(10, 20);
795
796 err = tegra_powergate_set(pg->pmc, pg->id, true);
797 if (err < 0)
798 return err;
799
800 usleep_range(10, 20);
801
802 err = tegra_powergate_prepare_clocks(pg);
803 if (err)
804 goto powergate_off;
805
806 err = tegra_powergate_enable_clocks(pg);
807 if (err)
808 goto unprepare_clks;
809
810 usleep_range(10, 20);
811
812 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id);
813 if (err)
814 goto disable_clks;
815
816 usleep_range(10, 20);
817
818 err = reset_control_deassert(pg->reset);
819 if (err)
820 goto disable_clks;
821
822 usleep_range(10, 20);
823
824 if (pg->pmc->soc->needs_mbist_war)
825 err = tegra210_clk_handle_mbist_war(pg->id);
826 if (err)
827 goto disable_clks;
828
829 if (disable_clocks)
830 tegra_powergate_disable_clocks(pg);
831
832 err = tegra_powergate_unprepare_clocks(pg);
833 if (err)
834 return err;
835
836 return 0;
837
838 disable_clks:
839 tegra_powergate_disable_clocks(pg);
840 usleep_range(10, 20);
841
842 unprepare_clks:
843 tegra_powergate_unprepare_clocks(pg);
844
845 powergate_off:
846 tegra_powergate_set(pg->pmc, pg->id, false);
847
848 return err;
849 }
850
tegra_powergate_power_down(struct tegra_powergate * pg)851 static int tegra_powergate_power_down(struct tegra_powergate *pg)
852 {
853 int err;
854
855 err = tegra_powergate_prepare_clocks(pg);
856 if (err)
857 return err;
858
859 err = tegra_powergate_enable_clocks(pg);
860 if (err)
861 goto unprepare_clks;
862
863 usleep_range(10, 20);
864
865 err = reset_control_assert(pg->reset);
866 if (err)
867 goto disable_clks;
868
869 usleep_range(10, 20);
870
871 tegra_powergate_disable_clocks(pg);
872
873 usleep_range(10, 20);
874
875 err = tegra_powergate_set(pg->pmc, pg->id, false);
876 if (err)
877 goto assert_resets;
878
879 err = tegra_powergate_unprepare_clocks(pg);
880 if (err)
881 return err;
882
883 return 0;
884
885 assert_resets:
886 tegra_powergate_enable_clocks(pg);
887 usleep_range(10, 20);
888 reset_control_deassert(pg->reset);
889 usleep_range(10, 20);
890
891 disable_clks:
892 tegra_powergate_disable_clocks(pg);
893
894 unprepare_clks:
895 tegra_powergate_unprepare_clocks(pg);
896
897 return err;
898 }
899
tegra_genpd_power_on(struct generic_pm_domain * domain)900 static int tegra_genpd_power_on(struct generic_pm_domain *domain)
901 {
902 struct tegra_powergate *pg = to_powergate(domain);
903 struct device *dev = pg->pmc->dev;
904 int err;
905
906 err = tegra_powergate_power_up(pg, true);
907 if (err) {
908 dev_err(dev, "failed to turn on PM domain %s: %d\n",
909 pg->genpd.name, err);
910 goto out;
911 }
912
913 reset_control_release(pg->reset);
914
915 out:
916 return err;
917 }
918
tegra_genpd_power_off(struct generic_pm_domain * domain)919 static int tegra_genpd_power_off(struct generic_pm_domain *domain)
920 {
921 struct tegra_powergate *pg = to_powergate(domain);
922 struct device *dev = pg->pmc->dev;
923 int err;
924
925 err = reset_control_acquire(pg->reset);
926 if (err < 0) {
927 dev_err(dev, "failed to acquire resets for PM domain %s: %d\n",
928 pg->genpd.name, err);
929 return err;
930 }
931
932 err = tegra_powergate_power_down(pg);
933 if (err) {
934 dev_err(dev, "failed to turn off PM domain %s: %d\n",
935 pg->genpd.name, err);
936 reset_control_release(pg->reset);
937 }
938
939 return err;
940 }
941
942 /**
943 * tegra_powergate_power_on() - power on partition
944 * @id: partition ID
945 */
tegra_powergate_power_on(unsigned int id)946 int tegra_powergate_power_on(unsigned int id)
947 {
948 if (!tegra_powergate_is_available(pmc, id))
949 return -EINVAL;
950
951 return tegra_powergate_set(pmc, id, true);
952 }
953 EXPORT_SYMBOL(tegra_powergate_power_on);
954
955 /**
956 * tegra_powergate_power_off() - power off partition
957 * @id: partition ID
958 */
tegra_powergate_power_off(unsigned int id)959 int tegra_powergate_power_off(unsigned int id)
960 {
961 if (!tegra_powergate_is_available(pmc, id))
962 return -EINVAL;
963
964 return tegra_powergate_set(pmc, id, false);
965 }
966 EXPORT_SYMBOL(tegra_powergate_power_off);
967
968 /**
969 * tegra_powergate_is_powered() - check if partition is powered
970 * @pmc: power management controller
971 * @id: partition ID
972 */
tegra_powergate_is_powered(struct tegra_pmc * pmc,unsigned int id)973 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id)
974 {
975 if (!tegra_powergate_is_valid(pmc, id))
976 return -EINVAL;
977
978 return tegra_powergate_state(id);
979 }
980
981 /**
982 * tegra_powergate_remove_clamping() - remove power clamps for partition
983 * @id: partition ID
984 */
tegra_powergate_remove_clamping(unsigned int id)985 int tegra_powergate_remove_clamping(unsigned int id)
986 {
987 if (!tegra_powergate_is_available(pmc, id))
988 return -EINVAL;
989
990 return __tegra_powergate_remove_clamping(pmc, id);
991 }
992 EXPORT_SYMBOL(tegra_powergate_remove_clamping);
993
994 /**
995 * tegra_powergate_sequence_power_up() - power up partition
996 * @id: partition ID
997 * @clk: clock for partition
998 * @rst: reset for partition
999 *
1000 * Must be called with clk disabled, and returns with clk enabled.
1001 */
tegra_powergate_sequence_power_up(unsigned int id,struct clk * clk,struct reset_control * rst)1002 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
1003 struct reset_control *rst)
1004 {
1005 struct tegra_powergate *pg;
1006 int err;
1007
1008 if (!tegra_powergate_is_available(pmc, id))
1009 return -EINVAL;
1010
1011 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
1012 if (!pg)
1013 return -ENOMEM;
1014
1015 pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL);
1016 if (!pg->clk_rates) {
1017 kfree(pg->clks);
1018 return -ENOMEM;
1019 }
1020
1021 pg->id = id;
1022 pg->clks = &clk;
1023 pg->num_clks = 1;
1024 pg->reset = rst;
1025 pg->pmc = pmc;
1026
1027 err = tegra_powergate_power_up(pg, false);
1028 if (err)
1029 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id,
1030 err);
1031
1032 kfree(pg->clk_rates);
1033 kfree(pg);
1034
1035 return err;
1036 }
1037 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
1038
1039 /**
1040 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
1041 * @pmc: power management controller
1042 * @cpuid: CPU partition ID
1043 *
1044 * Returns the partition ID corresponding to the CPU partition ID or a
1045 * negative error code on failure.
1046 */
tegra_get_cpu_powergate_id(struct tegra_pmc * pmc,unsigned int cpuid)1047 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc,
1048 unsigned int cpuid)
1049 {
1050 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
1051 return pmc->soc->cpu_powergates[cpuid];
1052
1053 return -EINVAL;
1054 }
1055
1056 /**
1057 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
1058 * @cpuid: CPU partition ID
1059 */
tegra_pmc_cpu_is_powered(unsigned int cpuid)1060 bool tegra_pmc_cpu_is_powered(unsigned int cpuid)
1061 {
1062 int id;
1063
1064 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1065 if (id < 0)
1066 return false;
1067
1068 return tegra_powergate_is_powered(pmc, id);
1069 }
1070
1071 /**
1072 * tegra_pmc_cpu_power_on() - power on CPU partition
1073 * @cpuid: CPU partition ID
1074 */
tegra_pmc_cpu_power_on(unsigned int cpuid)1075 int tegra_pmc_cpu_power_on(unsigned int cpuid)
1076 {
1077 int id;
1078
1079 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1080 if (id < 0)
1081 return id;
1082
1083 return tegra_powergate_set(pmc, id, true);
1084 }
1085
1086 /**
1087 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
1088 * @cpuid: CPU partition ID
1089 */
tegra_pmc_cpu_remove_clamping(unsigned int cpuid)1090 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
1091 {
1092 int id;
1093
1094 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1095 if (id < 0)
1096 return id;
1097
1098 return tegra_powergate_remove_clamping(id);
1099 }
1100
tegra_pmc_program_reboot_reason(const char * cmd)1101 static void tegra_pmc_program_reboot_reason(const char *cmd)
1102 {
1103 u32 value;
1104
1105 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0);
1106 value &= ~PMC_SCRATCH0_MODE_MASK;
1107
1108 if (cmd) {
1109 if (strcmp(cmd, "recovery") == 0)
1110 value |= PMC_SCRATCH0_MODE_RECOVERY;
1111
1112 if (strcmp(cmd, "bootloader") == 0)
1113 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
1114
1115 if (strcmp(cmd, "forced-recovery") == 0)
1116 value |= PMC_SCRATCH0_MODE_RCM;
1117 }
1118
1119 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0);
1120 }
1121
tegra_pmc_reboot_notify(struct notifier_block * this,unsigned long action,void * data)1122 static int tegra_pmc_reboot_notify(struct notifier_block *this,
1123 unsigned long action, void *data)
1124 {
1125 if (action == SYS_RESTART)
1126 tegra_pmc_program_reboot_reason(data);
1127
1128 return NOTIFY_DONE;
1129 }
1130
1131 static struct notifier_block tegra_pmc_reboot_notifier = {
1132 .notifier_call = tegra_pmc_reboot_notify,
1133 };
1134
tegra_pmc_restart(void)1135 static void tegra_pmc_restart(void)
1136 {
1137 u32 value;
1138
1139 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
1140 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1141 value |= PMC_CNTRL_MAIN_RST;
1142 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1143 }
1144
tegra_pmc_restart_handler(struct sys_off_data * data)1145 static int tegra_pmc_restart_handler(struct sys_off_data *data)
1146 {
1147 tegra_pmc_restart();
1148
1149 return NOTIFY_DONE;
1150 }
1151
tegra_pmc_power_off_handler(struct sys_off_data * data)1152 static int tegra_pmc_power_off_handler(struct sys_off_data *data)
1153 {
1154 /*
1155 * Reboot Nexus 7 into special bootloader mode if USB cable is
1156 * connected in order to display battery status and power off.
1157 */
1158 if (of_machine_is_compatible("asus,grouper") &&
1159 power_supply_is_system_supplied()) {
1160 const u32 go_to_charger_mode = 0xa5a55a5a;
1161
1162 tegra_pmc_writel(pmc, go_to_charger_mode, PMC_SCRATCH37);
1163 tegra_pmc_restart();
1164 }
1165
1166 return NOTIFY_DONE;
1167 }
1168
powergate_show(struct seq_file * s,void * data)1169 static int powergate_show(struct seq_file *s, void *data)
1170 {
1171 unsigned int i;
1172 int status;
1173
1174 seq_printf(s, " powergate powered\n");
1175 seq_printf(s, "------------------\n");
1176
1177 for (i = 0; i < pmc->soc->num_powergates; i++) {
1178 status = tegra_powergate_is_powered(pmc, i);
1179 if (status < 0)
1180 continue;
1181
1182 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
1183 status ? "yes" : "no");
1184 }
1185
1186 return 0;
1187 }
1188
1189 DEFINE_SHOW_ATTRIBUTE(powergate);
1190
tegra_powergate_of_get_clks(struct tegra_powergate * pg,struct device_node * np)1191 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
1192 struct device_node *np)
1193 {
1194 struct clk *clk;
1195 unsigned int i, count;
1196 int err;
1197
1198 count = of_clk_get_parent_count(np);
1199 if (count == 0)
1200 return -ENODEV;
1201
1202 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
1203 if (!pg->clks)
1204 return -ENOMEM;
1205
1206 pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL);
1207 if (!pg->clk_rates) {
1208 kfree(pg->clks);
1209 return -ENOMEM;
1210 }
1211
1212 for (i = 0; i < count; i++) {
1213 pg->clks[i] = of_clk_get(np, i);
1214 if (IS_ERR(pg->clks[i])) {
1215 err = PTR_ERR(pg->clks[i]);
1216 goto err;
1217 }
1218 }
1219
1220 pg->num_clks = count;
1221
1222 return 0;
1223
1224 err:
1225 while (i--)
1226 clk_put(pg->clks[i]);
1227
1228 kfree(pg->clk_rates);
1229 kfree(pg->clks);
1230
1231 return err;
1232 }
1233
tegra_powergate_of_get_resets(struct tegra_powergate * pg,struct device_node * np,bool off)1234 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
1235 struct device_node *np, bool off)
1236 {
1237 struct device *dev = pg->pmc->dev;
1238 int err;
1239
1240 pg->reset = of_reset_control_array_get_exclusive_released(np);
1241 if (IS_ERR(pg->reset)) {
1242 err = PTR_ERR(pg->reset);
1243 dev_err(dev, "failed to get device resets: %d\n", err);
1244 return err;
1245 }
1246
1247 err = reset_control_acquire(pg->reset);
1248 if (err < 0) {
1249 pr_err("failed to acquire resets: %d\n", err);
1250 goto out;
1251 }
1252
1253 if (off) {
1254 err = reset_control_assert(pg->reset);
1255 } else {
1256 err = reset_control_deassert(pg->reset);
1257 if (err < 0)
1258 goto out;
1259
1260 reset_control_release(pg->reset);
1261 }
1262
1263 out:
1264 if (err) {
1265 reset_control_release(pg->reset);
1266 reset_control_put(pg->reset);
1267 }
1268
1269 return err;
1270 }
1271
tegra_powergate_add(struct tegra_pmc * pmc,struct device_node * np)1272 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
1273 {
1274 struct device *dev = pmc->dev;
1275 struct tegra_powergate *pg;
1276 int id, err = 0;
1277 bool off;
1278
1279 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
1280 if (!pg)
1281 return -ENOMEM;
1282
1283 id = tegra_powergate_lookup(pmc, np->name);
1284 if (id < 0) {
1285 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id);
1286 err = -ENODEV;
1287 goto free_mem;
1288 }
1289
1290 /*
1291 * Clear the bit for this powergate so it cannot be managed
1292 * directly via the legacy APIs for controlling powergates.
1293 */
1294 clear_bit(id, pmc->powergates_available);
1295
1296 pg->id = id;
1297 pg->genpd.name = np->name;
1298 pg->genpd.power_off = tegra_genpd_power_off;
1299 pg->genpd.power_on = tegra_genpd_power_on;
1300 pg->pmc = pmc;
1301
1302 off = !tegra_powergate_is_powered(pmc, pg->id);
1303
1304 err = tegra_powergate_of_get_clks(pg, np);
1305 if (err < 0) {
1306 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err);
1307 goto set_available;
1308 }
1309
1310 err = tegra_powergate_of_get_resets(pg, np, off);
1311 if (err < 0) {
1312 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err);
1313 goto remove_clks;
1314 }
1315
1316 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
1317 if (off)
1318 WARN_ON(tegra_powergate_power_up(pg, true));
1319
1320 goto remove_resets;
1321 }
1322
1323 err = pm_genpd_init(&pg->genpd, NULL, off);
1324 if (err < 0) {
1325 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np,
1326 err);
1327 goto remove_resets;
1328 }
1329
1330 err = of_genpd_add_provider_simple(np, &pg->genpd);
1331 if (err < 0) {
1332 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n",
1333 np, err);
1334 goto remove_genpd;
1335 }
1336
1337 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name);
1338
1339 return 0;
1340
1341 remove_genpd:
1342 pm_genpd_remove(&pg->genpd);
1343
1344 remove_resets:
1345 reset_control_put(pg->reset);
1346
1347 remove_clks:
1348 while (pg->num_clks--)
1349 clk_put(pg->clks[pg->num_clks]);
1350
1351 kfree(pg->clks);
1352
1353 set_available:
1354 set_bit(id, pmc->powergates_available);
1355
1356 free_mem:
1357 kfree(pg);
1358
1359 return err;
1360 }
1361
tegra_pmc_core_domain_state_synced(void)1362 bool tegra_pmc_core_domain_state_synced(void)
1363 {
1364 return pmc->core_domain_state_synced;
1365 }
1366
1367 static int
tegra_pmc_core_pd_set_performance_state(struct generic_pm_domain * genpd,unsigned int level)1368 tegra_pmc_core_pd_set_performance_state(struct generic_pm_domain *genpd,
1369 unsigned int level)
1370 {
1371 struct dev_pm_opp *opp;
1372 int err;
1373
1374 opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level);
1375 if (IS_ERR(opp)) {
1376 dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n",
1377 level, opp);
1378 return PTR_ERR(opp);
1379 }
1380
1381 mutex_lock(&pmc->powergates_lock);
1382 err = dev_pm_opp_set_opp(pmc->dev, opp);
1383 mutex_unlock(&pmc->powergates_lock);
1384
1385 dev_pm_opp_put(opp);
1386
1387 if (err) {
1388 dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n",
1389 level, err);
1390 return err;
1391 }
1392
1393 return 0;
1394 }
1395
tegra_pmc_core_pd_add(struct tegra_pmc * pmc,struct device_node * np)1396 static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np)
1397 {
1398 struct generic_pm_domain *genpd;
1399 const char *rname[] = { "core", NULL};
1400 int err;
1401
1402 genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL);
1403 if (!genpd)
1404 return -ENOMEM;
1405
1406 genpd->name = "core";
1407 genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state;
1408
1409 err = devm_pm_opp_set_regulators(pmc->dev, rname);
1410 if (err)
1411 return dev_err_probe(pmc->dev, err,
1412 "failed to set core OPP regulator\n");
1413
1414 err = pm_genpd_init(genpd, NULL, false);
1415 if (err) {
1416 dev_err(pmc->dev, "failed to init core genpd: %d\n", err);
1417 return err;
1418 }
1419
1420 err = of_genpd_add_provider_simple(np, genpd);
1421 if (err) {
1422 dev_err(pmc->dev, "failed to add core genpd: %d\n", err);
1423 goto remove_genpd;
1424 }
1425
1426 pmc->core_domain_registered = true;
1427
1428 return 0;
1429
1430 remove_genpd:
1431 pm_genpd_remove(genpd);
1432
1433 return err;
1434 }
1435
tegra_powergate_init(struct tegra_pmc * pmc,struct device_node * parent)1436 static int tegra_powergate_init(struct tegra_pmc *pmc,
1437 struct device_node *parent)
1438 {
1439 struct of_phandle_args child_args, parent_args;
1440 struct device_node *np, *child;
1441 int err = 0;
1442
1443 /*
1444 * Core power domain is the parent of powergate domains, hence it
1445 * should be registered first.
1446 */
1447 np = of_get_child_by_name(parent, "core-domain");
1448 if (np) {
1449 err = tegra_pmc_core_pd_add(pmc, np);
1450 of_node_put(np);
1451 if (err)
1452 return err;
1453 }
1454
1455 np = of_get_child_by_name(parent, "powergates");
1456 if (!np)
1457 return 0;
1458
1459 for_each_child_of_node(np, child) {
1460 err = tegra_powergate_add(pmc, child);
1461 if (err < 0) {
1462 of_node_put(child);
1463 break;
1464 }
1465
1466 if (of_parse_phandle_with_args(child, "power-domains",
1467 "#power-domain-cells",
1468 0, &parent_args))
1469 continue;
1470
1471 child_args.np = child;
1472 child_args.args_count = 0;
1473
1474 err = of_genpd_add_subdomain(&parent_args, &child_args);
1475 of_node_put(parent_args.np);
1476 if (err) {
1477 of_node_put(child);
1478 break;
1479 }
1480 }
1481
1482 of_node_put(np);
1483
1484 return err;
1485 }
1486
tegra_powergate_remove(struct generic_pm_domain * genpd)1487 static void tegra_powergate_remove(struct generic_pm_domain *genpd)
1488 {
1489 struct tegra_powergate *pg = to_powergate(genpd);
1490
1491 reset_control_put(pg->reset);
1492
1493 while (pg->num_clks--)
1494 clk_put(pg->clks[pg->num_clks]);
1495
1496 kfree(pg->clks);
1497
1498 set_bit(pg->id, pmc->powergates_available);
1499
1500 kfree(pg);
1501 }
1502
tegra_powergate_remove_all(struct device_node * parent)1503 static void tegra_powergate_remove_all(struct device_node *parent)
1504 {
1505 struct generic_pm_domain *genpd;
1506 struct device_node *np, *child;
1507
1508 np = of_get_child_by_name(parent, "powergates");
1509 if (!np)
1510 return;
1511
1512 for_each_child_of_node(np, child) {
1513 of_genpd_del_provider(child);
1514
1515 genpd = of_genpd_remove_last(child);
1516 if (IS_ERR(genpd))
1517 continue;
1518
1519 tegra_powergate_remove(genpd);
1520 }
1521
1522 of_node_put(np);
1523
1524 np = of_get_child_by_name(parent, "core-domain");
1525 if (np) {
1526 of_genpd_del_provider(np);
1527 of_genpd_remove_last(np);
1528 }
1529 }
1530
1531 static const struct tegra_io_pad_soc *
tegra_io_pad_find(struct tegra_pmc * pmc,enum tegra_io_pad id)1532 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
1533 {
1534 unsigned int i;
1535
1536 for (i = 0; i < pmc->soc->num_io_pads; i++)
1537 if (pmc->soc->io_pads[i].id == id)
1538 return &pmc->soc->io_pads[i];
1539
1540 return NULL;
1541 }
1542
tegra_io_pad_prepare(struct tegra_pmc * pmc,const struct tegra_io_pad_soc * pad,unsigned long * request,unsigned long * status,u32 * mask)1543 static int tegra_io_pad_prepare(struct tegra_pmc *pmc,
1544 const struct tegra_io_pad_soc *pad,
1545 unsigned long *request,
1546 unsigned long *status,
1547 u32 *mask)
1548 {
1549 unsigned long rate, value;
1550
1551 if (pad->dpd == UINT_MAX)
1552 return -EINVAL;
1553
1554 *request = pad->request;
1555 *status = pad->status;
1556 *mask = BIT(pad->dpd);
1557
1558 if (pmc->clk) {
1559 rate = pmc->rate;
1560 if (!rate) {
1561 dev_err(pmc->dev, "failed to get clock rate\n");
1562 return -ENODEV;
1563 }
1564
1565 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE);
1566
1567 /* must be at least 200 ns, in APB (PCLK) clock cycles */
1568 value = DIV_ROUND_UP(1000000000, rate);
1569 value = DIV_ROUND_UP(200, value);
1570 tegra_pmc_writel(pmc, value, SEL_DPD_TIM);
1571 }
1572
1573 return 0;
1574 }
1575
tegra_io_pad_poll(struct tegra_pmc * pmc,unsigned long offset,u32 mask,u32 val,unsigned long timeout)1576 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset,
1577 u32 mask, u32 val, unsigned long timeout)
1578 {
1579 u32 value;
1580
1581 timeout = jiffies + msecs_to_jiffies(timeout);
1582
1583 while (time_after(timeout, jiffies)) {
1584 value = tegra_pmc_readl(pmc, offset);
1585 if ((value & mask) == val)
1586 return 0;
1587
1588 usleep_range(250, 1000);
1589 }
1590
1591 return -ETIMEDOUT;
1592 }
1593
tegra_io_pad_unprepare(struct tegra_pmc * pmc)1594 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc)
1595 {
1596 if (pmc->clk)
1597 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE);
1598 }
1599
1600 /**
1601 * tegra_io_pad_power_enable() - enable power to I/O pad
1602 * @id: Tegra I/O pad ID for which to enable power
1603 *
1604 * Returns: 0 on success or a negative error code on failure.
1605 */
tegra_io_pad_power_enable(enum tegra_io_pad id)1606 int tegra_io_pad_power_enable(enum tegra_io_pad id)
1607 {
1608 const struct tegra_io_pad_soc *pad;
1609 unsigned long request, status;
1610 u32 mask;
1611 int err;
1612
1613 pad = tegra_io_pad_find(pmc, id);
1614 if (!pad) {
1615 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1616 return -ENOENT;
1617 }
1618
1619 mutex_lock(&pmc->powergates_lock);
1620
1621 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask);
1622 if (err < 0) {
1623 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1624 goto unlock;
1625 }
1626
1627 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request);
1628
1629 err = tegra_io_pad_poll(pmc, status, mask, 0, 250);
1630 if (err < 0) {
1631 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err);
1632 goto unlock;
1633 }
1634
1635 tegra_io_pad_unprepare(pmc);
1636
1637 unlock:
1638 mutex_unlock(&pmc->powergates_lock);
1639 return err;
1640 }
1641 EXPORT_SYMBOL(tegra_io_pad_power_enable);
1642
1643 /**
1644 * tegra_io_pad_power_disable() - disable power to I/O pad
1645 * @id: Tegra I/O pad ID for which to disable power
1646 *
1647 * Returns: 0 on success or a negative error code on failure.
1648 */
tegra_io_pad_power_disable(enum tegra_io_pad id)1649 int tegra_io_pad_power_disable(enum tegra_io_pad id)
1650 {
1651 const struct tegra_io_pad_soc *pad;
1652 unsigned long request, status;
1653 u32 mask;
1654 int err;
1655
1656 pad = tegra_io_pad_find(pmc, id);
1657 if (!pad) {
1658 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1659 return -ENOENT;
1660 }
1661
1662 mutex_lock(&pmc->powergates_lock);
1663
1664 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask);
1665 if (err < 0) {
1666 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1667 goto unlock;
1668 }
1669
1670 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request);
1671
1672 err = tegra_io_pad_poll(pmc, status, mask, mask, 250);
1673 if (err < 0) {
1674 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err);
1675 goto unlock;
1676 }
1677
1678 tegra_io_pad_unprepare(pmc);
1679
1680 unlock:
1681 mutex_unlock(&pmc->powergates_lock);
1682 return err;
1683 }
1684 EXPORT_SYMBOL(tegra_io_pad_power_disable);
1685
tegra_io_pad_is_powered(struct tegra_pmc * pmc,enum tegra_io_pad id)1686 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id)
1687 {
1688 const struct tegra_io_pad_soc *pad;
1689 unsigned long status;
1690 u32 mask, value;
1691
1692 pad = tegra_io_pad_find(pmc, id);
1693 if (!pad) {
1694 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1695 return -ENOENT;
1696 }
1697
1698 if (pad->dpd == UINT_MAX)
1699 return -EINVAL;
1700
1701 status = pad->status;
1702 mask = BIT(pad->dpd);
1703
1704 value = tegra_pmc_readl(pmc, status);
1705
1706 return !(value & mask);
1707 }
1708
tegra_io_pad_set_voltage(struct tegra_pmc * pmc,enum tegra_io_pad id,int voltage)1709 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id,
1710 int voltage)
1711 {
1712 const struct tegra_io_pad_soc *pad;
1713 u32 value;
1714
1715 pad = tegra_io_pad_find(pmc, id);
1716 if (!pad)
1717 return -ENOENT;
1718
1719 if (pad->voltage == UINT_MAX)
1720 return -ENOTSUPP;
1721
1722 mutex_lock(&pmc->powergates_lock);
1723
1724 if (pmc->soc->has_impl_33v_pwr) {
1725 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1726
1727 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1728 value &= ~BIT(pad->voltage);
1729 else
1730 value |= BIT(pad->voltage);
1731
1732 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);
1733 } else {
1734 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */
1735 value = tegra_pmc_readl(pmc, PMC_PWR_DET);
1736 value |= BIT(pad->voltage);
1737 tegra_pmc_writel(pmc, value, PMC_PWR_DET);
1738
1739 /* update I/O voltage */
1740 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1741
1742 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1743 value &= ~BIT(pad->voltage);
1744 else
1745 value |= BIT(pad->voltage);
1746
1747 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);
1748 }
1749
1750 mutex_unlock(&pmc->powergates_lock);
1751
1752 usleep_range(100, 250);
1753
1754 return 0;
1755 }
1756
tegra_io_pad_get_voltage(struct tegra_pmc * pmc,enum tegra_io_pad id)1757 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id)
1758 {
1759 const struct tegra_io_pad_soc *pad;
1760 u32 value;
1761
1762 pad = tegra_io_pad_find(pmc, id);
1763 if (!pad)
1764 return -ENOENT;
1765
1766 if (pad->voltage == UINT_MAX)
1767 return -ENOTSUPP;
1768
1769 if (pmc->soc->has_impl_33v_pwr)
1770 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1771 else
1772 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1773
1774 if ((value & BIT(pad->voltage)) == 0)
1775 return TEGRA_IO_PAD_VOLTAGE_1V8;
1776
1777 return TEGRA_IO_PAD_VOLTAGE_3V3;
1778 }
1779
1780 /**
1781 * tegra_io_rail_power_on() - enable power to I/O rail
1782 * @id: Tegra I/O pad ID for which to enable power
1783 *
1784 * See also: tegra_io_pad_power_enable()
1785 */
tegra_io_rail_power_on(unsigned int id)1786 int tegra_io_rail_power_on(unsigned int id)
1787 {
1788 return tegra_io_pad_power_enable(id);
1789 }
1790 EXPORT_SYMBOL(tegra_io_rail_power_on);
1791
1792 /**
1793 * tegra_io_rail_power_off() - disable power to I/O rail
1794 * @id: Tegra I/O pad ID for which to disable power
1795 *
1796 * See also: tegra_io_pad_power_disable()
1797 */
tegra_io_rail_power_off(unsigned int id)1798 int tegra_io_rail_power_off(unsigned int id)
1799 {
1800 return tegra_io_pad_power_disable(id);
1801 }
1802 EXPORT_SYMBOL(tegra_io_rail_power_off);
1803
1804 #ifdef CONFIG_PM_SLEEP
tegra_pmc_get_suspend_mode(void)1805 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1806 {
1807 return pmc->suspend_mode;
1808 }
1809
tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)1810 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
1811 {
1812 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
1813 return;
1814
1815 pmc->suspend_mode = mode;
1816 }
1817
tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)1818 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
1819 {
1820 unsigned long long rate = 0;
1821 u64 ticks;
1822 u32 value;
1823
1824 switch (mode) {
1825 case TEGRA_SUSPEND_LP1:
1826 rate = 32768;
1827 break;
1828
1829 case TEGRA_SUSPEND_LP2:
1830 rate = pmc->rate;
1831 break;
1832
1833 default:
1834 break;
1835 }
1836
1837 if (WARN_ON_ONCE(rate == 0))
1838 rate = 100000000;
1839
1840 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1841 do_div(ticks, USEC_PER_SEC);
1842 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);
1843
1844 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1845 do_div(ticks, USEC_PER_SEC);
1846 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);
1847
1848 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1849 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1850 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1851 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1852 }
1853 #endif
1854
tegra_pmc_parse_dt(struct tegra_pmc * pmc,struct device_node * np)1855 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1856 {
1857 u32 value, values[2];
1858
1859 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
1860 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1861 } else {
1862 switch (value) {
1863 case 0:
1864 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1865 break;
1866
1867 case 1:
1868 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1869 break;
1870
1871 case 2:
1872 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1873 break;
1874
1875 default:
1876 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1877 break;
1878 }
1879 }
1880
1881 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1882
1883 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
1884 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1885
1886 pmc->cpu_good_time = value;
1887
1888 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
1889 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1890
1891 pmc->cpu_off_time = value;
1892
1893 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
1894 values, ARRAY_SIZE(values)))
1895 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1896
1897 pmc->core_osc_time = values[0];
1898 pmc->core_pmu_time = values[1];
1899
1900 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
1901 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1902
1903 pmc->core_off_time = value;
1904
1905 pmc->corereq_high = of_property_read_bool(np,
1906 "nvidia,core-power-req-active-high");
1907
1908 pmc->sysclkreq_high = of_property_read_bool(np,
1909 "nvidia,sys-clock-req-active-high");
1910
1911 pmc->combined_req = of_property_read_bool(np,
1912 "nvidia,combined-power-req");
1913
1914 pmc->cpu_pwr_good_en = of_property_read_bool(np,
1915 "nvidia,cpu-pwr-good-en");
1916
1917 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
1918 ARRAY_SIZE(values)))
1919 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1920 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1921
1922 pmc->lp0_vec_phys = values[0];
1923 pmc->lp0_vec_size = values[1];
1924
1925 return 0;
1926 }
1927
tegra_pmc_init(struct tegra_pmc * pmc)1928 static int tegra_pmc_init(struct tegra_pmc *pmc)
1929 {
1930 if (pmc->soc->max_wake_events > 0) {
1931 pmc->wake_type_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);
1932 if (!pmc->wake_type_level_map)
1933 return -ENOMEM;
1934
1935 pmc->wake_type_dual_edge_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);
1936 if (!pmc->wake_type_dual_edge_map)
1937 return -ENOMEM;
1938
1939 pmc->wake_sw_status_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);
1940 if (!pmc->wake_sw_status_map)
1941 return -ENOMEM;
1942
1943 pmc->wake_cntrl_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);
1944 if (!pmc->wake_cntrl_level_map)
1945 return -ENOMEM;
1946 }
1947
1948 if (pmc->soc->init)
1949 pmc->soc->init(pmc);
1950
1951 return 0;
1952 }
1953
tegra_pmc_init_tsense_reset(struct tegra_pmc * pmc)1954 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1955 {
1956 static const char disabled[] = "emergency thermal reset disabled";
1957 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
1958 struct device *dev = pmc->dev;
1959 struct device_node *np;
1960 u32 value, checksum;
1961
1962 if (!pmc->soc->has_tsense_reset)
1963 return;
1964
1965 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip");
1966 if (!np) {
1967 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
1968 return;
1969 }
1970
1971 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
1972 dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
1973 goto out;
1974 }
1975
1976 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
1977 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
1978 goto out;
1979 }
1980
1981 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) {
1982 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
1983 goto out;
1984 }
1985
1986 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) {
1987 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
1988 goto out;
1989 }
1990
1991 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
1992 pinmux = 0;
1993
1994 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1995 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
1996 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1997
1998 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
1999 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
2000 tegra_pmc_writel(pmc, value, PMC_SCRATCH54);
2001
2002 value = PMC_SCRATCH55_RESET_TEGRA;
2003 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
2004 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
2005 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
2006
2007 /*
2008 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
2009 * contain the checksum and are currently zero, so they are not added.
2010 */
2011 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
2012 + ((value >> 24) & 0xff);
2013 checksum &= 0xff;
2014 checksum = 0x100 - checksum;
2015
2016 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
2017
2018 tegra_pmc_writel(pmc, value, PMC_SCRATCH55);
2019
2020 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
2021 value |= PMC_SENSOR_CTRL_ENABLE_RST;
2022 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
2023
2024 dev_info(pmc->dev, "emergency thermal reset enabled\n");
2025
2026 out:
2027 of_node_put(np);
2028 }
2029
tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev * pctl_dev)2030 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev)
2031 {
2032 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2033
2034 return pmc->soc->num_io_pads;
2035 }
2036
tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev * pctl,unsigned int group)2037 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl,
2038 unsigned int group)
2039 {
2040 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl);
2041
2042 return pmc->soc->io_pads[group].name;
2043 }
2044
tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev * pctl_dev,unsigned int group,const unsigned int ** pins,unsigned int * num_pins)2045 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev,
2046 unsigned int group,
2047 const unsigned int **pins,
2048 unsigned int *num_pins)
2049 {
2050 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2051
2052 *pins = &pmc->soc->io_pads[group].id;
2053 *num_pins = 1;
2054
2055 return 0;
2056 }
2057
2058 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = {
2059 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count,
2060 .get_group_name = tegra_io_pad_pinctrl_get_group_name,
2061 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins,
2062 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
2063 .dt_free_map = pinconf_generic_dt_free_map,
2064 };
2065
tegra_io_pad_pinconf_get(struct pinctrl_dev * pctl_dev,unsigned int pin,unsigned long * config)2066 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev,
2067 unsigned int pin, unsigned long *config)
2068 {
2069 enum pin_config_param param = pinconf_to_config_param(*config);
2070 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2071 const struct tegra_io_pad_soc *pad;
2072 int ret;
2073 u32 arg;
2074
2075 pad = tegra_io_pad_find(pmc, pin);
2076 if (!pad)
2077 return -EINVAL;
2078
2079 switch (param) {
2080 case PIN_CONFIG_POWER_SOURCE:
2081 ret = tegra_io_pad_get_voltage(pmc, pad->id);
2082 if (ret < 0)
2083 return ret;
2084
2085 arg = ret;
2086 break;
2087
2088 case PIN_CONFIG_MODE_LOW_POWER:
2089 ret = tegra_io_pad_is_powered(pmc, pad->id);
2090 if (ret < 0)
2091 return ret;
2092
2093 arg = !ret;
2094 break;
2095
2096 default:
2097 return -EINVAL;
2098 }
2099
2100 *config = pinconf_to_config_packed(param, arg);
2101
2102 return 0;
2103 }
2104
tegra_io_pad_pinconf_set(struct pinctrl_dev * pctl_dev,unsigned int pin,unsigned long * configs,unsigned int num_configs)2105 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev,
2106 unsigned int pin, unsigned long *configs,
2107 unsigned int num_configs)
2108 {
2109 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2110 const struct tegra_io_pad_soc *pad;
2111 enum pin_config_param param;
2112 unsigned int i;
2113 int err;
2114 u32 arg;
2115
2116 pad = tegra_io_pad_find(pmc, pin);
2117 if (!pad)
2118 return -EINVAL;
2119
2120 for (i = 0; i < num_configs; ++i) {
2121 param = pinconf_to_config_param(configs[i]);
2122 arg = pinconf_to_config_argument(configs[i]);
2123
2124 switch (param) {
2125 case PIN_CONFIG_MODE_LOW_POWER:
2126 if (arg)
2127 err = tegra_io_pad_power_disable(pad->id);
2128 else
2129 err = tegra_io_pad_power_enable(pad->id);
2130 if (err)
2131 return err;
2132 break;
2133 case PIN_CONFIG_POWER_SOURCE:
2134 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 &&
2135 arg != TEGRA_IO_PAD_VOLTAGE_3V3)
2136 return -EINVAL;
2137 err = tegra_io_pad_set_voltage(pmc, pad->id, arg);
2138 if (err)
2139 return err;
2140 break;
2141 default:
2142 return -EINVAL;
2143 }
2144 }
2145
2146 return 0;
2147 }
2148
2149 static const struct pinconf_ops tegra_io_pad_pinconf_ops = {
2150 .pin_config_get = tegra_io_pad_pinconf_get,
2151 .pin_config_set = tegra_io_pad_pinconf_set,
2152 .is_generic = true,
2153 };
2154
2155 static struct pinctrl_desc tegra_pmc_pctl_desc = {
2156 .pctlops = &tegra_io_pad_pinctrl_ops,
2157 .confops = &tegra_io_pad_pinconf_ops,
2158 };
2159
tegra_pmc_pinctrl_init(struct tegra_pmc * pmc)2160 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc)
2161 {
2162 int err;
2163
2164 if (!pmc->soc->num_pin_descs)
2165 return 0;
2166
2167 tegra_pmc_pctl_desc.name = dev_name(pmc->dev);
2168 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs;
2169 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs;
2170
2171 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc,
2172 pmc);
2173 if (IS_ERR(pmc->pctl_dev)) {
2174 err = PTR_ERR(pmc->pctl_dev);
2175 dev_err(pmc->dev, "failed to register pin controller: %d\n",
2176 err);
2177 return err;
2178 }
2179
2180 return 0;
2181 }
2182
reset_reason_show(struct device * dev,struct device_attribute * attr,char * buf)2183 static ssize_t reset_reason_show(struct device *dev,
2184 struct device_attribute *attr, char *buf)
2185 {
2186 u32 value;
2187
2188 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
2189 value &= pmc->soc->regs->rst_source_mask;
2190 value >>= pmc->soc->regs->rst_source_shift;
2191
2192 if (WARN_ON(value >= pmc->soc->num_reset_sources))
2193 return sprintf(buf, "%s\n", "UNKNOWN");
2194
2195 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]);
2196 }
2197
2198 static DEVICE_ATTR_RO(reset_reason);
2199
reset_level_show(struct device * dev,struct device_attribute * attr,char * buf)2200 static ssize_t reset_level_show(struct device *dev,
2201 struct device_attribute *attr, char *buf)
2202 {
2203 u32 value;
2204
2205 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
2206 value &= pmc->soc->regs->rst_level_mask;
2207 value >>= pmc->soc->regs->rst_level_shift;
2208
2209 if (WARN_ON(value >= pmc->soc->num_reset_levels))
2210 return sprintf(buf, "%s\n", "UNKNOWN");
2211
2212 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]);
2213 }
2214
2215 static DEVICE_ATTR_RO(reset_level);
2216
tegra_pmc_reset_sysfs_init(struct tegra_pmc * pmc)2217 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc)
2218 {
2219 struct device *dev = pmc->dev;
2220 int err = 0;
2221
2222 if (pmc->soc->reset_sources) {
2223 err = device_create_file(dev, &dev_attr_reset_reason);
2224 if (err < 0)
2225 dev_warn(dev,
2226 "failed to create attr \"reset_reason\": %d\n",
2227 err);
2228 }
2229
2230 if (pmc->soc->reset_levels) {
2231 err = device_create_file(dev, &dev_attr_reset_level);
2232 if (err < 0)
2233 dev_warn(dev,
2234 "failed to create attr \"reset_level\": %d\n",
2235 err);
2236 }
2237 }
2238
tegra_pmc_irq_translate(struct irq_domain * domain,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)2239 static int tegra_pmc_irq_translate(struct irq_domain *domain,
2240 struct irq_fwspec *fwspec,
2241 unsigned long *hwirq,
2242 unsigned int *type)
2243 {
2244 if (WARN_ON(fwspec->param_count < 2))
2245 return -EINVAL;
2246
2247 *hwirq = fwspec->param[0];
2248 *type = fwspec->param[1];
2249
2250 return 0;
2251 }
2252
tegra_pmc_irq_alloc(struct irq_domain * domain,unsigned int virq,unsigned int num_irqs,void * data)2253 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq,
2254 unsigned int num_irqs, void *data)
2255 {
2256 struct tegra_pmc *pmc = domain->host_data;
2257 const struct tegra_pmc_soc *soc = pmc->soc;
2258 struct irq_fwspec *fwspec = data;
2259 unsigned int i;
2260 int err = 0;
2261
2262 if (WARN_ON(num_irqs > 1))
2263 return -EINVAL;
2264
2265 for (i = 0; i < soc->num_wake_events; i++) {
2266 const struct tegra_wake_event *event = &soc->wake_events[i];
2267
2268 /* IRQ and simple wake events */
2269 if (fwspec->param_count == 2) {
2270 struct irq_fwspec spec;
2271
2272 if (event->id != fwspec->param[0])
2273 continue;
2274
2275 err = irq_domain_set_hwirq_and_chip(domain, virq,
2276 event->id,
2277 &pmc->irq, pmc);
2278 if (err < 0)
2279 break;
2280
2281 /* simple hierarchies stop at the PMC level */
2282 if (event->irq == 0) {
2283 err = irq_domain_disconnect_hierarchy(domain->parent, virq);
2284 break;
2285 }
2286
2287 spec.fwnode = &pmc->dev->of_node->fwnode;
2288 spec.param_count = 3;
2289 spec.param[0] = GIC_SPI;
2290 spec.param[1] = event->irq;
2291 spec.param[2] = fwspec->param[1];
2292
2293 err = irq_domain_alloc_irqs_parent(domain, virq,
2294 num_irqs, &spec);
2295
2296 break;
2297 }
2298
2299 /* GPIO wake events */
2300 if (fwspec->param_count == 3) {
2301 if (event->gpio.instance != fwspec->param[0] ||
2302 event->gpio.pin != fwspec->param[1])
2303 continue;
2304
2305 err = irq_domain_set_hwirq_and_chip(domain, virq,
2306 event->id,
2307 &pmc->irq, pmc);
2308
2309 /* GPIO hierarchies stop at the PMC level */
2310 if (!err && domain->parent)
2311 err = irq_domain_disconnect_hierarchy(domain->parent,
2312 virq);
2313 break;
2314 }
2315 }
2316
2317 /* If there is no wake-up event, there is no PMC mapping */
2318 if (i == soc->num_wake_events)
2319 err = irq_domain_disconnect_hierarchy(domain, virq);
2320
2321 return err;
2322 }
2323
2324 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = {
2325 .translate = tegra_pmc_irq_translate,
2326 .alloc = tegra_pmc_irq_alloc,
2327 };
2328
tegra210_pmc_irq_set_wake(struct irq_data * data,unsigned int on)2329 static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2330 {
2331 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2332 unsigned int offset, bit;
2333 u32 value;
2334
2335 offset = data->hwirq / 32;
2336 bit = data->hwirq % 32;
2337
2338 /* clear wake status */
2339 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS);
2340 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS);
2341
2342 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS);
2343 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS);
2344
2345 /* enable PMC wake */
2346 if (data->hwirq >= 32)
2347 offset = PMC_WAKE2_MASK;
2348 else
2349 offset = PMC_WAKE_MASK;
2350
2351 value = tegra_pmc_readl(pmc, offset);
2352
2353 if (on)
2354 value |= BIT(bit);
2355 else
2356 value &= ~BIT(bit);
2357
2358 tegra_pmc_writel(pmc, value, offset);
2359
2360 return 0;
2361 }
2362
tegra210_pmc_irq_set_type(struct irq_data * data,unsigned int type)2363 static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2364 {
2365 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2366 unsigned int offset, bit;
2367 u32 value;
2368
2369 offset = data->hwirq / 32;
2370 bit = data->hwirq % 32;
2371
2372 if (data->hwirq >= 32)
2373 offset = PMC_WAKE2_LEVEL;
2374 else
2375 offset = PMC_WAKE_LEVEL;
2376
2377 value = tegra_pmc_readl(pmc, offset);
2378
2379 switch (type) {
2380 case IRQ_TYPE_EDGE_RISING:
2381 case IRQ_TYPE_LEVEL_HIGH:
2382 value |= BIT(bit);
2383 break;
2384
2385 case IRQ_TYPE_EDGE_FALLING:
2386 case IRQ_TYPE_LEVEL_LOW:
2387 value &= ~BIT(bit);
2388 break;
2389
2390 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2391 value ^= BIT(bit);
2392 break;
2393
2394 default:
2395 return -EINVAL;
2396 }
2397
2398 tegra_pmc_writel(pmc, value, offset);
2399
2400 return 0;
2401 }
2402
tegra186_pmc_set_wake_filters(struct tegra_pmc * pmc)2403 static void tegra186_pmc_set_wake_filters(struct tegra_pmc *pmc)
2404 {
2405 u32 value;
2406
2407 /* SW Wake (wake83) needs SR_CAPTURE filter to be enabled */
2408 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID));
2409 value |= WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN;
2410 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID));
2411 dev_dbg(pmc->dev, "WAKE_AOWAKE_CNTRL_83 = 0x%x\n", value);
2412 }
2413
tegra186_pmc_irq_set_wake(struct irq_data * data,unsigned int on)2414 static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2415 {
2416 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2417 unsigned int offset, bit;
2418 u32 value;
2419
2420 offset = data->hwirq / 32;
2421 bit = data->hwirq % 32;
2422
2423 /* clear wake status */
2424 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq));
2425
2426 /* route wake to tier 2 */
2427 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2428
2429 if (!on)
2430 value &= ~(1 << bit);
2431 else
2432 value |= 1 << bit;
2433
2434 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2435
2436 /* enable wakeup event */
2437 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq));
2438
2439 return 0;
2440 }
2441
tegra186_pmc_irq_set_type(struct irq_data * data,unsigned int type)2442 static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2443 {
2444 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2445 u32 value;
2446
2447 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2448
2449 switch (type) {
2450 case IRQ_TYPE_EDGE_RISING:
2451 case IRQ_TYPE_LEVEL_HIGH:
2452 value |= WAKE_AOWAKE_CNTRL_LEVEL;
2453 set_bit(data->hwirq, pmc->wake_type_level_map);
2454 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map);
2455 break;
2456
2457 case IRQ_TYPE_EDGE_FALLING:
2458 case IRQ_TYPE_LEVEL_LOW:
2459 value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
2460 clear_bit(data->hwirq, pmc->wake_type_level_map);
2461 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map);
2462 break;
2463
2464 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2465 value ^= WAKE_AOWAKE_CNTRL_LEVEL;
2466 clear_bit(data->hwirq, pmc->wake_type_level_map);
2467 set_bit(data->hwirq, pmc->wake_type_dual_edge_map);
2468 break;
2469
2470 default:
2471 return -EINVAL;
2472 }
2473
2474 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2475
2476 return 0;
2477 }
2478
tegra_irq_mask_parent(struct irq_data * data)2479 static void tegra_irq_mask_parent(struct irq_data *data)
2480 {
2481 if (data->parent_data)
2482 irq_chip_mask_parent(data);
2483 }
2484
tegra_irq_unmask_parent(struct irq_data * data)2485 static void tegra_irq_unmask_parent(struct irq_data *data)
2486 {
2487 if (data->parent_data)
2488 irq_chip_unmask_parent(data);
2489 }
2490
tegra_irq_eoi_parent(struct irq_data * data)2491 static void tegra_irq_eoi_parent(struct irq_data *data)
2492 {
2493 if (data->parent_data)
2494 irq_chip_eoi_parent(data);
2495 }
2496
tegra_irq_set_affinity_parent(struct irq_data * data,const struct cpumask * dest,bool force)2497 static int tegra_irq_set_affinity_parent(struct irq_data *data,
2498 const struct cpumask *dest,
2499 bool force)
2500 {
2501 if (data->parent_data)
2502 return irq_chip_set_affinity_parent(data, dest, force);
2503
2504 return -EINVAL;
2505 }
2506
tegra_pmc_irq_init(struct tegra_pmc * pmc)2507 static int tegra_pmc_irq_init(struct tegra_pmc *pmc)
2508 {
2509 struct irq_domain *parent = NULL;
2510 struct device_node *np;
2511
2512 np = of_irq_find_parent(pmc->dev->of_node);
2513 if (np) {
2514 parent = irq_find_host(np);
2515 of_node_put(np);
2516 }
2517
2518 if (!parent)
2519 return 0;
2520
2521 pmc->irq.name = dev_name(pmc->dev);
2522 pmc->irq.irq_mask = tegra_irq_mask_parent;
2523 pmc->irq.irq_unmask = tegra_irq_unmask_parent;
2524 pmc->irq.irq_eoi = tegra_irq_eoi_parent;
2525 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent;
2526 pmc->irq.irq_set_type = pmc->soc->irq_set_type;
2527 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake;
2528
2529 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node,
2530 &tegra_pmc_irq_domain_ops, pmc);
2531 if (!pmc->domain) {
2532 dev_err(pmc->dev, "failed to allocate domain\n");
2533 return -ENOMEM;
2534 }
2535
2536 return 0;
2537 }
2538
tegra_pmc_clk_notify_cb(struct notifier_block * nb,unsigned long action,void * ptr)2539 static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
2540 unsigned long action, void *ptr)
2541 {
2542 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb);
2543 struct clk_notifier_data *data = ptr;
2544
2545 switch (action) {
2546 case PRE_RATE_CHANGE:
2547 mutex_lock(&pmc->powergates_lock);
2548 break;
2549
2550 case POST_RATE_CHANGE:
2551 pmc->rate = data->new_rate;
2552 fallthrough;
2553
2554 case ABORT_RATE_CHANGE:
2555 mutex_unlock(&pmc->powergates_lock);
2556 break;
2557
2558 default:
2559 WARN_ON_ONCE(1);
2560 return notifier_from_errno(-EINVAL);
2561 }
2562
2563 return NOTIFY_OK;
2564 }
2565
pmc_clk_fence_udelay(u32 offset)2566 static void pmc_clk_fence_udelay(u32 offset)
2567 {
2568 tegra_pmc_readl(pmc, offset);
2569 /* pmc clk propagation delay 2 us */
2570 udelay(2);
2571 }
2572
pmc_clk_mux_get_parent(struct clk_hw * hw)2573 static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
2574 {
2575 struct pmc_clk *clk = to_pmc_clk(hw);
2576 u32 val;
2577
2578 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
2579 val &= PMC_CLK_OUT_MUX_MASK;
2580
2581 return val;
2582 }
2583
pmc_clk_mux_set_parent(struct clk_hw * hw,u8 index)2584 static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
2585 {
2586 struct pmc_clk *clk = to_pmc_clk(hw);
2587 u32 val;
2588
2589 val = tegra_pmc_readl(pmc, clk->offs);
2590 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift);
2591 val |= index << clk->mux_shift;
2592 tegra_pmc_writel(pmc, val, clk->offs);
2593 pmc_clk_fence_udelay(clk->offs);
2594
2595 return 0;
2596 }
2597
pmc_clk_is_enabled(struct clk_hw * hw)2598 static int pmc_clk_is_enabled(struct clk_hw *hw)
2599 {
2600 struct pmc_clk *clk = to_pmc_clk(hw);
2601 u32 val;
2602
2603 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift);
2604
2605 return val ? 1 : 0;
2606 }
2607
pmc_clk_set_state(unsigned long offs,u32 shift,int state)2608 static void pmc_clk_set_state(unsigned long offs, u32 shift, int state)
2609 {
2610 u32 val;
2611
2612 val = tegra_pmc_readl(pmc, offs);
2613 val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
2614 tegra_pmc_writel(pmc, val, offs);
2615 pmc_clk_fence_udelay(offs);
2616 }
2617
pmc_clk_enable(struct clk_hw * hw)2618 static int pmc_clk_enable(struct clk_hw *hw)
2619 {
2620 struct pmc_clk *clk = to_pmc_clk(hw);
2621
2622 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1);
2623
2624 return 0;
2625 }
2626
pmc_clk_disable(struct clk_hw * hw)2627 static void pmc_clk_disable(struct clk_hw *hw)
2628 {
2629 struct pmc_clk *clk = to_pmc_clk(hw);
2630
2631 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0);
2632 }
2633
2634 static const struct clk_ops pmc_clk_ops = {
2635 .get_parent = pmc_clk_mux_get_parent,
2636 .set_parent = pmc_clk_mux_set_parent,
2637 .determine_rate = __clk_mux_determine_rate,
2638 .is_enabled = pmc_clk_is_enabled,
2639 .enable = pmc_clk_enable,
2640 .disable = pmc_clk_disable,
2641 };
2642
2643 static struct clk *
tegra_pmc_clk_out_register(struct tegra_pmc * pmc,const struct pmc_clk_init_data * data,unsigned long offset)2644 tegra_pmc_clk_out_register(struct tegra_pmc *pmc,
2645 const struct pmc_clk_init_data *data,
2646 unsigned long offset)
2647 {
2648 struct clk_init_data init;
2649 struct pmc_clk *pmc_clk;
2650
2651 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL);
2652 if (!pmc_clk)
2653 return ERR_PTR(-ENOMEM);
2654
2655 init.name = data->name;
2656 init.ops = &pmc_clk_ops;
2657 init.parent_names = data->parents;
2658 init.num_parents = data->num_parents;
2659 init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
2660 CLK_SET_PARENT_GATE;
2661
2662 pmc_clk->hw.init = &init;
2663 pmc_clk->offs = offset;
2664 pmc_clk->mux_shift = data->mux_shift;
2665 pmc_clk->force_en_shift = data->force_en_shift;
2666
2667 return clk_register(NULL, &pmc_clk->hw);
2668 }
2669
pmc_clk_gate_is_enabled(struct clk_hw * hw)2670 static int pmc_clk_gate_is_enabled(struct clk_hw *hw)
2671 {
2672 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2673
2674 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;
2675 }
2676
pmc_clk_gate_enable(struct clk_hw * hw)2677 static int pmc_clk_gate_enable(struct clk_hw *hw)
2678 {
2679 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2680
2681 pmc_clk_set_state(gate->offs, gate->shift, 1);
2682
2683 return 0;
2684 }
2685
pmc_clk_gate_disable(struct clk_hw * hw)2686 static void pmc_clk_gate_disable(struct clk_hw *hw)
2687 {
2688 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2689
2690 pmc_clk_set_state(gate->offs, gate->shift, 0);
2691 }
2692
2693 static const struct clk_ops pmc_clk_gate_ops = {
2694 .is_enabled = pmc_clk_gate_is_enabled,
2695 .enable = pmc_clk_gate_enable,
2696 .disable = pmc_clk_gate_disable,
2697 };
2698
2699 static struct clk *
tegra_pmc_clk_gate_register(struct tegra_pmc * pmc,const char * name,const char * parent_name,unsigned long offset,u32 shift)2700 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name,
2701 const char *parent_name, unsigned long offset,
2702 u32 shift)
2703 {
2704 struct clk_init_data init;
2705 struct pmc_clk_gate *gate;
2706
2707 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL);
2708 if (!gate)
2709 return ERR_PTR(-ENOMEM);
2710
2711 init.name = name;
2712 init.ops = &pmc_clk_gate_ops;
2713 init.parent_names = &parent_name;
2714 init.num_parents = 1;
2715 init.flags = 0;
2716
2717 gate->hw.init = &init;
2718 gate->offs = offset;
2719 gate->shift = shift;
2720
2721 return clk_register(NULL, &gate->hw);
2722 }
2723
tegra_pmc_clock_register(struct tegra_pmc * pmc,struct device_node * np)2724 static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
2725 struct device_node *np)
2726 {
2727 struct clk *clk;
2728 struct clk_onecell_data *clk_data;
2729 unsigned int num_clks;
2730 int i, err;
2731
2732 num_clks = pmc->soc->num_pmc_clks;
2733 if (pmc->soc->has_blink_output)
2734 num_clks += 1;
2735
2736 if (!num_clks)
2737 return;
2738
2739 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL);
2740 if (!clk_data)
2741 return;
2742
2743 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX,
2744 sizeof(*clk_data->clks), GFP_KERNEL);
2745 if (!clk_data->clks)
2746 return;
2747
2748 clk_data->clk_num = TEGRA_PMC_CLK_MAX;
2749
2750 for (i = 0; i < TEGRA_PMC_CLK_MAX; i++)
2751 clk_data->clks[i] = ERR_PTR(-ENOENT);
2752
2753 for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
2754 const struct pmc_clk_init_data *data;
2755
2756 data = pmc->soc->pmc_clks_data + i;
2757
2758 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL);
2759 if (IS_ERR(clk)) {
2760 dev_warn(pmc->dev, "unable to register clock %s: %d\n",
2761 data->name, PTR_ERR_OR_ZERO(clk));
2762 return;
2763 }
2764
2765 err = clk_register_clkdev(clk, data->name, NULL);
2766 if (err) {
2767 dev_warn(pmc->dev,
2768 "unable to register %s clock lookup: %d\n",
2769 data->name, err);
2770 return;
2771 }
2772
2773 clk_data->clks[data->clk_id] = clk;
2774 }
2775
2776 if (pmc->soc->has_blink_output) {
2777 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER);
2778 clk = tegra_pmc_clk_gate_register(pmc,
2779 "pmc_blink_override",
2780 "clk_32k",
2781 PMC_DPD_PADS_ORIDE,
2782 PMC_DPD_PADS_ORIDE_BLINK);
2783 if (IS_ERR(clk)) {
2784 dev_warn(pmc->dev,
2785 "unable to register pmc_blink_override: %d\n",
2786 PTR_ERR_OR_ZERO(clk));
2787 return;
2788 }
2789
2790 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink",
2791 "pmc_blink_override",
2792 PMC_CNTRL,
2793 PMC_CNTRL_BLINK_EN);
2794 if (IS_ERR(clk)) {
2795 dev_warn(pmc->dev,
2796 "unable to register pmc_blink: %d\n",
2797 PTR_ERR_OR_ZERO(clk));
2798 return;
2799 }
2800
2801 err = clk_register_clkdev(clk, "pmc_blink", NULL);
2802 if (err) {
2803 dev_warn(pmc->dev,
2804 "unable to register pmc_blink lookup: %d\n",
2805 err);
2806 return;
2807 }
2808
2809 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk;
2810 }
2811
2812 err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
2813 if (err)
2814 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n",
2815 err);
2816 }
2817
2818 static const struct regmap_range pmc_usb_sleepwalk_ranges[] = {
2819 regmap_reg_range(PMC_USB_DEBOUNCE_DEL, PMC_USB_AO),
2820 regmap_reg_range(PMC_UTMIP_UHSIC_TRIGGERS, PMC_UTMIP_UHSIC_SAVED_STATE),
2821 regmap_reg_range(PMC_UTMIP_TERM_PAD_CFG, PMC_UTMIP_UHSIC_FAKE),
2822 regmap_reg_range(PMC_UTMIP_UHSIC_LINE_WAKEUP, PMC_UTMIP_UHSIC_LINE_WAKEUP),
2823 regmap_reg_range(PMC_UTMIP_BIAS_MASTER_CNTRL, PMC_UTMIP_MASTER_CONFIG),
2824 regmap_reg_range(PMC_UTMIP_UHSIC2_TRIGGERS, PMC_UTMIP_MASTER2_CONFIG),
2825 regmap_reg_range(PMC_UTMIP_PAD_CFG0, PMC_UTMIP_UHSIC_SLEEP_CFG1),
2826 regmap_reg_range(PMC_UTMIP_SLEEPWALK_P3, PMC_UTMIP_SLEEPWALK_P3),
2827 };
2828
2829 static const struct regmap_access_table pmc_usb_sleepwalk_table = {
2830 .yes_ranges = pmc_usb_sleepwalk_ranges,
2831 .n_yes_ranges = ARRAY_SIZE(pmc_usb_sleepwalk_ranges),
2832 };
2833
tegra_pmc_regmap_readl(void * context,unsigned int offset,unsigned int * value)2834 static int tegra_pmc_regmap_readl(void *context, unsigned int offset, unsigned int *value)
2835 {
2836 struct tegra_pmc *pmc = context;
2837
2838 *value = tegra_pmc_readl(pmc, offset);
2839 return 0;
2840 }
2841
tegra_pmc_regmap_writel(void * context,unsigned int offset,unsigned int value)2842 static int tegra_pmc_regmap_writel(void *context, unsigned int offset, unsigned int value)
2843 {
2844 struct tegra_pmc *pmc = context;
2845
2846 tegra_pmc_writel(pmc, value, offset);
2847 return 0;
2848 }
2849
2850 static const struct regmap_config usb_sleepwalk_regmap_config = {
2851 .name = "usb_sleepwalk",
2852 .reg_bits = 32,
2853 .val_bits = 32,
2854 .reg_stride = 4,
2855 .fast_io = true,
2856 .rd_table = &pmc_usb_sleepwalk_table,
2857 .wr_table = &pmc_usb_sleepwalk_table,
2858 .reg_read = tegra_pmc_regmap_readl,
2859 .reg_write = tegra_pmc_regmap_writel,
2860 };
2861
tegra_pmc_regmap_init(struct tegra_pmc * pmc)2862 static int tegra_pmc_regmap_init(struct tegra_pmc *pmc)
2863 {
2864 struct regmap *regmap;
2865 int err;
2866
2867 if (pmc->soc->has_usb_sleepwalk) {
2868 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config);
2869 if (IS_ERR(regmap)) {
2870 err = PTR_ERR(regmap);
2871 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err);
2872 return err;
2873 }
2874 }
2875
2876 return 0;
2877 }
2878
tegra_pmc_reset_suspend_mode(void * data)2879 static void tegra_pmc_reset_suspend_mode(void *data)
2880 {
2881 pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY;
2882 }
2883
tegra_pmc_probe(struct platform_device * pdev)2884 static int tegra_pmc_probe(struct platform_device *pdev)
2885 {
2886 void __iomem *base;
2887 struct resource *res;
2888 int err;
2889
2890 /*
2891 * Early initialisation should have configured an initial
2892 * register mapping and setup the soc data pointer. If these
2893 * are not valid then something went badly wrong!
2894 */
2895 if (WARN_ON(!pmc->base || !pmc->soc))
2896 return -ENODEV;
2897
2898 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
2899 if (err < 0)
2900 return err;
2901
2902 err = devm_add_action_or_reset(&pdev->dev, tegra_pmc_reset_suspend_mode,
2903 NULL);
2904 if (err)
2905 return err;
2906
2907 /* take over the memory region from the early initialization */
2908 base = devm_platform_ioremap_resource(pdev, 0);
2909 if (IS_ERR(base))
2910 return PTR_ERR(base);
2911
2912 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake");
2913 if (res) {
2914 pmc->wake = devm_ioremap_resource(&pdev->dev, res);
2915 if (IS_ERR(pmc->wake))
2916 return PTR_ERR(pmc->wake);
2917 } else {
2918 pmc->wake = base;
2919 }
2920
2921 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag");
2922 if (res) {
2923 pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
2924 if (IS_ERR(pmc->aotag))
2925 return PTR_ERR(pmc->aotag);
2926 } else {
2927 pmc->aotag = base;
2928 }
2929
2930 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch");
2931 if (res) {
2932 pmc->scratch = devm_ioremap_resource(&pdev->dev, res);
2933 if (IS_ERR(pmc->scratch))
2934 return PTR_ERR(pmc->scratch);
2935 } else {
2936 pmc->scratch = base;
2937 }
2938
2939 pmc->clk = devm_clk_get_optional(&pdev->dev, "pclk");
2940 if (IS_ERR(pmc->clk))
2941 return dev_err_probe(&pdev->dev, PTR_ERR(pmc->clk),
2942 "failed to get pclk\n");
2943
2944 /*
2945 * PMC should be last resort for restarting since it soft-resets
2946 * CPU without resetting everything else.
2947 */
2948 err = devm_register_reboot_notifier(&pdev->dev,
2949 &tegra_pmc_reboot_notifier);
2950 if (err) {
2951 dev_err(&pdev->dev, "unable to register reboot notifier, %d\n",
2952 err);
2953 return err;
2954 }
2955
2956 err = devm_register_sys_off_handler(&pdev->dev,
2957 SYS_OFF_MODE_RESTART,
2958 SYS_OFF_PRIO_LOW,
2959 tegra_pmc_restart_handler, NULL);
2960 if (err) {
2961 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n",
2962 err);
2963 return err;
2964 }
2965
2966 /*
2967 * PMC should be primary power-off method if it soft-resets CPU,
2968 * asking bootloader to shutdown hardware.
2969 */
2970 err = devm_register_sys_off_handler(&pdev->dev,
2971 SYS_OFF_MODE_POWER_OFF,
2972 SYS_OFF_PRIO_FIRMWARE,
2973 tegra_pmc_power_off_handler, NULL);
2974 if (err) {
2975 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n",
2976 err);
2977 return err;
2978 }
2979
2980 /*
2981 * PCLK clock rate can't be retrieved using CLK API because it
2982 * causes lockup if CPU enters LP2 idle state from some other
2983 * CLK notifier, hence we're caching the rate's value locally.
2984 */
2985 if (pmc->clk) {
2986 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb;
2987 err = devm_clk_notifier_register(&pdev->dev, pmc->clk,
2988 &pmc->clk_nb);
2989 if (err) {
2990 dev_err(&pdev->dev,
2991 "failed to register clk notifier\n");
2992 return err;
2993 }
2994
2995 pmc->rate = clk_get_rate(pmc->clk);
2996 }
2997
2998 pmc->dev = &pdev->dev;
2999
3000 err = tegra_pmc_init(pmc);
3001 if (err < 0) {
3002 dev_err(&pdev->dev, "failed to initialize PMC: %d\n", err);
3003 return err;
3004 }
3005
3006 tegra_pmc_init_tsense_reset(pmc);
3007
3008 tegra_pmc_reset_sysfs_init(pmc);
3009
3010 err = tegra_pmc_pinctrl_init(pmc);
3011 if (err)
3012 goto cleanup_sysfs;
3013
3014 err = tegra_pmc_regmap_init(pmc);
3015 if (err < 0)
3016 goto cleanup_sysfs;
3017
3018 err = tegra_powergate_init(pmc, pdev->dev.of_node);
3019 if (err < 0)
3020 goto cleanup_powergates;
3021
3022 err = tegra_pmc_irq_init(pmc);
3023 if (err < 0)
3024 goto cleanup_powergates;
3025
3026 mutex_lock(&pmc->powergates_lock);
3027 iounmap(pmc->base);
3028 pmc->base = base;
3029 mutex_unlock(&pmc->powergates_lock);
3030
3031 tegra_pmc_clock_register(pmc, pdev->dev.of_node);
3032 platform_set_drvdata(pdev, pmc);
3033 tegra_pm_init_suspend();
3034
3035 /* Some wakes require specific filter configuration */
3036 if (pmc->soc->set_wake_filters)
3037 pmc->soc->set_wake_filters(pmc);
3038
3039 debugfs_create_file("powergate", 0444, NULL, NULL, &powergate_fops);
3040
3041 return 0;
3042
3043 cleanup_powergates:
3044 tegra_powergate_remove_all(pdev->dev.of_node);
3045 cleanup_sysfs:
3046 device_remove_file(&pdev->dev, &dev_attr_reset_reason);
3047 device_remove_file(&pdev->dev, &dev_attr_reset_level);
3048
3049 return err;
3050 }
3051
3052 /*
3053 * Ensures that sufficient time is passed for a register write to
3054 * serialize into the 32KHz domain.
3055 */
wke_32kwritel(struct tegra_pmc * pmc,u32 value,unsigned int offset)3056 static void wke_32kwritel(struct tegra_pmc *pmc, u32 value, unsigned int offset)
3057 {
3058 writel(value, pmc->wake + offset);
3059 udelay(130);
3060 }
3061
wke_write_wake_level(struct tegra_pmc * pmc,int wake,int level)3062 static void wke_write_wake_level(struct tegra_pmc *pmc, int wake, int level)
3063 {
3064 unsigned int offset = WAKE_AOWAKE_CNTRL(wake);
3065 u32 value;
3066
3067 value = readl(pmc->wake + offset);
3068 if (level)
3069 value |= WAKE_AOWAKE_CNTRL_LEVEL;
3070 else
3071 value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
3072
3073 writel(value, pmc->wake + offset);
3074 }
3075
wke_write_wake_levels(struct tegra_pmc * pmc)3076 static void wke_write_wake_levels(struct tegra_pmc *pmc)
3077 {
3078 unsigned int i;
3079
3080 for (i = 0; i < pmc->soc->max_wake_events; i++)
3081 wke_write_wake_level(pmc, i, test_bit(i, pmc->wake_cntrl_level_map));
3082 }
3083
wke_clear_sw_wake_status(struct tegra_pmc * pmc)3084 static void wke_clear_sw_wake_status(struct tegra_pmc *pmc)
3085 {
3086 wke_32kwritel(pmc, 1, WAKE_AOWAKE_SW_STATUS_W_0);
3087 }
3088
wke_read_sw_wake_status(struct tegra_pmc * pmc)3089 static void wke_read_sw_wake_status(struct tegra_pmc *pmc)
3090 {
3091 unsigned long status;
3092 unsigned int wake, i;
3093
3094 for (i = 0; i < pmc->soc->max_wake_events; i++)
3095 wke_write_wake_level(pmc, i, 0);
3096
3097 wke_clear_sw_wake_status(pmc);
3098
3099 wke_32kwritel(pmc, 1, WAKE_LATCH_SW);
3100
3101 /*
3102 * WAKE_AOWAKE_SW_STATUS is edge triggered, so in order to
3103 * obtain the current status of the input wake signals, change
3104 * the polarity of the wake level from 0->1 while latching to force
3105 * a positive edge if the sampled signal is '1'.
3106 */
3107 for (i = 0; i < pmc->soc->max_wake_events; i++)
3108 wke_write_wake_level(pmc, i, 1);
3109
3110 /*
3111 * Wait for the update to be synced into the 32kHz domain,
3112 * and let enough time lapse, so that the wake signals have time to
3113 * be sampled.
3114 */
3115 udelay(300);
3116
3117 wke_32kwritel(pmc, 0, WAKE_LATCH_SW);
3118
3119 bitmap_zero(pmc->wake_sw_status_map, pmc->soc->max_wake_events);
3120
3121 for (i = 0; i < pmc->soc->max_wake_vectors; i++) {
3122 status = readl(pmc->wake + WAKE_AOWAKE_SW_STATUS(i));
3123
3124 for_each_set_bit(wake, &status, 32)
3125 set_bit(wake + (i * 32), pmc->wake_sw_status_map);
3126 }
3127 }
3128
wke_clear_wake_status(struct tegra_pmc * pmc)3129 static void wke_clear_wake_status(struct tegra_pmc *pmc)
3130 {
3131 unsigned long status;
3132 unsigned int i, wake;
3133 u32 mask;
3134
3135 for (i = 0; i < pmc->soc->max_wake_vectors; i++) {
3136 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i));
3137 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask;
3138
3139 for_each_set_bit(wake, &status, 32)
3140 wke_32kwritel(pmc, 0x1, WAKE_AOWAKE_STATUS_W((i * 32) + wake));
3141 }
3142 }
3143
3144 /* translate sc7 wake sources back into IRQs to catch edge triggered wakeups */
tegra186_pmc_process_wake_events(struct tegra_pmc * pmc,unsigned int index,unsigned long status)3145 static void tegra186_pmc_process_wake_events(struct tegra_pmc *pmc, unsigned int index,
3146 unsigned long status)
3147 {
3148 unsigned int wake;
3149
3150 dev_dbg(pmc->dev, "Wake[%d:%d] status=%#lx\n", (index * 32) + 31, index * 32, status);
3151
3152 for_each_set_bit(wake, &status, 32) {
3153 irq_hw_number_t hwirq = wake + 32 * index;
3154 struct irq_desc *desc;
3155 unsigned int irq;
3156
3157 irq = irq_find_mapping(pmc->domain, hwirq);
3158
3159 desc = irq_to_desc(irq);
3160 if (!desc || !desc->action || !desc->action->name) {
3161 dev_dbg(pmc->dev, "Resume caused by WAKE%ld, IRQ %d\n", hwirq, irq);
3162 continue;
3163 }
3164
3165 dev_dbg(pmc->dev, "Resume caused by WAKE%ld, %s\n", hwirq, desc->action->name);
3166 generic_handle_irq(irq);
3167 }
3168 }
3169
tegra186_pmc_wake_syscore_resume(void)3170 static void tegra186_pmc_wake_syscore_resume(void)
3171 {
3172 u32 status, mask;
3173 unsigned int i;
3174
3175 for (i = 0; i < pmc->soc->max_wake_vectors; i++) {
3176 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i));
3177 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask;
3178
3179 tegra186_pmc_process_wake_events(pmc, i, status);
3180 }
3181 }
3182
tegra186_pmc_wake_syscore_suspend(void)3183 static int tegra186_pmc_wake_syscore_suspend(void)
3184 {
3185 wke_read_sw_wake_status(pmc);
3186
3187 /* flip the wakeup trigger for dual-edge triggered pads
3188 * which are currently asserting as wakeups
3189 */
3190 bitmap_andnot(pmc->wake_cntrl_level_map, pmc->wake_type_dual_edge_map,
3191 pmc->wake_sw_status_map, pmc->soc->max_wake_events);
3192 bitmap_or(pmc->wake_cntrl_level_map, pmc->wake_cntrl_level_map,
3193 pmc->wake_type_level_map, pmc->soc->max_wake_events);
3194
3195 /* Clear PMC Wake Status registers while going to suspend */
3196 wke_clear_wake_status(pmc);
3197 wke_write_wake_levels(pmc);
3198
3199 return 0;
3200 }
3201
3202 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
tegra_pmc_suspend(struct device * dev)3203 static int tegra_pmc_suspend(struct device *dev)
3204 {
3205 struct tegra_pmc *pmc = dev_get_drvdata(dev);
3206
3207 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41);
3208
3209 return 0;
3210 }
3211
tegra_pmc_resume(struct device * dev)3212 static int tegra_pmc_resume(struct device *dev)
3213 {
3214 struct tegra_pmc *pmc = dev_get_drvdata(dev);
3215
3216 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41);
3217
3218 return 0;
3219 }
3220
3221 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
3222
3223 #endif
3224
3225 static const char * const tegra20_powergates[] = {
3226 [TEGRA_POWERGATE_CPU] = "cpu",
3227 [TEGRA_POWERGATE_3D] = "td",
3228 [TEGRA_POWERGATE_VENC] = "venc",
3229 [TEGRA_POWERGATE_VDEC] = "vdec",
3230 [TEGRA_POWERGATE_PCIE] = "pcie",
3231 [TEGRA_POWERGATE_L2] = "l2",
3232 [TEGRA_POWERGATE_MPE] = "mpe",
3233 };
3234
3235 static const struct tegra_pmc_regs tegra20_pmc_regs = {
3236 .scratch0 = 0x50,
3237 .rst_status = 0x1b4,
3238 .rst_source_shift = 0x0,
3239 .rst_source_mask = 0x7,
3240 .rst_level_shift = 0x0,
3241 .rst_level_mask = 0x0,
3242 };
3243
tegra20_pmc_init(struct tegra_pmc * pmc)3244 static void tegra20_pmc_init(struct tegra_pmc *pmc)
3245 {
3246 u32 value, osc, pmu, off;
3247
3248 /* Always enable CPU power request */
3249 value = tegra_pmc_readl(pmc, PMC_CNTRL);
3250 value |= PMC_CNTRL_CPU_PWRREQ_OE;
3251 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3252
3253 value = tegra_pmc_readl(pmc, PMC_CNTRL);
3254
3255 if (pmc->sysclkreq_high)
3256 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
3257 else
3258 value |= PMC_CNTRL_SYSCLK_POLARITY;
3259
3260 if (pmc->corereq_high)
3261 value &= ~PMC_CNTRL_PWRREQ_POLARITY;
3262 else
3263 value |= PMC_CNTRL_PWRREQ_POLARITY;
3264
3265 /* configure the output polarity while the request is tristated */
3266 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3267
3268 /* now enable the request */
3269 value = tegra_pmc_readl(pmc, PMC_CNTRL);
3270 value |= PMC_CNTRL_SYSCLK_OE;
3271 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3272
3273 /* program core timings which are applicable only for suspend state */
3274 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) {
3275 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000);
3276 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000);
3277 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000);
3278 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff),
3279 PMC_COREPWRGOOD_TIMER);
3280 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER);
3281 }
3282 }
3283
tegra20_pmc_setup_irq_polarity(struct tegra_pmc * pmc,struct device_node * np,bool invert)3284 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
3285 struct device_node *np,
3286 bool invert)
3287 {
3288 u32 value;
3289
3290 value = tegra_pmc_readl(pmc, PMC_CNTRL);
3291
3292 if (invert)
3293 value |= PMC_CNTRL_INTR_POLARITY;
3294 else
3295 value &= ~PMC_CNTRL_INTR_POLARITY;
3296
3297 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3298 }
3299
3300 static const struct tegra_pmc_soc tegra20_pmc_soc = {
3301 .supports_core_domain = true,
3302 .num_powergates = ARRAY_SIZE(tegra20_powergates),
3303 .powergates = tegra20_powergates,
3304 .num_cpu_powergates = 0,
3305 .cpu_powergates = NULL,
3306 .has_tsense_reset = false,
3307 .has_gpu_clamps = false,
3308 .needs_mbist_war = false,
3309 .has_impl_33v_pwr = false,
3310 .maybe_tz_only = false,
3311 .num_io_pads = 0,
3312 .io_pads = NULL,
3313 .num_pin_descs = 0,
3314 .pin_descs = NULL,
3315 .regs = &tegra20_pmc_regs,
3316 .init = tegra20_pmc_init,
3317 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3318 .powergate_set = tegra20_powergate_set,
3319 .reset_sources = NULL,
3320 .num_reset_sources = 0,
3321 .reset_levels = NULL,
3322 .num_reset_levels = 0,
3323 .pmc_clks_data = NULL,
3324 .num_pmc_clks = 0,
3325 .has_blink_output = true,
3326 .has_usb_sleepwalk = true,
3327 };
3328
3329 static const char * const tegra30_powergates[] = {
3330 [TEGRA_POWERGATE_CPU] = "cpu0",
3331 [TEGRA_POWERGATE_3D] = "td",
3332 [TEGRA_POWERGATE_VENC] = "venc",
3333 [TEGRA_POWERGATE_VDEC] = "vdec",
3334 [TEGRA_POWERGATE_PCIE] = "pcie",
3335 [TEGRA_POWERGATE_L2] = "l2",
3336 [TEGRA_POWERGATE_MPE] = "mpe",
3337 [TEGRA_POWERGATE_HEG] = "heg",
3338 [TEGRA_POWERGATE_SATA] = "sata",
3339 [TEGRA_POWERGATE_CPU1] = "cpu1",
3340 [TEGRA_POWERGATE_CPU2] = "cpu2",
3341 [TEGRA_POWERGATE_CPU3] = "cpu3",
3342 [TEGRA_POWERGATE_CELP] = "celp",
3343 [TEGRA_POWERGATE_3D1] = "td2",
3344 };
3345
3346 static const u8 tegra30_cpu_powergates[] = {
3347 TEGRA_POWERGATE_CPU,
3348 TEGRA_POWERGATE_CPU1,
3349 TEGRA_POWERGATE_CPU2,
3350 TEGRA_POWERGATE_CPU3,
3351 };
3352
3353 static const char * const tegra30_reset_sources[] = {
3354 "POWER_ON_RESET",
3355 "WATCHDOG",
3356 "SENSOR",
3357 "SW_MAIN",
3358 "LP0"
3359 };
3360
3361 static const struct tegra_pmc_soc tegra30_pmc_soc = {
3362 .supports_core_domain = true,
3363 .num_powergates = ARRAY_SIZE(tegra30_powergates),
3364 .powergates = tegra30_powergates,
3365 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
3366 .cpu_powergates = tegra30_cpu_powergates,
3367 .has_tsense_reset = true,
3368 .has_gpu_clamps = false,
3369 .needs_mbist_war = false,
3370 .has_impl_33v_pwr = false,
3371 .maybe_tz_only = false,
3372 .num_io_pads = 0,
3373 .io_pads = NULL,
3374 .num_pin_descs = 0,
3375 .pin_descs = NULL,
3376 .regs = &tegra20_pmc_regs,
3377 .init = tegra20_pmc_init,
3378 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3379 .powergate_set = tegra20_powergate_set,
3380 .reset_sources = tegra30_reset_sources,
3381 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3382 .reset_levels = NULL,
3383 .num_reset_levels = 0,
3384 .pmc_clks_data = tegra_pmc_clks_data,
3385 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3386 .has_blink_output = true,
3387 .has_usb_sleepwalk = true,
3388 };
3389
3390 static const char * const tegra114_powergates[] = {
3391 [TEGRA_POWERGATE_CPU] = "crail",
3392 [TEGRA_POWERGATE_3D] = "td",
3393 [TEGRA_POWERGATE_VENC] = "venc",
3394 [TEGRA_POWERGATE_VDEC] = "vdec",
3395 [TEGRA_POWERGATE_MPE] = "mpe",
3396 [TEGRA_POWERGATE_HEG] = "heg",
3397 [TEGRA_POWERGATE_CPU1] = "cpu1",
3398 [TEGRA_POWERGATE_CPU2] = "cpu2",
3399 [TEGRA_POWERGATE_CPU3] = "cpu3",
3400 [TEGRA_POWERGATE_CELP] = "celp",
3401 [TEGRA_POWERGATE_CPU0] = "cpu0",
3402 [TEGRA_POWERGATE_C0NC] = "c0nc",
3403 [TEGRA_POWERGATE_C1NC] = "c1nc",
3404 [TEGRA_POWERGATE_DIS] = "dis",
3405 [TEGRA_POWERGATE_DISB] = "disb",
3406 [TEGRA_POWERGATE_XUSBA] = "xusba",
3407 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3408 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3409 };
3410
3411 static const u8 tegra114_cpu_powergates[] = {
3412 TEGRA_POWERGATE_CPU0,
3413 TEGRA_POWERGATE_CPU1,
3414 TEGRA_POWERGATE_CPU2,
3415 TEGRA_POWERGATE_CPU3,
3416 };
3417
3418 static const struct tegra_pmc_soc tegra114_pmc_soc = {
3419 .supports_core_domain = false,
3420 .num_powergates = ARRAY_SIZE(tegra114_powergates),
3421 .powergates = tegra114_powergates,
3422 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
3423 .cpu_powergates = tegra114_cpu_powergates,
3424 .has_tsense_reset = true,
3425 .has_gpu_clamps = false,
3426 .needs_mbist_war = false,
3427 .has_impl_33v_pwr = false,
3428 .maybe_tz_only = false,
3429 .num_io_pads = 0,
3430 .io_pads = NULL,
3431 .num_pin_descs = 0,
3432 .pin_descs = NULL,
3433 .regs = &tegra20_pmc_regs,
3434 .init = tegra20_pmc_init,
3435 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3436 .powergate_set = tegra114_powergate_set,
3437 .reset_sources = tegra30_reset_sources,
3438 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3439 .reset_levels = NULL,
3440 .num_reset_levels = 0,
3441 .pmc_clks_data = tegra_pmc_clks_data,
3442 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3443 .has_blink_output = true,
3444 .has_usb_sleepwalk = true,
3445 };
3446
3447 static const char * const tegra124_powergates[] = {
3448 [TEGRA_POWERGATE_CPU] = "crail",
3449 [TEGRA_POWERGATE_3D] = "3d",
3450 [TEGRA_POWERGATE_VENC] = "venc",
3451 [TEGRA_POWERGATE_PCIE] = "pcie",
3452 [TEGRA_POWERGATE_VDEC] = "vdec",
3453 [TEGRA_POWERGATE_MPE] = "mpe",
3454 [TEGRA_POWERGATE_HEG] = "heg",
3455 [TEGRA_POWERGATE_SATA] = "sata",
3456 [TEGRA_POWERGATE_CPU1] = "cpu1",
3457 [TEGRA_POWERGATE_CPU2] = "cpu2",
3458 [TEGRA_POWERGATE_CPU3] = "cpu3",
3459 [TEGRA_POWERGATE_CELP] = "celp",
3460 [TEGRA_POWERGATE_CPU0] = "cpu0",
3461 [TEGRA_POWERGATE_C0NC] = "c0nc",
3462 [TEGRA_POWERGATE_C1NC] = "c1nc",
3463 [TEGRA_POWERGATE_SOR] = "sor",
3464 [TEGRA_POWERGATE_DIS] = "dis",
3465 [TEGRA_POWERGATE_DISB] = "disb",
3466 [TEGRA_POWERGATE_XUSBA] = "xusba",
3467 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3468 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3469 [TEGRA_POWERGATE_VIC] = "vic",
3470 [TEGRA_POWERGATE_IRAM] = "iram",
3471 };
3472
3473 static const u8 tegra124_cpu_powergates[] = {
3474 TEGRA_POWERGATE_CPU0,
3475 TEGRA_POWERGATE_CPU1,
3476 TEGRA_POWERGATE_CPU2,
3477 TEGRA_POWERGATE_CPU3,
3478 };
3479
3480 #define TEGRA_IO_PAD(_id, _dpd, _request, _status, _voltage, _name) \
3481 ((struct tegra_io_pad_soc) { \
3482 .id = (_id), \
3483 .dpd = (_dpd), \
3484 .request = (_request), \
3485 .status = (_status), \
3486 .voltage = (_voltage), \
3487 .name = (_name), \
3488 })
3489
3490 #define TEGRA_IO_PIN_DESC(_id, _name) \
3491 ((struct pinctrl_pin_desc) { \
3492 .number = (_id), \
3493 .name = (_name), \
3494 })
3495
3496 static const struct tegra_io_pad_soc tegra124_io_pads[] = {
3497 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, UINT_MAX, "audio"),
3498 TEGRA_IO_PAD(TEGRA_IO_PAD_BB, 15, 0x1b8, 0x1bc, UINT_MAX, "bb"),
3499 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, UINT_MAX, "cam"),
3500 TEGRA_IO_PAD(TEGRA_IO_PAD_COMP, 22, 0x1b8, 0x1bc, UINT_MAX, "comp"),
3501 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, UINT_MAX, "csia"),
3502 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, UINT_MAX, "csib"),
3503 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, UINT_MAX, "csie"),
3504 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, UINT_MAX, "dsi"),
3505 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, "dsib"),
3506 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, UINT_MAX, "dsic"),
3507 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, UINT_MAX, "dsid"),
3508 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, UINT_MAX, "hdmi"),
3509 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, UINT_MAX, "hsic"),
3510 TEGRA_IO_PAD(TEGRA_IO_PAD_HV, 6, 0x1c0, 0x1c4, UINT_MAX, "hv"),
3511 TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, UINT_MAX, "lvds"),
3512 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"),
3513 TEGRA_IO_PAD(TEGRA_IO_PAD_NAND, 13, 0x1b8, 0x1bc, UINT_MAX, "nand"),
3514 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"),
3515 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"),
3516 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"),
3517 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x1c0, 0x1c4, UINT_MAX, "pex-cntrl"),
3518 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, UINT_MAX, "sdmmc1"),
3519 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, UINT_MAX, "sdmmc3"),
3520 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 3, 0x1c0, 0x1c4, UINT_MAX, "sdmmc4"),
3521 TEGRA_IO_PAD(TEGRA_IO_PAD_SYS_DDC, 26, 0x1c0, 0x1c4, UINT_MAX, "sys_ddc"),
3522 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, UINT_MAX, "uart"),
3523 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, UINT_MAX, "usb0"),
3524 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, UINT_MAX, "usb1"),
3525 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, UINT_MAX, "usb2"),
3526 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, "usb_bias"),
3527 };
3528
3529 static const struct pinctrl_pin_desc tegra124_pin_descs[] = {
3530 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"),
3531 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_BB, "bb"),
3532 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"),
3533 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_COMP, "comp"),
3534 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),
3535 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),
3536 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),
3537 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"),
3538 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"),
3539 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"),
3540 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"),
3541 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"),
3542 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"),
3543 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HV, "hv"),
3544 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"),
3545 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
3546 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_NAND, "nand"),
3547 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"),
3548 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
3549 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3550 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
3551 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"),
3552 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"),
3553 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"),
3554 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SYS_DDC, "sys_ddc"),
3555 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"),
3556 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"),
3557 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"),
3558 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"),
3559 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb_bias"),
3560 };
3561
3562 static const struct tegra_pmc_soc tegra124_pmc_soc = {
3563 .supports_core_domain = false,
3564 .num_powergates = ARRAY_SIZE(tegra124_powergates),
3565 .powergates = tegra124_powergates,
3566 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
3567 .cpu_powergates = tegra124_cpu_powergates,
3568 .has_tsense_reset = true,
3569 .has_gpu_clamps = true,
3570 .needs_mbist_war = false,
3571 .has_impl_33v_pwr = false,
3572 .maybe_tz_only = false,
3573 .num_io_pads = ARRAY_SIZE(tegra124_io_pads),
3574 .io_pads = tegra124_io_pads,
3575 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs),
3576 .pin_descs = tegra124_pin_descs,
3577 .regs = &tegra20_pmc_regs,
3578 .init = tegra20_pmc_init,
3579 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3580 .powergate_set = tegra114_powergate_set,
3581 .reset_sources = tegra30_reset_sources,
3582 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3583 .reset_levels = NULL,
3584 .num_reset_levels = 0,
3585 .pmc_clks_data = tegra_pmc_clks_data,
3586 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3587 .has_blink_output = true,
3588 .has_usb_sleepwalk = true,
3589 };
3590
3591 static const char * const tegra210_powergates[] = {
3592 [TEGRA_POWERGATE_CPU] = "crail",
3593 [TEGRA_POWERGATE_3D] = "3d",
3594 [TEGRA_POWERGATE_VENC] = "venc",
3595 [TEGRA_POWERGATE_PCIE] = "pcie",
3596 [TEGRA_POWERGATE_MPE] = "mpe",
3597 [TEGRA_POWERGATE_SATA] = "sata",
3598 [TEGRA_POWERGATE_CPU1] = "cpu1",
3599 [TEGRA_POWERGATE_CPU2] = "cpu2",
3600 [TEGRA_POWERGATE_CPU3] = "cpu3",
3601 [TEGRA_POWERGATE_CPU0] = "cpu0",
3602 [TEGRA_POWERGATE_C0NC] = "c0nc",
3603 [TEGRA_POWERGATE_SOR] = "sor",
3604 [TEGRA_POWERGATE_DIS] = "dis",
3605 [TEGRA_POWERGATE_DISB] = "disb",
3606 [TEGRA_POWERGATE_XUSBA] = "xusba",
3607 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3608 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3609 [TEGRA_POWERGATE_VIC] = "vic",
3610 [TEGRA_POWERGATE_IRAM] = "iram",
3611 [TEGRA_POWERGATE_NVDEC] = "nvdec",
3612 [TEGRA_POWERGATE_NVJPG] = "nvjpg",
3613 [TEGRA_POWERGATE_AUD] = "aud",
3614 [TEGRA_POWERGATE_DFD] = "dfd",
3615 [TEGRA_POWERGATE_VE2] = "ve2",
3616 };
3617
3618 static const u8 tegra210_cpu_powergates[] = {
3619 TEGRA_POWERGATE_CPU0,
3620 TEGRA_POWERGATE_CPU1,
3621 TEGRA_POWERGATE_CPU2,
3622 TEGRA_POWERGATE_CPU3,
3623 };
3624
3625 static const struct tegra_io_pad_soc tegra210_io_pads[] = {
3626 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, 5, "audio"),
3627 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x1c0, 0x1c4, 18, "audio-hv"),
3628 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, 10, "cam"),
3629 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, UINT_MAX, "csia"),
3630 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, UINT_MAX, "csib"),
3631 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 10, 0x1c0, 0x1c4, UINT_MAX, "csic"),
3632 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 11, 0x1c0, 0x1c4, UINT_MAX, "csid"),
3633 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, UINT_MAX, "csie"),
3634 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 13, 0x1c0, 0x1c4, UINT_MAX, "csif"),
3635 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x1b8, 0x1bc, 19, "dbg"),
3636 TEGRA_IO_PAD(TEGRA_IO_PAD_DEBUG_NONAO, 26, 0x1b8, 0x1bc, UINT_MAX, "debug-nonao"),
3637 TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC, 18, 0x1c0, 0x1c4, 20, "dmic"),
3638 TEGRA_IO_PAD(TEGRA_IO_PAD_DP, 19, 0x1c0, 0x1c4, UINT_MAX, "dp"),
3639 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, UINT_MAX, "dsi"),
3640 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, "dsib"),
3641 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, UINT_MAX, "dsic"),
3642 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, UINT_MAX, "dsid"),
3643 TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC, 3, 0x1c0, 0x1c4, UINT_MAX, "emmc"),
3644 TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC2, 5, 0x1c0, 0x1c4, UINT_MAX, "emmc2"),
3645 TEGRA_IO_PAD(TEGRA_IO_PAD_GPIO, 27, 0x1b8, 0x1bc, 21, "gpio"),
3646 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, UINT_MAX, "hdmi"),
3647 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, UINT_MAX, "hsic"),
3648 TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, UINT_MAX, "lvds"),
3649 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"),
3650 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"),
3651 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"),
3652 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"),
3653 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, UINT_MAX, UINT_MAX, 11, "pex-cntrl"),
3654 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, 12, "sdmmc1"),
3655 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, 13, "sdmmc3"),
3656 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 14, 0x1c0, 0x1c4, 22, "spi"),
3657 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI_HV, 15, 0x1c0, 0x1c4, 23, "spi-hv"),
3658 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, 2, "uart"),
3659 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, UINT_MAX, "usb0"),
3660 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, UINT_MAX, "usb1"),
3661 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, UINT_MAX, "usb2"),
3662 TEGRA_IO_PAD(TEGRA_IO_PAD_USB3, 18, 0x1b8, 0x1bc, UINT_MAX, "usb3"),
3663 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, "usb-bias"),
3664 };
3665
3666 static const struct pinctrl_pin_desc tegra210_pin_descs[] = {
3667 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"),
3668 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
3669 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"),
3670 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),
3671 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),
3672 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"),
3673 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"),
3674 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),
3675 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"),
3676 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"),
3677 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DEBUG_NONAO, "debug-nonao"),
3678 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC, "dmic"),
3679 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DP, "dp"),
3680 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"),
3681 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"),
3682 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"),
3683 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"),
3684 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC, "emmc"),
3685 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC2, "emmc2"),
3686 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GPIO, "gpio"),
3687 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"),
3688 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"),
3689 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"),
3690 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
3691 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"),
3692 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
3693 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3694 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
3695 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"),
3696 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"),
3697 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"),
3698 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI_HV, "spi-hv"),
3699 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"),
3700 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"),
3701 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"),
3702 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"),
3703 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB3, "usb3"),
3704 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"),
3705 };
3706
3707 static const char * const tegra210_reset_sources[] = {
3708 "POWER_ON_RESET",
3709 "WATCHDOG",
3710 "SENSOR",
3711 "SW_MAIN",
3712 "LP0",
3713 "AOTAG"
3714 };
3715
3716 static const struct tegra_wake_event tegra210_wake_events[] = {
3717 TEGRA_WAKE_IRQ("rtc", 16, 2),
3718 TEGRA_WAKE_IRQ("pmu", 51, 86),
3719 };
3720
3721 static const struct tegra_pmc_soc tegra210_pmc_soc = {
3722 .supports_core_domain = false,
3723 .num_powergates = ARRAY_SIZE(tegra210_powergates),
3724 .powergates = tegra210_powergates,
3725 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
3726 .cpu_powergates = tegra210_cpu_powergates,
3727 .has_tsense_reset = true,
3728 .has_gpu_clamps = true,
3729 .needs_mbist_war = true,
3730 .has_impl_33v_pwr = false,
3731 .maybe_tz_only = true,
3732 .num_io_pads = ARRAY_SIZE(tegra210_io_pads),
3733 .io_pads = tegra210_io_pads,
3734 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),
3735 .pin_descs = tegra210_pin_descs,
3736 .regs = &tegra20_pmc_regs,
3737 .init = tegra20_pmc_init,
3738 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3739 .powergate_set = tegra114_powergate_set,
3740 .irq_set_wake = tegra210_pmc_irq_set_wake,
3741 .irq_set_type = tegra210_pmc_irq_set_type,
3742 .reset_sources = tegra210_reset_sources,
3743 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),
3744 .reset_levels = NULL,
3745 .num_reset_levels = 0,
3746 .num_wake_events = ARRAY_SIZE(tegra210_wake_events),
3747 .wake_events = tegra210_wake_events,
3748 .pmc_clks_data = tegra_pmc_clks_data,
3749 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3750 .has_blink_output = true,
3751 .has_usb_sleepwalk = true,
3752 };
3753
3754 static const struct tegra_io_pad_soc tegra186_io_pads[] = {
3755 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, UINT_MAX, "csia"),
3756 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, UINT_MAX, "csib"),
3757 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x74, 0x78, UINT_MAX, "dsi"),
3758 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"),
3759 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"),
3760 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"),
3761 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"),
3762 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"),
3763 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x74, 0x78, UINT_MAX, "usb0"),
3764 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x74, 0x78, UINT_MAX, "usb1"),
3765 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x74, 0x78, UINT_MAX, "usb2"),
3766 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x74, 0x78, UINT_MAX, "usb-bias"),
3767 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, UINT_MAX, "uart"),
3768 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, UINT_MAX, "audio"),
3769 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x74, 0x78, UINT_MAX, "hsic"),
3770 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, UINT_MAX, "dbg"),
3771 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"),
3772 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"),
3773 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"),
3774 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC2_HV, 2, 0x7c, 0x80, 5, "sdmmc2-hv"),
3775 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, UINT_MAX, "sdmmc4"),
3776 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, UINT_MAX, "cam"),
3777 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 8, 0x7c, 0x80, UINT_MAX, "dsib"),
3778 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 9, 0x7c, 0x80, UINT_MAX, "dsic"),
3779 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 10, 0x7c, 0x80, UINT_MAX, "dsid"),
3780 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, UINT_MAX, "csic"),
3781 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, UINT_MAX, "csid"),
3782 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, UINT_MAX, "csie"),
3783 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, UINT_MAX, "csif"),
3784 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, UINT_MAX, "spi"),
3785 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, UINT_MAX, "ufs"),
3786 TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC_HV, 20, 0x7c, 0x80, 2, "dmic-hv"),
3787 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, UINT_MAX, "edp"),
3788 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"),
3789 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"),
3790 TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, UINT_MAX, "conn"),
3791 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"),
3792 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"),
3793 };
3794
3795 static const struct pinctrl_pin_desc tegra186_pin_descs[] = {
3796 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),
3797 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),
3798 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"),
3799 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
3800 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"),
3801 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"),
3802 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3803 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
3804 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"),
3805 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"),
3806 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"),
3807 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"),
3808 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"),
3809 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"),
3810 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"),
3811 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"),
3812 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),
3813 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"),
3814 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
3815 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC2_HV, "sdmmc2-hv"),
3816 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"),
3817 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"),
3818 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"),
3819 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"),
3820 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"),
3821 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"),
3822 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"),
3823 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),
3824 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"),
3825 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"),
3826 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"),
3827 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC_HV, "dmic-hv"),
3828 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"),
3829 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"),
3830 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"),
3831 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"),
3832 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
3833 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"),
3834 };
3835
3836 static const struct tegra_pmc_regs tegra186_pmc_regs = {
3837 .scratch0 = 0x2000,
3838 .rst_status = 0x70,
3839 .rst_source_shift = 0x2,
3840 .rst_source_mask = 0x3c,
3841 .rst_level_shift = 0x0,
3842 .rst_level_mask = 0x3,
3843 };
3844
tegra186_pmc_init(struct tegra_pmc * pmc)3845 static void tegra186_pmc_init(struct tegra_pmc *pmc)
3846 {
3847 pmc->syscore.suspend = tegra186_pmc_wake_syscore_suspend;
3848 pmc->syscore.resume = tegra186_pmc_wake_syscore_resume;
3849
3850 register_syscore_ops(&pmc->syscore);
3851 }
3852
tegra186_pmc_setup_irq_polarity(struct tegra_pmc * pmc,struct device_node * np,bool invert)3853 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
3854 struct device_node *np,
3855 bool invert)
3856 {
3857 struct resource regs;
3858 void __iomem *wake;
3859 u32 value;
3860 int index;
3861
3862 index = of_property_match_string(np, "reg-names", "wake");
3863 if (index < 0) {
3864 dev_err(pmc->dev, "failed to find PMC wake registers\n");
3865 return;
3866 }
3867
3868 of_address_to_resource(np, index, ®s);
3869
3870 wake = ioremap(regs.start, resource_size(®s));
3871 if (!wake) {
3872 dev_err(pmc->dev, "failed to map PMC wake registers\n");
3873 return;
3874 }
3875
3876 value = readl(wake + WAKE_AOWAKE_CTRL);
3877
3878 if (invert)
3879 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY;
3880 else
3881 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;
3882
3883 writel(value, wake + WAKE_AOWAKE_CTRL);
3884
3885 iounmap(wake);
3886 }
3887
3888 static const char * const tegra186_reset_sources[] = {
3889 "SYS_RESET",
3890 "AOWDT",
3891 "MCCPLEXWDT",
3892 "BPMPWDT",
3893 "SCEWDT",
3894 "SPEWDT",
3895 "APEWDT",
3896 "BCCPLEXWDT",
3897 "SENSOR",
3898 "AOTAG",
3899 "VFSENSOR",
3900 "SWREST",
3901 "SC7",
3902 "HSM",
3903 "CORESIGHT"
3904 };
3905
3906 static const char * const tegra186_reset_levels[] = {
3907 "L0", "L1", "L2", "WARM"
3908 };
3909
3910 static const struct tegra_wake_event tegra186_wake_events[] = {
3911 TEGRA_WAKE_IRQ("pmu", 24, 209),
3912 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)),
3913 TEGRA_WAKE_IRQ("rtc", 73, 10),
3914 };
3915
3916 static const struct tegra_pmc_soc tegra186_pmc_soc = {
3917 .supports_core_domain = false,
3918 .num_powergates = 0,
3919 .powergates = NULL,
3920 .num_cpu_powergates = 0,
3921 .cpu_powergates = NULL,
3922 .has_tsense_reset = false,
3923 .has_gpu_clamps = false,
3924 .needs_mbist_war = false,
3925 .has_impl_33v_pwr = true,
3926 .maybe_tz_only = false,
3927 .num_io_pads = ARRAY_SIZE(tegra186_io_pads),
3928 .io_pads = tegra186_io_pads,
3929 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs),
3930 .pin_descs = tegra186_pin_descs,
3931 .regs = &tegra186_pmc_regs,
3932 .init = tegra186_pmc_init,
3933 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3934 .set_wake_filters = tegra186_pmc_set_wake_filters,
3935 .irq_set_wake = tegra186_pmc_irq_set_wake,
3936 .irq_set_type = tegra186_pmc_irq_set_type,
3937 .reset_sources = tegra186_reset_sources,
3938 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources),
3939 .reset_levels = tegra186_reset_levels,
3940 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3941 .num_wake_events = ARRAY_SIZE(tegra186_wake_events),
3942 .wake_events = tegra186_wake_events,
3943 .max_wake_events = 96,
3944 .max_wake_vectors = 3,
3945 .pmc_clks_data = NULL,
3946 .num_pmc_clks = 0,
3947 .has_blink_output = false,
3948 .has_usb_sleepwalk = false,
3949 };
3950
3951 static const struct tegra_io_pad_soc tegra194_io_pads[] = {
3952 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, UINT_MAX, "csia"),
3953 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, UINT_MAX, "csib"),
3954 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"),
3955 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"),
3956 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"),
3957 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"),
3958 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"),
3959 TEGRA_IO_PAD(TEGRA_IO_PAD_EQOS, 8, 0x74, 0x78, UINT_MAX, "eqos"),
3960 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, 0x74, 0x78, UINT_MAX, "pex-clk-2-bias"),
3961 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2, 10, 0x74, 0x78, UINT_MAX, "pex-clk-2"),
3962 TEGRA_IO_PAD(TEGRA_IO_PAD_DAP3, 11, 0x74, 0x78, UINT_MAX, "dap3"),
3963 TEGRA_IO_PAD(TEGRA_IO_PAD_DAP5, 12, 0x74, 0x78, UINT_MAX, "dap5"),
3964 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, UINT_MAX, "uart"),
3965 TEGRA_IO_PAD(TEGRA_IO_PAD_PWR_CTL, 15, 0x74, 0x78, UINT_MAX, "pwr-ctl"),
3966 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO53, 16, 0x74, 0x78, UINT_MAX, "soc-gpio53"),
3967 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, UINT_MAX, "audio"),
3968 TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM2, 18, 0x74, 0x78, UINT_MAX, "gp-pwm2"),
3969 TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM3, 19, 0x74, 0x78, UINT_MAX, "gp-pwm3"),
3970 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO12, 20, 0x74, 0x78, UINT_MAX, "soc-gpio12"),
3971 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO13, 21, 0x74, 0x78, UINT_MAX, "soc-gpio13"),
3972 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO10, 22, 0x74, 0x78, UINT_MAX, "soc-gpio10"),
3973 TEGRA_IO_PAD(TEGRA_IO_PAD_UART4, 23, 0x74, 0x78, UINT_MAX, "uart4"),
3974 TEGRA_IO_PAD(TEGRA_IO_PAD_UART5, 24, 0x74, 0x78, UINT_MAX, "uart5"),
3975 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, UINT_MAX, "dbg"),
3976 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP3, 26, 0x74, 0x78, UINT_MAX, "hdmi-dp3"),
3977 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP2, 27, 0x74, 0x78, UINT_MAX, "hdmi-dp2"),
3978 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"),
3979 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"),
3980 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"),
3981 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CTL2, 1, 0x7c, 0x80, UINT_MAX, "pex-ctl2"),
3982 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L0_RST, 2, 0x7c, 0x80, UINT_MAX, "pex-l0-rst"),
3983 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L1_RST, 3, 0x7c, 0x80, UINT_MAX, "pex-l1-rst"),
3984 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, UINT_MAX, "sdmmc4"),
3985 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L5_RST, 5, 0x7c, 0x80, UINT_MAX, "pex-l5-rst"),
3986 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, UINT_MAX, "cam"),
3987 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, UINT_MAX, "csic"),
3988 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, UINT_MAX, "csid"),
3989 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, UINT_MAX, "csie"),
3990 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, UINT_MAX, "csif"),
3991 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, UINT_MAX, "spi"),
3992 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, UINT_MAX, "ufs"),
3993 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 18, 0x7c, 0x80, UINT_MAX, "csig"),
3994 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 19, 0x7c, 0x80, UINT_MAX, "csih"),
3995 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, UINT_MAX, "edp"),
3996 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"),
3997 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"),
3998 TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, UINT_MAX, "conn"),
3999 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"),
4000 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"),
4001 };
4002
4003 static const struct pinctrl_pin_desc tegra194_pin_descs[] = {
4004 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),
4005 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),
4006 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
4007 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"),
4008 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"),
4009 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
4010 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
4011 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EQOS, "eqos"),
4012 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2_BIAS, "pex-clk-2-bias"),
4013 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2, "pex-clk-2"),
4014 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP3, "dap3"),
4015 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP5, "dap5"),
4016 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"),
4017 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PWR_CTL, "pwr-ctl"),
4018 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO53, "soc-gpio53"),
4019 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"),
4020 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM2, "gp-pwm2"),
4021 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM3, "gp-pwm3"),
4022 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO12, "soc-gpio12"),
4023 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO13, "soc-gpio13"),
4024 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO10, "soc-gpio10"),
4025 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART4, "uart4"),
4026 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART5, "uart5"),
4027 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"),
4028 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP3, "hdmi-dp3"),
4029 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP2, "hdmi-dp2"),
4030 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),
4031 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"),
4032 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
4033 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CTL2, "pex-ctl2"),
4034 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L0_RST, "pex-l0-rst"),
4035 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L1_RST, "pex-l1-rst"),
4036 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"),
4037 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L5_RST, "pex-l5-rst"),
4038 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"),
4039 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"),
4040 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"),
4041 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),
4042 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"),
4043 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"),
4044 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"),
4045 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"),
4046 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"),
4047 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"),
4048 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"),
4049 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"),
4050 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"),
4051 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
4052 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"),
4053 };
4054
4055 static const struct tegra_pmc_regs tegra194_pmc_regs = {
4056 .scratch0 = 0x2000,
4057 .rst_status = 0x70,
4058 .rst_source_shift = 0x2,
4059 .rst_source_mask = 0x7c,
4060 .rst_level_shift = 0x0,
4061 .rst_level_mask = 0x3,
4062 };
4063
4064 static const char * const tegra194_reset_sources[] = {
4065 "SYS_RESET_N",
4066 "AOWDT",
4067 "BCCPLEXWDT",
4068 "BPMPWDT",
4069 "SCEWDT",
4070 "SPEWDT",
4071 "APEWDT",
4072 "LCCPLEXWDT",
4073 "SENSOR",
4074 "AOTAG",
4075 "VFSENSOR",
4076 "MAINSWRST",
4077 "SC7",
4078 "HSM",
4079 "CSITE",
4080 "RCEWDT",
4081 "PVA0WDT",
4082 "PVA1WDT",
4083 "L1A_ASYNC",
4084 "BPMPBOOT",
4085 "FUSECRC",
4086 };
4087
4088 static const struct tegra_wake_event tegra194_wake_events[] = {
4089 TEGRA_WAKE_IRQ("pmu", 24, 209),
4090 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)),
4091 TEGRA_WAKE_IRQ("rtc", 73, 10),
4092 TEGRA_WAKE_SIMPLE("usb3-port-0", 76),
4093 TEGRA_WAKE_SIMPLE("usb3-port-1", 77),
4094 TEGRA_WAKE_SIMPLE("usb3-port-2-3", 78),
4095 TEGRA_WAKE_SIMPLE("usb2-port-0", 79),
4096 TEGRA_WAKE_SIMPLE("usb2-port-1", 80),
4097 TEGRA_WAKE_SIMPLE("usb2-port-2", 81),
4098 TEGRA_WAKE_SIMPLE("usb2-port-3", 82),
4099 };
4100
4101 static const struct tegra_pmc_soc tegra194_pmc_soc = {
4102 .supports_core_domain = false,
4103 .num_powergates = 0,
4104 .powergates = NULL,
4105 .num_cpu_powergates = 0,
4106 .cpu_powergates = NULL,
4107 .has_tsense_reset = false,
4108 .has_gpu_clamps = false,
4109 .needs_mbist_war = false,
4110 .has_impl_33v_pwr = true,
4111 .maybe_tz_only = false,
4112 .num_io_pads = ARRAY_SIZE(tegra194_io_pads),
4113 .io_pads = tegra194_io_pads,
4114 .num_pin_descs = ARRAY_SIZE(tegra194_pin_descs),
4115 .pin_descs = tegra194_pin_descs,
4116 .regs = &tegra194_pmc_regs,
4117 .init = tegra186_pmc_init,
4118 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
4119 .set_wake_filters = tegra186_pmc_set_wake_filters,
4120 .irq_set_wake = tegra186_pmc_irq_set_wake,
4121 .irq_set_type = tegra186_pmc_irq_set_type,
4122 .reset_sources = tegra194_reset_sources,
4123 .num_reset_sources = ARRAY_SIZE(tegra194_reset_sources),
4124 .reset_levels = tegra186_reset_levels,
4125 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
4126 .num_wake_events = ARRAY_SIZE(tegra194_wake_events),
4127 .wake_events = tegra194_wake_events,
4128 .max_wake_events = 96,
4129 .max_wake_vectors = 3,
4130 .pmc_clks_data = NULL,
4131 .num_pmc_clks = 0,
4132 .has_blink_output = false,
4133 .has_usb_sleepwalk = false,
4134 };
4135
4136 static const struct tegra_io_pad_soc tegra234_io_pads[] = {
4137 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0xe0c0, 0xe0c4, UINT_MAX, "csia"),
4138 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0xe0c0, 0xe0c4, UINT_MAX, "csib"),
4139 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 0, 0xe0d0, 0xe0d4, UINT_MAX, "hdmi-dp0"),
4140 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 2, 0xe0c0, 0xe0c4, UINT_MAX, "csic"),
4141 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 3, 0xe0c0, 0xe0c4, UINT_MAX, "csid"),
4142 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 4, 0xe0c0, 0xe0c4, UINT_MAX, "csie"),
4143 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 5, 0xe0c0, 0xe0c4, UINT_MAX, "csif"),
4144 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 0, 0xe064, 0xe068, UINT_MAX, "ufs"),
4145 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 1, 0xe05c, 0xe060, UINT_MAX, "edp"),
4146 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 0, 0xe054, 0xe058, 4, "sdmmc1-hv"),
4147 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, UINT_MAX, UINT_MAX, UINT_MAX, 6, "sdmmc3-hv"),
4148 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 1, "audio-hv"),
4149 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"),
4150 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 6, 0xe0c0, 0xe0c4, UINT_MAX, "csig"),
4151 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 7, 0xe0c0, 0xe0c4, UINT_MAX, "csih"),
4152 };
4153
4154 static const struct pinctrl_pin_desc tegra234_pin_descs[] = {
4155 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),
4156 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),
4157 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),
4158 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"),
4159 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"),
4160 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),
4161 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"),
4162 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"),
4163 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"),
4164 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"),
4165 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"),
4166 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
4167 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"),
4168 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"),
4169 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"),
4170 };
4171
4172 static const struct tegra_pmc_regs tegra234_pmc_regs = {
4173 .scratch0 = 0x2000,
4174 .rst_status = 0x70,
4175 .rst_source_shift = 0x2,
4176 .rst_source_mask = 0xfc,
4177 .rst_level_shift = 0x0,
4178 .rst_level_mask = 0x3,
4179 };
4180
4181 static const char * const tegra234_reset_sources[] = {
4182 "SYS_RESET_N", /* 0x0 */
4183 "AOWDT",
4184 "BCCPLEXWDT",
4185 "BPMPWDT",
4186 "SCEWDT",
4187 "SPEWDT",
4188 "APEWDT",
4189 "LCCPLEXWDT",
4190 "SENSOR", /* 0x8 */
4191 NULL,
4192 NULL,
4193 "MAINSWRST",
4194 "SC7",
4195 "HSM",
4196 NULL,
4197 "RCEWDT",
4198 NULL, /* 0x10 */
4199 NULL,
4200 NULL,
4201 "BPMPBOOT",
4202 "FUSECRC",
4203 "DCEWDT",
4204 "PSCWDT",
4205 "PSC",
4206 "CSITE_SW", /* 0x18 */
4207 "POD",
4208 "SCPM",
4209 "VREFRO_POWERBAD",
4210 "VMON",
4211 "FMON",
4212 "FSI_R5WDT",
4213 "FSI_THERM",
4214 "FSI_R52C0WDT", /* 0x20 */
4215 "FSI_R52C1WDT",
4216 "FSI_R52C2WDT",
4217 "FSI_R52C3WDT",
4218 "FSI_FMON",
4219 "FSI_VMON", /* 0x25 */
4220 };
4221
4222 static const struct tegra_wake_event tegra234_wake_events[] = {
4223 TEGRA_WAKE_IRQ("pmu", 24, 209),
4224 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA234_AON_GPIO(EE, 4)),
4225 TEGRA_WAKE_GPIO("mgbe", 56, 0, TEGRA234_MAIN_GPIO(Y, 3)),
4226 TEGRA_WAKE_IRQ("rtc", 73, 10),
4227 TEGRA_WAKE_IRQ("sw-wake", SW_WAKE_ID, 179),
4228 };
4229
4230 static const struct tegra_pmc_soc tegra234_pmc_soc = {
4231 .supports_core_domain = false,
4232 .num_powergates = 0,
4233 .powergates = NULL,
4234 .num_cpu_powergates = 0,
4235 .cpu_powergates = NULL,
4236 .has_tsense_reset = false,
4237 .has_gpu_clamps = false,
4238 .needs_mbist_war = false,
4239 .has_impl_33v_pwr = true,
4240 .maybe_tz_only = false,
4241 .num_io_pads = ARRAY_SIZE(tegra234_io_pads),
4242 .io_pads = tegra234_io_pads,
4243 .num_pin_descs = ARRAY_SIZE(tegra234_pin_descs),
4244 .pin_descs = tegra234_pin_descs,
4245 .regs = &tegra234_pmc_regs,
4246 .init = tegra186_pmc_init,
4247 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
4248 .set_wake_filters = tegra186_pmc_set_wake_filters,
4249 .irq_set_wake = tegra186_pmc_irq_set_wake,
4250 .irq_set_type = tegra186_pmc_irq_set_type,
4251 .reset_sources = tegra234_reset_sources,
4252 .num_reset_sources = ARRAY_SIZE(tegra234_reset_sources),
4253 .reset_levels = tegra186_reset_levels,
4254 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
4255 .num_wake_events = ARRAY_SIZE(tegra234_wake_events),
4256 .wake_events = tegra234_wake_events,
4257 .max_wake_events = 96,
4258 .max_wake_vectors = 3,
4259 .pmc_clks_data = NULL,
4260 .num_pmc_clks = 0,
4261 .has_blink_output = false,
4262 };
4263
4264 static const struct of_device_id tegra_pmc_match[] = {
4265 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
4266 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
4267 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
4268 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
4269 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
4270 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
4271 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
4272 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
4273 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
4274 { }
4275 };
4276
tegra_pmc_sync_state(struct device * dev)4277 static void tegra_pmc_sync_state(struct device *dev)
4278 {
4279 int err;
4280
4281 /*
4282 * Newer device-trees have power domains, but we need to prepare all
4283 * device drivers with runtime PM and OPP support first, otherwise
4284 * state syncing is unsafe.
4285 */
4286 if (!pmc->soc->supports_core_domain)
4287 return;
4288
4289 /*
4290 * Older device-trees don't have core PD, and thus, there are
4291 * no dependencies that will block the state syncing. We shouldn't
4292 * mark the domain as synced in this case.
4293 */
4294 if (!pmc->core_domain_registered)
4295 return;
4296
4297 pmc->core_domain_state_synced = true;
4298
4299 /* this is a no-op if core regulator isn't used */
4300 mutex_lock(&pmc->powergates_lock);
4301 err = dev_pm_opp_sync_regulators(dev);
4302 mutex_unlock(&pmc->powergates_lock);
4303
4304 if (err)
4305 dev_err(dev, "failed to sync regulators: %d\n", err);
4306 }
4307
4308 static struct platform_driver tegra_pmc_driver = {
4309 .driver = {
4310 .name = "tegra-pmc",
4311 .suppress_bind_attrs = true,
4312 .of_match_table = tegra_pmc_match,
4313 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
4314 .pm = &tegra_pmc_pm_ops,
4315 #endif
4316 .sync_state = tegra_pmc_sync_state,
4317 },
4318 .probe = tegra_pmc_probe,
4319 };
4320 builtin_platform_driver(tegra_pmc_driver);
4321
tegra_pmc_detect_tz_only(struct tegra_pmc * pmc)4322 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc)
4323 {
4324 u32 value, saved;
4325
4326 saved = readl(pmc->base + pmc->soc->regs->scratch0);
4327 value = saved ^ 0xffffffff;
4328
4329 if (value == 0xffffffff)
4330 value = 0xdeadbeef;
4331
4332 /* write pattern and read it back */
4333 writel(value, pmc->base + pmc->soc->regs->scratch0);
4334 value = readl(pmc->base + pmc->soc->regs->scratch0);
4335
4336 /* if we read all-zeroes, access is restricted to TZ only */
4337 if (value == 0) {
4338 pr_info("access to PMC is restricted to TZ\n");
4339 return true;
4340 }
4341
4342 /* restore original value */
4343 writel(saved, pmc->base + pmc->soc->regs->scratch0);
4344
4345 return false;
4346 }
4347
4348 /*
4349 * Early initialization to allow access to registers in the very early boot
4350 * process.
4351 */
tegra_pmc_early_init(void)4352 static int __init tegra_pmc_early_init(void)
4353 {
4354 const struct of_device_id *match;
4355 struct device_node *np;
4356 struct resource regs;
4357 unsigned int i;
4358 bool invert;
4359
4360 mutex_init(&pmc->powergates_lock);
4361
4362 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
4363 if (!np) {
4364 /*
4365 * Fall back to legacy initialization for 32-bit ARM only. All
4366 * 64-bit ARM device tree files for Tegra are required to have
4367 * a PMC node.
4368 *
4369 * This is for backwards-compatibility with old device trees
4370 * that didn't contain a PMC node. Note that in this case the
4371 * SoC data can't be matched and therefore powergating is
4372 * disabled.
4373 */
4374 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
4375 pr_warn("DT node not found, powergating disabled\n");
4376
4377 regs.start = 0x7000e400;
4378 regs.end = 0x7000e7ff;
4379 regs.flags = IORESOURCE_MEM;
4380
4381 pr_warn("Using memory region %pR\n", ®s);
4382 } else {
4383 /*
4384 * At this point we're not running on Tegra, so play
4385 * nice with multi-platform kernels.
4386 */
4387 return 0;
4388 }
4389 } else {
4390 /*
4391 * Extract information from the device tree if we've found a
4392 * matching node.
4393 */
4394 if (of_address_to_resource(np, 0, ®s) < 0) {
4395 pr_err("failed to get PMC registers\n");
4396 of_node_put(np);
4397 return -ENXIO;
4398 }
4399 }
4400
4401 pmc->base = ioremap(regs.start, resource_size(®s));
4402 if (!pmc->base) {
4403 pr_err("failed to map PMC registers\n");
4404 of_node_put(np);
4405 return -ENXIO;
4406 }
4407
4408 if (of_device_is_available(np)) {
4409 pmc->soc = match->data;
4410
4411 if (pmc->soc->maybe_tz_only)
4412 pmc->tz_only = tegra_pmc_detect_tz_only(pmc);
4413
4414 /* Create a bitmap of the available and valid partitions */
4415 for (i = 0; i < pmc->soc->num_powergates; i++)
4416 if (pmc->soc->powergates[i])
4417 set_bit(i, pmc->powergates_available);
4418
4419 /*
4420 * Invert the interrupt polarity if a PMC device tree node
4421 * exists and contains the nvidia,invert-interrupt property.
4422 */
4423 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
4424
4425 pmc->soc->setup_irq_polarity(pmc, np, invert);
4426
4427 of_node_put(np);
4428 }
4429
4430 return 0;
4431 }
4432 early_initcall(tegra_pmc_early_init);
4433