1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Generic GPIO driver for logic cells found in the Nomadik SoC
4 *
5 * Copyright (C) 2008,2009 STMicroelectronics
6 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
7 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
8 * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org>
9 */
10 #include <linux/bitops.h>
11 #include <linux/cleanup.h>
12 #include <linux/clk.h>
13 #include <linux/device.h>
14 #include <linux/err.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/kernel.h>
20 #include <linux/of.h>
21 #include <linux/of_address.h>
22 #include <linux/of_platform.h>
23 #include <linux/platform_device.h>
24 #include <linux/property.h>
25 #include <linux/seq_file.h>
26 #include <linux/slab.h>
27 #include <linux/spinlock.h>
28
29 /* Since we request GPIOs from ourself */
30 #include <linux/pinctrl/consumer.h>
31 #include <linux/pinctrl/machine.h>
32 #include <linux/pinctrl/pinconf.h>
33 #include <linux/pinctrl/pinctrl.h>
34 #include <linux/pinctrl/pinmux.h>
35
36 #include "../core.h"
37 #include "../pinctrl-utils.h"
38
39 #include "pinctrl-nomadik.h"
40
41 /*
42 * The GPIO module in the Nomadik family of Systems-on-Chip is an
43 * AMBA device, managing 32 pins and alternate functions. The logic block
44 * is currently used in the Nomadik and ux500.
45 *
46 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
47 */
48
49 /*
50 * pin configurations are represented by 32-bit integers:
51 *
52 * bit 0.. 8 - Pin Number (512 Pins Maximum)
53 * bit 9..10 - Alternate Function Selection
54 * bit 11..12 - Pull up/down state
55 * bit 13 - Sleep mode behaviour
56 * bit 14 - Direction
57 * bit 15 - Value (if output)
58 * bit 16..18 - SLPM pull up/down state
59 * bit 19..20 - SLPM direction
60 * bit 21..22 - SLPM Value (if output)
61 * bit 23..25 - PDIS value (if input)
62 * bit 26 - Gpio mode
63 * bit 27 - Sleep mode
64 *
65 * to facilitate the definition, the following macros are provided
66 *
67 * PIN_CFG_DEFAULT - default config (0):
68 * pull up/down = disabled
69 * sleep mode = input/wakeup
70 * direction = input
71 * value = low
72 * SLPM direction = same as normal
73 * SLPM pull = same as normal
74 * SLPM value = same as normal
75 *
76 * PIN_CFG - default config with alternate function
77 */
78
79 typedef unsigned long pin_cfg_t;
80
81 #define PIN_NUM_MASK 0x1ff
82 #define PIN_NUM(x) ((x) & PIN_NUM_MASK)
83
84 #define PIN_ALT_SHIFT 9
85 #define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)
86 #define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
87 #define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
88 #define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
89 #define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
90 #define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
91
92 #define PIN_PULL_SHIFT 11
93 #define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)
94 #define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
95 #define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
96 #define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
97 #define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
98
99 #define PIN_SLPM_SHIFT 13
100 #define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
101 #define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
102 #define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
103 #define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
104 /* These two replace the above in DB8500v2+ */
105 #define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
106 #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
107 #define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
108
109 #define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
110 #define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
111
112 #define PIN_DIR_SHIFT 14
113 #define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
114 #define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
115 #define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)
116 #define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)
117
118 #define PIN_VAL_SHIFT 15
119 #define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)
120 #define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
121 #define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
122 #define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
123
124 #define PIN_SLPM_PULL_SHIFT 16
125 #define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)
126 #define PIN_SLPM_PULL(x) \
127 (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
128 #define PIN_SLPM_PULL_NONE \
129 ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
130 #define PIN_SLPM_PULL_UP \
131 ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
132 #define PIN_SLPM_PULL_DOWN \
133 ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
134
135 #define PIN_SLPM_DIR_SHIFT 19
136 #define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)
137 #define PIN_SLPM_DIR(x) \
138 (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
139 #define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)
140 #define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)
141
142 #define PIN_SLPM_VAL_SHIFT 21
143 #define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)
144 #define PIN_SLPM_VAL(x) \
145 (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
146 #define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
147 #define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
148
149 #define PIN_SLPM_PDIS_SHIFT 23
150 #define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT)
151 #define PIN_SLPM_PDIS(x) \
152 (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
153 #define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT)
154 #define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT)
155 #define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT)
156
157 #define PIN_LOWEMI_SHIFT 25
158 #define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT)
159 #define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
160 #define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)
161 #define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)
162
163 #define PIN_GPIOMODE_SHIFT 26
164 #define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)
165 #define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
166 #define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)
167 #define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)
168
169 #define PIN_SLEEPMODE_SHIFT 27
170 #define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)
171 #define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
172 #define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)
173 #define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)
174
175
176 /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
177 #define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
178 #define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
179 #define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)
180 #define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
181 #define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
182
183 #define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
184 #define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
185 #define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
186 #define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
187 #define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
188
189 #define PIN_CFG_DEFAULT (0)
190
191 #define PIN_CFG(num, alt) \
192 (PIN_CFG_DEFAULT |\
193 (PIN_NUM(num) | PIN_##alt))
194
195 #define PIN_CFG_INPUT(num, alt, pull) \
196 (PIN_CFG_DEFAULT |\
197 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
198
199 #define PIN_CFG_OUTPUT(num, alt, val) \
200 (PIN_CFG_DEFAULT |\
201 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
202
203 /*
204 * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving
205 * the "gpio" namespace for generic and cross-machine functions
206 */
207
208 #define GPIO_BLOCK_SHIFT 5
209 #define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT)
210 #define NMK_MAX_BANKS DIV_ROUND_UP(512, NMK_GPIO_PER_CHIP)
211
212 /* Register in the logic block */
213 #define NMK_GPIO_DAT 0x00
214 #define NMK_GPIO_DATS 0x04
215 #define NMK_GPIO_DATC 0x08
216 #define NMK_GPIO_PDIS 0x0c
217 #define NMK_GPIO_DIR 0x10
218 #define NMK_GPIO_DIRS 0x14
219 #define NMK_GPIO_DIRC 0x18
220 #define NMK_GPIO_SLPC 0x1c
221 #define NMK_GPIO_AFSLA 0x20
222 #define NMK_GPIO_AFSLB 0x24
223 #define NMK_GPIO_LOWEMI 0x28
224
225 #define NMK_GPIO_RIMSC 0x40
226 #define NMK_GPIO_FIMSC 0x44
227 #define NMK_GPIO_IS 0x48
228 #define NMK_GPIO_IC 0x4c
229 #define NMK_GPIO_RWIMSC 0x50
230 #define NMK_GPIO_FWIMSC 0x54
231 #define NMK_GPIO_WKS 0x58
232 /* These appear in DB8540 and later ASICs */
233 #define NMK_GPIO_EDGELEVEL 0x5C
234 #define NMK_GPIO_LEVEL 0x60
235
236
237 /* Pull up/down values */
238 enum nmk_gpio_pull {
239 NMK_GPIO_PULL_NONE,
240 NMK_GPIO_PULL_UP,
241 NMK_GPIO_PULL_DOWN,
242 };
243
244 /* Sleep mode */
245 enum nmk_gpio_slpm {
246 NMK_GPIO_SLPM_INPUT,
247 NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
248 NMK_GPIO_SLPM_NOCHANGE,
249 NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
250 };
251
252 struct nmk_gpio_chip {
253 struct gpio_chip chip;
254 void __iomem *addr;
255 struct clk *clk;
256 unsigned int bank;
257 void (*set_ioforce)(bool enable);
258 spinlock_t lock;
259 bool sleepmode;
260 /* Keep track of configured edges */
261 u32 edge_rising;
262 u32 edge_falling;
263 u32 real_wake;
264 u32 rwimsc;
265 u32 fwimsc;
266 u32 rimsc;
267 u32 fimsc;
268 u32 pull_up;
269 u32 lowemi;
270 };
271
272 /**
273 * struct nmk_pinctrl - state container for the Nomadik pin controller
274 * @dev: containing device pointer
275 * @pctl: corresponding pin controller device
276 * @soc: SoC data for this specific chip
277 * @prcm_base: PRCM register range virtual base
278 */
279 struct nmk_pinctrl {
280 struct device *dev;
281 struct pinctrl_dev *pctl;
282 const struct nmk_pinctrl_soc_data *soc;
283 void __iomem *prcm_base;
284 };
285
286 static struct nmk_gpio_chip *nmk_gpio_chips[NMK_MAX_BANKS];
287
288 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
289
290 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
291
__nmk_gpio_set_mode(struct nmk_gpio_chip * nmk_chip,unsigned offset,int gpio_mode)292 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
293 unsigned offset, int gpio_mode)
294 {
295 u32 afunc, bfunc;
296
297 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~BIT(offset);
298 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~BIT(offset);
299 if (gpio_mode & NMK_GPIO_ALT_A)
300 afunc |= BIT(offset);
301 if (gpio_mode & NMK_GPIO_ALT_B)
302 bfunc |= BIT(offset);
303 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
304 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
305 }
306
__nmk_gpio_set_slpm(struct nmk_gpio_chip * nmk_chip,unsigned offset,enum nmk_gpio_slpm mode)307 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
308 unsigned offset, enum nmk_gpio_slpm mode)
309 {
310 u32 slpm;
311
312 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
313 if (mode == NMK_GPIO_SLPM_NOCHANGE)
314 slpm |= BIT(offset);
315 else
316 slpm &= ~BIT(offset);
317 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
318 }
319
__nmk_gpio_set_pull(struct nmk_gpio_chip * nmk_chip,unsigned offset,enum nmk_gpio_pull pull)320 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
321 unsigned offset, enum nmk_gpio_pull pull)
322 {
323 u32 pdis;
324
325 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
326 if (pull == NMK_GPIO_PULL_NONE) {
327 pdis |= BIT(offset);
328 nmk_chip->pull_up &= ~BIT(offset);
329 } else {
330 pdis &= ~BIT(offset);
331 }
332
333 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
334
335 if (pull == NMK_GPIO_PULL_UP) {
336 nmk_chip->pull_up |= BIT(offset);
337 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
338 } else if (pull == NMK_GPIO_PULL_DOWN) {
339 nmk_chip->pull_up &= ~BIT(offset);
340 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
341 }
342 }
343
__nmk_gpio_set_lowemi(struct nmk_gpio_chip * nmk_chip,unsigned offset,bool lowemi)344 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
345 unsigned offset, bool lowemi)
346 {
347 bool enabled = nmk_chip->lowemi & BIT(offset);
348
349 if (lowemi == enabled)
350 return;
351
352 if (lowemi)
353 nmk_chip->lowemi |= BIT(offset);
354 else
355 nmk_chip->lowemi &= ~BIT(offset);
356
357 writel_relaxed(nmk_chip->lowemi,
358 nmk_chip->addr + NMK_GPIO_LOWEMI);
359 }
360
__nmk_gpio_make_input(struct nmk_gpio_chip * nmk_chip,unsigned offset)361 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
362 unsigned offset)
363 {
364 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
365 }
366
__nmk_gpio_set_output(struct nmk_gpio_chip * nmk_chip,unsigned offset,int val)367 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
368 unsigned offset, int val)
369 {
370 if (val)
371 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
372 else
373 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
374 }
375
__nmk_gpio_make_output(struct nmk_gpio_chip * nmk_chip,unsigned offset,int val)376 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
377 unsigned offset, int val)
378 {
379 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRS);
380 __nmk_gpio_set_output(nmk_chip, offset, val);
381 }
382
__nmk_gpio_set_mode_safe(struct nmk_gpio_chip * nmk_chip,unsigned offset,int gpio_mode,bool glitch)383 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
384 unsigned offset, int gpio_mode,
385 bool glitch)
386 {
387 u32 rwimsc = nmk_chip->rwimsc;
388 u32 fwimsc = nmk_chip->fwimsc;
389
390 if (glitch && nmk_chip->set_ioforce) {
391 u32 bit = BIT(offset);
392
393 /* Prevent spurious wakeups */
394 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
395 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
396
397 nmk_chip->set_ioforce(true);
398 }
399
400 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
401
402 if (glitch && nmk_chip->set_ioforce) {
403 nmk_chip->set_ioforce(false);
404
405 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
406 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
407 }
408 }
409
410 static void
nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip * nmk_chip,unsigned offset)411 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
412 {
413 u32 falling = nmk_chip->fimsc & BIT(offset);
414 u32 rising = nmk_chip->rimsc & BIT(offset);
415 int gpio = nmk_chip->chip.base + offset;
416 int irq = irq_find_mapping(nmk_chip->chip.irq.domain, offset);
417 struct irq_data *d = irq_get_irq_data(irq);
418
419 if (!rising && !falling)
420 return;
421
422 if (!d || !irqd_irq_disabled(d))
423 return;
424
425 if (rising) {
426 nmk_chip->rimsc &= ~BIT(offset);
427 writel_relaxed(nmk_chip->rimsc,
428 nmk_chip->addr + NMK_GPIO_RIMSC);
429 }
430
431 if (falling) {
432 nmk_chip->fimsc &= ~BIT(offset);
433 writel_relaxed(nmk_chip->fimsc,
434 nmk_chip->addr + NMK_GPIO_FIMSC);
435 }
436
437 dev_dbg(nmk_chip->chip.parent, "%d: clearing interrupt mask\n", gpio);
438 }
439
nmk_write_masked(void __iomem * reg,u32 mask,u32 value)440 static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value)
441 {
442 u32 val;
443
444 val = readl(reg);
445 val = ((val & ~mask) | (value & mask));
446 writel(val, reg);
447 }
448
nmk_prcm_altcx_set_mode(struct nmk_pinctrl * npct,unsigned offset,unsigned alt_num)449 static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
450 unsigned offset, unsigned alt_num)
451 {
452 int i;
453 u16 reg;
454 u8 bit;
455 u8 alt_index;
456 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
457 const u16 *gpiocr_regs;
458
459 if (!npct->prcm_base)
460 return;
461
462 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
463 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
464 alt_num);
465 return;
466 }
467
468 for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
469 if (npct->soc->altcx_pins[i].pin == offset)
470 break;
471 }
472 if (i == npct->soc->npins_altcx) {
473 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
474 offset);
475 return;
476 }
477
478 pin_desc = npct->soc->altcx_pins + i;
479 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
480
481 /*
482 * If alt_num is NULL, just clear current ALTCx selection
483 * to make sure we come back to a pure ALTC selection
484 */
485 if (!alt_num) {
486 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
487 if (pin_desc->altcx[i].used == true) {
488 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
489 bit = pin_desc->altcx[i].control_bit;
490 if (readl(npct->prcm_base + reg) & BIT(bit)) {
491 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
492 dev_dbg(npct->dev,
493 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
494 offset, i+1);
495 }
496 }
497 }
498 return;
499 }
500
501 alt_index = alt_num - 1;
502 if (pin_desc->altcx[alt_index].used == false) {
503 dev_warn(npct->dev,
504 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
505 offset, alt_num);
506 return;
507 }
508
509 /*
510 * Check if any other ALTCx functions are activated on this pin
511 * and disable it first.
512 */
513 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
514 if (i == alt_index)
515 continue;
516 if (pin_desc->altcx[i].used == true) {
517 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
518 bit = pin_desc->altcx[i].control_bit;
519 if (readl(npct->prcm_base + reg) & BIT(bit)) {
520 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
521 dev_dbg(npct->dev,
522 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
523 offset, i+1);
524 }
525 }
526 }
527
528 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
529 bit = pin_desc->altcx[alt_index].control_bit;
530 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
531 offset, alt_index+1);
532 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));
533 }
534
535 /*
536 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
537 * - Save SLPM registers
538 * - Set SLPM=0 for the IOs you want to switch and others to 1
539 * - Configure the GPIO registers for the IOs that are being switched
540 * - Set IOFORCE=1
541 * - Modify the AFLSA/B registers for the IOs that are being switched
542 * - Set IOFORCE=0
543 * - Restore SLPM registers
544 * - Any spurious wake up event during switch sequence to be ignored and
545 * cleared
546 */
nmk_gpio_glitch_slpm_init(unsigned int * slpm)547 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
548 {
549 int i;
550
551 for (i = 0; i < NUM_BANKS; i++) {
552 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
553 unsigned int temp = slpm[i];
554
555 if (!chip)
556 break;
557
558 clk_enable(chip->clk);
559
560 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
561 writel(temp, chip->addr + NMK_GPIO_SLPC);
562 }
563 }
564
nmk_gpio_glitch_slpm_restore(unsigned int * slpm)565 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
566 {
567 int i;
568
569 for (i = 0; i < NUM_BANKS; i++) {
570 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
571
572 if (!chip)
573 break;
574
575 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
576
577 clk_disable(chip->clk);
578 }
579 }
580
nmk_prcm_gpiocr_get_mode(struct pinctrl_dev * pctldev,int gpio)581 static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
582 {
583 int i;
584 u16 reg;
585 u8 bit;
586 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
587 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
588 const u16 *gpiocr_regs;
589
590 if (!npct->prcm_base)
591 return NMK_GPIO_ALT_C;
592
593 for (i = 0; i < npct->soc->npins_altcx; i++) {
594 if (npct->soc->altcx_pins[i].pin == gpio)
595 break;
596 }
597 if (i == npct->soc->npins_altcx)
598 return NMK_GPIO_ALT_C;
599
600 pin_desc = npct->soc->altcx_pins + i;
601 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
602 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) {
603 if (pin_desc->altcx[i].used == true) {
604 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
605 bit = pin_desc->altcx[i].control_bit;
606 if (readl(npct->prcm_base + reg) & BIT(bit))
607 return NMK_GPIO_ALT_C+i+1;
608 }
609 }
610 return NMK_GPIO_ALT_C;
611 }
612
613 /* IRQ functions */
614
nmk_gpio_irq_ack(struct irq_data * d)615 static void nmk_gpio_irq_ack(struct irq_data *d)
616 {
617 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
618 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
619
620 clk_enable(nmk_chip->clk);
621 writel(BIT(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
622 clk_disable(nmk_chip->clk);
623 }
624
625 enum nmk_gpio_irq_type {
626 NORMAL,
627 WAKE,
628 };
629
__nmk_gpio_irq_modify(struct nmk_gpio_chip * nmk_chip,int offset,enum nmk_gpio_irq_type which,bool enable)630 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
631 int offset, enum nmk_gpio_irq_type which,
632 bool enable)
633 {
634 u32 *rimscval;
635 u32 *fimscval;
636 u32 rimscreg;
637 u32 fimscreg;
638
639 if (which == NORMAL) {
640 rimscreg = NMK_GPIO_RIMSC;
641 fimscreg = NMK_GPIO_FIMSC;
642 rimscval = &nmk_chip->rimsc;
643 fimscval = &nmk_chip->fimsc;
644 } else {
645 rimscreg = NMK_GPIO_RWIMSC;
646 fimscreg = NMK_GPIO_FWIMSC;
647 rimscval = &nmk_chip->rwimsc;
648 fimscval = &nmk_chip->fwimsc;
649 }
650
651 /* we must individually set/clear the two edges */
652 if (nmk_chip->edge_rising & BIT(offset)) {
653 if (enable)
654 *rimscval |= BIT(offset);
655 else
656 *rimscval &= ~BIT(offset);
657 writel(*rimscval, nmk_chip->addr + rimscreg);
658 }
659 if (nmk_chip->edge_falling & BIT(offset)) {
660 if (enable)
661 *fimscval |= BIT(offset);
662 else
663 *fimscval &= ~BIT(offset);
664 writel(*fimscval, nmk_chip->addr + fimscreg);
665 }
666 }
667
__nmk_gpio_set_wake(struct nmk_gpio_chip * nmk_chip,int offset,bool on)668 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
669 int offset, bool on)
670 {
671 /*
672 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
673 * disabled, since setting SLPM to 1 increases power consumption, and
674 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
675 */
676 if (nmk_chip->sleepmode && on) {
677 __nmk_gpio_set_slpm(nmk_chip, offset,
678 NMK_GPIO_SLPM_WAKEUP_ENABLE);
679 }
680
681 __nmk_gpio_irq_modify(nmk_chip, offset, WAKE, on);
682 }
683
nmk_gpio_irq_maskunmask(struct nmk_gpio_chip * nmk_chip,struct irq_data * d,bool enable)684 static void nmk_gpio_irq_maskunmask(struct nmk_gpio_chip *nmk_chip,
685 struct irq_data *d, bool enable)
686 {
687 unsigned long flags;
688
689 clk_enable(nmk_chip->clk);
690 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
691 spin_lock(&nmk_chip->lock);
692
693 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
694
695 if (!(nmk_chip->real_wake & BIT(d->hwirq)))
696 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
697
698 spin_unlock(&nmk_chip->lock);
699 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
700 clk_disable(nmk_chip->clk);
701 }
702
nmk_gpio_irq_mask(struct irq_data * d)703 static void nmk_gpio_irq_mask(struct irq_data *d)
704 {
705 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
706 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
707
708 nmk_gpio_irq_maskunmask(nmk_chip, d, false);
709 gpiochip_disable_irq(gc, irqd_to_hwirq(d));
710 }
711
nmk_gpio_irq_unmask(struct irq_data * d)712 static void nmk_gpio_irq_unmask(struct irq_data *d)
713 {
714 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
715 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
716
717 gpiochip_enable_irq(gc, irqd_to_hwirq(d));
718 nmk_gpio_irq_maskunmask(nmk_chip, d, true);
719 }
720
nmk_gpio_irq_set_wake(struct irq_data * d,unsigned int on)721 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
722 {
723 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
724 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
725 unsigned long flags;
726
727 clk_enable(nmk_chip->clk);
728 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
729 spin_lock(&nmk_chip->lock);
730
731 if (irqd_irq_disabled(d))
732 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
733
734 if (on)
735 nmk_chip->real_wake |= BIT(d->hwirq);
736 else
737 nmk_chip->real_wake &= ~BIT(d->hwirq);
738
739 spin_unlock(&nmk_chip->lock);
740 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
741 clk_disable(nmk_chip->clk);
742
743 return 0;
744 }
745
nmk_gpio_irq_set_type(struct irq_data * d,unsigned int type)746 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
747 {
748 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
749 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
750 bool enabled = !irqd_irq_disabled(d);
751 bool wake = irqd_is_wakeup_set(d);
752 unsigned long flags;
753
754 if (type & IRQ_TYPE_LEVEL_HIGH)
755 return -EINVAL;
756 if (type & IRQ_TYPE_LEVEL_LOW)
757 return -EINVAL;
758
759 clk_enable(nmk_chip->clk);
760 spin_lock_irqsave(&nmk_chip->lock, flags);
761
762 if (enabled)
763 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
764
765 if (enabled || wake)
766 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
767
768 nmk_chip->edge_rising &= ~BIT(d->hwirq);
769 if (type & IRQ_TYPE_EDGE_RISING)
770 nmk_chip->edge_rising |= BIT(d->hwirq);
771
772 nmk_chip->edge_falling &= ~BIT(d->hwirq);
773 if (type & IRQ_TYPE_EDGE_FALLING)
774 nmk_chip->edge_falling |= BIT(d->hwirq);
775
776 if (enabled)
777 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
778
779 if (enabled || wake)
780 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
781
782 spin_unlock_irqrestore(&nmk_chip->lock, flags);
783 clk_disable(nmk_chip->clk);
784
785 return 0;
786 }
787
nmk_gpio_irq_startup(struct irq_data * d)788 static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
789 {
790 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
791 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
792
793 clk_enable(nmk_chip->clk);
794 nmk_gpio_irq_unmask(d);
795 return 0;
796 }
797
nmk_gpio_irq_shutdown(struct irq_data * d)798 static void nmk_gpio_irq_shutdown(struct irq_data *d)
799 {
800 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
801 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
802
803 nmk_gpio_irq_mask(d);
804 clk_disable(nmk_chip->clk);
805 }
806
nmk_gpio_irq_handler(struct irq_desc * desc)807 static void nmk_gpio_irq_handler(struct irq_desc *desc)
808 {
809 struct irq_chip *host_chip = irq_desc_get_chip(desc);
810 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
811 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
812 u32 status;
813
814 chained_irq_enter(host_chip, desc);
815
816 clk_enable(nmk_chip->clk);
817 status = readl(nmk_chip->addr + NMK_GPIO_IS);
818 clk_disable(nmk_chip->clk);
819
820 while (status) {
821 int bit = __ffs(status);
822
823 generic_handle_domain_irq(chip->irq.domain, bit);
824 status &= ~BIT(bit);
825 }
826
827 chained_irq_exit(host_chip, desc);
828 }
829
830 /* I/O Functions */
831
nmk_gpio_get_dir(struct gpio_chip * chip,unsigned offset)832 static int nmk_gpio_get_dir(struct gpio_chip *chip, unsigned offset)
833 {
834 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
835 int dir;
836
837 clk_enable(nmk_chip->clk);
838
839 dir = readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset);
840
841 clk_disable(nmk_chip->clk);
842
843 if (dir)
844 return GPIO_LINE_DIRECTION_OUT;
845
846 return GPIO_LINE_DIRECTION_IN;
847 }
848
nmk_gpio_make_input(struct gpio_chip * chip,unsigned offset)849 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
850 {
851 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
852
853 clk_enable(nmk_chip->clk);
854
855 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
856
857 clk_disable(nmk_chip->clk);
858
859 return 0;
860 }
861
nmk_gpio_get_input(struct gpio_chip * chip,unsigned offset)862 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
863 {
864 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
865 int value;
866
867 clk_enable(nmk_chip->clk);
868
869 value = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
870
871 clk_disable(nmk_chip->clk);
872
873 return value;
874 }
875
nmk_gpio_set_output(struct gpio_chip * chip,unsigned offset,int val)876 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
877 int val)
878 {
879 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
880
881 clk_enable(nmk_chip->clk);
882
883 __nmk_gpio_set_output(nmk_chip, offset, val);
884
885 clk_disable(nmk_chip->clk);
886 }
887
nmk_gpio_make_output(struct gpio_chip * chip,unsigned offset,int val)888 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
889 int val)
890 {
891 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
892
893 clk_enable(nmk_chip->clk);
894
895 __nmk_gpio_make_output(nmk_chip, offset, val);
896
897 clk_disable(nmk_chip->clk);
898
899 return 0;
900 }
901
902 #ifdef CONFIG_DEBUG_FS
nmk_gpio_get_mode(struct nmk_gpio_chip * nmk_chip,int offset)903 static int nmk_gpio_get_mode(struct nmk_gpio_chip *nmk_chip, int offset)
904 {
905 u32 afunc, bfunc;
906
907 clk_enable(nmk_chip->clk);
908
909 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & BIT(offset);
910 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & BIT(offset);
911
912 clk_disable(nmk_chip->clk);
913
914 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
915 }
916
nmk_gpio_dbg_show_one(struct seq_file * s,struct pinctrl_dev * pctldev,struct gpio_chip * chip,unsigned offset,unsigned gpio)917 static void nmk_gpio_dbg_show_one(struct seq_file *s,
918 struct pinctrl_dev *pctldev, struct gpio_chip *chip,
919 unsigned offset, unsigned gpio)
920 {
921 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
922 int mode;
923 bool is_out;
924 bool data_out;
925 bool pull;
926 const char *modes[] = {
927 [NMK_GPIO_ALT_GPIO] = "gpio",
928 [NMK_GPIO_ALT_A] = "altA",
929 [NMK_GPIO_ALT_B] = "altB",
930 [NMK_GPIO_ALT_C] = "altC",
931 [NMK_GPIO_ALT_C+1] = "altC1",
932 [NMK_GPIO_ALT_C+2] = "altC2",
933 [NMK_GPIO_ALT_C+3] = "altC3",
934 [NMK_GPIO_ALT_C+4] = "altC4",
935 };
936
937 char *label = gpiochip_dup_line_label(chip, offset);
938 if (IS_ERR(label))
939 return;
940
941 clk_enable(nmk_chip->clk);
942 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset));
943 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & BIT(offset));
944 data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
945 mode = nmk_gpio_get_mode(nmk_chip, offset);
946 if ((mode == NMK_GPIO_ALT_C) && pctldev)
947 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
948
949 if (is_out) {
950 seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s",
951 gpio,
952 label ?: "(none)",
953 data_out ? "hi" : "lo",
954 (mode < 0) ? "unknown" : modes[mode]);
955 } else {
956 int irq = chip->to_irq(chip, offset);
957 const int pullidx = pull ? 1 : 0;
958 int val;
959 static const char * const pulls[] = {
960 "none ",
961 "pull enabled",
962 };
963
964 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s",
965 gpio,
966 label ?: "(none)",
967 pulls[pullidx],
968 (mode < 0) ? "unknown" : modes[mode]);
969
970 val = nmk_gpio_get_input(chip, offset);
971 seq_printf(s, " VAL %d", val);
972
973 /*
974 * This races with request_irq(), set_irq_type(),
975 * and set_irq_wake() ... but those are "rare".
976 */
977 if (irq > 0 && irq_has_action(irq)) {
978 char *trigger;
979 bool wake;
980
981 if (nmk_chip->edge_rising & BIT(offset))
982 trigger = "edge-rising";
983 else if (nmk_chip->edge_falling & BIT(offset))
984 trigger = "edge-falling";
985 else
986 trigger = "edge-undefined";
987
988 wake = !!(nmk_chip->real_wake & BIT(offset));
989
990 seq_printf(s, " irq-%d %s%s",
991 irq, trigger, wake ? " wakeup" : "");
992 }
993 }
994 clk_disable(nmk_chip->clk);
995 }
996
nmk_gpio_dbg_show(struct seq_file * s,struct gpio_chip * chip)997 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
998 {
999 unsigned i;
1000 unsigned gpio = chip->base;
1001
1002 for (i = 0; i < chip->ngpio; i++, gpio++) {
1003 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio);
1004 seq_printf(s, "\n");
1005 }
1006 }
1007
1008 #else
nmk_gpio_dbg_show_one(struct seq_file * s,struct pinctrl_dev * pctldev,struct gpio_chip * chip,unsigned offset,unsigned gpio)1009 static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1010 struct pinctrl_dev *pctldev,
1011 struct gpio_chip *chip,
1012 unsigned offset, unsigned gpio)
1013 {
1014 }
1015 #define nmk_gpio_dbg_show NULL
1016 #endif
1017
1018 /*
1019 * We will allocate memory for the state container using devm* allocators
1020 * binding to the first device reaching this point, it doesn't matter if
1021 * it is the pin controller or GPIO driver. However we need to use the right
1022 * platform device when looking up resources so pay attention to pdev.
1023 */
nmk_gpio_populate_chip(struct device_node * np,struct platform_device * pdev)1024 static struct nmk_gpio_chip *nmk_gpio_populate_chip(struct device_node *np,
1025 struct platform_device *pdev)
1026 {
1027 struct nmk_gpio_chip *nmk_chip;
1028 struct platform_device *gpio_pdev;
1029 struct gpio_chip *chip;
1030 struct resource *res;
1031 struct clk *clk;
1032 void __iomem *base;
1033 u32 id;
1034
1035 gpio_pdev = of_find_device_by_node(np);
1036 if (!gpio_pdev) {
1037 pr_err("populate \"%pOFn\": device not found\n", np);
1038 return ERR_PTR(-ENODEV);
1039 }
1040 if (of_property_read_u32(np, "gpio-bank", &id)) {
1041 dev_err(&pdev->dev, "populate: gpio-bank property not found\n");
1042 platform_device_put(gpio_pdev);
1043 return ERR_PTR(-EINVAL);
1044 }
1045
1046 /* Already populated? */
1047 nmk_chip = nmk_gpio_chips[id];
1048 if (nmk_chip) {
1049 platform_device_put(gpio_pdev);
1050 return nmk_chip;
1051 }
1052
1053 nmk_chip = devm_kzalloc(&pdev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1054 if (!nmk_chip) {
1055 platform_device_put(gpio_pdev);
1056 return ERR_PTR(-ENOMEM);
1057 }
1058
1059 nmk_chip->bank = id;
1060 chip = &nmk_chip->chip;
1061 chip->base = id * NMK_GPIO_PER_CHIP;
1062 chip->ngpio = NMK_GPIO_PER_CHIP;
1063 chip->label = dev_name(&gpio_pdev->dev);
1064 chip->parent = &gpio_pdev->dev;
1065
1066 res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0);
1067 base = devm_ioremap_resource(&pdev->dev, res);
1068 if (IS_ERR(base)) {
1069 platform_device_put(gpio_pdev);
1070 return ERR_CAST(base);
1071 }
1072 nmk_chip->addr = base;
1073
1074 clk = clk_get(&gpio_pdev->dev, NULL);
1075 if (IS_ERR(clk)) {
1076 platform_device_put(gpio_pdev);
1077 return (void *) clk;
1078 }
1079 clk_prepare(clk);
1080 nmk_chip->clk = clk;
1081
1082 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1083 nmk_gpio_chips[id] = nmk_chip;
1084 return nmk_chip;
1085 }
1086
nmk_gpio_irq_print_chip(struct irq_data * d,struct seq_file * p)1087 static void nmk_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p)
1088 {
1089 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1090 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
1091
1092 seq_printf(p, "nmk%u-%u-%u", nmk_chip->bank,
1093 gc->base, gc->base + gc->ngpio - 1);
1094 }
1095
1096 static const struct irq_chip nmk_irq_chip = {
1097 .irq_ack = nmk_gpio_irq_ack,
1098 .irq_mask = nmk_gpio_irq_mask,
1099 .irq_unmask = nmk_gpio_irq_unmask,
1100 .irq_set_type = nmk_gpio_irq_set_type,
1101 .irq_set_wake = nmk_gpio_irq_set_wake,
1102 .irq_startup = nmk_gpio_irq_startup,
1103 .irq_shutdown = nmk_gpio_irq_shutdown,
1104 .irq_print_chip = nmk_gpio_irq_print_chip,
1105 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
1106 GPIOCHIP_IRQ_RESOURCE_HELPERS,
1107 };
1108
nmk_gpio_probe(struct platform_device * dev)1109 static int nmk_gpio_probe(struct platform_device *dev)
1110 {
1111 struct device_node *np = dev->dev.of_node;
1112 struct nmk_gpio_chip *nmk_chip;
1113 struct gpio_chip *chip;
1114 struct gpio_irq_chip *girq;
1115 bool supports_sleepmode;
1116 int irq;
1117 int ret;
1118
1119 nmk_chip = nmk_gpio_populate_chip(np, dev);
1120 if (IS_ERR(nmk_chip)) {
1121 dev_err(&dev->dev, "could not populate nmk chip struct\n");
1122 return PTR_ERR(nmk_chip);
1123 }
1124
1125 supports_sleepmode =
1126 of_property_read_bool(np, "st,supports-sleepmode");
1127
1128 /* Correct platform device ID */
1129 dev->id = nmk_chip->bank;
1130
1131 irq = platform_get_irq(dev, 0);
1132 if (irq < 0)
1133 return irq;
1134
1135 /*
1136 * The virt address in nmk_chip->addr is in the nomadik register space,
1137 * so we can simply convert the resource address, without remapping
1138 */
1139 nmk_chip->sleepmode = supports_sleepmode;
1140 spin_lock_init(&nmk_chip->lock);
1141
1142 chip = &nmk_chip->chip;
1143 chip->parent = &dev->dev;
1144 chip->request = gpiochip_generic_request;
1145 chip->free = gpiochip_generic_free;
1146 chip->get_direction = nmk_gpio_get_dir;
1147 chip->direction_input = nmk_gpio_make_input;
1148 chip->get = nmk_gpio_get_input;
1149 chip->direction_output = nmk_gpio_make_output;
1150 chip->set = nmk_gpio_set_output;
1151 chip->dbg_show = nmk_gpio_dbg_show;
1152 chip->can_sleep = false;
1153 chip->owner = THIS_MODULE;
1154
1155 girq = &chip->irq;
1156 gpio_irq_chip_set_chip(girq, &nmk_irq_chip);
1157 girq->parent_handler = nmk_gpio_irq_handler;
1158 girq->num_parents = 1;
1159 girq->parents = devm_kcalloc(&dev->dev, 1,
1160 sizeof(*girq->parents),
1161 GFP_KERNEL);
1162 if (!girq->parents)
1163 return -ENOMEM;
1164 girq->parents[0] = irq;
1165 girq->default_type = IRQ_TYPE_NONE;
1166 girq->handler = handle_edge_irq;
1167
1168 clk_enable(nmk_chip->clk);
1169 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1170 clk_disable(nmk_chip->clk);
1171
1172 ret = gpiochip_add_data(chip, nmk_chip);
1173 if (ret)
1174 return ret;
1175
1176 platform_set_drvdata(dev, nmk_chip);
1177
1178 dev_info(&dev->dev, "chip registered\n");
1179
1180 return 0;
1181 }
1182
nmk_get_groups_cnt(struct pinctrl_dev * pctldev)1183 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1184 {
1185 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1186
1187 return npct->soc->ngroups;
1188 }
1189
nmk_get_group_name(struct pinctrl_dev * pctldev,unsigned selector)1190 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1191 unsigned selector)
1192 {
1193 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1194
1195 return npct->soc->groups[selector].grp.name;
1196 }
1197
nmk_get_group_pins(struct pinctrl_dev * pctldev,unsigned selector,const unsigned ** pins,unsigned * npins)1198 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1199 const unsigned **pins,
1200 unsigned *npins)
1201 {
1202 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1203
1204 *pins = npct->soc->groups[selector].grp.pins;
1205 *npins = npct->soc->groups[selector].grp.npins;
1206 return 0;
1207 }
1208
find_nmk_gpio_from_pin(unsigned pin)1209 static struct nmk_gpio_chip *find_nmk_gpio_from_pin(unsigned pin)
1210 {
1211 int i;
1212 struct nmk_gpio_chip *nmk_gpio;
1213
1214 for(i = 0; i < NMK_MAX_BANKS; i++) {
1215 nmk_gpio = nmk_gpio_chips[i];
1216 if (!nmk_gpio)
1217 continue;
1218 if (pin >= nmk_gpio->chip.base &&
1219 pin < nmk_gpio->chip.base + nmk_gpio->chip.ngpio)
1220 return nmk_gpio;
1221 }
1222 return NULL;
1223 }
1224
find_gc_from_pin(unsigned pin)1225 static struct gpio_chip *find_gc_from_pin(unsigned pin)
1226 {
1227 struct nmk_gpio_chip *nmk_gpio = find_nmk_gpio_from_pin(pin);
1228
1229 if (nmk_gpio)
1230 return &nmk_gpio->chip;
1231 return NULL;
1232 }
1233
nmk_pin_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned offset)1234 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1235 unsigned offset)
1236 {
1237 struct gpio_chip *chip = find_gc_from_pin(offset);
1238
1239 if (!chip) {
1240 seq_printf(s, "invalid pin offset");
1241 return;
1242 }
1243 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
1244 }
1245
nmk_dt_add_map_mux(struct pinctrl_map ** map,unsigned * reserved_maps,unsigned * num_maps,const char * group,const char * function)1246 static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
1247 unsigned *num_maps, const char *group,
1248 const char *function)
1249 {
1250 if (*num_maps == *reserved_maps)
1251 return -ENOSPC;
1252
1253 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
1254 (*map)[*num_maps].data.mux.group = group;
1255 (*map)[*num_maps].data.mux.function = function;
1256 (*num_maps)++;
1257
1258 return 0;
1259 }
1260
nmk_dt_add_map_configs(struct pinctrl_map ** map,unsigned * reserved_maps,unsigned * num_maps,const char * group,unsigned long * configs,unsigned num_configs)1261 static int nmk_dt_add_map_configs(struct pinctrl_map **map,
1262 unsigned *reserved_maps,
1263 unsigned *num_maps, const char *group,
1264 unsigned long *configs, unsigned num_configs)
1265 {
1266 unsigned long *dup_configs;
1267
1268 if (*num_maps == *reserved_maps)
1269 return -ENOSPC;
1270
1271 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
1272 GFP_KERNEL);
1273 if (!dup_configs)
1274 return -ENOMEM;
1275
1276 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
1277
1278 (*map)[*num_maps].data.configs.group_or_pin = group;
1279 (*map)[*num_maps].data.configs.configs = dup_configs;
1280 (*map)[*num_maps].data.configs.num_configs = num_configs;
1281 (*num_maps)++;
1282
1283 return 0;
1284 }
1285
1286 #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, }
1287 #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \
1288 .size = ARRAY_SIZE(y), }
1289
1290 static const unsigned long nmk_pin_input_modes[] = {
1291 PIN_INPUT_NOPULL,
1292 PIN_INPUT_PULLUP,
1293 PIN_INPUT_PULLDOWN,
1294 };
1295
1296 static const unsigned long nmk_pin_output_modes[] = {
1297 PIN_OUTPUT_LOW,
1298 PIN_OUTPUT_HIGH,
1299 PIN_DIR_OUTPUT,
1300 };
1301
1302 static const unsigned long nmk_pin_sleep_modes[] = {
1303 PIN_SLEEPMODE_DISABLED,
1304 PIN_SLEEPMODE_ENABLED,
1305 };
1306
1307 static const unsigned long nmk_pin_sleep_input_modes[] = {
1308 PIN_SLPM_INPUT_NOPULL,
1309 PIN_SLPM_INPUT_PULLUP,
1310 PIN_SLPM_INPUT_PULLDOWN,
1311 PIN_SLPM_DIR_INPUT,
1312 };
1313
1314 static const unsigned long nmk_pin_sleep_output_modes[] = {
1315 PIN_SLPM_OUTPUT_LOW,
1316 PIN_SLPM_OUTPUT_HIGH,
1317 PIN_SLPM_DIR_OUTPUT,
1318 };
1319
1320 static const unsigned long nmk_pin_sleep_wakeup_modes[] = {
1321 PIN_SLPM_WAKEUP_DISABLE,
1322 PIN_SLPM_WAKEUP_ENABLE,
1323 };
1324
1325 static const unsigned long nmk_pin_gpio_modes[] = {
1326 PIN_GPIOMODE_DISABLED,
1327 PIN_GPIOMODE_ENABLED,
1328 };
1329
1330 static const unsigned long nmk_pin_sleep_pdis_modes[] = {
1331 PIN_SLPM_PDIS_DISABLED,
1332 PIN_SLPM_PDIS_ENABLED,
1333 };
1334
1335 struct nmk_cfg_param {
1336 const char *property;
1337 unsigned long config;
1338 const unsigned long *choice;
1339 int size;
1340 };
1341
1342 static const struct nmk_cfg_param nmk_cfg_params[] = {
1343 NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes),
1344 NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes),
1345 NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes),
1346 NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes),
1347 NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes),
1348 NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes),
1349 NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes),
1350 NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes),
1351 };
1352
nmk_dt_pin_config(int index,int val,unsigned long * config)1353 static int nmk_dt_pin_config(int index, int val, unsigned long *config)
1354 {
1355 if (nmk_cfg_params[index].choice == NULL)
1356 *config = nmk_cfg_params[index].config;
1357 else {
1358 /* test if out of range */
1359 if (val < nmk_cfg_params[index].size) {
1360 *config = nmk_cfg_params[index].config |
1361 nmk_cfg_params[index].choice[val];
1362 }
1363 }
1364 return 0;
1365 }
1366
nmk_find_pin_name(struct pinctrl_dev * pctldev,const char * pin_name)1367 static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name)
1368 {
1369 int i, pin_number;
1370 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1371
1372 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
1373 for (i = 0; i < npct->soc->npins; i++)
1374 if (npct->soc->pins[i].number == pin_number)
1375 return npct->soc->pins[i].name;
1376 return NULL;
1377 }
1378
nmk_pinctrl_dt_get_config(struct device_node * np,unsigned long * configs)1379 static bool nmk_pinctrl_dt_get_config(struct device_node *np,
1380 unsigned long *configs)
1381 {
1382 bool has_config = 0;
1383 unsigned long cfg = 0;
1384 int i, val, ret;
1385
1386 for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) {
1387 ret = of_property_read_u32(np,
1388 nmk_cfg_params[i].property, &val);
1389 if (ret != -EINVAL) {
1390 if (nmk_dt_pin_config(i, val, &cfg) == 0) {
1391 *configs |= cfg;
1392 has_config = 1;
1393 }
1394 }
1395 }
1396
1397 return has_config;
1398 }
1399
nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned * reserved_maps,unsigned * num_maps)1400 static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
1401 struct device_node *np,
1402 struct pinctrl_map **map,
1403 unsigned *reserved_maps,
1404 unsigned *num_maps)
1405 {
1406 int ret;
1407 const char *function = NULL;
1408 unsigned long configs = 0;
1409 bool has_config = 0;
1410 struct property *prop;
1411 struct device_node *np_config;
1412
1413 ret = of_property_read_string(np, "function", &function);
1414 if (ret >= 0) {
1415 const char *group;
1416
1417 ret = of_property_count_strings(np, "groups");
1418 if (ret < 0)
1419 goto exit;
1420
1421 ret = pinctrl_utils_reserve_map(pctldev, map,
1422 reserved_maps,
1423 num_maps, ret);
1424 if (ret < 0)
1425 goto exit;
1426
1427 of_property_for_each_string(np, "groups", prop, group) {
1428 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
1429 group, function);
1430 if (ret < 0)
1431 goto exit;
1432 }
1433 }
1434
1435 has_config = nmk_pinctrl_dt_get_config(np, &configs);
1436 np_config = of_parse_phandle(np, "ste,config", 0);
1437 if (np_config) {
1438 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
1439 of_node_put(np_config);
1440 }
1441 if (has_config) {
1442 const char *gpio_name;
1443 const char *pin;
1444
1445 ret = of_property_count_strings(np, "pins");
1446 if (ret < 0)
1447 goto exit;
1448 ret = pinctrl_utils_reserve_map(pctldev, map,
1449 reserved_maps,
1450 num_maps, ret);
1451 if (ret < 0)
1452 goto exit;
1453
1454 of_property_for_each_string(np, "pins", prop, pin) {
1455 gpio_name = nmk_find_pin_name(pctldev, pin);
1456
1457 ret = nmk_dt_add_map_configs(map, reserved_maps,
1458 num_maps,
1459 gpio_name, &configs, 1);
1460 if (ret < 0)
1461 goto exit;
1462 }
1463 }
1464
1465 exit:
1466 return ret;
1467 }
1468
nmk_pinctrl_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np_config,struct pinctrl_map ** map,unsigned * num_maps)1469 static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
1470 struct device_node *np_config,
1471 struct pinctrl_map **map, unsigned *num_maps)
1472 {
1473 unsigned reserved_maps;
1474 struct device_node *np;
1475 int ret;
1476
1477 reserved_maps = 0;
1478 *map = NULL;
1479 *num_maps = 0;
1480
1481 for_each_child_of_node(np_config, np) {
1482 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
1483 &reserved_maps, num_maps);
1484 if (ret < 0) {
1485 pinctrl_utils_free_map(pctldev, *map, *num_maps);
1486 of_node_put(np);
1487 return ret;
1488 }
1489 }
1490
1491 return 0;
1492 }
1493
1494 static const struct pinctrl_ops nmk_pinctrl_ops = {
1495 .get_groups_count = nmk_get_groups_cnt,
1496 .get_group_name = nmk_get_group_name,
1497 .get_group_pins = nmk_get_group_pins,
1498 .pin_dbg_show = nmk_pin_dbg_show,
1499 .dt_node_to_map = nmk_pinctrl_dt_node_to_map,
1500 .dt_free_map = pinctrl_utils_free_map,
1501 };
1502
nmk_pmx_get_funcs_cnt(struct pinctrl_dev * pctldev)1503 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1504 {
1505 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1506
1507 return npct->soc->nfunctions;
1508 }
1509
nmk_pmx_get_func_name(struct pinctrl_dev * pctldev,unsigned function)1510 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1511 unsigned function)
1512 {
1513 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1514
1515 return npct->soc->functions[function].name;
1516 }
1517
nmk_pmx_get_func_groups(struct pinctrl_dev * pctldev,unsigned function,const char * const ** groups,unsigned * const num_groups)1518 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1519 unsigned function,
1520 const char * const **groups,
1521 unsigned * const num_groups)
1522 {
1523 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1524
1525 *groups = npct->soc->functions[function].groups;
1526 *num_groups = npct->soc->functions[function].ngroups;
1527
1528 return 0;
1529 }
1530
nmk_pmx_set(struct pinctrl_dev * pctldev,unsigned function,unsigned group)1531 static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
1532 unsigned group)
1533 {
1534 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1535 const struct nmk_pingroup *g;
1536 static unsigned int slpm[NUM_BANKS];
1537 unsigned long flags = 0;
1538 bool glitch;
1539 int ret = -EINVAL;
1540 int i;
1541
1542 g = &npct->soc->groups[group];
1543
1544 if (g->altsetting < 0)
1545 return -EINVAL;
1546
1547 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->grp.name, g->grp.npins);
1548
1549 /*
1550 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
1551 * we may pass through an undesired state. In this case we take
1552 * some extra care.
1553 *
1554 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
1555 * - Save SLPM registers (since we have a shadow register in the
1556 * nmk_chip we're using that as backup)
1557 * - Set SLPM=0 for the IOs you want to switch and others to 1
1558 * - Configure the GPIO registers for the IOs that are being switched
1559 * - Set IOFORCE=1
1560 * - Modify the AFLSA/B registers for the IOs that are being switched
1561 * - Set IOFORCE=0
1562 * - Restore SLPM registers
1563 * - Any spurious wake up event during switch sequence to be ignored
1564 * and cleared
1565 *
1566 * We REALLY need to save ALL slpm registers, because the external
1567 * IOFORCE will switch *all* ports to their sleepmode setting to as
1568 * to avoid glitches. (Not just one port!)
1569 */
1570 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
1571
1572 if (glitch) {
1573 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1574
1575 /* Initially don't put any pins to sleep when switching */
1576 memset(slpm, 0xff, sizeof(slpm));
1577
1578 /*
1579 * Then mask the pins that need to be sleeping now when we're
1580 * switching to the ALT C function.
1581 */
1582 for (i = 0; i < g->grp.npins; i++)
1583 slpm[g->grp.pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->grp.pins[i]);
1584 nmk_gpio_glitch_slpm_init(slpm);
1585 }
1586
1587 for (i = 0; i < g->grp.npins; i++) {
1588 struct nmk_gpio_chip *nmk_chip;
1589 unsigned bit;
1590
1591 nmk_chip = find_nmk_gpio_from_pin(g->grp.pins[i]);
1592 if (!nmk_chip) {
1593 dev_err(npct->dev,
1594 "invalid pin offset %d in group %s at index %d\n",
1595 g->grp.pins[i], g->grp.name, i);
1596 goto out_glitch;
1597 }
1598 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->grp.pins[i], g->altsetting);
1599
1600 clk_enable(nmk_chip->clk);
1601 bit = g->grp.pins[i] % NMK_GPIO_PER_CHIP;
1602 /*
1603 * If the pin is switching to altfunc, and there was an
1604 * interrupt installed on it which has been lazy disabled,
1605 * actually mask the interrupt to prevent spurious interrupts
1606 * that would occur while the pin is under control of the
1607 * peripheral. Only SKE does this.
1608 */
1609 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1610
1611 __nmk_gpio_set_mode_safe(nmk_chip, bit,
1612 (g->altsetting & NMK_GPIO_ALT_C), glitch);
1613 clk_disable(nmk_chip->clk);
1614
1615 /*
1616 * Call PRCM GPIOCR config function in case ALTC
1617 * has been selected:
1618 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
1619 * must be set.
1620 * - If selection is pure ALTC and previous selection was ALTCx,
1621 * then some bits in PRCM GPIOCR registers must be cleared.
1622 */
1623 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
1624 nmk_prcm_altcx_set_mode(npct, g->grp.pins[i],
1625 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
1626 }
1627
1628 /* When all pins are successfully reconfigured we get here */
1629 ret = 0;
1630
1631 out_glitch:
1632 if (glitch) {
1633 nmk_gpio_glitch_slpm_restore(slpm);
1634 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1635 }
1636
1637 return ret;
1638 }
1639
nmk_gpio_request_enable(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned offset)1640 static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1641 struct pinctrl_gpio_range *range,
1642 unsigned offset)
1643 {
1644 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1645 struct nmk_gpio_chip *nmk_chip;
1646 struct gpio_chip *chip;
1647 unsigned bit;
1648
1649 if (!range) {
1650 dev_err(npct->dev, "invalid range\n");
1651 return -EINVAL;
1652 }
1653 if (!range->gc) {
1654 dev_err(npct->dev, "missing GPIO chip in range\n");
1655 return -EINVAL;
1656 }
1657 chip = range->gc;
1658 nmk_chip = gpiochip_get_data(chip);
1659
1660 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1661
1662 clk_enable(nmk_chip->clk);
1663 bit = offset % NMK_GPIO_PER_CHIP;
1664 /* There is no glitch when converting any pin to GPIO */
1665 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1666 clk_disable(nmk_chip->clk);
1667
1668 return 0;
1669 }
1670
nmk_gpio_disable_free(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned offset)1671 static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1672 struct pinctrl_gpio_range *range,
1673 unsigned offset)
1674 {
1675 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1676
1677 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1678 /* Set the pin to some default state, GPIO is usually default */
1679 }
1680
1681 static const struct pinmux_ops nmk_pinmux_ops = {
1682 .get_functions_count = nmk_pmx_get_funcs_cnt,
1683 .get_function_name = nmk_pmx_get_func_name,
1684 .get_function_groups = nmk_pmx_get_func_groups,
1685 .set_mux = nmk_pmx_set,
1686 .gpio_request_enable = nmk_gpio_request_enable,
1687 .gpio_disable_free = nmk_gpio_disable_free,
1688 .strict = true,
1689 };
1690
nmk_pin_config_get(struct pinctrl_dev * pctldev,unsigned pin,unsigned long * config)1691 static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
1692 unsigned long *config)
1693 {
1694 /* Not implemented */
1695 return -EINVAL;
1696 }
1697
nmk_pin_config_set(struct pinctrl_dev * pctldev,unsigned pin,unsigned long * configs,unsigned num_configs)1698 static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1699 unsigned long *configs, unsigned num_configs)
1700 {
1701 static const char *pullnames[] = {
1702 [NMK_GPIO_PULL_NONE] = "none",
1703 [NMK_GPIO_PULL_UP] = "up",
1704 [NMK_GPIO_PULL_DOWN] = "down",
1705 [3] /* illegal */ = "??"
1706 };
1707 static const char *slpmnames[] = {
1708 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
1709 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
1710 };
1711 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1712 struct nmk_gpio_chip *nmk_chip;
1713 unsigned bit;
1714 pin_cfg_t cfg;
1715 int pull, slpm, output, val, i;
1716 bool lowemi, gpiomode, sleep;
1717
1718 nmk_chip = find_nmk_gpio_from_pin(pin);
1719 if (!nmk_chip) {
1720 dev_err(npct->dev,
1721 "invalid pin offset %d\n", pin);
1722 return -EINVAL;
1723 }
1724
1725 for (i = 0; i < num_configs; i++) {
1726 /*
1727 * The pin config contains pin number and altfunction fields,
1728 * here we just ignore that part. It's being handled by the
1729 * framework and pinmux callback respectively.
1730 */
1731 cfg = (pin_cfg_t) configs[i];
1732 pull = PIN_PULL(cfg);
1733 slpm = PIN_SLPM(cfg);
1734 output = PIN_DIR(cfg);
1735 val = PIN_VAL(cfg);
1736 lowemi = PIN_LOWEMI(cfg);
1737 gpiomode = PIN_GPIOMODE(cfg);
1738 sleep = PIN_SLEEPMODE(cfg);
1739
1740 if (sleep) {
1741 int slpm_pull = PIN_SLPM_PULL(cfg);
1742 int slpm_output = PIN_SLPM_DIR(cfg);
1743 int slpm_val = PIN_SLPM_VAL(cfg);
1744
1745 /* All pins go into GPIO mode at sleep */
1746 gpiomode = true;
1747
1748 /*
1749 * The SLPM_* values are normal values + 1 to allow zero
1750 * to mean "same as normal".
1751 */
1752 if (slpm_pull)
1753 pull = slpm_pull - 1;
1754 if (slpm_output)
1755 output = slpm_output - 1;
1756 if (slpm_val)
1757 val = slpm_val - 1;
1758
1759 dev_dbg(nmk_chip->chip.parent,
1760 "pin %d: sleep pull %s, dir %s, val %s\n",
1761 pin,
1762 slpm_pull ? pullnames[pull] : "same",
1763 slpm_output ? (output ? "output" : "input")
1764 : "same",
1765 slpm_val ? (val ? "high" : "low") : "same");
1766 }
1767
1768 dev_dbg(nmk_chip->chip.parent,
1769 "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1770 pin, cfg, pullnames[pull], slpmnames[slpm],
1771 output ? "output " : "input",
1772 output ? (val ? "high" : "low") : "",
1773 lowemi ? "on" : "off");
1774
1775 clk_enable(nmk_chip->clk);
1776 bit = pin % NMK_GPIO_PER_CHIP;
1777 if (gpiomode)
1778 /* No glitch when going to GPIO mode */
1779 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1780 if (output)
1781 __nmk_gpio_make_output(nmk_chip, bit, val);
1782 else {
1783 __nmk_gpio_make_input(nmk_chip, bit);
1784 __nmk_gpio_set_pull(nmk_chip, bit, pull);
1785 }
1786 /* TODO: isn't this only applicable on output pins? */
1787 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1788
1789 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1790 clk_disable(nmk_chip->clk);
1791 } /* for each config */
1792
1793 return 0;
1794 }
1795
1796 static const struct pinconf_ops nmk_pinconf_ops = {
1797 .pin_config_get = nmk_pin_config_get,
1798 .pin_config_set = nmk_pin_config_set,
1799 };
1800
1801 static struct pinctrl_desc nmk_pinctrl_desc = {
1802 .name = "pinctrl-nomadik",
1803 .pctlops = &nmk_pinctrl_ops,
1804 .pmxops = &nmk_pinmux_ops,
1805 .confops = &nmk_pinconf_ops,
1806 .owner = THIS_MODULE,
1807 };
1808
1809 static const struct of_device_id nmk_pinctrl_match[] = {
1810 {
1811 .compatible = "stericsson,stn8815-pinctrl",
1812 .data = (void *)PINCTRL_NMK_STN8815,
1813 },
1814 {
1815 .compatible = "stericsson,db8500-pinctrl",
1816 .data = (void *)PINCTRL_NMK_DB8500,
1817 },
1818 {},
1819 };
1820
1821 #ifdef CONFIG_PM_SLEEP
nmk_pinctrl_suspend(struct device * dev)1822 static int nmk_pinctrl_suspend(struct device *dev)
1823 {
1824 struct nmk_pinctrl *npct;
1825
1826 npct = dev_get_drvdata(dev);
1827 if (!npct)
1828 return -EINVAL;
1829
1830 return pinctrl_force_sleep(npct->pctl);
1831 }
1832
nmk_pinctrl_resume(struct device * dev)1833 static int nmk_pinctrl_resume(struct device *dev)
1834 {
1835 struct nmk_pinctrl *npct;
1836
1837 npct = dev_get_drvdata(dev);
1838 if (!npct)
1839 return -EINVAL;
1840
1841 return pinctrl_force_default(npct->pctl);
1842 }
1843 #endif
1844
nmk_pinctrl_probe(struct platform_device * pdev)1845 static int nmk_pinctrl_probe(struct platform_device *pdev)
1846 {
1847 struct device_node *np = pdev->dev.of_node;
1848 struct device_node *prcm_np;
1849 struct nmk_pinctrl *npct;
1850 unsigned int version = 0;
1851 int i;
1852
1853 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1854 if (!npct)
1855 return -ENOMEM;
1856
1857 version = (unsigned int)device_get_match_data(&pdev->dev);
1858
1859 /* Poke in other ASIC variants here */
1860 if (version == PINCTRL_NMK_STN8815)
1861 nmk_pinctrl_stn8815_init(&npct->soc);
1862 if (version == PINCTRL_NMK_DB8500)
1863 nmk_pinctrl_db8500_init(&npct->soc);
1864
1865 /*
1866 * Since we depend on the GPIO chips to provide clock and register base
1867 * for the pin control operations, make sure that we have these
1868 * populated before we continue. Follow the phandles to instantiate
1869 * them. The GPIO portion of the actual hardware may be probed before
1870 * or after this point: it shouldn't matter as the APIs are orthogonal.
1871 */
1872 for (i = 0; i < NMK_MAX_BANKS; i++) {
1873 struct device_node *gpio_np;
1874 struct nmk_gpio_chip *nmk_chip;
1875
1876 gpio_np = of_parse_phandle(np, "nomadik-gpio-chips", i);
1877 if (gpio_np) {
1878 dev_info(&pdev->dev,
1879 "populate NMK GPIO %d \"%pOFn\"\n",
1880 i, gpio_np);
1881 nmk_chip = nmk_gpio_populate_chip(gpio_np, pdev);
1882 if (IS_ERR(nmk_chip))
1883 dev_err(&pdev->dev,
1884 "could not populate nmk chip struct "
1885 "- continue anyway\n");
1886 of_node_put(gpio_np);
1887 }
1888 }
1889
1890 prcm_np = of_parse_phandle(np, "prcm", 0);
1891 if (prcm_np) {
1892 npct->prcm_base = of_iomap(prcm_np, 0);
1893 of_node_put(prcm_np);
1894 }
1895 if (!npct->prcm_base) {
1896 if (version == PINCTRL_NMK_STN8815) {
1897 dev_info(&pdev->dev,
1898 "No PRCM base, "
1899 "assuming no ALT-Cx control is available\n");
1900 } else {
1901 dev_err(&pdev->dev, "missing PRCM base address\n");
1902 return -EINVAL;
1903 }
1904 }
1905
1906 nmk_pinctrl_desc.pins = npct->soc->pins;
1907 nmk_pinctrl_desc.npins = npct->soc->npins;
1908 npct->dev = &pdev->dev;
1909
1910 npct->pctl = devm_pinctrl_register(&pdev->dev, &nmk_pinctrl_desc, npct);
1911 if (IS_ERR(npct->pctl)) {
1912 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
1913 return PTR_ERR(npct->pctl);
1914 }
1915
1916 platform_set_drvdata(pdev, npct);
1917 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
1918
1919 return 0;
1920 }
1921
1922 static const struct of_device_id nmk_gpio_match[] = {
1923 { .compatible = "st,nomadik-gpio", },
1924 {}
1925 };
1926
1927 static struct platform_driver nmk_gpio_driver = {
1928 .driver = {
1929 .name = "gpio",
1930 .of_match_table = nmk_gpio_match,
1931 },
1932 .probe = nmk_gpio_probe,
1933 };
1934
1935 static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops,
1936 nmk_pinctrl_suspend,
1937 nmk_pinctrl_resume);
1938
1939 static struct platform_driver nmk_pinctrl_driver = {
1940 .driver = {
1941 .name = "pinctrl-nomadik",
1942 .of_match_table = nmk_pinctrl_match,
1943 .pm = &nmk_pinctrl_pm_ops,
1944 },
1945 .probe = nmk_pinctrl_probe,
1946 };
1947
nmk_gpio_init(void)1948 static int __init nmk_gpio_init(void)
1949 {
1950 return platform_driver_register(&nmk_gpio_driver);
1951 }
1952 subsys_initcall(nmk_gpio_init);
1953
nmk_pinctrl_init(void)1954 static int __init nmk_pinctrl_init(void)
1955 {
1956 return platform_driver_register(&nmk_pinctrl_driver);
1957 }
1958 core_initcall(nmk_pinctrl_init);
1959