1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef DRIVERS_PCI_H
3 #define DRIVERS_PCI_H
4
5 #include <linux/pci.h>
6
7 /* Number of possible devfns: 0.0 to 1f.7 inclusive */
8 #define MAX_NR_DEVFNS 256
9
10 #define PCI_FIND_CAP_TTL 48
11
12 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
13
14 #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000
15
16 /* Power stable to PERST# inactive from PCIe card Electromechanical Spec */
17 #define PCIE_T_PVPERL_MS 100
18
19 /*
20 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization>
21 * Recommends 1ms to 10ms timeout to check L2 ready.
22 */
23 #define PCIE_PME_TO_L2_TIMEOUT_US 10000
24
25 extern const unsigned char pcie_link_speed[];
26 extern bool pci_early_dump;
27
28 bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
29 bool pcie_cap_has_lnkctl2(const struct pci_dev *dev);
30 bool pcie_cap_has_rtctl(const struct pci_dev *dev);
31
32 /* Functions internal to the PCI core code */
33
34 int pci_create_sysfs_dev_files(struct pci_dev *pdev);
35 void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
36 void pci_cleanup_rom(struct pci_dev *dev);
37 #ifdef CONFIG_DMI
38 extern const struct attribute_group pci_dev_smbios_attr_group;
39 #endif
40
41 enum pci_mmap_api {
42 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
43 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
44 };
45 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
46 enum pci_mmap_api mmap_api);
47
48 bool pci_reset_supported(struct pci_dev *dev);
49 void pci_init_reset_methods(struct pci_dev *dev);
50 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
51 int pci_bus_error_reset(struct pci_dev *dev);
52
53 struct pci_cap_saved_data {
54 u16 cap_nr;
55 bool cap_extended;
56 unsigned int size;
57 u32 data[];
58 };
59
60 struct pci_cap_saved_state {
61 struct hlist_node next;
62 struct pci_cap_saved_data cap;
63 };
64
65 void pci_allocate_cap_save_buffers(struct pci_dev *dev);
66 void pci_free_cap_save_buffers(struct pci_dev *dev);
67 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
68 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
69 u16 cap, unsigned int size);
70 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
71 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
72 u16 cap);
73
74 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */
75 #define PCI_PM_D3HOT_WAIT 10 /* msec */
76 #define PCI_PM_D3COLD_WAIT 100 /* msec */
77
78 void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
79 void pci_refresh_power_state(struct pci_dev *dev);
80 int pci_power_up(struct pci_dev *dev);
81 void pci_disable_enabled_device(struct pci_dev *dev);
82 int pci_finish_runtime_suspend(struct pci_dev *dev);
83 void pcie_clear_device_status(struct pci_dev *dev);
84 void pcie_clear_root_pme_status(struct pci_dev *dev);
85 bool pci_check_pme_status(struct pci_dev *dev);
86 void pci_pme_wakeup_bus(struct pci_bus *bus);
87 int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
88 void pci_pme_restore(struct pci_dev *dev);
89 bool pci_dev_need_resume(struct pci_dev *dev);
90 void pci_dev_adjust_pme(struct pci_dev *dev);
91 void pci_dev_complete_resume(struct pci_dev *pci_dev);
92 void pci_config_pm_runtime_get(struct pci_dev *dev);
93 void pci_config_pm_runtime_put(struct pci_dev *dev);
94 void pci_pm_init(struct pci_dev *dev);
95 void pci_ea_init(struct pci_dev *dev);
96 void pci_msi_init(struct pci_dev *dev);
97 void pci_msix_init(struct pci_dev *dev);
98 bool pci_bridge_d3_possible(struct pci_dev *dev);
99 void pci_bridge_d3_update(struct pci_dev *dev);
100 void pci_bridge_reconfigure_ltr(struct pci_dev *dev);
101 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type);
102
pci_wakeup_event(struct pci_dev * dev)103 static inline void pci_wakeup_event(struct pci_dev *dev)
104 {
105 /* Wait 100 ms before the system can be put into a sleep state. */
106 pm_wakeup_event(&dev->dev, 100);
107 }
108
pci_has_subordinate(struct pci_dev * pci_dev)109 static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
110 {
111 return !!(pci_dev->subordinate);
112 }
113
pci_power_manageable(struct pci_dev * pci_dev)114 static inline bool pci_power_manageable(struct pci_dev *pci_dev)
115 {
116 /*
117 * Currently we allow normal PCI devices and PCI bridges transition
118 * into D3 if their bridge_d3 is set.
119 */
120 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
121 }
122
pcie_downstream_port(const struct pci_dev * dev)123 static inline bool pcie_downstream_port(const struct pci_dev *dev)
124 {
125 int type = pci_pcie_type(dev);
126
127 return type == PCI_EXP_TYPE_ROOT_PORT ||
128 type == PCI_EXP_TYPE_DOWNSTREAM ||
129 type == PCI_EXP_TYPE_PCIE_BRIDGE;
130 }
131
132 void pci_vpd_init(struct pci_dev *dev);
133 void pci_vpd_release(struct pci_dev *dev);
134 extern const struct attribute_group pci_dev_vpd_attr_group;
135
136 /* PCI Virtual Channel */
137 int pci_save_vc_state(struct pci_dev *dev);
138 void pci_restore_vc_state(struct pci_dev *dev);
139 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
140
141 /* PCI /proc functions */
142 #ifdef CONFIG_PROC_FS
143 int pci_proc_attach_device(struct pci_dev *dev);
144 int pci_proc_detach_device(struct pci_dev *dev);
145 int pci_proc_detach_bus(struct pci_bus *bus);
146 #else
pci_proc_attach_device(struct pci_dev * dev)147 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
pci_proc_detach_device(struct pci_dev * dev)148 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
pci_proc_detach_bus(struct pci_bus * bus)149 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
150 #endif
151
152 /* Functions for PCI Hotplug drivers to use */
153 int pci_hp_add_bridge(struct pci_dev *dev);
154
155 #ifdef HAVE_PCI_LEGACY
156 void pci_create_legacy_files(struct pci_bus *bus);
157 void pci_remove_legacy_files(struct pci_bus *bus);
158 #else
pci_create_legacy_files(struct pci_bus * bus)159 static inline void pci_create_legacy_files(struct pci_bus *bus) { }
pci_remove_legacy_files(struct pci_bus * bus)160 static inline void pci_remove_legacy_files(struct pci_bus *bus) { }
161 #endif
162
163 /* Lock for read/write access to pci device and bus lists */
164 extern struct rw_semaphore pci_bus_sem;
165 extern struct mutex pci_slot_mutex;
166
167 extern raw_spinlock_t pci_lock;
168
169 extern unsigned int pci_pm_d3hot_delay;
170
171 #ifdef CONFIG_PCI_MSI
172 void pci_no_msi(void);
173 #else
pci_no_msi(void)174 static inline void pci_no_msi(void) { }
175 #endif
176
177 void pci_realloc_get_opt(char *);
178
pci_no_d1d2(struct pci_dev * dev)179 static inline int pci_no_d1d2(struct pci_dev *dev)
180 {
181 unsigned int parent_dstates = 0;
182
183 if (dev->bus->self)
184 parent_dstates = dev->bus->self->no_d1d2;
185 return (dev->no_d1d2 || parent_dstates);
186
187 }
188 extern const struct attribute_group *pci_dev_groups[];
189 extern const struct attribute_group *pcibus_groups[];
190 extern const struct device_type pci_dev_type;
191 extern const struct attribute_group *pci_bus_groups[];
192
193 extern unsigned long pci_hotplug_io_size;
194 extern unsigned long pci_hotplug_mmio_size;
195 extern unsigned long pci_hotplug_mmio_pref_size;
196 extern unsigned long pci_hotplug_bus_size;
197
198 /**
199 * pci_match_one_device - Tell if a PCI device structure has a matching
200 * PCI device id structure
201 * @id: single PCI device id structure to match
202 * @dev: the PCI device structure to match against
203 *
204 * Returns the matching pci_device_id structure or %NULL if there is no match.
205 */
206 static inline const struct pci_device_id *
pci_match_one_device(const struct pci_device_id * id,const struct pci_dev * dev)207 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
208 {
209 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
210 (id->device == PCI_ANY_ID || id->device == dev->device) &&
211 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
212 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
213 !((id->class ^ dev->class) & id->class_mask))
214 return id;
215 return NULL;
216 }
217
218 /* PCI slot sysfs helper code */
219 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
220
221 extern struct kset *pci_slots_kset;
222
223 struct pci_slot_attribute {
224 struct attribute attr;
225 ssize_t (*show)(struct pci_slot *, char *);
226 ssize_t (*store)(struct pci_slot *, const char *, size_t);
227 };
228 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
229
230 enum pci_bar_type {
231 pci_bar_unknown, /* Standard PCI BAR probe */
232 pci_bar_io, /* An I/O port BAR */
233 pci_bar_mem32, /* A 32-bit memory BAR */
234 pci_bar_mem64, /* A 64-bit memory BAR */
235 };
236
237 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
238 void pci_put_host_bridge_device(struct device *dev);
239
240 int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
241 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
242 int crs_timeout);
243 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
244 int crs_timeout);
245 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
246
247 int pci_setup_device(struct pci_dev *dev);
248 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
249 struct resource *res, unsigned int reg);
250 void pci_configure_ari(struct pci_dev *dev);
251 void __pci_bus_size_bridges(struct pci_bus *bus,
252 struct list_head *realloc_head);
253 void __pci_bus_assign_resources(const struct pci_bus *bus,
254 struct list_head *realloc_head,
255 struct list_head *fail_head);
256 bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
257
258 const char *pci_resource_name(struct pci_dev *dev, unsigned int i);
259
260 void pci_reassigndev_resource_alignment(struct pci_dev *dev);
261 void pci_disable_bridge_window(struct pci_dev *dev);
262 struct pci_bus *pci_bus_get(struct pci_bus *bus);
263 void pci_bus_put(struct pci_bus *bus);
264
265 /* PCIe link information from Link Capabilities 2 */
266 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
267 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
268 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
269 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
270 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
271 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
272 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
273 PCI_SPEED_UNKNOWN)
274
275 /* PCIe speed to Mb/s reduced by encoding overhead */
276 #define PCIE_SPEED2MBS_ENC(speed) \
277 ((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \
278 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
279 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
280 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
281 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
282 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
283 0)
284
285 const char *pci_speed_string(enum pci_bus_speed speed);
286 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
287 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
288 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
289 enum pcie_link_width *width);
290 void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
291 void pcie_report_downtraining(struct pci_dev *dev);
292 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
293
294 /* Single Root I/O Virtualization */
295 struct pci_sriov {
296 int pos; /* Capability position */
297 int nres; /* Number of resources */
298 u32 cap; /* SR-IOV Capabilities */
299 u16 ctrl; /* SR-IOV Control */
300 u16 total_VFs; /* Total VFs associated with the PF */
301 u16 initial_VFs; /* Initial VFs associated with the PF */
302 u16 num_VFs; /* Number of VFs available */
303 u16 offset; /* First VF Routing ID offset */
304 u16 stride; /* Following VF stride */
305 u16 vf_device; /* VF device ID */
306 u32 pgsz; /* Page size for BAR alignment */
307 u8 link; /* Function Dependency Link */
308 u8 max_VF_buses; /* Max buses consumed by VFs */
309 u16 driver_max_VFs; /* Max num VFs driver supports */
310 struct pci_dev *dev; /* Lowest numbered PF */
311 struct pci_dev *self; /* This PF */
312 u32 class; /* VF device */
313 u8 hdr_type; /* VF header type */
314 u16 subsystem_vendor; /* VF subsystem vendor */
315 u16 subsystem_device; /* VF subsystem device */
316 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
317 bool drivers_autoprobe; /* Auto probing of VFs by driver */
318 };
319
320 #ifdef CONFIG_PCI_DOE
321 void pci_doe_init(struct pci_dev *pdev);
322 void pci_doe_destroy(struct pci_dev *pdev);
323 void pci_doe_disconnected(struct pci_dev *pdev);
324 #else
pci_doe_init(struct pci_dev * pdev)325 static inline void pci_doe_init(struct pci_dev *pdev) { }
pci_doe_destroy(struct pci_dev * pdev)326 static inline void pci_doe_destroy(struct pci_dev *pdev) { }
pci_doe_disconnected(struct pci_dev * pdev)327 static inline void pci_doe_disconnected(struct pci_dev *pdev) { }
328 #endif
329
330 /**
331 * pci_dev_set_io_state - Set the new error state if possible.
332 *
333 * @dev: PCI device to set new error_state
334 * @new: the state we want dev to be in
335 *
336 * If the device is experiencing perm_failure, it has to remain in that state.
337 * Any other transition is allowed.
338 *
339 * Returns true if state has been changed to the requested state.
340 */
pci_dev_set_io_state(struct pci_dev * dev,pci_channel_state_t new)341 static inline bool pci_dev_set_io_state(struct pci_dev *dev,
342 pci_channel_state_t new)
343 {
344 pci_channel_state_t old;
345
346 switch (new) {
347 case pci_channel_io_perm_failure:
348 xchg(&dev->error_state, pci_channel_io_perm_failure);
349 return true;
350 case pci_channel_io_frozen:
351 old = cmpxchg(&dev->error_state, pci_channel_io_normal,
352 pci_channel_io_frozen);
353 return old != pci_channel_io_perm_failure;
354 case pci_channel_io_normal:
355 old = cmpxchg(&dev->error_state, pci_channel_io_frozen,
356 pci_channel_io_normal);
357 return old != pci_channel_io_perm_failure;
358 default:
359 return false;
360 }
361 }
362
pci_dev_set_disconnected(struct pci_dev * dev,void * unused)363 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
364 {
365 pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
366 pci_doe_disconnected(dev);
367
368 return 0;
369 }
370
pci_dev_is_disconnected(const struct pci_dev * dev)371 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
372 {
373 return dev->error_state == pci_channel_io_perm_failure;
374 }
375
376 /* pci_dev priv_flags */
377 #define PCI_DEV_ADDED 0
378 #define PCI_DPC_RECOVERED 1
379 #define PCI_DPC_RECOVERING 2
380
pci_dev_assign_added(struct pci_dev * dev,bool added)381 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
382 {
383 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
384 }
385
pci_dev_is_added(const struct pci_dev * dev)386 static inline bool pci_dev_is_added(const struct pci_dev *dev)
387 {
388 return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
389 }
390
391 #ifdef CONFIG_PCIEAER
392 #include <linux/aer.h>
393
394 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
395
396 struct aer_err_info {
397 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
398 int error_dev_num;
399
400 unsigned int id:16;
401
402 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
403 unsigned int __pad1:5;
404 unsigned int multi_error_valid:1;
405
406 unsigned int first_error:5;
407 unsigned int __pad2:2;
408 unsigned int tlp_header_valid:1;
409
410 unsigned int status; /* COR/UNCOR Error Status */
411 unsigned int mask; /* COR/UNCOR Error Mask */
412 struct aer_header_log_regs tlp; /* TLP Header */
413 };
414
415 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
416 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
417 #endif /* CONFIG_PCIEAER */
418
419 #ifdef CONFIG_PCIEPORTBUS
420 /* Cached RCEC Endpoint Association */
421 struct rcec_ea {
422 u8 nextbusn;
423 u8 lastbusn;
424 u32 bitmap;
425 };
426 #endif
427
428 #ifdef CONFIG_PCIE_DPC
429 void pci_save_dpc_state(struct pci_dev *dev);
430 void pci_restore_dpc_state(struct pci_dev *dev);
431 void pci_dpc_init(struct pci_dev *pdev);
432 void dpc_process_error(struct pci_dev *pdev);
433 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
434 bool pci_dpc_recovered(struct pci_dev *pdev);
435 #else
pci_save_dpc_state(struct pci_dev * dev)436 static inline void pci_save_dpc_state(struct pci_dev *dev) { }
pci_restore_dpc_state(struct pci_dev * dev)437 static inline void pci_restore_dpc_state(struct pci_dev *dev) { }
pci_dpc_init(struct pci_dev * pdev)438 static inline void pci_dpc_init(struct pci_dev *pdev) { }
pci_dpc_recovered(struct pci_dev * pdev)439 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; }
440 #endif
441
442 #ifdef CONFIG_PCIEPORTBUS
443 void pci_rcec_init(struct pci_dev *dev);
444 void pci_rcec_exit(struct pci_dev *dev);
445 void pcie_link_rcec(struct pci_dev *rcec);
446 void pcie_walk_rcec(struct pci_dev *rcec,
447 int (*cb)(struct pci_dev *, void *),
448 void *userdata);
449 #else
pci_rcec_init(struct pci_dev * dev)450 static inline void pci_rcec_init(struct pci_dev *dev) { }
pci_rcec_exit(struct pci_dev * dev)451 static inline void pci_rcec_exit(struct pci_dev *dev) { }
pcie_link_rcec(struct pci_dev * rcec)452 static inline void pcie_link_rcec(struct pci_dev *rcec) { }
pcie_walk_rcec(struct pci_dev * rcec,int (* cb)(struct pci_dev *,void *),void * userdata)453 static inline void pcie_walk_rcec(struct pci_dev *rcec,
454 int (*cb)(struct pci_dev *, void *),
455 void *userdata) { }
456 #endif
457
458 #ifdef CONFIG_PCI_ATS
459 /* Address Translation Service */
460 void pci_ats_init(struct pci_dev *dev);
461 void pci_restore_ats_state(struct pci_dev *dev);
462 #else
pci_ats_init(struct pci_dev * d)463 static inline void pci_ats_init(struct pci_dev *d) { }
pci_restore_ats_state(struct pci_dev * dev)464 static inline void pci_restore_ats_state(struct pci_dev *dev) { }
465 #endif /* CONFIG_PCI_ATS */
466
467 #ifdef CONFIG_PCI_PRI
468 void pci_pri_init(struct pci_dev *dev);
469 void pci_restore_pri_state(struct pci_dev *pdev);
470 #else
pci_pri_init(struct pci_dev * dev)471 static inline void pci_pri_init(struct pci_dev *dev) { }
pci_restore_pri_state(struct pci_dev * pdev)472 static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
473 #endif
474
475 #ifdef CONFIG_PCI_PASID
476 void pci_pasid_init(struct pci_dev *dev);
477 void pci_restore_pasid_state(struct pci_dev *pdev);
478 #else
pci_pasid_init(struct pci_dev * dev)479 static inline void pci_pasid_init(struct pci_dev *dev) { }
pci_restore_pasid_state(struct pci_dev * pdev)480 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
481 #endif
482
483 #ifdef CONFIG_PCI_IOV
484 int pci_iov_init(struct pci_dev *dev);
485 void pci_iov_release(struct pci_dev *dev);
486 void pci_iov_remove(struct pci_dev *dev);
487 void pci_iov_update_resource(struct pci_dev *dev, int resno);
488 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
489 void pci_restore_iov_state(struct pci_dev *dev);
490 int pci_iov_bus_range(struct pci_bus *bus);
491 extern const struct attribute_group sriov_pf_dev_attr_group;
492 extern const struct attribute_group sriov_vf_dev_attr_group;
493 #else
pci_iov_init(struct pci_dev * dev)494 static inline int pci_iov_init(struct pci_dev *dev)
495 {
496 return -ENODEV;
497 }
pci_iov_release(struct pci_dev * dev)498 static inline void pci_iov_release(struct pci_dev *dev) { }
pci_iov_remove(struct pci_dev * dev)499 static inline void pci_iov_remove(struct pci_dev *dev) { }
pci_restore_iov_state(struct pci_dev * dev)500 static inline void pci_restore_iov_state(struct pci_dev *dev) { }
pci_iov_bus_range(struct pci_bus * bus)501 static inline int pci_iov_bus_range(struct pci_bus *bus)
502 {
503 return 0;
504 }
505
506 #endif /* CONFIG_PCI_IOV */
507
508 #ifdef CONFIG_PCIE_PTM
509 void pci_ptm_init(struct pci_dev *dev);
510 void pci_save_ptm_state(struct pci_dev *dev);
511 void pci_restore_ptm_state(struct pci_dev *dev);
512 void pci_suspend_ptm(struct pci_dev *dev);
513 void pci_resume_ptm(struct pci_dev *dev);
514 #else
pci_ptm_init(struct pci_dev * dev)515 static inline void pci_ptm_init(struct pci_dev *dev) { }
pci_save_ptm_state(struct pci_dev * dev)516 static inline void pci_save_ptm_state(struct pci_dev *dev) { }
pci_restore_ptm_state(struct pci_dev * dev)517 static inline void pci_restore_ptm_state(struct pci_dev *dev) { }
pci_suspend_ptm(struct pci_dev * dev)518 static inline void pci_suspend_ptm(struct pci_dev *dev) { }
pci_resume_ptm(struct pci_dev * dev)519 static inline void pci_resume_ptm(struct pci_dev *dev) { }
520 #endif
521
522 unsigned long pci_cardbus_resource_alignment(struct resource *);
523
pci_resource_alignment(struct pci_dev * dev,struct resource * res)524 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
525 struct resource *res)
526 {
527 #ifdef CONFIG_PCI_IOV
528 int resno = res - dev->resource;
529
530 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
531 return pci_sriov_resource_alignment(dev, resno);
532 #endif
533 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
534 return pci_cardbus_resource_alignment(res);
535 return resource_alignment(res);
536 }
537
538 void pci_acs_init(struct pci_dev *dev);
539 #ifdef CONFIG_PCI_QUIRKS
540 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
541 int pci_dev_specific_enable_acs(struct pci_dev *dev);
542 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
543 bool pcie_failed_link_retrain(struct pci_dev *dev);
544 #else
pci_dev_specific_acs_enabled(struct pci_dev * dev,u16 acs_flags)545 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
546 u16 acs_flags)
547 {
548 return -ENOTTY;
549 }
pci_dev_specific_enable_acs(struct pci_dev * dev)550 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
551 {
552 return -ENOTTY;
553 }
pci_dev_specific_disable_acs_redir(struct pci_dev * dev)554 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
555 {
556 return -ENOTTY;
557 }
pcie_failed_link_retrain(struct pci_dev * dev)558 static inline bool pcie_failed_link_retrain(struct pci_dev *dev)
559 {
560 return false;
561 }
562 #endif
563
564 /* PCI error reporting and recovery */
565 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
566 pci_channel_state_t state,
567 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev));
568
569 bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
570 int pcie_retrain_link(struct pci_dev *pdev, bool use_lt);
571 #ifdef CONFIG_PCIEASPM
572 void pcie_aspm_init_link_state(struct pci_dev *pdev);
573 void pcie_aspm_exit_link_state(struct pci_dev *pdev);
574 void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked);
575 void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
576 #else
pcie_aspm_init_link_state(struct pci_dev * pdev)577 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
pcie_aspm_exit_link_state(struct pci_dev * pdev)578 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
pcie_aspm_pm_state_change(struct pci_dev * pdev,bool locked)579 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) { }
pcie_aspm_powersave_config_link(struct pci_dev * pdev)580 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
581 #endif
582
583 #ifdef CONFIG_PCIE_ECRC
584 void pcie_set_ecrc_checking(struct pci_dev *dev);
585 void pcie_ecrc_get_policy(char *str);
586 #else
pcie_set_ecrc_checking(struct pci_dev * dev)587 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
pcie_ecrc_get_policy(char * str)588 static inline void pcie_ecrc_get_policy(char *str) { }
589 #endif
590
591 struct pci_dev_reset_methods {
592 u16 vendor;
593 u16 device;
594 int (*reset)(struct pci_dev *dev, bool probe);
595 };
596
597 struct pci_reset_fn_method {
598 int (*reset_fn)(struct pci_dev *pdev, bool probe);
599 char *name;
600 };
601
602 #ifdef CONFIG_PCI_QUIRKS
603 int pci_dev_specific_reset(struct pci_dev *dev, bool probe);
604 #else
pci_dev_specific_reset(struct pci_dev * dev,bool probe)605 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
606 {
607 return -ENOTTY;
608 }
609 #endif
610
611 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
612 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
613 struct resource *res);
614 #else
acpi_get_rc_resources(struct device * dev,const char * hid,u16 segment,struct resource * res)615 static inline int acpi_get_rc_resources(struct device *dev, const char *hid,
616 u16 segment, struct resource *res)
617 {
618 return -ENODEV;
619 }
620 #endif
621
622 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
623 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
pci_rebar_size_to_bytes(int size)624 static inline u64 pci_rebar_size_to_bytes(int size)
625 {
626 return 1ULL << (size + 20);
627 }
628
629 struct device_node;
630
631 #ifdef CONFIG_OF
632 int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
633 int of_get_pci_domain_nr(struct device_node *node);
634 int of_pci_get_max_link_speed(struct device_node *node);
635 u32 of_pci_get_slot_power_limit(struct device_node *node,
636 u8 *slot_power_limit_value,
637 u8 *slot_power_limit_scale);
638 int pci_set_of_node(struct pci_dev *dev);
639 void pci_release_of_node(struct pci_dev *dev);
640 void pci_set_bus_of_node(struct pci_bus *bus);
641 void pci_release_bus_of_node(struct pci_bus *bus);
642
643 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
644
645 #else
646 static inline int
of_pci_parse_bus_range(struct device_node * node,struct resource * res)647 of_pci_parse_bus_range(struct device_node *node, struct resource *res)
648 {
649 return -EINVAL;
650 }
651
652 static inline int
of_get_pci_domain_nr(struct device_node * node)653 of_get_pci_domain_nr(struct device_node *node)
654 {
655 return -1;
656 }
657
658 static inline int
of_pci_get_max_link_speed(struct device_node * node)659 of_pci_get_max_link_speed(struct device_node *node)
660 {
661 return -EINVAL;
662 }
663
664 static inline u32
of_pci_get_slot_power_limit(struct device_node * node,u8 * slot_power_limit_value,u8 * slot_power_limit_scale)665 of_pci_get_slot_power_limit(struct device_node *node,
666 u8 *slot_power_limit_value,
667 u8 *slot_power_limit_scale)
668 {
669 if (slot_power_limit_value)
670 *slot_power_limit_value = 0;
671 if (slot_power_limit_scale)
672 *slot_power_limit_scale = 0;
673 return 0;
674 }
675
pci_set_of_node(struct pci_dev * dev)676 static inline int pci_set_of_node(struct pci_dev *dev) { return 0; }
pci_release_of_node(struct pci_dev * dev)677 static inline void pci_release_of_node(struct pci_dev *dev) { }
pci_set_bus_of_node(struct pci_bus * bus)678 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
pci_release_bus_of_node(struct pci_bus * bus)679 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
680
devm_of_pci_bridge_init(struct device * dev,struct pci_host_bridge * bridge)681 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
682 {
683 return 0;
684 }
685
686 #endif /* CONFIG_OF */
687
688 struct of_changeset;
689
690 #ifdef CONFIG_PCI_DYNAMIC_OF_NODES
691 void of_pci_make_dev_node(struct pci_dev *pdev);
692 void of_pci_remove_node(struct pci_dev *pdev);
693 int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs,
694 struct device_node *np);
695 #else
of_pci_make_dev_node(struct pci_dev * pdev)696 static inline void of_pci_make_dev_node(struct pci_dev *pdev) { }
of_pci_remove_node(struct pci_dev * pdev)697 static inline void of_pci_remove_node(struct pci_dev *pdev) { }
698 #endif
699
700 #ifdef CONFIG_PCIEAER
701 void pci_no_aer(void);
702 void pci_aer_init(struct pci_dev *dev);
703 void pci_aer_exit(struct pci_dev *dev);
704 extern const struct attribute_group aer_stats_attr_group;
705 void pci_aer_clear_fatal_status(struct pci_dev *dev);
706 int pci_aer_clear_status(struct pci_dev *dev);
707 int pci_aer_raw_clear_status(struct pci_dev *dev);
708 void pci_save_aer_state(struct pci_dev *dev);
709 void pci_restore_aer_state(struct pci_dev *dev);
710 #else
pci_no_aer(void)711 static inline void pci_no_aer(void) { }
pci_aer_init(struct pci_dev * d)712 static inline void pci_aer_init(struct pci_dev *d) { }
pci_aer_exit(struct pci_dev * d)713 static inline void pci_aer_exit(struct pci_dev *d) { }
pci_aer_clear_fatal_status(struct pci_dev * dev)714 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
pci_aer_clear_status(struct pci_dev * dev)715 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
pci_aer_raw_clear_status(struct pci_dev * dev)716 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
pci_save_aer_state(struct pci_dev * dev)717 static inline void pci_save_aer_state(struct pci_dev *dev) { }
pci_restore_aer_state(struct pci_dev * dev)718 static inline void pci_restore_aer_state(struct pci_dev *dev) { }
719 #endif
720
721 #ifdef CONFIG_ACPI
722 int pci_acpi_program_hp_params(struct pci_dev *dev);
723 extern const struct attribute_group pci_dev_acpi_attr_group;
724 void pci_set_acpi_fwnode(struct pci_dev *dev);
725 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe);
726 bool acpi_pci_power_manageable(struct pci_dev *dev);
727 bool acpi_pci_bridge_d3(struct pci_dev *dev);
728 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state);
729 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev);
730 void acpi_pci_refresh_power_state(struct pci_dev *dev);
731 int acpi_pci_wakeup(struct pci_dev *dev, bool enable);
732 bool acpi_pci_need_resume(struct pci_dev *dev);
733 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev);
734 #else
pci_dev_acpi_reset(struct pci_dev * dev,bool probe)735 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe)
736 {
737 return -ENOTTY;
738 }
pci_set_acpi_fwnode(struct pci_dev * dev)739 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { }
pci_acpi_program_hp_params(struct pci_dev * dev)740 static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
741 {
742 return -ENODEV;
743 }
acpi_pci_power_manageable(struct pci_dev * dev)744 static inline bool acpi_pci_power_manageable(struct pci_dev *dev)
745 {
746 return false;
747 }
acpi_pci_bridge_d3(struct pci_dev * dev)748 static inline bool acpi_pci_bridge_d3(struct pci_dev *dev)
749 {
750 return false;
751 }
acpi_pci_set_power_state(struct pci_dev * dev,pci_power_t state)752 static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
753 {
754 return -ENODEV;
755 }
acpi_pci_get_power_state(struct pci_dev * dev)756 static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev)
757 {
758 return PCI_UNKNOWN;
759 }
acpi_pci_refresh_power_state(struct pci_dev * dev)760 static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { }
acpi_pci_wakeup(struct pci_dev * dev,bool enable)761 static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable)
762 {
763 return -ENODEV;
764 }
acpi_pci_need_resume(struct pci_dev * dev)765 static inline bool acpi_pci_need_resume(struct pci_dev *dev)
766 {
767 return false;
768 }
acpi_pci_choose_state(struct pci_dev * pdev)769 static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
770 {
771 return PCI_POWER_ERROR;
772 }
773 #endif
774
775 #ifdef CONFIG_PCIEASPM
776 extern const struct attribute_group aspm_ctrl_attr_group;
777 #endif
778
779 extern const struct attribute_group pci_dev_reset_method_attr_group;
780
781 #ifdef CONFIG_X86_INTEL_MID
782 bool pci_use_mid_pm(void);
783 int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
784 pci_power_t mid_pci_get_power_state(struct pci_dev *pdev);
785 #else
pci_use_mid_pm(void)786 static inline bool pci_use_mid_pm(void)
787 {
788 return false;
789 }
mid_pci_set_power_state(struct pci_dev * pdev,pci_power_t state)790 static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
791 {
792 return -ENODEV;
793 }
mid_pci_get_power_state(struct pci_dev * pdev)794 static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev)
795 {
796 return PCI_UNKNOWN;
797 }
798 #endif
799
800 /*
801 * Config Address for PCI Configuration Mechanism #1
802 *
803 * See PCI Local Bus Specification, Revision 3.0,
804 * Section 3.2.2.3.2, Figure 3-2, p. 50.
805 */
806
807 #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */
808 #define PCI_CONF1_DEV_SHIFT 11 /* Device number */
809 #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */
810
811 #define PCI_CONF1_BUS_MASK 0xff
812 #define PCI_CONF1_DEV_MASK 0x1f
813 #define PCI_CONF1_FUNC_MASK 0x7
814 #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */
815
816 #define PCI_CONF1_ENABLE BIT(31)
817 #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT)
818 #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT)
819 #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT)
820 #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK)
821
822 #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \
823 (PCI_CONF1_ENABLE | \
824 PCI_CONF1_BUS(bus) | \
825 PCI_CONF1_DEV(dev) | \
826 PCI_CONF1_FUNC(func) | \
827 PCI_CONF1_REG(reg))
828
829 /*
830 * Extension of PCI Config Address for accessing extended PCIe registers
831 *
832 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs
833 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address
834 * are used for specifying additional 4 high bits of PCI Express register.
835 */
836
837 #define PCI_CONF1_EXT_REG_SHIFT 16
838 #define PCI_CONF1_EXT_REG_MASK 0xf00
839 #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT)
840
841 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \
842 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \
843 PCI_CONF1_EXT_REG(reg))
844
845 #endif /* DRIVERS_PCI_H */
846